1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_HAL_H 8 #define ATH11K_HAL_H 9 10 #include "hal_desc.h" 11 #include "rx_desc.h" 12 13 struct ath11k_base; 14 15 #define HAL_LINK_DESC_SIZE (32 << 2) 16 #define HAL_LINK_DESC_ALIGN 128 17 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 18 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 19 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 20 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 21 #define HAL_MAX_AVAIL_BLK_RES 3 22 23 #define HAL_RING_BASE_ALIGN 8 24 25 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 26 /* TODO: Check with hw team on the supported scatter buf size */ 27 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 29 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 30 31 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 32 #define HAL_DSCP_TID_TBL_SIZE 24 33 34 /* calculate the register address from bar0 of shadow register x */ 35 #define HAL_SHADOW_BASE_ADDR(ab) ab->hw_params.regs->hal_shadow_base_addr 36 #define HAL_SHADOW_NUM_REGS 36 37 #define HAL_HP_OFFSET_IN_REG_START 1 38 #define HAL_OFFSET_FROM_HP_TO_TP 4 39 40 #define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x))) 41 42 /* WCSS Relative address */ 43 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 44 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 46 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \ 47 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg) 48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \ 49 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg) 50 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \ 51 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg) 52 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \ 53 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg) 54 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 55 56 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 57 #define HAL_WLAON_REG_BASE 0x01f80000 58 59 /* SW2TCL(x) R0 ring configuration address */ 60 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 61 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 62 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb 63 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb 64 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id 65 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc 66 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 67 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb 68 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 69 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb 70 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 71 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0 72 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 73 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1 74 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 75 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb 76 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 77 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb 78 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 79 ab->hw_params.regs->hal_tcl1_ring_msi1_data 80 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb 81 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb 82 83 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 84 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 85 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 86 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 87 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \ 88 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 89 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) \ 90 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 91 #define HAL_TCL1_RING_ID_OFFSET(ab) \ 92 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 93 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \ 94 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 95 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \ 96 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 97 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \ 98 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 99 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \ 100 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 101 #define HAL_TCL1_RING_MISC_OFFSET(ab) \ 102 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 103 104 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 105 #define HAL_TCL1_RING_HP 0x00002000 106 #define HAL_TCL1_RING_TP 0x00002004 107 #define HAL_TCL2_RING_HP 0x00002008 108 #define HAL_TCL_RING_HP 0x00002018 109 110 #define HAL_TCL1_RING_TP_OFFSET \ 111 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 112 113 /* TCL STATUS ring address */ 114 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 115 ab->hw_params.regs->hal_tcl_status_ring_base_lsb 116 #define HAL_TCL_STATUS_RING_HP 0x00002030 117 118 /* REO2SW(x) R0 ring configuration address */ 119 #define HAL_REO1_GEN_ENABLE 0x00000000 120 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 121 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 122 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 123 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 124 #define HAL_REO1_MISC_CTL(ab) ab->hw_params.regs->hal_reo1_misc_ctl 125 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb 126 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb 127 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id 128 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc 129 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \ 130 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb 131 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \ 132 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb 133 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 134 ab->hw_params.regs->hal_reo1_ring_producer_int_setup 135 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 136 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb 137 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 138 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb 139 #define HAL_REO1_RING_MSI1_DATA(ab) \ 140 ab->hw_params.regs->hal_reo1_ring_msi1_data 141 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb 142 #define HAL_REO1_AGING_THRESH_IX_0(ab) \ 143 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0 144 #define HAL_REO1_AGING_THRESH_IX_1(ab) \ 145 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1 146 #define HAL_REO1_AGING_THRESH_IX_2(ab) \ 147 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2 148 #define HAL_REO1_AGING_THRESH_IX_3(ab) \ 149 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3 150 151 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 152 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 153 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 154 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 155 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \ 156 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab)) 157 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \ 158 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 159 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab)) 160 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \ 161 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab)) 162 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \ 163 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 164 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \ 165 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 166 #define HAL_REO1_RING_MISC_OFFSET(ab) \ 167 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab)) 168 169 /* REO2SW(x) R2 ring pointers (head/tail) address */ 170 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp 171 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp 172 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp 173 174 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)) 175 176 /* REO2TCL R0 ring configuration address */ 177 #define HAL_REO_TCL_RING_BASE_LSB(ab) \ 178 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb 179 180 /* REO2TCL R2 ring pointer (head/tail) address */ 181 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp 182 183 /* REO CMD R0 address */ 184 #define HAL_REO_CMD_RING_BASE_LSB(ab) \ 185 ab->hw_params.regs->hal_reo_cmd_ring_base_lsb 186 187 /* REO CMD R2 address */ 188 #define HAL_REO_CMD_HP(ab) ab->hw_params.regs->hal_reo_cmd_ring_hp 189 190 /* SW2REO R0 address */ 191 #define HAL_SW2REO_RING_BASE_LSB(ab) \ 192 ab->hw_params.regs->hal_sw2reo_ring_base_lsb 193 194 /* SW2REO R2 address */ 195 #define HAL_SW2REO_RING_HP(ab) ab->hw_params.regs->hal_sw2reo_ring_hp 196 197 /* CE ring R0 address */ 198 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 199 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 200 #define HAL_CE_DST_RING_CTRL 0x000000b0 201 202 /* CE ring R2 address */ 203 #define HAL_CE_DST_RING_HP 0x00000400 204 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 205 206 /* REO status address */ 207 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 208 ab->hw_params.regs->hal_reo_status_ring_base_lsb 209 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp 210 211 /* WBM Idle R0 address */ 212 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \ 213 (ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb) 214 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \ 215 (ab->hw_params.regs->hal_wbm_idle_link_ring_misc) 216 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 217 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 218 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 219 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 220 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 221 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 222 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 224 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 225 226 /* WBM Idle R2 address */ 227 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 228 229 /* SW2WBM R0 release address */ 230 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \ 231 (ab->hw_params.regs->hal_wbm_release_ring_base_lsb) 232 233 /* SW2WBM R2 release address */ 234 #define HAL_WBM_RELEASE_RING_HP 0x00003018 235 236 /* WBM2SW R0 release address */ 237 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \ 238 (ab->hw_params.regs->hal_wbm0_release_ring_base_lsb) 239 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \ 240 (ab->hw_params.regs->hal_wbm1_release_ring_base_lsb) 241 242 /* WBM2SW R2 release address */ 243 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 244 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 245 246 /* TCL ring field mask and offset */ 247 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 248 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 249 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 250 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 251 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 252 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 253 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 254 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 255 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 256 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 257 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 258 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 259 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 260 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 264 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 265 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 266 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 267 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 268 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 269 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 270 271 /* REO ring field mask and offset */ 272 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 273 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 274 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 275 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 276 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 277 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 278 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 279 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 280 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 281 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 282 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 283 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 284 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 285 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 286 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 287 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17) 288 289 /* CE ring bit field mask and shift */ 290 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 291 292 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 293 294 #define HAL_ADDR_MSB_REG_SHIFT 32 295 296 /* WBM ring bit field mask and shift */ 297 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 298 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 299 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 300 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 301 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 302 303 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 304 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 305 306 #define BASE_ADDR_MATCH_TAG_VAL 0x5 307 308 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 309 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 310 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 311 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 312 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 313 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 314 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 315 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 316 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 317 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 318 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 319 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 320 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 321 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 322 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 323 324 /* Add any other errors here and return them in 325 * ath11k_hal_rx_desc_get_err(). 326 */ 327 328 enum hal_srng_ring_id { 329 HAL_SRNG_RING_ID_REO2SW1 = 0, 330 HAL_SRNG_RING_ID_REO2SW2, 331 HAL_SRNG_RING_ID_REO2SW3, 332 HAL_SRNG_RING_ID_REO2SW4, 333 HAL_SRNG_RING_ID_REO2TCL, 334 HAL_SRNG_RING_ID_SW2REO, 335 336 HAL_SRNG_RING_ID_REO_CMD = 8, 337 HAL_SRNG_RING_ID_REO_STATUS, 338 339 HAL_SRNG_RING_ID_SW2TCL1 = 16, 340 HAL_SRNG_RING_ID_SW2TCL2, 341 HAL_SRNG_RING_ID_SW2TCL3, 342 HAL_SRNG_RING_ID_SW2TCL4, 343 344 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 345 HAL_SRNG_RING_ID_TCL_STATUS, 346 347 HAL_SRNG_RING_ID_CE0_SRC = 32, 348 HAL_SRNG_RING_ID_CE1_SRC, 349 HAL_SRNG_RING_ID_CE2_SRC, 350 HAL_SRNG_RING_ID_CE3_SRC, 351 HAL_SRNG_RING_ID_CE4_SRC, 352 HAL_SRNG_RING_ID_CE5_SRC, 353 HAL_SRNG_RING_ID_CE6_SRC, 354 HAL_SRNG_RING_ID_CE7_SRC, 355 HAL_SRNG_RING_ID_CE8_SRC, 356 HAL_SRNG_RING_ID_CE9_SRC, 357 HAL_SRNG_RING_ID_CE10_SRC, 358 HAL_SRNG_RING_ID_CE11_SRC, 359 360 HAL_SRNG_RING_ID_CE0_DST = 56, 361 HAL_SRNG_RING_ID_CE1_DST, 362 HAL_SRNG_RING_ID_CE2_DST, 363 HAL_SRNG_RING_ID_CE3_DST, 364 HAL_SRNG_RING_ID_CE4_DST, 365 HAL_SRNG_RING_ID_CE5_DST, 366 HAL_SRNG_RING_ID_CE6_DST, 367 HAL_SRNG_RING_ID_CE7_DST, 368 HAL_SRNG_RING_ID_CE8_DST, 369 HAL_SRNG_RING_ID_CE9_DST, 370 HAL_SRNG_RING_ID_CE10_DST, 371 HAL_SRNG_RING_ID_CE11_DST, 372 373 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 374 HAL_SRNG_RING_ID_CE1_DST_STATUS, 375 HAL_SRNG_RING_ID_CE2_DST_STATUS, 376 HAL_SRNG_RING_ID_CE3_DST_STATUS, 377 HAL_SRNG_RING_ID_CE4_DST_STATUS, 378 HAL_SRNG_RING_ID_CE5_DST_STATUS, 379 HAL_SRNG_RING_ID_CE6_DST_STATUS, 380 HAL_SRNG_RING_ID_CE7_DST_STATUS, 381 HAL_SRNG_RING_ID_CE8_DST_STATUS, 382 HAL_SRNG_RING_ID_CE9_DST_STATUS, 383 HAL_SRNG_RING_ID_CE10_DST_STATUS, 384 HAL_SRNG_RING_ID_CE11_DST_STATUS, 385 386 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 387 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 388 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 389 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 390 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 391 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 392 HAL_SRNG_RING_ID_WBM2SW4_RELEASE, 393 394 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 395 HAL_SRNG_RING_ID_LMAC1_ID_START, 396 397 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 398 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 399 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 400 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 401 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 402 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 403 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 404 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 405 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 406 407 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 408 }; 409 410 /* SRNG registers are split into two groups R0 and R2 */ 411 #define HAL_SRNG_REG_GRP_R0 0 412 #define HAL_SRNG_REG_GRP_R2 1 413 #define HAL_SRNG_NUM_REG_GRP 2 414 415 #define HAL_SRNG_NUM_LMACS 3 416 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 417 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 418 HAL_SRNG_RING_ID_LMAC1_ID_START) 419 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 420 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 421 HAL_SRNG_NUM_LMAC_RINGS) 422 423 enum hal_ring_type { 424 HAL_REO_DST, 425 HAL_REO_EXCEPTION, 426 HAL_REO_REINJECT, 427 HAL_REO_CMD, 428 HAL_REO_STATUS, 429 HAL_TCL_DATA, 430 HAL_TCL_CMD, 431 HAL_TCL_STATUS, 432 HAL_CE_SRC, 433 HAL_CE_DST, 434 HAL_CE_DST_STATUS, 435 HAL_WBM_IDLE_LINK, 436 HAL_SW2WBM_RELEASE, 437 HAL_WBM2SW_RELEASE, 438 HAL_RXDMA_BUF, 439 HAL_RXDMA_DST, 440 HAL_RXDMA_MONITOR_BUF, 441 HAL_RXDMA_MONITOR_STATUS, 442 HAL_RXDMA_MONITOR_DST, 443 HAL_RXDMA_MONITOR_DESC, 444 HAL_RXDMA_DIR_BUF, 445 HAL_MAX_RING_TYPES, 446 }; 447 448 #define HAL_RX_MAX_BA_WINDOW 256 449 450 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 451 452 /** 453 * enum hal_reo_cmd_type: Enum for REO command type 454 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats 455 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue 456 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache 457 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 458 * earlier with a 'REO_FLUSH_CACHE' command 459 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 460 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings 461 */ 462 enum hal_reo_cmd_type { 463 HAL_REO_CMD_GET_QUEUE_STATS = 0, 464 HAL_REO_CMD_FLUSH_QUEUE = 1, 465 HAL_REO_CMD_FLUSH_CACHE = 2, 466 HAL_REO_CMD_UNBLOCK_CACHE = 3, 467 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 468 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 469 }; 470 471 /** 472 * enum hal_reo_cmd_status: Enum for execution status of REO command 473 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 474 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 475 * or cache was blocked 476 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 477 * invalid queue desc 478 * @HAL_REO_CMD_RESOURCE_BLOCKED: 479 * @HAL_REO_CMD_DRAIN: 480 */ 481 enum hal_reo_cmd_status { 482 HAL_REO_CMD_SUCCESS = 0, 483 HAL_REO_CMD_BLOCKED = 1, 484 HAL_REO_CMD_FAILED = 2, 485 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 486 HAL_REO_CMD_DRAIN = 0xff, 487 }; 488 489 struct hal_wbm_idle_scatter_list { 490 dma_addr_t paddr; 491 struct hal_wbm_link_desc *vaddr; 492 }; 493 494 struct hal_srng_params { 495 dma_addr_t ring_base_paddr; 496 u32 *ring_base_vaddr; 497 int num_entries; 498 u32 intr_batch_cntr_thres_entries; 499 u32 intr_timer_thres_us; 500 u32 flags; 501 u32 max_buffer_len; 502 u32 low_threshold; 503 dma_addr_t msi_addr; 504 u32 msi_data; 505 506 /* Add more params as needed */ 507 }; 508 509 enum hal_srng_dir { 510 HAL_SRNG_DIR_SRC, 511 HAL_SRNG_DIR_DST 512 }; 513 514 /* srng flags */ 515 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 516 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 517 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 518 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 519 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 520 #define HAL_SRNG_FLAGS_CACHED 0x20000000 521 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 522 523 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 524 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 525 526 /* Common SRNG ring structure for source and destination rings */ 527 struct hal_srng { 528 /* Unique SRNG ring ID */ 529 u8 ring_id; 530 531 /* Ring initialization done */ 532 u8 initialized; 533 534 /* Interrupt/MSI value assigned to this ring */ 535 int irq; 536 537 /* Physical base address of the ring */ 538 dma_addr_t ring_base_paddr; 539 540 /* Virtual base address of the ring */ 541 u32 *ring_base_vaddr; 542 543 /* Number of entries in ring */ 544 u32 num_entries; 545 546 /* Ring size */ 547 u32 ring_size; 548 549 /* Ring size mask */ 550 u32 ring_size_mask; 551 552 /* Size of ring entry */ 553 u32 entry_size; 554 555 /* Interrupt timer threshold - in micro seconds */ 556 u32 intr_timer_thres_us; 557 558 /* Interrupt batch counter threshold - in number of ring entries */ 559 u32 intr_batch_cntr_thres_entries; 560 561 /* MSI Address */ 562 dma_addr_t msi_addr; 563 564 /* MSI data */ 565 u32 msi_data; 566 567 /* Misc flags */ 568 u32 flags; 569 570 /* Lock for serializing ring index updates */ 571 spinlock_t lock; 572 573 /* Start offset of SRNG register groups for this ring 574 * TBD: See if this is required - register address can be derived 575 * from ring ID 576 */ 577 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 578 579 u64 timestamp; 580 581 /* Source or Destination ring */ 582 enum hal_srng_dir ring_dir; 583 584 union { 585 struct { 586 /* SW tail pointer */ 587 u32 tp; 588 589 /* Shadow head pointer location to be updated by HW */ 590 volatile u32 *hp_addr; 591 592 /* Cached head pointer */ 593 u32 cached_hp; 594 595 /* Tail pointer location to be updated by SW - This 596 * will be a register address and need not be 597 * accessed through SW structure 598 */ 599 u32 *tp_addr; 600 601 /* Current SW loop cnt */ 602 u32 loop_cnt; 603 604 /* max transfer size */ 605 u16 max_buffer_length; 606 607 /* head pointer at access end */ 608 u32 last_hp; 609 } dst_ring; 610 611 struct { 612 /* SW head pointer */ 613 u32 hp; 614 615 /* SW reap head pointer */ 616 u32 reap_hp; 617 618 /* Shadow tail pointer location to be updated by HW */ 619 u32 *tp_addr; 620 621 /* Cached tail pointer */ 622 u32 cached_tp; 623 624 /* Head pointer location to be updated by SW - This 625 * will be a register address and need not be accessed 626 * through SW structure 627 */ 628 u32 *hp_addr; 629 630 /* Low threshold - in number of ring entries */ 631 u32 low_threshold; 632 633 /* tail pointer at access end */ 634 u32 last_tp; 635 } src_ring; 636 } u; 637 }; 638 639 /* Interrupt mitigation - Batch threshold in terms of number of frames */ 640 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 641 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 642 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 643 644 /* Interrupt mitigation - timer threshold in us */ 645 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 646 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 647 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 648 649 /* HW SRNG configuration table */ 650 struct hal_srng_config { 651 int start_ring_id; 652 u16 max_rings; 653 u16 entry_size; 654 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 655 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 656 u8 lmac_ring; 657 enum hal_srng_dir ring_dir; 658 u32 max_size; 659 }; 660 661 /** 662 * enum hal_rx_buf_return_buf_manager 663 * 664 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 665 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 666 * descriptor list. 667 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 668 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 669 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 670 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 671 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 672 */ 673 674 enum hal_rx_buf_return_buf_manager { 675 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 676 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 677 HAL_RX_BUF_RBM_FW_BM, 678 HAL_RX_BUF_RBM_SW0_BM, 679 HAL_RX_BUF_RBM_SW1_BM, 680 HAL_RX_BUF_RBM_SW2_BM, 681 HAL_RX_BUF_RBM_SW3_BM, 682 HAL_RX_BUF_RBM_SW4_BM, 683 }; 684 685 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 686 687 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 688 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 689 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 690 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 691 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 692 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 693 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 694 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 695 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 696 697 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 698 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 699 #define HAL_REO_CMD_UPD0_VLD BIT(9) 700 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 701 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 702 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 703 #define HAL_REO_CMD_UPD0_AC BIT(13) 704 #define HAL_REO_CMD_UPD0_BAR BIT(14) 705 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 706 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 707 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 708 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 709 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 710 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 711 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 712 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 713 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 714 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 715 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 716 #define HAL_REO_CMD_UPD0_SSN BIT(26) 717 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 718 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 719 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 720 #define HAL_REO_CMD_UPD0_PN BIT(30) 721 722 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 723 #define HAL_REO_CMD_UPD1_VLD BIT(16) 724 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 725 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 726 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 727 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 728 #define HAL_REO_CMD_UPD1_BAR BIT(23) 729 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 730 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 731 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 732 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 733 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 734 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 735 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 736 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 737 738 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 739 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 740 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 741 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 742 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 743 744 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 745 746 struct ath11k_hal_reo_cmd { 747 u32 addr_lo; 748 u32 flag; 749 u32 upd0; 750 u32 upd1; 751 u32 upd2; 752 u32 pn[4]; 753 u16 rx_queue_num; 754 u16 min_rel; 755 u16 min_fwd; 756 u8 addr_hi; 757 u8 ac_list; 758 u8 blocking_idx; 759 u16 ba_window_size; 760 u8 pn_size; 761 }; 762 763 enum hal_pn_type { 764 HAL_PN_TYPE_NONE, 765 HAL_PN_TYPE_WPA, 766 HAL_PN_TYPE_WAPI_EVEN, 767 HAL_PN_TYPE_WAPI_UNEVEN, 768 }; 769 770 enum hal_ce_desc { 771 HAL_CE_DESC_SRC, 772 HAL_CE_DESC_DST, 773 HAL_CE_DESC_DST_STATUS, 774 }; 775 776 #define HAL_HASH_ROUTING_RING_TCL 0 777 #define HAL_HASH_ROUTING_RING_SW1 1 778 #define HAL_HASH_ROUTING_RING_SW2 2 779 #define HAL_HASH_ROUTING_RING_SW3 3 780 #define HAL_HASH_ROUTING_RING_SW4 4 781 #define HAL_HASH_ROUTING_RING_REL 5 782 #define HAL_HASH_ROUTING_RING_FW 6 783 784 struct hal_reo_status_header { 785 u16 cmd_num; 786 enum hal_reo_cmd_status cmd_status; 787 u16 cmd_exe_time; 788 u32 timestamp; 789 }; 790 791 struct hal_reo_status_queue_stats { 792 u16 ssn; 793 u16 curr_idx; 794 u32 pn[4]; 795 u32 last_rx_queue_ts; 796 u32 last_rx_dequeue_ts; 797 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 798 u32 curr_mpdu_cnt; 799 u32 curr_msdu_cnt; 800 u16 fwd_due_to_bar_cnt; 801 u16 dup_cnt; 802 u32 frames_in_order_cnt; 803 u32 num_mpdu_processed_cnt; 804 u32 num_msdu_processed_cnt; 805 u32 total_num_processed_byte_cnt; 806 u32 late_rx_mpdu_cnt; 807 u32 reorder_hole_cnt; 808 u8 timeout_cnt; 809 u8 bar_rx_cnt; 810 u8 num_window_2k_jump_cnt; 811 }; 812 813 struct hal_reo_status_flush_queue { 814 bool err_detected; 815 }; 816 817 enum hal_reo_status_flush_cache_err_code { 818 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 819 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 820 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 821 }; 822 823 struct hal_reo_status_flush_cache { 824 bool err_detected; 825 enum hal_reo_status_flush_cache_err_code err_code; 826 bool cache_controller_flush_status_hit; 827 u8 cache_controller_flush_status_desc_type; 828 u8 cache_controller_flush_status_client_id; 829 u8 cache_controller_flush_status_err; 830 u8 cache_controller_flush_status_cnt; 831 }; 832 833 enum hal_reo_status_unblock_cache_type { 834 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 835 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 836 }; 837 838 struct hal_reo_status_unblock_cache { 839 bool err_detected; 840 enum hal_reo_status_unblock_cache_type unblock_type; 841 }; 842 843 struct hal_reo_status_flush_timeout_list { 844 bool err_detected; 845 bool list_empty; 846 u16 release_desc_cnt; 847 u16 fwd_buf_cnt; 848 }; 849 850 enum hal_reo_threshold_idx { 851 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 852 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 853 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 854 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 855 }; 856 857 struct hal_reo_status_desc_thresh_reached { 858 enum hal_reo_threshold_idx threshold_idx; 859 u32 link_desc_counter0; 860 u32 link_desc_counter1; 861 u32 link_desc_counter2; 862 u32 link_desc_counter_sum; 863 }; 864 865 struct hal_reo_status { 866 struct hal_reo_status_header uniform_hdr; 867 u8 loop_cnt; 868 union { 869 struct hal_reo_status_queue_stats queue_stats; 870 struct hal_reo_status_flush_queue flush_queue; 871 struct hal_reo_status_flush_cache flush_cache; 872 struct hal_reo_status_unblock_cache unblock_cache; 873 struct hal_reo_status_flush_timeout_list timeout_list; 874 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 875 } u; 876 }; 877 878 /* HAL context to be used to access SRNG APIs (currently used by data path 879 * and transport (CE) modules) 880 */ 881 struct ath11k_hal { 882 /* HAL internal state for all SRNG rings. 883 */ 884 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 885 886 /* SRNG configuration table */ 887 struct hal_srng_config *srng_config; 888 889 /* Remote pointer memory for HW/FW updates */ 890 struct { 891 u32 *vaddr; 892 dma_addr_t paddr; 893 } rdp; 894 895 /* Shared memory for ring pointer updates from host to FW */ 896 struct { 897 u32 *vaddr; 898 dma_addr_t paddr; 899 } wrp; 900 901 /* Available REO blocking resources bitmap */ 902 u8 avail_blk_resource; 903 904 u8 current_blk_index; 905 906 /* shadow register configuration */ 907 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 908 int num_shadow_reg_configured; 909 910 struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX]; 911 }; 912 913 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 914 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 915 u32 start_seq, enum hal_pn_type type); 916 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 917 struct hal_srng *srng); 918 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 919 struct hal_wbm_idle_scatter_list *sbuf, 920 u32 nsbufs, u32 tot_link_desc, 921 u32 end_offset); 922 923 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 924 struct hal_srng *srng); 925 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 926 struct hal_srng *srng); 927 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 928 dma_addr_t paddr); 929 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 930 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 931 u8 byte_swap_data); 932 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 933 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 934 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type); 935 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type); 936 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 937 struct hal_srng_params *params); 938 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 939 struct hal_srng *srng); 940 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 941 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 942 bool sync_hw_ptr); 943 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 944 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 945 struct hal_srng *srng); 946 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 947 struct hal_srng *srng); 948 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 949 struct hal_srng *srng); 950 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 951 bool sync_hw_ptr); 952 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 953 struct hal_srng *srng); 954 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 955 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 956 int ring_num, int mac_id, 957 struct hal_srng_params *params); 958 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 959 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 960 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 961 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 962 u32 **cfg, u32 *len); 963 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 964 enum hal_ring_type ring_type, 965 int ring_num); 966 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab); 967 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, 968 struct hal_srng *srng); 969 #endif 970