1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HAL_H 7 #define ATH11K_HAL_H 8 9 #include "hal_desc.h" 10 #include "rx_desc.h" 11 12 struct ath11k_base; 13 14 #define HAL_LINK_DESC_SIZE (32 << 2) 15 #define HAL_LINK_DESC_ALIGN 128 16 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 20 #define HAL_MAX_AVAIL_BLK_RES 3 21 22 #define HAL_RING_BASE_ALIGN 8 23 24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 25 /* TODO: Check with hw team on the supported scatter buf size */ 26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 28 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 29 30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 31 #define HAL_DSCP_TID_TBL_SIZE 24 32 33 /* calculate the register address from bar0 of shadow register x */ 34 #define HAL_SHADOW_BASE_ADDR 0x000008fc 35 #define HAL_SHADOW_NUM_REGS 36 36 #define HAL_HP_OFFSET_IN_REG_START 1 37 #define HAL_OFFSET_FROM_HP_TO_TP 4 38 39 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 40 41 /* WCSS Relative address */ 42 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 43 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 44 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 45 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \ 46 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg) 47 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \ 48 (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg) 49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \ 50 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg) 51 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \ 52 (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg) 53 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 54 55 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 56 #define HAL_WLAON_REG_BASE 0x01f80000 57 58 /* SW2TCL(x) R0 ring configuration address */ 59 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 60 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 61 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb 62 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb 63 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id 64 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc 65 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 66 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb 67 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 68 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb 69 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 70 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0 71 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 72 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1 73 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 74 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb 75 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 76 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb 77 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 78 ab->hw_params.regs->hal_tcl1_ring_msi1_data 79 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb 80 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb 81 82 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 83 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 84 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 85 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 86 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \ 87 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 88 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) \ 89 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 90 #define HAL_TCL1_RING_ID_OFFSET(ab) \ 91 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 92 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \ 93 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 94 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \ 95 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 96 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \ 97 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 98 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \ 99 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 100 #define HAL_TCL1_RING_MISC_OFFSET(ab) \ 101 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 102 103 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 104 #define HAL_TCL1_RING_HP 0x00002000 105 #define HAL_TCL1_RING_TP 0x00002004 106 #define HAL_TCL2_RING_HP 0x00002008 107 #define HAL_TCL_RING_HP 0x00002018 108 109 #define HAL_TCL1_RING_TP_OFFSET \ 110 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 111 112 /* TCL STATUS ring address */ 113 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 114 ab->hw_params.regs->hal_tcl_status_ring_base_lsb 115 #define HAL_TCL_STATUS_RING_HP 0x00002030 116 117 /* REO2SW(x) R0 ring configuration address */ 118 #define HAL_REO1_GEN_ENABLE 0x00000000 119 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 120 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 121 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 122 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 123 #define HAL_REO1_MISC_CTL 0x00000630 124 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb 125 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb 126 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id 127 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc 128 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \ 129 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb 130 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \ 131 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb 132 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 133 ab->hw_params.regs->hal_reo1_ring_producer_int_setup 134 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 135 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb 136 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 137 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb 138 #define HAL_REO1_RING_MSI1_DATA(ab) \ 139 ab->hw_params.regs->hal_reo1_ring_msi1_data 140 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb 141 #define HAL_REO1_AGING_THRESH_IX_0(ab) \ 142 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0 143 #define HAL_REO1_AGING_THRESH_IX_1(ab) \ 144 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1 145 #define HAL_REO1_AGING_THRESH_IX_2(ab) \ 146 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2 147 #define HAL_REO1_AGING_THRESH_IX_3(ab) \ 148 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3 149 150 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 151 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 152 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 153 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 154 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \ 155 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab)) 156 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \ 157 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 158 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab)) 159 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \ 160 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab)) 161 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \ 162 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 163 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \ 164 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 165 #define HAL_REO1_RING_MISC_OFFSET(ab) \ 166 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab)) 167 168 /* REO2SW(x) R2 ring pointers (head/tail) address */ 169 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp 170 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp 171 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp 172 173 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)) 174 175 /* REO2TCL R0 ring configuration address */ 176 #define HAL_REO_TCL_RING_BASE_LSB(ab) \ 177 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb 178 179 /* REO2TCL R2 ring pointer (head/tail) address */ 180 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp 181 182 /* REO CMD R0 address */ 183 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 184 185 /* REO CMD R2 address */ 186 #define HAL_REO_CMD_HP 0x00003020 187 188 /* SW2REO R0 address */ 189 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec 190 191 /* SW2REO R2 address */ 192 #define HAL_SW2REO_RING_HP 0x00003028 193 194 /* CE ring R0 address */ 195 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 196 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 197 #define HAL_CE_DST_RING_CTRL 0x000000b0 198 199 /* CE ring R2 address */ 200 #define HAL_CE_DST_RING_HP 0x00000400 201 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 202 203 /* REO status address */ 204 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 205 ab->hw_params.regs->hal_reo_status_ring_base_lsb 206 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp 207 208 /* WBM Idle R0 address */ 209 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \ 210 (ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb) 211 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \ 212 (ab->hw_params.regs->hal_wbm_idle_link_ring_misc) 213 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 214 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 215 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 216 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 217 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 218 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 219 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 220 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 221 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 222 223 /* WBM Idle R2 address */ 224 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 225 226 /* SW2WBM R0 release address */ 227 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \ 228 (ab->hw_params.regs->hal_wbm_release_ring_base_lsb) 229 230 /* SW2WBM R2 release address */ 231 #define HAL_WBM_RELEASE_RING_HP 0x00003018 232 233 /* WBM2SW R0 release address */ 234 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \ 235 (ab->hw_params.regs->hal_wbm0_release_ring_base_lsb) 236 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \ 237 (ab->hw_params.regs->hal_wbm1_release_ring_base_lsb) 238 239 /* WBM2SW R2 release address */ 240 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 241 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 242 243 /* TCL ring feild mask and offset */ 244 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 245 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 246 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 247 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 248 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 249 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 250 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 251 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 252 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 253 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 254 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 255 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 256 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 257 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 258 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 259 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 260 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 264 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 265 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 266 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 267 268 /* REO ring feild mask and offset */ 269 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 270 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 271 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 272 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 273 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 274 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 275 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 276 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 277 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 278 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 279 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 280 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 281 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 282 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 283 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 284 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING GENMASK(20, 17) 285 286 /* CE ring bit field mask and shift */ 287 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 288 289 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 290 291 #define HAL_ADDR_MSB_REG_SHIFT 32 292 293 /* WBM ring bit field mask and shift */ 294 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 295 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 296 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 297 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 298 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 299 300 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 301 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 302 303 #define BASE_ADDR_MATCH_TAG_VAL 0x5 304 305 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 306 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 307 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 308 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 309 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 310 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 311 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 312 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 313 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 314 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 315 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 316 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 317 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 318 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 319 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 320 321 /* Add any other errors here and return them in 322 * ath11k_hal_rx_desc_get_err(). 323 */ 324 325 enum hal_srng_ring_id { 326 HAL_SRNG_RING_ID_REO2SW1 = 0, 327 HAL_SRNG_RING_ID_REO2SW2, 328 HAL_SRNG_RING_ID_REO2SW3, 329 HAL_SRNG_RING_ID_REO2SW4, 330 HAL_SRNG_RING_ID_REO2TCL, 331 HAL_SRNG_RING_ID_SW2REO, 332 333 HAL_SRNG_RING_ID_REO_CMD = 8, 334 HAL_SRNG_RING_ID_REO_STATUS, 335 336 HAL_SRNG_RING_ID_SW2TCL1 = 16, 337 HAL_SRNG_RING_ID_SW2TCL2, 338 HAL_SRNG_RING_ID_SW2TCL3, 339 HAL_SRNG_RING_ID_SW2TCL4, 340 341 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 342 HAL_SRNG_RING_ID_TCL_STATUS, 343 344 HAL_SRNG_RING_ID_CE0_SRC = 32, 345 HAL_SRNG_RING_ID_CE1_SRC, 346 HAL_SRNG_RING_ID_CE2_SRC, 347 HAL_SRNG_RING_ID_CE3_SRC, 348 HAL_SRNG_RING_ID_CE4_SRC, 349 HAL_SRNG_RING_ID_CE5_SRC, 350 HAL_SRNG_RING_ID_CE6_SRC, 351 HAL_SRNG_RING_ID_CE7_SRC, 352 HAL_SRNG_RING_ID_CE8_SRC, 353 HAL_SRNG_RING_ID_CE9_SRC, 354 HAL_SRNG_RING_ID_CE10_SRC, 355 HAL_SRNG_RING_ID_CE11_SRC, 356 357 HAL_SRNG_RING_ID_CE0_DST = 56, 358 HAL_SRNG_RING_ID_CE1_DST, 359 HAL_SRNG_RING_ID_CE2_DST, 360 HAL_SRNG_RING_ID_CE3_DST, 361 HAL_SRNG_RING_ID_CE4_DST, 362 HAL_SRNG_RING_ID_CE5_DST, 363 HAL_SRNG_RING_ID_CE6_DST, 364 HAL_SRNG_RING_ID_CE7_DST, 365 HAL_SRNG_RING_ID_CE8_DST, 366 HAL_SRNG_RING_ID_CE9_DST, 367 HAL_SRNG_RING_ID_CE10_DST, 368 HAL_SRNG_RING_ID_CE11_DST, 369 370 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 371 HAL_SRNG_RING_ID_CE1_DST_STATUS, 372 HAL_SRNG_RING_ID_CE2_DST_STATUS, 373 HAL_SRNG_RING_ID_CE3_DST_STATUS, 374 HAL_SRNG_RING_ID_CE4_DST_STATUS, 375 HAL_SRNG_RING_ID_CE5_DST_STATUS, 376 HAL_SRNG_RING_ID_CE6_DST_STATUS, 377 HAL_SRNG_RING_ID_CE7_DST_STATUS, 378 HAL_SRNG_RING_ID_CE8_DST_STATUS, 379 HAL_SRNG_RING_ID_CE9_DST_STATUS, 380 HAL_SRNG_RING_ID_CE10_DST_STATUS, 381 HAL_SRNG_RING_ID_CE11_DST_STATUS, 382 383 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 384 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 385 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 386 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 387 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 388 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 389 390 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 391 HAL_SRNG_RING_ID_LMAC1_ID_START, 392 393 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 394 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 395 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 396 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 397 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 398 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 399 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 400 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 401 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 402 403 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 404 }; 405 406 /* SRNG registers are split into two groups R0 and R2 */ 407 #define HAL_SRNG_REG_GRP_R0 0 408 #define HAL_SRNG_REG_GRP_R2 1 409 #define HAL_SRNG_NUM_REG_GRP 2 410 411 #define HAL_SRNG_NUM_LMACS 3 412 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 413 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 414 HAL_SRNG_RING_ID_LMAC1_ID_START) 415 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 416 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 417 HAL_SRNG_NUM_LMAC_RINGS) 418 419 enum hal_ring_type { 420 HAL_REO_DST, 421 HAL_REO_EXCEPTION, 422 HAL_REO_REINJECT, 423 HAL_REO_CMD, 424 HAL_REO_STATUS, 425 HAL_TCL_DATA, 426 HAL_TCL_CMD, 427 HAL_TCL_STATUS, 428 HAL_CE_SRC, 429 HAL_CE_DST, 430 HAL_CE_DST_STATUS, 431 HAL_WBM_IDLE_LINK, 432 HAL_SW2WBM_RELEASE, 433 HAL_WBM2SW_RELEASE, 434 HAL_RXDMA_BUF, 435 HAL_RXDMA_DST, 436 HAL_RXDMA_MONITOR_BUF, 437 HAL_RXDMA_MONITOR_STATUS, 438 HAL_RXDMA_MONITOR_DST, 439 HAL_RXDMA_MONITOR_DESC, 440 HAL_RXDMA_DIR_BUF, 441 HAL_MAX_RING_TYPES, 442 }; 443 444 #define HAL_RX_MAX_BA_WINDOW 256 445 446 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 447 448 /** 449 * enum hal_reo_cmd_type: Enum for REO command type 450 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 451 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 452 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 453 * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 454 * earlier with a 'REO_FLUSH_CACHE' command 455 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 456 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 457 */ 458 enum hal_reo_cmd_type { 459 HAL_REO_CMD_GET_QUEUE_STATS = 0, 460 HAL_REO_CMD_FLUSH_QUEUE = 1, 461 HAL_REO_CMD_FLUSH_CACHE = 2, 462 HAL_REO_CMD_UNBLOCK_CACHE = 3, 463 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 464 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 465 }; 466 467 /** 468 * enum hal_reo_cmd_status: Enum for execution status of REO command 469 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 470 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 471 * or cache was blocked 472 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 473 * invalid queue desc 474 * @HAL_REO_CMD_RESOURCE_BLOCKED: 475 * @HAL_REO_CMD_DRAIN: 476 */ 477 enum hal_reo_cmd_status { 478 HAL_REO_CMD_SUCCESS = 0, 479 HAL_REO_CMD_BLOCKED = 1, 480 HAL_REO_CMD_FAILED = 2, 481 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 482 HAL_REO_CMD_DRAIN = 0xff, 483 }; 484 485 struct hal_wbm_idle_scatter_list { 486 dma_addr_t paddr; 487 struct hal_wbm_link_desc *vaddr; 488 }; 489 490 struct hal_srng_params { 491 dma_addr_t ring_base_paddr; 492 u32 *ring_base_vaddr; 493 int num_entries; 494 u32 intr_batch_cntr_thres_entries; 495 u32 intr_timer_thres_us; 496 u32 flags; 497 u32 max_buffer_len; 498 u32 low_threshold; 499 dma_addr_t msi_addr; 500 u32 msi_data; 501 502 /* Add more params as needed */ 503 }; 504 505 enum hal_srng_dir { 506 HAL_SRNG_DIR_SRC, 507 HAL_SRNG_DIR_DST 508 }; 509 510 /* srng flags */ 511 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 512 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 513 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 514 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 515 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 516 #define HAL_SRNG_FLAGS_CACHED 0x20000000 517 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 518 519 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 520 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 521 522 /* Common SRNG ring structure for source and destination rings */ 523 struct hal_srng { 524 /* Unique SRNG ring ID */ 525 u8 ring_id; 526 527 /* Ring initialization done */ 528 u8 initialized; 529 530 /* Interrupt/MSI value assigned to this ring */ 531 int irq; 532 533 /* Physical base address of the ring */ 534 dma_addr_t ring_base_paddr; 535 536 /* Virtual base address of the ring */ 537 u32 *ring_base_vaddr; 538 539 /* Number of entries in ring */ 540 u32 num_entries; 541 542 /* Ring size */ 543 u32 ring_size; 544 545 /* Ring size mask */ 546 u32 ring_size_mask; 547 548 /* Size of ring entry */ 549 u32 entry_size; 550 551 /* Interrupt timer threshold - in micro seconds */ 552 u32 intr_timer_thres_us; 553 554 /* Interrupt batch counter threshold - in number of ring entries */ 555 u32 intr_batch_cntr_thres_entries; 556 557 /* MSI Address */ 558 dma_addr_t msi_addr; 559 560 /* MSI data */ 561 u32 msi_data; 562 563 /* Misc flags */ 564 u32 flags; 565 566 /* Lock for serializing ring index updates */ 567 spinlock_t lock; 568 569 /* Start offset of SRNG register groups for this ring 570 * TBD: See if this is required - register address can be derived 571 * from ring ID 572 */ 573 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 574 575 u64 timestamp; 576 577 /* Source or Destination ring */ 578 enum hal_srng_dir ring_dir; 579 580 union { 581 struct { 582 /* SW tail pointer */ 583 u32 tp; 584 585 /* Shadow head pointer location to be updated by HW */ 586 volatile u32 *hp_addr; 587 588 /* Cached head pointer */ 589 u32 cached_hp; 590 591 /* Tail pointer location to be updated by SW - This 592 * will be a register address and need not be 593 * accessed through SW structure 594 */ 595 u32 *tp_addr; 596 597 /* Current SW loop cnt */ 598 u32 loop_cnt; 599 600 /* max transfer size */ 601 u16 max_buffer_length; 602 603 /* head pointer at access end */ 604 u32 last_hp; 605 } dst_ring; 606 607 struct { 608 /* SW head pointer */ 609 u32 hp; 610 611 /* SW reap head pointer */ 612 u32 reap_hp; 613 614 /* Shadow tail pointer location to be updated by HW */ 615 u32 *tp_addr; 616 617 /* Cached tail pointer */ 618 u32 cached_tp; 619 620 /* Head pointer location to be updated by SW - This 621 * will be a register address and need not be accessed 622 * through SW structure 623 */ 624 u32 *hp_addr; 625 626 /* Low threshold - in number of ring entries */ 627 u32 low_threshold; 628 629 /* tail pointer at access end */ 630 u32 last_tp; 631 } src_ring; 632 } u; 633 }; 634 635 /* Interrupt mitigation - Batch threshold in terms of numer of frames */ 636 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 637 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 638 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 639 640 /* Interrupt mitigation - timer threshold in us */ 641 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 642 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 643 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 644 645 /* HW SRNG configuration table */ 646 struct hal_srng_config { 647 int start_ring_id; 648 u16 max_rings; 649 u16 entry_size; 650 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 651 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 652 u8 lmac_ring; 653 enum hal_srng_dir ring_dir; 654 u32 max_size; 655 }; 656 657 /** 658 * enum hal_rx_buf_return_buf_manager 659 * 660 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 661 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 662 * descriptor list. 663 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 664 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 665 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 666 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 667 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 668 */ 669 670 enum hal_rx_buf_return_buf_manager { 671 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 672 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 673 HAL_RX_BUF_RBM_FW_BM, 674 HAL_RX_BUF_RBM_SW0_BM, 675 HAL_RX_BUF_RBM_SW1_BM, 676 HAL_RX_BUF_RBM_SW2_BM, 677 HAL_RX_BUF_RBM_SW3_BM, 678 }; 679 680 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 681 682 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 683 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 684 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 685 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 686 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 687 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 688 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 689 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 690 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 691 692 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 693 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 694 #define HAL_REO_CMD_UPD0_VLD BIT(9) 695 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 696 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 697 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 698 #define HAL_REO_CMD_UPD0_AC BIT(13) 699 #define HAL_REO_CMD_UPD0_BAR BIT(14) 700 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 701 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 702 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 703 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 704 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 705 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 706 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 707 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 708 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 709 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 710 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 711 #define HAL_REO_CMD_UPD0_SSN BIT(26) 712 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 713 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 714 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 715 #define HAL_REO_CMD_UPD0_PN BIT(30) 716 717 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 718 #define HAL_REO_CMD_UPD1_VLD BIT(16) 719 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 720 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 721 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 722 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 723 #define HAL_REO_CMD_UPD1_BAR BIT(23) 724 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 725 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 726 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 727 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 728 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 729 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 730 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 731 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 732 733 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 734 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 735 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 736 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 737 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 738 739 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 740 741 struct ath11k_hal_reo_cmd { 742 u32 addr_lo; 743 u32 flag; 744 u32 upd0; 745 u32 upd1; 746 u32 upd2; 747 u32 pn[4]; 748 u16 rx_queue_num; 749 u16 min_rel; 750 u16 min_fwd; 751 u8 addr_hi; 752 u8 ac_list; 753 u8 blocking_idx; 754 u16 ba_window_size; 755 u8 pn_size; 756 }; 757 758 enum hal_pn_type { 759 HAL_PN_TYPE_NONE, 760 HAL_PN_TYPE_WPA, 761 HAL_PN_TYPE_WAPI_EVEN, 762 HAL_PN_TYPE_WAPI_UNEVEN, 763 }; 764 765 enum hal_ce_desc { 766 HAL_CE_DESC_SRC, 767 HAL_CE_DESC_DST, 768 HAL_CE_DESC_DST_STATUS, 769 }; 770 771 #define HAL_HASH_ROUTING_RING_TCL 0 772 #define HAL_HASH_ROUTING_RING_SW1 1 773 #define HAL_HASH_ROUTING_RING_SW2 2 774 #define HAL_HASH_ROUTING_RING_SW3 3 775 #define HAL_HASH_ROUTING_RING_SW4 4 776 #define HAL_HASH_ROUTING_RING_REL 5 777 #define HAL_HASH_ROUTING_RING_FW 6 778 779 struct hal_reo_status_header { 780 u16 cmd_num; 781 enum hal_reo_cmd_status cmd_status; 782 u16 cmd_exe_time; 783 u32 timestamp; 784 }; 785 786 struct hal_reo_status_queue_stats { 787 u16 ssn; 788 u16 curr_idx; 789 u32 pn[4]; 790 u32 last_rx_queue_ts; 791 u32 last_rx_dequeue_ts; 792 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 793 u32 curr_mpdu_cnt; 794 u32 curr_msdu_cnt; 795 u16 fwd_due_to_bar_cnt; 796 u16 dup_cnt; 797 u32 frames_in_order_cnt; 798 u32 num_mpdu_processed_cnt; 799 u32 num_msdu_processed_cnt; 800 u32 total_num_processed_byte_cnt; 801 u32 late_rx_mpdu_cnt; 802 u32 reorder_hole_cnt; 803 u8 timeout_cnt; 804 u8 bar_rx_cnt; 805 u8 num_window_2k_jump_cnt; 806 }; 807 808 struct hal_reo_status_flush_queue { 809 bool err_detected; 810 }; 811 812 enum hal_reo_status_flush_cache_err_code { 813 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 814 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 815 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 816 }; 817 818 struct hal_reo_status_flush_cache { 819 bool err_detected; 820 enum hal_reo_status_flush_cache_err_code err_code; 821 bool cache_controller_flush_status_hit; 822 u8 cache_controller_flush_status_desc_type; 823 u8 cache_controller_flush_status_client_id; 824 u8 cache_controller_flush_status_err; 825 u8 cache_controller_flush_status_cnt; 826 }; 827 828 enum hal_reo_status_unblock_cache_type { 829 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 830 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 831 }; 832 833 struct hal_reo_status_unblock_cache { 834 bool err_detected; 835 enum hal_reo_status_unblock_cache_type unblock_type; 836 }; 837 838 struct hal_reo_status_flush_timeout_list { 839 bool err_detected; 840 bool list_empty; 841 u16 release_desc_cnt; 842 u16 fwd_buf_cnt; 843 }; 844 845 enum hal_reo_threshold_idx { 846 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 847 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 848 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 849 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 850 }; 851 852 struct hal_reo_status_desc_thresh_reached { 853 enum hal_reo_threshold_idx threshold_idx; 854 u32 link_desc_counter0; 855 u32 link_desc_counter1; 856 u32 link_desc_counter2; 857 u32 link_desc_counter_sum; 858 }; 859 860 struct hal_reo_status { 861 struct hal_reo_status_header uniform_hdr; 862 u8 loop_cnt; 863 union { 864 struct hal_reo_status_queue_stats queue_stats; 865 struct hal_reo_status_flush_queue flush_queue; 866 struct hal_reo_status_flush_cache flush_cache; 867 struct hal_reo_status_unblock_cache unblock_cache; 868 struct hal_reo_status_flush_timeout_list timeout_list; 869 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 870 } u; 871 }; 872 873 /** 874 * HAL context to be used to access SRNG APIs (currently used by data path 875 * and transport (CE) modules) 876 */ 877 struct ath11k_hal { 878 /* HAL internal state for all SRNG rings. 879 */ 880 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 881 882 /* SRNG configuration table */ 883 struct hal_srng_config *srng_config; 884 885 /* Remote pointer memory for HW/FW updates */ 886 struct { 887 u32 *vaddr; 888 dma_addr_t paddr; 889 } rdp; 890 891 /* Shared memory for ring pointer updates from host to FW */ 892 struct { 893 u32 *vaddr; 894 dma_addr_t paddr; 895 } wrp; 896 897 /* Available REO blocking resources bitmap */ 898 u8 avail_blk_resource; 899 900 u8 current_blk_index; 901 902 /* shadow register configuration */ 903 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 904 int num_shadow_reg_configured; 905 906 struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX]; 907 }; 908 909 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 910 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 911 u32 start_seq, enum hal_pn_type type); 912 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 913 struct hal_srng *srng); 914 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 915 struct hal_wbm_idle_scatter_list *sbuf, 916 u32 nsbufs, u32 tot_link_desc, 917 u32 end_offset); 918 919 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 920 struct hal_srng *srng); 921 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 922 struct hal_srng *srng); 923 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 924 dma_addr_t paddr); 925 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 926 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 927 u8 byte_swap_data); 928 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 929 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 930 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type); 931 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type); 932 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 933 struct hal_srng_params *params); 934 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 935 struct hal_srng *srng); 936 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 937 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 938 bool sync_hw_ptr); 939 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 940 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 941 struct hal_srng *srng); 942 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 943 struct hal_srng *srng); 944 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 945 struct hal_srng *srng); 946 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 947 bool sync_hw_ptr); 948 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 949 struct hal_srng *srng); 950 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 951 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 952 int ring_num, int mac_id, 953 struct hal_srng_params *params); 954 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 955 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 956 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 957 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 958 u32 **cfg, u32 *len); 959 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 960 enum hal_ring_type ring_type, 961 int ring_num); 962 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab); 963 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, 964 struct hal_srng *srng); 965 #endif 966