1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HAL_H 7 #define ATH11K_HAL_H 8 9 #include "hal_desc.h" 10 #include "rx_desc.h" 11 12 struct ath11k_base; 13 14 #define HAL_LINK_DESC_SIZE (32 << 2) 15 #define HAL_LINK_DESC_ALIGN 128 16 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 20 #define HAL_MAX_AVAIL_BLK_RES 3 21 22 #define HAL_RING_BASE_ALIGN 8 23 24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 25 /* TODO: Check with hw team on the supported scatter buf size */ 26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 28 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 29 30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 31 #define HAL_DSCP_TID_TBL_SIZE 24 32 33 /* calculate the register address from bar0 of shadow register x */ 34 #define SHADOW_BASE_ADDRESS 0x00003024 35 #define SHADOW_NUM_REGISTERS 36 36 37 /* WCSS Relative address */ 38 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 39 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 40 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 41 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000 42 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000 43 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 44 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 45 46 /* SW2TCL(x) R0 ring configuration address */ 47 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 48 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 49 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb 50 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb 51 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id 52 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc 53 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 54 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb 55 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 56 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb 57 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 58 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0 59 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 60 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1 61 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 62 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb 63 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 64 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb 65 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 66 ab->hw_params.regs->hal_tcl1_ring_msi1_data 67 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb 68 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb 69 70 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 71 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 72 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 73 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 74 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \ 75 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 76 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) \ 77 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 78 #define HAL_TCL1_RING_ID_OFFSET(ab) \ 79 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 80 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \ 81 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 82 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \ 83 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 84 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \ 85 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 86 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \ 87 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 88 #define HAL_TCL1_RING_MISC_OFFSET(ab) \ 89 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 90 91 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 92 #define HAL_TCL1_RING_HP 0x00002000 93 #define HAL_TCL1_RING_TP 0x00002004 94 #define HAL_TCL2_RING_HP 0x00002008 95 #define HAL_TCL_RING_HP 0x00002018 96 97 #define HAL_TCL1_RING_TP_OFFSET \ 98 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 99 100 /* TCL STATUS ring address */ 101 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 102 ab->hw_params.regs->hal_tcl_status_ring_base_lsb 103 #define HAL_TCL_STATUS_RING_HP 0x00002030 104 105 /* REO2SW(x) R0 ring configuration address */ 106 #define HAL_REO1_GEN_ENABLE 0x00000000 107 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 108 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 109 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 110 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 111 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb 112 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb 113 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id 114 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc 115 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \ 116 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb 117 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \ 118 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb 119 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 120 ab->hw_params.regs->hal_reo1_ring_producer_int_setup 121 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 122 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb 123 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 124 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb 125 #define HAL_REO1_RING_MSI1_DATA(ab) \ 126 ab->hw_params.regs->hal_reo1_ring_msi1_data 127 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb 128 #define HAL_REO1_AGING_THRESH_IX_0(ab) \ 129 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0 130 #define HAL_REO1_AGING_THRESH_IX_1(ab) \ 131 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1 132 #define HAL_REO1_AGING_THRESH_IX_2(ab) \ 133 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2 134 #define HAL_REO1_AGING_THRESH_IX_3(ab) \ 135 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3 136 137 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 138 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 139 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 140 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 141 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \ 142 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab)) 143 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \ 144 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 145 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab)) 146 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \ 147 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab)) 148 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \ 149 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 150 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \ 151 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 152 #define HAL_REO1_RING_MISC_OFFSET(ab) \ 153 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab)) 154 155 /* REO2SW(x) R2 ring pointers (head/tail) address */ 156 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp 157 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp 158 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp 159 160 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)) 161 162 /* REO2TCL R0 ring configuration address */ 163 #define HAL_REO_TCL_RING_BASE_LSB(ab) \ 164 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb 165 166 /* REO2TCL R2 ring pointer (head/tail) address */ 167 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp 168 169 /* REO CMD R0 address */ 170 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 171 172 /* REO CMD R2 address */ 173 #define HAL_REO_CMD_HP 0x00003020 174 175 /* SW2REO R0 address */ 176 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec 177 178 /* SW2REO R2 address */ 179 #define HAL_SW2REO_RING_HP 0x00003028 180 181 /* CE ring R0 address */ 182 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 183 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 184 #define HAL_CE_DST_RING_CTRL 0x000000b0 185 186 /* CE ring R2 address */ 187 #define HAL_CE_DST_RING_HP 0x00000400 188 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 189 190 /* REO status address */ 191 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 192 ab->hw_params.regs->hal_reo_status_ring_base_lsb 193 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp 194 195 /* WBM Idle R0 address */ 196 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860 197 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870 198 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 199 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 200 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 201 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 202 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 203 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 204 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 205 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 206 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 207 208 /* WBM Idle R2 address */ 209 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 210 211 /* SW2WBM R0 release address */ 212 #define HAL_WBM_RELEASE_RING_BASE_LSB 0x000001d8 213 214 /* SW2WBM R2 release address */ 215 #define HAL_WBM_RELEASE_RING_HP 0x00003018 216 217 /* WBM2SW R0 release address */ 218 #define HAL_WBM0_RELEASE_RING_BASE_LSB 0x00000910 219 #define HAL_WBM1_RELEASE_RING_BASE_LSB 0x00000968 220 221 /* WBM2SW R2 release address */ 222 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 223 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 224 225 /* TCL ring feild mask and offset */ 226 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 227 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 228 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 229 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 230 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 231 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 232 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 233 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 234 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 235 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 236 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 237 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 238 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 239 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 240 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 241 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 242 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 243 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 244 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 245 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 246 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 247 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 248 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 249 250 /* REO ring feild mask and offset */ 251 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 252 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 253 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 254 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 255 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 256 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 257 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 258 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 259 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 260 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 261 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 262 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 263 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 264 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 265 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 266 267 /* CE ring bit field mask and shift */ 268 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 269 270 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 271 272 #define HAL_ADDR_MSB_REG_SHIFT 32 273 274 /* WBM ring bit field mask and shift */ 275 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 276 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 277 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 278 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 279 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 280 281 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 282 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 283 284 #define BASE_ADDR_MATCH_TAG_VAL 0x5 285 286 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 287 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 288 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 289 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 290 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 291 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 292 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 293 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 294 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 295 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 296 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 297 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 298 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 299 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 300 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 301 302 #define HAL_RX_DESC_SIZE (sizeof(struct hal_rx_desc)) 303 304 /* Add any other errors here and return them in 305 * ath11k_hal_rx_desc_get_err(). 306 */ 307 308 enum hal_srng_ring_id { 309 HAL_SRNG_RING_ID_REO2SW1 = 0, 310 HAL_SRNG_RING_ID_REO2SW2, 311 HAL_SRNG_RING_ID_REO2SW3, 312 HAL_SRNG_RING_ID_REO2SW4, 313 HAL_SRNG_RING_ID_REO2TCL, 314 HAL_SRNG_RING_ID_SW2REO, 315 316 HAL_SRNG_RING_ID_REO_CMD = 8, 317 HAL_SRNG_RING_ID_REO_STATUS, 318 319 HAL_SRNG_RING_ID_SW2TCL1 = 16, 320 HAL_SRNG_RING_ID_SW2TCL2, 321 HAL_SRNG_RING_ID_SW2TCL3, 322 HAL_SRNG_RING_ID_SW2TCL4, 323 324 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 325 HAL_SRNG_RING_ID_TCL_STATUS, 326 327 HAL_SRNG_RING_ID_CE0_SRC = 32, 328 HAL_SRNG_RING_ID_CE1_SRC, 329 HAL_SRNG_RING_ID_CE2_SRC, 330 HAL_SRNG_RING_ID_CE3_SRC, 331 HAL_SRNG_RING_ID_CE4_SRC, 332 HAL_SRNG_RING_ID_CE5_SRC, 333 HAL_SRNG_RING_ID_CE6_SRC, 334 HAL_SRNG_RING_ID_CE7_SRC, 335 HAL_SRNG_RING_ID_CE8_SRC, 336 HAL_SRNG_RING_ID_CE9_SRC, 337 HAL_SRNG_RING_ID_CE10_SRC, 338 HAL_SRNG_RING_ID_CE11_SRC, 339 340 HAL_SRNG_RING_ID_CE0_DST = 56, 341 HAL_SRNG_RING_ID_CE1_DST, 342 HAL_SRNG_RING_ID_CE2_DST, 343 HAL_SRNG_RING_ID_CE3_DST, 344 HAL_SRNG_RING_ID_CE4_DST, 345 HAL_SRNG_RING_ID_CE5_DST, 346 HAL_SRNG_RING_ID_CE6_DST, 347 HAL_SRNG_RING_ID_CE7_DST, 348 HAL_SRNG_RING_ID_CE8_DST, 349 HAL_SRNG_RING_ID_CE9_DST, 350 HAL_SRNG_RING_ID_CE10_DST, 351 HAL_SRNG_RING_ID_CE11_DST, 352 353 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 354 HAL_SRNG_RING_ID_CE1_DST_STATUS, 355 HAL_SRNG_RING_ID_CE2_DST_STATUS, 356 HAL_SRNG_RING_ID_CE3_DST_STATUS, 357 HAL_SRNG_RING_ID_CE4_DST_STATUS, 358 HAL_SRNG_RING_ID_CE5_DST_STATUS, 359 HAL_SRNG_RING_ID_CE6_DST_STATUS, 360 HAL_SRNG_RING_ID_CE7_DST_STATUS, 361 HAL_SRNG_RING_ID_CE8_DST_STATUS, 362 HAL_SRNG_RING_ID_CE9_DST_STATUS, 363 HAL_SRNG_RING_ID_CE10_DST_STATUS, 364 HAL_SRNG_RING_ID_CE11_DST_STATUS, 365 366 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 367 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 368 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 369 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 370 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 371 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 372 373 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 374 HAL_SRNG_RING_ID_LMAC1_ID_START, 375 376 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 377 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 378 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 379 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 380 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 381 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 382 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 383 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 384 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 385 386 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 387 }; 388 389 /* SRNG registers are split into two groups R0 and R2 */ 390 #define HAL_SRNG_REG_GRP_R0 0 391 #define HAL_SRNG_REG_GRP_R2 1 392 #define HAL_SRNG_NUM_REG_GRP 2 393 394 #define HAL_SRNG_NUM_LMACS 3 395 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 396 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 397 HAL_SRNG_RING_ID_LMAC1_ID_START) 398 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 399 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 400 HAL_SRNG_NUM_LMAC_RINGS) 401 402 enum hal_ring_type { 403 HAL_REO_DST, 404 HAL_REO_EXCEPTION, 405 HAL_REO_REINJECT, 406 HAL_REO_CMD, 407 HAL_REO_STATUS, 408 HAL_TCL_DATA, 409 HAL_TCL_CMD, 410 HAL_TCL_STATUS, 411 HAL_CE_SRC, 412 HAL_CE_DST, 413 HAL_CE_DST_STATUS, 414 HAL_WBM_IDLE_LINK, 415 HAL_SW2WBM_RELEASE, 416 HAL_WBM2SW_RELEASE, 417 HAL_RXDMA_BUF, 418 HAL_RXDMA_DST, 419 HAL_RXDMA_MONITOR_BUF, 420 HAL_RXDMA_MONITOR_STATUS, 421 HAL_RXDMA_MONITOR_DST, 422 HAL_RXDMA_MONITOR_DESC, 423 HAL_RXDMA_DIR_BUF, 424 HAL_MAX_RING_TYPES, 425 }; 426 427 #define HAL_RX_MAX_BA_WINDOW 256 428 429 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 430 431 /** 432 * enum hal_reo_cmd_type: Enum for REO command type 433 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 434 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 435 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 436 * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 437 * earlier with a 'REO_FLUSH_CACHE' command 438 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 439 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 440 */ 441 enum hal_reo_cmd_type { 442 HAL_REO_CMD_GET_QUEUE_STATS = 0, 443 HAL_REO_CMD_FLUSH_QUEUE = 1, 444 HAL_REO_CMD_FLUSH_CACHE = 2, 445 HAL_REO_CMD_UNBLOCK_CACHE = 3, 446 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 447 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 448 }; 449 450 /** 451 * enum hal_reo_cmd_status: Enum for execution status of REO command 452 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 453 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 454 * or cache was blocked 455 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 456 * invalid queue desc 457 * @HAL_REO_CMD_RESOURCE_BLOCKED: 458 * @HAL_REO_CMD_DRAIN: 459 */ 460 enum hal_reo_cmd_status { 461 HAL_REO_CMD_SUCCESS = 0, 462 HAL_REO_CMD_BLOCKED = 1, 463 HAL_REO_CMD_FAILED = 2, 464 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 465 HAL_REO_CMD_DRAIN = 0xff, 466 }; 467 468 struct hal_wbm_idle_scatter_list { 469 dma_addr_t paddr; 470 struct hal_wbm_link_desc *vaddr; 471 }; 472 473 struct hal_srng_params { 474 dma_addr_t ring_base_paddr; 475 u32 *ring_base_vaddr; 476 int num_entries; 477 u32 intr_batch_cntr_thres_entries; 478 u32 intr_timer_thres_us; 479 u32 flags; 480 u32 max_buffer_len; 481 u32 low_threshold; 482 dma_addr_t msi_addr; 483 u32 msi_data; 484 485 /* Add more params as needed */ 486 }; 487 488 enum hal_srng_dir { 489 HAL_SRNG_DIR_SRC, 490 HAL_SRNG_DIR_DST 491 }; 492 493 /* srng flags */ 494 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 495 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 496 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 497 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 498 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 499 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 500 501 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 502 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 503 504 /* Common SRNG ring structure for source and destination rings */ 505 struct hal_srng { 506 /* Unique SRNG ring ID */ 507 u8 ring_id; 508 509 /* Ring initialization done */ 510 u8 initialized; 511 512 /* Interrupt/MSI value assigned to this ring */ 513 int irq; 514 515 /* Physical base address of the ring */ 516 dma_addr_t ring_base_paddr; 517 518 /* Virtual base address of the ring */ 519 u32 *ring_base_vaddr; 520 521 /* Number of entries in ring */ 522 u32 num_entries; 523 524 /* Ring size */ 525 u32 ring_size; 526 527 /* Ring size mask */ 528 u32 ring_size_mask; 529 530 /* Size of ring entry */ 531 u32 entry_size; 532 533 /* Interrupt timer threshold - in micro seconds */ 534 u32 intr_timer_thres_us; 535 536 /* Interrupt batch counter threshold - in number of ring entries */ 537 u32 intr_batch_cntr_thres_entries; 538 539 /* MSI Address */ 540 dma_addr_t msi_addr; 541 542 /* MSI data */ 543 u32 msi_data; 544 545 /* Misc flags */ 546 u32 flags; 547 548 /* Lock for serializing ring index updates */ 549 spinlock_t lock; 550 551 /* Start offset of SRNG register groups for this ring 552 * TBD: See if this is required - register address can be derived 553 * from ring ID 554 */ 555 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 556 557 u64 timestamp; 558 559 /* Source or Destination ring */ 560 enum hal_srng_dir ring_dir; 561 562 union { 563 struct { 564 /* SW tail pointer */ 565 u32 tp; 566 567 /* Shadow head pointer location to be updated by HW */ 568 volatile u32 *hp_addr; 569 570 /* Cached head pointer */ 571 u32 cached_hp; 572 573 /* Tail pointer location to be updated by SW - This 574 * will be a register address and need not be 575 * accessed through SW structure 576 */ 577 u32 *tp_addr; 578 579 /* Current SW loop cnt */ 580 u32 loop_cnt; 581 582 /* max transfer size */ 583 u16 max_buffer_length; 584 585 /* head pointer at access end */ 586 u32 last_hp; 587 } dst_ring; 588 589 struct { 590 /* SW head pointer */ 591 u32 hp; 592 593 /* SW reap head pointer */ 594 u32 reap_hp; 595 596 /* Shadow tail pointer location to be updated by HW */ 597 u32 *tp_addr; 598 599 /* Cached tail pointer */ 600 u32 cached_tp; 601 602 /* Head pointer location to be updated by SW - This 603 * will be a register address and need not be accessed 604 * through SW structure 605 */ 606 u32 *hp_addr; 607 608 /* Low threshold - in number of ring entries */ 609 u32 low_threshold; 610 611 /* tail pointer at access end */ 612 u32 last_tp; 613 } src_ring; 614 } u; 615 }; 616 617 /* Interrupt mitigation - Batch threshold in terms of numer of frames */ 618 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 619 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 620 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 621 622 /* Interrupt mitigation - timer threshold in us */ 623 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 624 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 625 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 626 627 /* HW SRNG configuration table */ 628 struct hal_srng_config { 629 int start_ring_id; 630 u16 max_rings; 631 u16 entry_size; 632 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 633 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 634 u8 lmac_ring; 635 enum hal_srng_dir ring_dir; 636 u32 max_size; 637 }; 638 639 /** 640 * enum hal_rx_buf_return_buf_manager 641 * 642 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 643 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 644 * descriptor list. 645 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 646 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 647 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 648 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 649 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 650 */ 651 652 enum hal_rx_buf_return_buf_manager { 653 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 654 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 655 HAL_RX_BUF_RBM_FW_BM, 656 HAL_RX_BUF_RBM_SW0_BM, 657 HAL_RX_BUF_RBM_SW1_BM, 658 HAL_RX_BUF_RBM_SW2_BM, 659 HAL_RX_BUF_RBM_SW3_BM, 660 }; 661 662 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 663 664 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 665 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 666 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 667 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 668 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 669 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 670 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 671 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 672 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 673 674 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 675 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 676 #define HAL_REO_CMD_UPD0_VLD BIT(9) 677 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 678 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 679 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 680 #define HAL_REO_CMD_UPD0_AC BIT(13) 681 #define HAL_REO_CMD_UPD0_BAR BIT(14) 682 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 683 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 684 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 685 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 686 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 687 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 688 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 689 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 690 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 691 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 692 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 693 #define HAL_REO_CMD_UPD0_SSN BIT(26) 694 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 695 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 696 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 697 #define HAL_REO_CMD_UPD0_PN BIT(30) 698 699 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 700 #define HAL_REO_CMD_UPD1_VLD BIT(16) 701 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 702 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 703 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 704 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 705 #define HAL_REO_CMD_UPD1_BAR BIT(23) 706 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 707 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 708 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 709 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 710 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 711 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 712 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 713 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 714 715 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 716 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 717 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 718 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 719 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 720 721 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 722 723 struct ath11k_hal_reo_cmd { 724 u32 addr_lo; 725 u32 flag; 726 u32 upd0; 727 u32 upd1; 728 u32 upd2; 729 u32 pn[4]; 730 u16 rx_queue_num; 731 u16 min_rel; 732 u16 min_fwd; 733 u8 addr_hi; 734 u8 ac_list; 735 u8 blocking_idx; 736 u16 ba_window_size; 737 u8 pn_size; 738 }; 739 740 enum hal_pn_type { 741 HAL_PN_TYPE_NONE, 742 HAL_PN_TYPE_WPA, 743 HAL_PN_TYPE_WAPI_EVEN, 744 HAL_PN_TYPE_WAPI_UNEVEN, 745 }; 746 747 enum hal_ce_desc { 748 HAL_CE_DESC_SRC, 749 HAL_CE_DESC_DST, 750 HAL_CE_DESC_DST_STATUS, 751 }; 752 753 #define HAL_HASH_ROUTING_RING_TCL 0 754 #define HAL_HASH_ROUTING_RING_SW1 1 755 #define HAL_HASH_ROUTING_RING_SW2 2 756 #define HAL_HASH_ROUTING_RING_SW3 3 757 #define HAL_HASH_ROUTING_RING_SW4 4 758 #define HAL_HASH_ROUTING_RING_REL 5 759 #define HAL_HASH_ROUTING_RING_FW 6 760 761 struct hal_reo_status_header { 762 u16 cmd_num; 763 enum hal_reo_cmd_status cmd_status; 764 u16 cmd_exe_time; 765 u32 timestamp; 766 }; 767 768 struct hal_reo_status_queue_stats { 769 u16 ssn; 770 u16 curr_idx; 771 u32 pn[4]; 772 u32 last_rx_queue_ts; 773 u32 last_rx_dequeue_ts; 774 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 775 u32 curr_mpdu_cnt; 776 u32 curr_msdu_cnt; 777 u16 fwd_due_to_bar_cnt; 778 u16 dup_cnt; 779 u32 frames_in_order_cnt; 780 u32 num_mpdu_processed_cnt; 781 u32 num_msdu_processed_cnt; 782 u32 total_num_processed_byte_cnt; 783 u32 late_rx_mpdu_cnt; 784 u32 reorder_hole_cnt; 785 u8 timeout_cnt; 786 u8 bar_rx_cnt; 787 u8 num_window_2k_jump_cnt; 788 }; 789 790 struct hal_reo_status_flush_queue { 791 bool err_detected; 792 }; 793 794 enum hal_reo_status_flush_cache_err_code { 795 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 796 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 797 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 798 }; 799 800 struct hal_reo_status_flush_cache { 801 bool err_detected; 802 enum hal_reo_status_flush_cache_err_code err_code; 803 bool cache_controller_flush_status_hit; 804 u8 cache_controller_flush_status_desc_type; 805 u8 cache_controller_flush_status_client_id; 806 u8 cache_controller_flush_status_err; 807 u8 cache_controller_flush_status_cnt; 808 }; 809 810 enum hal_reo_status_unblock_cache_type { 811 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 812 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 813 }; 814 815 struct hal_reo_status_unblock_cache { 816 bool err_detected; 817 enum hal_reo_status_unblock_cache_type unblock_type; 818 }; 819 820 struct hal_reo_status_flush_timeout_list { 821 bool err_detected; 822 bool list_empty; 823 u16 release_desc_cnt; 824 u16 fwd_buf_cnt; 825 }; 826 827 enum hal_reo_threshold_idx { 828 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 829 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 830 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 831 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 832 }; 833 834 struct hal_reo_status_desc_thresh_reached { 835 enum hal_reo_threshold_idx threshold_idx; 836 u32 link_desc_counter0; 837 u32 link_desc_counter1; 838 u32 link_desc_counter2; 839 u32 link_desc_counter_sum; 840 }; 841 842 struct hal_reo_status { 843 struct hal_reo_status_header uniform_hdr; 844 u8 loop_cnt; 845 union { 846 struct hal_reo_status_queue_stats queue_stats; 847 struct hal_reo_status_flush_queue flush_queue; 848 struct hal_reo_status_flush_cache flush_cache; 849 struct hal_reo_status_unblock_cache unblock_cache; 850 struct hal_reo_status_flush_timeout_list timeout_list; 851 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 852 } u; 853 }; 854 855 /** 856 * HAL context to be used to access SRNG APIs (currently used by data path 857 * and transport (CE) modules) 858 */ 859 struct ath11k_hal { 860 /* HAL internal state for all SRNG rings. 861 */ 862 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 863 864 /* SRNG configuration table */ 865 struct hal_srng_config *srng_config; 866 867 /* Remote pointer memory for HW/FW updates */ 868 struct { 869 u32 *vaddr; 870 dma_addr_t paddr; 871 } rdp; 872 873 /* Shared memory for ring pointer updates from host to FW */ 874 struct { 875 u32 *vaddr; 876 dma_addr_t paddr; 877 } wrp; 878 879 /* Available REO blocking resources bitmap */ 880 u8 avail_blk_resource; 881 882 u8 current_blk_index; 883 884 /* shadow register configuration */ 885 u32 shadow_reg_addr[SHADOW_NUM_REGISTERS]; 886 int num_shadow_reg_configured; 887 }; 888 889 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 890 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 891 u32 start_seq, enum hal_pn_type type); 892 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 893 struct hal_srng *srng); 894 void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map); 895 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 896 struct hal_wbm_idle_scatter_list *sbuf, 897 u32 nsbufs, u32 tot_link_desc, 898 u32 end_offset); 899 900 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 901 struct hal_srng *srng); 902 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 903 struct hal_srng *srng); 904 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 905 dma_addr_t paddr); 906 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 907 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 908 u8 byte_swap_data); 909 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 910 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 911 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type); 912 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type); 913 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 914 struct hal_srng_params *params); 915 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 916 struct hal_srng *srng); 917 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 918 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 919 bool sync_hw_ptr); 920 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 921 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 922 struct hal_srng *srng); 923 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 924 struct hal_srng *srng); 925 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 926 struct hal_srng *srng); 927 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 928 bool sync_hw_ptr); 929 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 930 struct hal_srng *srng); 931 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 932 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 933 int ring_num, int mac_id, 934 struct hal_srng_params *params); 935 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 936 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 937 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 938 939 #endif 940