1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HAL_H 7 #define ATH11K_HAL_H 8 9 #include "hal_desc.h" 10 #include "rx_desc.h" 11 12 struct ath11k_base; 13 14 #define HAL_LINK_DESC_SIZE (32 << 2) 15 #define HAL_LINK_DESC_ALIGN 128 16 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 20 #define HAL_MAX_AVAIL_BLK_RES 3 21 22 #define HAL_RING_BASE_ALIGN 8 23 24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 25 /* TODO: Check with hw team on the supported scatter buf size */ 26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 28 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 29 30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 31 #define HAL_DSCP_TID_TBL_SIZE 24 32 33 /* calculate the register address from bar0 of shadow register x */ 34 #define HAL_SHADOW_BASE_ADDR 0x000008fc 35 #define HAL_SHADOW_NUM_REGS 36 36 #define HAL_HP_OFFSET_IN_REG_START 1 37 #define HAL_OFFSET_FROM_HP_TO_TP 4 38 39 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 40 41 /* WCSS Relative address */ 42 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 43 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 44 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 45 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000 46 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000 47 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 48 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 49 50 /* SW2TCL(x) R0 ring configuration address */ 51 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 52 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 53 #define HAL_TCL1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_lsb 54 #define HAL_TCL1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_tcl1_ring_base_msb 55 #define HAL_TCL1_RING_ID(ab) ab->hw_params.regs->hal_tcl1_ring_id 56 #define HAL_TCL1_RING_MISC(ab) ab->hw_params.regs->hal_tcl1_ring_misc 57 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \ 58 ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb 59 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \ 60 ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb 61 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \ 62 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0 63 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \ 64 ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1 65 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \ 66 ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb 67 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \ 68 ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb 69 #define HAL_TCL1_RING_MSI1_DATA(ab) \ 70 ab->hw_params.regs->hal_tcl1_ring_msi1_data 71 #define HAL_TCL2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl2_ring_base_lsb 72 #define HAL_TCL_RING_BASE_LSB(ab) ab->hw_params.regs->hal_tcl_ring_base_lsb 73 74 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 75 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 76 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 77 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 78 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \ 79 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 80 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab) \ 81 (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 82 #define HAL_TCL1_RING_ID_OFFSET(ab) \ 83 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 84 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \ 85 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 86 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \ 87 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 88 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \ 89 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 90 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \ 91 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 92 #define HAL_TCL1_RING_MISC_OFFSET(ab) \ 93 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab)) 94 95 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 96 #define HAL_TCL1_RING_HP 0x00002000 97 #define HAL_TCL1_RING_TP 0x00002004 98 #define HAL_TCL2_RING_HP 0x00002008 99 #define HAL_TCL_RING_HP 0x00002018 100 101 #define HAL_TCL1_RING_TP_OFFSET \ 102 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 103 104 /* TCL STATUS ring address */ 105 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ 106 ab->hw_params.regs->hal_tcl_status_ring_base_lsb 107 #define HAL_TCL_STATUS_RING_HP 0x00002030 108 109 /* REO2SW(x) R0 ring configuration address */ 110 #define HAL_REO1_GEN_ENABLE 0x00000000 111 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 112 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 113 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 114 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 115 #define HAL_REO1_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo1_ring_base_lsb 116 #define HAL_REO1_RING_BASE_MSB(ab) ab->hw_params.regs->hal_reo1_ring_base_msb 117 #define HAL_REO1_RING_ID(ab) ab->hw_params.regs->hal_reo1_ring_id 118 #define HAL_REO1_RING_MISC(ab) ab->hw_params.regs->hal_reo1_ring_misc 119 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \ 120 ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb 121 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \ 122 ab->hw_params.regs->hal_reo1_ring_hp_addr_msb 123 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \ 124 ab->hw_params.regs->hal_reo1_ring_producer_int_setup 125 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \ 126 ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb 127 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \ 128 ab->hw_params.regs->hal_reo1_ring_msi1_base_msb 129 #define HAL_REO1_RING_MSI1_DATA(ab) \ 130 ab->hw_params.regs->hal_reo1_ring_msi1_data 131 #define HAL_REO2_RING_BASE_LSB(ab) ab->hw_params.regs->hal_reo2_ring_base_lsb 132 #define HAL_REO1_AGING_THRESH_IX_0(ab) \ 133 ab->hw_params.regs->hal_reo1_aging_thresh_ix_0 134 #define HAL_REO1_AGING_THRESH_IX_1(ab) \ 135 ab->hw_params.regs->hal_reo1_aging_thresh_ix_1 136 #define HAL_REO1_AGING_THRESH_IX_2(ab) \ 137 ab->hw_params.regs->hal_reo1_aging_thresh_ix_2 138 #define HAL_REO1_AGING_THRESH_IX_3(ab) \ 139 ab->hw_params.regs->hal_reo1_aging_thresh_ix_3 140 141 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \ 142 (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 143 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \ 144 (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 145 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \ 146 (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab)) 147 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \ 148 (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 149 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab)) 150 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \ 151 (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab)) 152 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \ 153 (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 154 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \ 155 (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) 156 #define HAL_REO1_RING_MISC_OFFSET(ab) \ 157 (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab)) 158 159 /* REO2SW(x) R2 ring pointers (head/tail) address */ 160 #define HAL_REO1_RING_HP(ab) ab->hw_params.regs->hal_reo1_ring_hp 161 #define HAL_REO1_RING_TP(ab) ab->hw_params.regs->hal_reo1_ring_tp 162 #define HAL_REO2_RING_HP(ab) ab->hw_params.regs->hal_reo2_ring_hp 163 164 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab)) 165 166 /* REO2TCL R0 ring configuration address */ 167 #define HAL_REO_TCL_RING_BASE_LSB(ab) \ 168 ab->hw_params.regs->hal_reo_tcl_ring_base_lsb 169 170 /* REO2TCL R2 ring pointer (head/tail) address */ 171 #define HAL_REO_TCL_RING_HP(ab) ab->hw_params.regs->hal_reo_tcl_ring_hp 172 173 /* REO CMD R0 address */ 174 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 175 176 /* REO CMD R2 address */ 177 #define HAL_REO_CMD_HP 0x00003020 178 179 /* SW2REO R0 address */ 180 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec 181 182 /* SW2REO R2 address */ 183 #define HAL_SW2REO_RING_HP 0x00003028 184 185 /* CE ring R0 address */ 186 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 187 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 188 #define HAL_CE_DST_RING_CTRL 0x000000b0 189 190 /* CE ring R2 address */ 191 #define HAL_CE_DST_RING_HP 0x00000400 192 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 193 194 /* REO status address */ 195 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \ 196 ab->hw_params.regs->hal_reo_status_ring_base_lsb 197 #define HAL_REO_STATUS_HP(ab) ab->hw_params.regs->hal_reo_status_hp 198 199 /* WBM Idle R0 address */ 200 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860 201 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870 202 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 203 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 204 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 205 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 206 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 207 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 208 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 209 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 210 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 211 212 /* WBM Idle R2 address */ 213 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 214 215 /* SW2WBM R0 release address */ 216 #define HAL_WBM_RELEASE_RING_BASE_LSB 0x000001d8 217 218 /* SW2WBM R2 release address */ 219 #define HAL_WBM_RELEASE_RING_HP 0x00003018 220 221 /* WBM2SW R0 release address */ 222 #define HAL_WBM0_RELEASE_RING_BASE_LSB 0x00000910 223 #define HAL_WBM1_RELEASE_RING_BASE_LSB 0x00000968 224 225 /* WBM2SW R2 release address */ 226 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 227 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 228 229 /* TCL ring feild mask and offset */ 230 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 231 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 232 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 233 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 234 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 235 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 236 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 237 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 238 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 239 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 240 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 241 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 242 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 243 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 244 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 245 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 246 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 247 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 248 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 249 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 250 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 251 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 252 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 253 254 /* REO ring feild mask and offset */ 255 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 256 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 257 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 258 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 259 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 260 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 261 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 262 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 263 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 264 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 265 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 266 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 267 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 268 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 269 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 270 271 /* CE ring bit field mask and shift */ 272 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 273 274 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 275 276 #define HAL_ADDR_MSB_REG_SHIFT 32 277 278 /* WBM ring bit field mask and shift */ 279 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 280 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 281 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 282 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 283 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 284 285 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 286 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 287 288 #define BASE_ADDR_MATCH_TAG_VAL 0x5 289 290 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 291 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 292 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 293 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 294 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 295 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 296 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 297 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 298 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 299 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 300 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 301 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 302 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 303 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 304 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 305 306 #define HAL_RX_DESC_SIZE (sizeof(struct hal_rx_desc)) 307 308 /* Add any other errors here and return them in 309 * ath11k_hal_rx_desc_get_err(). 310 */ 311 312 enum hal_srng_ring_id { 313 HAL_SRNG_RING_ID_REO2SW1 = 0, 314 HAL_SRNG_RING_ID_REO2SW2, 315 HAL_SRNG_RING_ID_REO2SW3, 316 HAL_SRNG_RING_ID_REO2SW4, 317 HAL_SRNG_RING_ID_REO2TCL, 318 HAL_SRNG_RING_ID_SW2REO, 319 320 HAL_SRNG_RING_ID_REO_CMD = 8, 321 HAL_SRNG_RING_ID_REO_STATUS, 322 323 HAL_SRNG_RING_ID_SW2TCL1 = 16, 324 HAL_SRNG_RING_ID_SW2TCL2, 325 HAL_SRNG_RING_ID_SW2TCL3, 326 HAL_SRNG_RING_ID_SW2TCL4, 327 328 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 329 HAL_SRNG_RING_ID_TCL_STATUS, 330 331 HAL_SRNG_RING_ID_CE0_SRC = 32, 332 HAL_SRNG_RING_ID_CE1_SRC, 333 HAL_SRNG_RING_ID_CE2_SRC, 334 HAL_SRNG_RING_ID_CE3_SRC, 335 HAL_SRNG_RING_ID_CE4_SRC, 336 HAL_SRNG_RING_ID_CE5_SRC, 337 HAL_SRNG_RING_ID_CE6_SRC, 338 HAL_SRNG_RING_ID_CE7_SRC, 339 HAL_SRNG_RING_ID_CE8_SRC, 340 HAL_SRNG_RING_ID_CE9_SRC, 341 HAL_SRNG_RING_ID_CE10_SRC, 342 HAL_SRNG_RING_ID_CE11_SRC, 343 344 HAL_SRNG_RING_ID_CE0_DST = 56, 345 HAL_SRNG_RING_ID_CE1_DST, 346 HAL_SRNG_RING_ID_CE2_DST, 347 HAL_SRNG_RING_ID_CE3_DST, 348 HAL_SRNG_RING_ID_CE4_DST, 349 HAL_SRNG_RING_ID_CE5_DST, 350 HAL_SRNG_RING_ID_CE6_DST, 351 HAL_SRNG_RING_ID_CE7_DST, 352 HAL_SRNG_RING_ID_CE8_DST, 353 HAL_SRNG_RING_ID_CE9_DST, 354 HAL_SRNG_RING_ID_CE10_DST, 355 HAL_SRNG_RING_ID_CE11_DST, 356 357 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 358 HAL_SRNG_RING_ID_CE1_DST_STATUS, 359 HAL_SRNG_RING_ID_CE2_DST_STATUS, 360 HAL_SRNG_RING_ID_CE3_DST_STATUS, 361 HAL_SRNG_RING_ID_CE4_DST_STATUS, 362 HAL_SRNG_RING_ID_CE5_DST_STATUS, 363 HAL_SRNG_RING_ID_CE6_DST_STATUS, 364 HAL_SRNG_RING_ID_CE7_DST_STATUS, 365 HAL_SRNG_RING_ID_CE8_DST_STATUS, 366 HAL_SRNG_RING_ID_CE9_DST_STATUS, 367 HAL_SRNG_RING_ID_CE10_DST_STATUS, 368 HAL_SRNG_RING_ID_CE11_DST_STATUS, 369 370 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 371 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 372 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 373 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 374 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 375 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 376 377 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 378 HAL_SRNG_RING_ID_LMAC1_ID_START, 379 380 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 381 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 382 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 383 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 384 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 385 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 386 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 387 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 388 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 389 390 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 391 }; 392 393 /* SRNG registers are split into two groups R0 and R2 */ 394 #define HAL_SRNG_REG_GRP_R0 0 395 #define HAL_SRNG_REG_GRP_R2 1 396 #define HAL_SRNG_NUM_REG_GRP 2 397 398 #define HAL_SRNG_NUM_LMACS 3 399 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 400 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 401 HAL_SRNG_RING_ID_LMAC1_ID_START) 402 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 403 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 404 HAL_SRNG_NUM_LMAC_RINGS) 405 406 enum hal_ring_type { 407 HAL_REO_DST, 408 HAL_REO_EXCEPTION, 409 HAL_REO_REINJECT, 410 HAL_REO_CMD, 411 HAL_REO_STATUS, 412 HAL_TCL_DATA, 413 HAL_TCL_CMD, 414 HAL_TCL_STATUS, 415 HAL_CE_SRC, 416 HAL_CE_DST, 417 HAL_CE_DST_STATUS, 418 HAL_WBM_IDLE_LINK, 419 HAL_SW2WBM_RELEASE, 420 HAL_WBM2SW_RELEASE, 421 HAL_RXDMA_BUF, 422 HAL_RXDMA_DST, 423 HAL_RXDMA_MONITOR_BUF, 424 HAL_RXDMA_MONITOR_STATUS, 425 HAL_RXDMA_MONITOR_DST, 426 HAL_RXDMA_MONITOR_DESC, 427 HAL_RXDMA_DIR_BUF, 428 HAL_MAX_RING_TYPES, 429 }; 430 431 #define HAL_RX_MAX_BA_WINDOW 256 432 433 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 434 435 /** 436 * enum hal_reo_cmd_type: Enum for REO command type 437 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 438 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 439 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 440 * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 441 * earlier with a 'REO_FLUSH_CACHE' command 442 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 443 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 444 */ 445 enum hal_reo_cmd_type { 446 HAL_REO_CMD_GET_QUEUE_STATS = 0, 447 HAL_REO_CMD_FLUSH_QUEUE = 1, 448 HAL_REO_CMD_FLUSH_CACHE = 2, 449 HAL_REO_CMD_UNBLOCK_CACHE = 3, 450 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 451 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 452 }; 453 454 /** 455 * enum hal_reo_cmd_status: Enum for execution status of REO command 456 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 457 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 458 * or cache was blocked 459 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 460 * invalid queue desc 461 * @HAL_REO_CMD_RESOURCE_BLOCKED: 462 * @HAL_REO_CMD_DRAIN: 463 */ 464 enum hal_reo_cmd_status { 465 HAL_REO_CMD_SUCCESS = 0, 466 HAL_REO_CMD_BLOCKED = 1, 467 HAL_REO_CMD_FAILED = 2, 468 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 469 HAL_REO_CMD_DRAIN = 0xff, 470 }; 471 472 struct hal_wbm_idle_scatter_list { 473 dma_addr_t paddr; 474 struct hal_wbm_link_desc *vaddr; 475 }; 476 477 struct hal_srng_params { 478 dma_addr_t ring_base_paddr; 479 u32 *ring_base_vaddr; 480 int num_entries; 481 u32 intr_batch_cntr_thres_entries; 482 u32 intr_timer_thres_us; 483 u32 flags; 484 u32 max_buffer_len; 485 u32 low_threshold; 486 dma_addr_t msi_addr; 487 u32 msi_data; 488 489 /* Add more params as needed */ 490 }; 491 492 enum hal_srng_dir { 493 HAL_SRNG_DIR_SRC, 494 HAL_SRNG_DIR_DST 495 }; 496 497 /* srng flags */ 498 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 499 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 500 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 501 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 502 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 503 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 504 505 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 506 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 507 508 /* Common SRNG ring structure for source and destination rings */ 509 struct hal_srng { 510 /* Unique SRNG ring ID */ 511 u8 ring_id; 512 513 /* Ring initialization done */ 514 u8 initialized; 515 516 /* Interrupt/MSI value assigned to this ring */ 517 int irq; 518 519 /* Physical base address of the ring */ 520 dma_addr_t ring_base_paddr; 521 522 /* Virtual base address of the ring */ 523 u32 *ring_base_vaddr; 524 525 /* Number of entries in ring */ 526 u32 num_entries; 527 528 /* Ring size */ 529 u32 ring_size; 530 531 /* Ring size mask */ 532 u32 ring_size_mask; 533 534 /* Size of ring entry */ 535 u32 entry_size; 536 537 /* Interrupt timer threshold - in micro seconds */ 538 u32 intr_timer_thres_us; 539 540 /* Interrupt batch counter threshold - in number of ring entries */ 541 u32 intr_batch_cntr_thres_entries; 542 543 /* MSI Address */ 544 dma_addr_t msi_addr; 545 546 /* MSI data */ 547 u32 msi_data; 548 549 /* Misc flags */ 550 u32 flags; 551 552 /* Lock for serializing ring index updates */ 553 spinlock_t lock; 554 555 /* Start offset of SRNG register groups for this ring 556 * TBD: See if this is required - register address can be derived 557 * from ring ID 558 */ 559 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 560 561 u64 timestamp; 562 563 /* Source or Destination ring */ 564 enum hal_srng_dir ring_dir; 565 566 union { 567 struct { 568 /* SW tail pointer */ 569 u32 tp; 570 571 /* Shadow head pointer location to be updated by HW */ 572 volatile u32 *hp_addr; 573 574 /* Cached head pointer */ 575 u32 cached_hp; 576 577 /* Tail pointer location to be updated by SW - This 578 * will be a register address and need not be 579 * accessed through SW structure 580 */ 581 u32 *tp_addr; 582 583 /* Current SW loop cnt */ 584 u32 loop_cnt; 585 586 /* max transfer size */ 587 u16 max_buffer_length; 588 589 /* head pointer at access end */ 590 u32 last_hp; 591 } dst_ring; 592 593 struct { 594 /* SW head pointer */ 595 u32 hp; 596 597 /* SW reap head pointer */ 598 u32 reap_hp; 599 600 /* Shadow tail pointer location to be updated by HW */ 601 u32 *tp_addr; 602 603 /* Cached tail pointer */ 604 u32 cached_tp; 605 606 /* Head pointer location to be updated by SW - This 607 * will be a register address and need not be accessed 608 * through SW structure 609 */ 610 u32 *hp_addr; 611 612 /* Low threshold - in number of ring entries */ 613 u32 low_threshold; 614 615 /* tail pointer at access end */ 616 u32 last_tp; 617 } src_ring; 618 } u; 619 }; 620 621 /* Interrupt mitigation - Batch threshold in terms of numer of frames */ 622 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 623 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 624 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 625 626 /* Interrupt mitigation - timer threshold in us */ 627 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 628 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 629 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 630 631 /* HW SRNG configuration table */ 632 struct hal_srng_config { 633 int start_ring_id; 634 u16 max_rings; 635 u16 entry_size; 636 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 637 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 638 u8 lmac_ring; 639 enum hal_srng_dir ring_dir; 640 u32 max_size; 641 }; 642 643 /** 644 * enum hal_rx_buf_return_buf_manager 645 * 646 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 647 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 648 * descriptor list. 649 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 650 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 651 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 652 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 653 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 654 */ 655 656 enum hal_rx_buf_return_buf_manager { 657 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 658 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 659 HAL_RX_BUF_RBM_FW_BM, 660 HAL_RX_BUF_RBM_SW0_BM, 661 HAL_RX_BUF_RBM_SW1_BM, 662 HAL_RX_BUF_RBM_SW2_BM, 663 HAL_RX_BUF_RBM_SW3_BM, 664 }; 665 666 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 667 668 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 669 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 670 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 671 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 672 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 673 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 674 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 675 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 676 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 677 678 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 679 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 680 #define HAL_REO_CMD_UPD0_VLD BIT(9) 681 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 682 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 683 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 684 #define HAL_REO_CMD_UPD0_AC BIT(13) 685 #define HAL_REO_CMD_UPD0_BAR BIT(14) 686 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 687 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 688 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 689 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 690 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 691 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 692 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 693 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 694 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 695 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 696 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 697 #define HAL_REO_CMD_UPD0_SSN BIT(26) 698 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 699 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 700 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 701 #define HAL_REO_CMD_UPD0_PN BIT(30) 702 703 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 704 #define HAL_REO_CMD_UPD1_VLD BIT(16) 705 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 706 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 707 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 708 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 709 #define HAL_REO_CMD_UPD1_BAR BIT(23) 710 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 711 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 712 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 713 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 714 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 715 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 716 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 717 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 718 719 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 720 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 721 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 722 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 723 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 724 725 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 726 727 struct ath11k_hal_reo_cmd { 728 u32 addr_lo; 729 u32 flag; 730 u32 upd0; 731 u32 upd1; 732 u32 upd2; 733 u32 pn[4]; 734 u16 rx_queue_num; 735 u16 min_rel; 736 u16 min_fwd; 737 u8 addr_hi; 738 u8 ac_list; 739 u8 blocking_idx; 740 u16 ba_window_size; 741 u8 pn_size; 742 }; 743 744 enum hal_pn_type { 745 HAL_PN_TYPE_NONE, 746 HAL_PN_TYPE_WPA, 747 HAL_PN_TYPE_WAPI_EVEN, 748 HAL_PN_TYPE_WAPI_UNEVEN, 749 }; 750 751 enum hal_ce_desc { 752 HAL_CE_DESC_SRC, 753 HAL_CE_DESC_DST, 754 HAL_CE_DESC_DST_STATUS, 755 }; 756 757 #define HAL_HASH_ROUTING_RING_TCL 0 758 #define HAL_HASH_ROUTING_RING_SW1 1 759 #define HAL_HASH_ROUTING_RING_SW2 2 760 #define HAL_HASH_ROUTING_RING_SW3 3 761 #define HAL_HASH_ROUTING_RING_SW4 4 762 #define HAL_HASH_ROUTING_RING_REL 5 763 #define HAL_HASH_ROUTING_RING_FW 6 764 765 struct hal_reo_status_header { 766 u16 cmd_num; 767 enum hal_reo_cmd_status cmd_status; 768 u16 cmd_exe_time; 769 u32 timestamp; 770 }; 771 772 struct hal_reo_status_queue_stats { 773 u16 ssn; 774 u16 curr_idx; 775 u32 pn[4]; 776 u32 last_rx_queue_ts; 777 u32 last_rx_dequeue_ts; 778 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 779 u32 curr_mpdu_cnt; 780 u32 curr_msdu_cnt; 781 u16 fwd_due_to_bar_cnt; 782 u16 dup_cnt; 783 u32 frames_in_order_cnt; 784 u32 num_mpdu_processed_cnt; 785 u32 num_msdu_processed_cnt; 786 u32 total_num_processed_byte_cnt; 787 u32 late_rx_mpdu_cnt; 788 u32 reorder_hole_cnt; 789 u8 timeout_cnt; 790 u8 bar_rx_cnt; 791 u8 num_window_2k_jump_cnt; 792 }; 793 794 struct hal_reo_status_flush_queue { 795 bool err_detected; 796 }; 797 798 enum hal_reo_status_flush_cache_err_code { 799 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 800 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 801 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 802 }; 803 804 struct hal_reo_status_flush_cache { 805 bool err_detected; 806 enum hal_reo_status_flush_cache_err_code err_code; 807 bool cache_controller_flush_status_hit; 808 u8 cache_controller_flush_status_desc_type; 809 u8 cache_controller_flush_status_client_id; 810 u8 cache_controller_flush_status_err; 811 u8 cache_controller_flush_status_cnt; 812 }; 813 814 enum hal_reo_status_unblock_cache_type { 815 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 816 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 817 }; 818 819 struct hal_reo_status_unblock_cache { 820 bool err_detected; 821 enum hal_reo_status_unblock_cache_type unblock_type; 822 }; 823 824 struct hal_reo_status_flush_timeout_list { 825 bool err_detected; 826 bool list_empty; 827 u16 release_desc_cnt; 828 u16 fwd_buf_cnt; 829 }; 830 831 enum hal_reo_threshold_idx { 832 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 833 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 834 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 835 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 836 }; 837 838 struct hal_reo_status_desc_thresh_reached { 839 enum hal_reo_threshold_idx threshold_idx; 840 u32 link_desc_counter0; 841 u32 link_desc_counter1; 842 u32 link_desc_counter2; 843 u32 link_desc_counter_sum; 844 }; 845 846 struct hal_reo_status { 847 struct hal_reo_status_header uniform_hdr; 848 u8 loop_cnt; 849 union { 850 struct hal_reo_status_queue_stats queue_stats; 851 struct hal_reo_status_flush_queue flush_queue; 852 struct hal_reo_status_flush_cache flush_cache; 853 struct hal_reo_status_unblock_cache unblock_cache; 854 struct hal_reo_status_flush_timeout_list timeout_list; 855 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 856 } u; 857 }; 858 859 /** 860 * HAL context to be used to access SRNG APIs (currently used by data path 861 * and transport (CE) modules) 862 */ 863 struct ath11k_hal { 864 /* HAL internal state for all SRNG rings. 865 */ 866 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 867 868 /* SRNG configuration table */ 869 struct hal_srng_config *srng_config; 870 871 /* Remote pointer memory for HW/FW updates */ 872 struct { 873 u32 *vaddr; 874 dma_addr_t paddr; 875 } rdp; 876 877 /* Shared memory for ring pointer updates from host to FW */ 878 struct { 879 u32 *vaddr; 880 dma_addr_t paddr; 881 } wrp; 882 883 /* Available REO blocking resources bitmap */ 884 u8 avail_blk_resource; 885 886 u8 current_blk_index; 887 888 /* shadow register configuration */ 889 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS]; 890 int num_shadow_reg_configured; 891 }; 892 893 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 894 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 895 u32 start_seq, enum hal_pn_type type); 896 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 897 struct hal_srng *srng); 898 void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map); 899 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 900 struct hal_wbm_idle_scatter_list *sbuf, 901 u32 nsbufs, u32 tot_link_desc, 902 u32 end_offset); 903 904 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 905 struct hal_srng *srng); 906 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 907 struct hal_srng *srng); 908 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 909 dma_addr_t paddr); 910 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 911 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 912 u8 byte_swap_data); 913 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 914 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 915 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type); 916 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type); 917 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 918 struct hal_srng_params *params); 919 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 920 struct hal_srng *srng); 921 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 922 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 923 bool sync_hw_ptr); 924 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 925 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 926 struct hal_srng *srng); 927 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 928 struct hal_srng *srng); 929 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 930 struct hal_srng *srng); 931 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 932 bool sync_hw_ptr); 933 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 934 struct hal_srng *srng); 935 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 936 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 937 int ring_num, int mac_id, 938 struct hal_srng_params *params); 939 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 940 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 941 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 942 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab, 943 u32 **cfg, u32 *len); 944 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab, 945 enum hal_ring_type ring_type, 946 int ring_num); 947 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab); 948 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab, 949 struct hal_srng *srng); 950 #endif 951