1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #include "core.h"
7 #include "dp_tx.h"
8 #include "debug.h"
9 #include "hw.h"
10 #include "peer.h"
11 
12 /* NOTE: Any of the mapped ring id value must not exceed DP_TCL_NUM_RING_MAX */
13 static const u8
14 ath11k_txq_tcl_ring_map[ATH11K_HW_MAX_QUEUES] = { 0x0, 0x1, 0x2, 0x2 };
15 
16 static enum hal_tcl_encap_type
17 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
18 {
19 	/* TODO: Determine encap type based on vif_type and configuration */
20 	return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
21 }
22 
23 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
24 {
25 	struct ieee80211_hdr *hdr = (void *)skb->data;
26 	u8 *qos_ctl;
27 
28 	if (!ieee80211_is_data_qos(hdr->frame_control))
29 		return;
30 
31 	qos_ctl = ieee80211_get_qos_ctl(hdr);
32 	memmove(skb->data + IEEE80211_QOS_CTL_LEN,
33 		skb->data, (void *)qos_ctl - (void *)skb->data);
34 	skb_pull(skb, IEEE80211_QOS_CTL_LEN);
35 
36 	hdr = (void *)skb->data;
37 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
38 }
39 
40 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
41 {
42 	struct ieee80211_hdr *hdr = (void *)skb->data;
43 
44 	if (!ieee80211_is_data_qos(hdr->frame_control))
45 		return HAL_DESC_REO_NON_QOS_TID;
46 	else
47 		return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
48 }
49 
50 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
51 {
52 	switch (cipher) {
53 	case WLAN_CIPHER_SUITE_WEP40:
54 		return HAL_ENCRYPT_TYPE_WEP_40;
55 	case WLAN_CIPHER_SUITE_WEP104:
56 		return HAL_ENCRYPT_TYPE_WEP_104;
57 	case WLAN_CIPHER_SUITE_TKIP:
58 		return HAL_ENCRYPT_TYPE_TKIP_MIC;
59 	case WLAN_CIPHER_SUITE_CCMP:
60 		return HAL_ENCRYPT_TYPE_CCMP_128;
61 	case WLAN_CIPHER_SUITE_CCMP_256:
62 		return HAL_ENCRYPT_TYPE_CCMP_256;
63 	case WLAN_CIPHER_SUITE_GCMP:
64 		return HAL_ENCRYPT_TYPE_GCMP_128;
65 	case WLAN_CIPHER_SUITE_GCMP_256:
66 		return HAL_ENCRYPT_TYPE_AES_GCMP_256;
67 	default:
68 		return HAL_ENCRYPT_TYPE_OPEN;
69 	}
70 }
71 
72 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
73 		 struct sk_buff *skb)
74 {
75 	struct ath11k_base *ab = ar->ab;
76 	struct ath11k_dp *dp = &ab->dp;
77 	struct hal_tx_info ti = {0};
78 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
79 	struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
80 	struct hal_srng *tcl_ring;
81 	struct ieee80211_hdr *hdr = (void *)skb->data;
82 	struct dp_tx_ring *tx_ring;
83 	void *hal_tcl_desc;
84 	u8 pool_id;
85 	u8 hal_ring_id;
86 	int ret;
87 
88 	if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
89 		return -ESHUTDOWN;
90 
91 	if (!ieee80211_is_data(hdr->frame_control))
92 		return -ENOTSUPP;
93 
94 	pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
95 	ti.ring_id = ath11k_txq_tcl_ring_map[pool_id];
96 
97 	tx_ring = &dp->tx_ring[ti.ring_id];
98 
99 	spin_lock_bh(&tx_ring->tx_idr_lock);
100 	ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
101 			DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
102 	spin_unlock_bh(&tx_ring->tx_idr_lock);
103 
104 	if (ret < 0)
105 		return -ENOSPC;
106 
107 	ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
108 		     FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
109 		     FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
110 	ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
111 	ti.meta_data_flags = arvif->tcl_metadata;
112 
113 	if (info->control.hw_key)
114 		ti.encrypt_type =
115 			ath11k_dp_tx_get_encrypt_type(info->control.hw_key->cipher);
116 	else
117 		ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
118 
119 	ti.addr_search_flags = arvif->hal_addr_search_flags;
120 	ti.search_type = arvif->search_type;
121 	ti.type = HAL_TCL_DESC_TYPE_BUFFER;
122 	ti.pkt_offset = 0;
123 	ti.lmac_id = ar->lmac_id;
124 	ti.bss_ast_hash = arvif->ast_hash;
125 	ti.dscp_tid_tbl_idx = 0;
126 
127 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
128 		ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
129 			     FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
130 			     FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
131 			     FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
132 			     FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
133 	}
134 
135 	if (ieee80211_vif_is_mesh(arvif->vif))
136 		ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1);
137 
138 	ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
139 
140 	ti.tid = ath11k_dp_tx_get_tid(skb);
141 
142 	switch (ti.encap_type) {
143 	case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
144 		ath11k_dp_tx_encap_nwifi(skb);
145 		break;
146 	case HAL_TCL_ENCAP_TYPE_RAW:
147 		/*  TODO: for CHECKSUM_PARTIAL case in raw mode, HW checksum offload
148 		 *	  is not applicable, hence manual checksum calculation using
149 		 *	  skb_checksum_help() is needed
150 		 */
151 	case HAL_TCL_ENCAP_TYPE_ETHERNET:
152 	case HAL_TCL_ENCAP_TYPE_802_3:
153 		/* TODO: Take care of other encap modes as well */
154 		ret = -EINVAL;
155 		goto fail_remove_idr;
156 	}
157 
158 	ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
159 	if (dma_mapping_error(ab->dev, ti.paddr)) {
160 		ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
161 		ret = -ENOMEM;
162 		goto fail_remove_idr;
163 	}
164 
165 	ti.data_len = skb->len;
166 	skb_cb->paddr = ti.paddr;
167 	skb_cb->vif = arvif->vif;
168 	skb_cb->ar = ar;
169 
170 	hal_ring_id = tx_ring->tcl_data_ring.ring_id;
171 	tcl_ring = &ab->hal.srng_list[hal_ring_id];
172 
173 	spin_lock_bh(&tcl_ring->lock);
174 
175 	ath11k_hal_srng_access_begin(ab, tcl_ring);
176 
177 	hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
178 	if (!hal_tcl_desc) {
179 		/* NOTE: It is highly unlikely we'll be running out of tcl_ring
180 		 * desc because the desc is directly enqueued onto hw queue.
181 		 * So add tx packet throttling logic in future if required.
182 		 */
183 		ath11k_hal_srng_access_end(ab, tcl_ring);
184 		spin_unlock_bh(&tcl_ring->lock);
185 		ret = -ENOMEM;
186 		goto fail_unmap_dma;
187 	}
188 
189 	ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
190 					 sizeof(struct hal_tlv_hdr), &ti);
191 
192 	ath11k_hal_srng_access_end(ab, tcl_ring);
193 
194 	spin_unlock_bh(&tcl_ring->lock);
195 
196 	atomic_inc(&ar->dp.num_tx_pending);
197 
198 	return 0;
199 
200 fail_unmap_dma:
201 	dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
202 
203 fail_remove_idr:
204 	spin_lock_bh(&tx_ring->tx_idr_lock);
205 	idr_remove(&tx_ring->txbuf_idr,
206 		   FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
207 	spin_unlock_bh(&tx_ring->tx_idr_lock);
208 
209 	return ret;
210 }
211 
212 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
213 				    int msdu_id,
214 				    struct dp_tx_ring *tx_ring)
215 {
216 	struct ath11k *ar;
217 	struct sk_buff *msdu;
218 	struct ath11k_skb_cb *skb_cb;
219 
220 	spin_lock_bh(&tx_ring->tx_idr_lock);
221 	msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
222 	if (!msdu) {
223 		ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
224 			    msdu_id);
225 		spin_unlock_bh(&tx_ring->tx_idr_lock);
226 		return;
227 	}
228 
229 	skb_cb = ATH11K_SKB_CB(msdu);
230 
231 	idr_remove(&tx_ring->txbuf_idr, msdu_id);
232 	spin_unlock_bh(&tx_ring->tx_idr_lock);
233 
234 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
235 	dev_kfree_skb_any(msdu);
236 
237 	ar = ab->pdevs[mac_id].ar;
238 	if (atomic_dec_and_test(&ar->dp.num_tx_pending))
239 		wake_up(&ar->dp.tx_empty_waitq);
240 }
241 
242 static void
243 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
244 				 struct dp_tx_ring *tx_ring,
245 				 struct ath11k_dp_htt_wbm_tx_status *ts)
246 {
247 	struct sk_buff *msdu;
248 	struct ieee80211_tx_info *info;
249 	struct ath11k_skb_cb *skb_cb;
250 	struct ath11k *ar;
251 
252 	spin_lock_bh(&tx_ring->tx_idr_lock);
253 	msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id);
254 	if (!msdu) {
255 		ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
256 			    ts->msdu_id);
257 		spin_unlock_bh(&tx_ring->tx_idr_lock);
258 		return;
259 	}
260 
261 	skb_cb = ATH11K_SKB_CB(msdu);
262 	info = IEEE80211_SKB_CB(msdu);
263 
264 	ar = skb_cb->ar;
265 
266 	idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
267 	spin_unlock_bh(&tx_ring->tx_idr_lock);
268 
269 	if (atomic_dec_and_test(&ar->dp.num_tx_pending))
270 		wake_up(&ar->dp.tx_empty_waitq);
271 
272 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
273 
274 	memset(&info->status, 0, sizeof(info->status));
275 
276 	if (ts->acked) {
277 		if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
278 			info->flags |= IEEE80211_TX_STAT_ACK;
279 			info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
280 						  ts->ack_rssi;
281 			info->status.is_valid_ack_signal = true;
282 		} else {
283 			info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
284 		}
285 	}
286 
287 	ieee80211_tx_status(ar->hw, msdu);
288 }
289 
290 static void
291 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
292 				     void *desc, u8 mac_id,
293 				     u32 msdu_id, struct dp_tx_ring *tx_ring)
294 {
295 	struct htt_tx_wbm_completion *status_desc;
296 	struct ath11k_dp_htt_wbm_tx_status ts = {0};
297 	enum hal_wbm_htt_tx_comp_status wbm_status;
298 
299 	status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
300 
301 	wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
302 			       status_desc->info0);
303 
304 	switch (wbm_status) {
305 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
306 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
307 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
308 		ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
309 		ts.msdu_id = msdu_id;
310 		ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
311 					status_desc->info1);
312 		ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
313 		break;
314 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
315 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
316 		ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
317 		break;
318 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
319 		/* This event is to be handled only when the driver decides to
320 		 * use WDS offload functionality.
321 		 */
322 		break;
323 	default:
324 		ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
325 		break;
326 	}
327 }
328 
329 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
330 					  struct sk_buff *msdu,
331 					  struct hal_tx_status *ts)
332 {
333 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
334 
335 	if (ts->try_cnt > 1) {
336 		peer_stats->retry_pkts += ts->try_cnt - 1;
337 		peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
338 
339 		if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
340 			peer_stats->failed_pkts += 1;
341 			peer_stats->failed_bytes += msdu->len;
342 		}
343 	}
344 }
345 
346 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
347 				       struct sk_buff *msdu,
348 				       struct hal_tx_status *ts)
349 {
350 	struct ath11k_base *ab = ar->ab;
351 	struct ieee80211_tx_info *info;
352 	struct ath11k_skb_cb *skb_cb;
353 
354 	if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
355 		/* Must not happen */
356 		return;
357 	}
358 
359 	skb_cb = ATH11K_SKB_CB(msdu);
360 
361 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
362 
363 	rcu_read_lock();
364 
365 	if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
366 		dev_kfree_skb_any(msdu);
367 		goto exit;
368 	}
369 
370 	if (!skb_cb->vif) {
371 		dev_kfree_skb_any(msdu);
372 		goto exit;
373 	}
374 
375 	info = IEEE80211_SKB_CB(msdu);
376 	memset(&info->status, 0, sizeof(info->status));
377 
378 	/* skip tx rate update from ieee80211_status*/
379 	info->status.rates[0].idx = -1;
380 
381 	if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
382 	    !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
383 		info->flags |= IEEE80211_TX_STAT_ACK;
384 		info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
385 					  ts->ack_rssi;
386 		info->status.is_valid_ack_signal = true;
387 	}
388 
389 	if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
390 	    (info->flags & IEEE80211_TX_CTL_NO_ACK))
391 		info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
392 
393 	if (ath11k_debug_is_extd_tx_stats_enabled(ar)) {
394 		if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
395 			if (ar->last_ppdu_id == 0) {
396 				ar->last_ppdu_id = ts->ppdu_id;
397 			} else if (ar->last_ppdu_id == ts->ppdu_id ||
398 				   ar->cached_ppdu_id == ar->last_ppdu_id) {
399 				ar->cached_ppdu_id = ar->last_ppdu_id;
400 				ar->cached_stats.is_ampdu = true;
401 				ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
402 				memset(&ar->cached_stats, 0,
403 				       sizeof(struct ath11k_per_peer_tx_stats));
404 			} else {
405 				ar->cached_stats.is_ampdu = false;
406 				ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts);
407 				memset(&ar->cached_stats, 0,
408 				       sizeof(struct ath11k_per_peer_tx_stats));
409 			}
410 			ar->last_ppdu_id = ts->ppdu_id;
411 		}
412 
413 		ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
414 	}
415 
416 	/* NOTE: Tx rate status reporting. Tx completion status does not have
417 	 * necessary information (for example nss) to build the tx rate.
418 	 * Might end up reporting it out-of-band from HTT stats.
419 	 */
420 
421 	ieee80211_tx_status(ar->hw, msdu);
422 
423 exit:
424 	rcu_read_unlock();
425 }
426 
427 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
428 					     struct hal_wbm_release_ring *desc,
429 					     struct hal_tx_status *ts)
430 {
431 	ts->buf_rel_source =
432 		FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
433 	if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
434 	    ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
435 		return;
436 
437 	if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
438 		return;
439 
440 	ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
441 			       desc->info0);
442 	ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
443 				desc->info1);
444 	ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
445 				desc->info1);
446 	ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
447 				 desc->info2);
448 	if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
449 		ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
450 	ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
451 	ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
452 	if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
453 		ts->rate_stats = desc->rate_stats.info0;
454 	else
455 		ts->rate_stats = 0;
456 }
457 
458 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
459 {
460 	struct ath11k *ar;
461 	struct ath11k_dp *dp = &ab->dp;
462 	int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
463 	struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
464 	struct sk_buff *msdu;
465 	struct hal_tx_status ts = { 0 };
466 	struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
467 	u32 *desc;
468 	u32 msdu_id;
469 	u8 mac_id;
470 
471 	ath11k_hal_srng_access_begin(ab, status_ring);
472 
473 	while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
474 		tx_ring->tx_status_tail) &&
475 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
476 		memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
477 		       desc, sizeof(struct hal_wbm_release_ring));
478 		tx_ring->tx_status_head =
479 			ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
480 	}
481 
482 	if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
483 	    (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
484 		/* TODO: Process pending tx_status messages when kfifo_is_full() */
485 		ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
486 	}
487 
488 	ath11k_hal_srng_access_end(ab, status_ring);
489 
490 	while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
491 		struct hal_wbm_release_ring *tx_status;
492 		u32 desc_id;
493 
494 		tx_ring->tx_status_tail =
495 			ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
496 		tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
497 		ath11k_dp_tx_status_parse(ab, tx_status, &ts);
498 
499 		desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
500 				    tx_status->buf_addr_info.info1);
501 		mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
502 		msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
503 
504 		if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
505 			ath11k_dp_tx_process_htt_tx_complete(ab,
506 							     (void *)tx_status,
507 							     mac_id, msdu_id,
508 							     tx_ring);
509 			continue;
510 		}
511 
512 		spin_lock_bh(&tx_ring->tx_idr_lock);
513 		msdu = idr_find(&tx_ring->txbuf_idr, msdu_id);
514 		if (!msdu) {
515 			ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
516 				    msdu_id);
517 			spin_unlock_bh(&tx_ring->tx_idr_lock);
518 			continue;
519 		}
520 		idr_remove(&tx_ring->txbuf_idr, msdu_id);
521 		spin_unlock_bh(&tx_ring->tx_idr_lock);
522 
523 		ar = ab->pdevs[mac_id].ar;
524 
525 		if (atomic_dec_and_test(&ar->dp.num_tx_pending))
526 			wake_up(&ar->dp.tx_empty_waitq);
527 
528 		ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
529 	}
530 }
531 
532 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
533 			      enum hal_reo_cmd_type type,
534 			      struct ath11k_hal_reo_cmd *cmd,
535 			      void (*cb)(struct ath11k_dp *, void *,
536 					 enum hal_reo_cmd_status))
537 {
538 	struct ath11k_dp *dp = &ab->dp;
539 	struct dp_reo_cmd *dp_cmd;
540 	struct hal_srng *cmd_ring;
541 	int cmd_num;
542 
543 	cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
544 	cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
545 
546 	/* reo cmd ring descriptors has cmd_num starting from 1 */
547 	if (cmd_num <= 0)
548 		return -EINVAL;
549 
550 	if (!cb)
551 		return 0;
552 
553 	/* Can this be optimized so that we keep the pending command list only
554 	 * for tid delete command to free up the resoruce on the command status
555 	 * indication?
556 	 */
557 	dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
558 
559 	if (!dp_cmd)
560 		return -ENOMEM;
561 
562 	memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
563 	dp_cmd->cmd_num = cmd_num;
564 	dp_cmd->handler = cb;
565 
566 	spin_lock_bh(&dp->reo_cmd_lock);
567 	list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
568 	spin_unlock_bh(&dp->reo_cmd_lock);
569 
570 	return 0;
571 }
572 
573 static int
574 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
575 			      int mac_id, u32 ring_id,
576 			      enum hal_ring_type ring_type,
577 			      enum htt_srng_ring_type *htt_ring_type,
578 			      enum htt_srng_ring_id *htt_ring_id)
579 {
580 	int lmac_ring_id_offset = 0;
581 	int ret = 0;
582 
583 	switch (ring_type) {
584 	case HAL_RXDMA_BUF:
585 		lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
586 		if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
587 				  lmac_ring_id_offset) ||
588 		    ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
589 				lmac_ring_id_offset))) {
590 			ret = -EINVAL;
591 		}
592 		*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
593 		*htt_ring_type = HTT_SW_TO_HW_RING;
594 		break;
595 	case HAL_RXDMA_DST:
596 		*htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
597 		*htt_ring_type = HTT_HW_TO_SW_RING;
598 		break;
599 	case HAL_RXDMA_MONITOR_BUF:
600 		*htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
601 		*htt_ring_type = HTT_SW_TO_HW_RING;
602 		break;
603 	case HAL_RXDMA_MONITOR_STATUS:
604 		*htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
605 		*htt_ring_type = HTT_SW_TO_HW_RING;
606 		break;
607 	case HAL_RXDMA_MONITOR_DST:
608 		*htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
609 		*htt_ring_type = HTT_HW_TO_SW_RING;
610 		break;
611 	case HAL_RXDMA_MONITOR_DESC:
612 		*htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
613 		*htt_ring_type = HTT_SW_TO_HW_RING;
614 		break;
615 	default:
616 		ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
617 		ret = -EINVAL;
618 	}
619 	return ret;
620 }
621 
622 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
623 				int mac_id, enum hal_ring_type ring_type)
624 {
625 	struct htt_srng_setup_cmd *cmd;
626 	struct hal_srng *srng = &ab->hal.srng_list[ring_id];
627 	struct hal_srng_params params;
628 	struct sk_buff *skb;
629 	u32 ring_entry_sz;
630 	int len = sizeof(*cmd);
631 	dma_addr_t hp_addr, tp_addr;
632 	enum htt_srng_ring_type htt_ring_type;
633 	enum htt_srng_ring_id htt_ring_id;
634 	int ret;
635 
636 	skb = ath11k_htc_alloc_skb(ab, len);
637 	if (!skb)
638 		return -ENOMEM;
639 
640 	memset(&params, 0, sizeof(params));
641 	ath11k_hal_srng_get_params(ab, srng, &params);
642 
643 	hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
644 	tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
645 
646 	ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
647 					    ring_type, &htt_ring_type,
648 					    &htt_ring_id);
649 	if (ret)
650 		goto err_free;
651 
652 	skb_put(skb, len);
653 	cmd = (struct htt_srng_setup_cmd *)skb->data;
654 	cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
655 				HTT_H2T_MSG_TYPE_SRING_SETUP);
656 	if (htt_ring_type == HTT_SW_TO_HW_RING ||
657 	    htt_ring_type == HTT_HW_TO_SW_RING)
658 		cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
659 					 DP_SW2HW_MACID(mac_id));
660 	else
661 		cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
662 					 mac_id);
663 	cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
664 				 htt_ring_type);
665 	cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
666 
667 	cmd->ring_base_addr_lo = params.ring_base_paddr &
668 				 HAL_ADDR_LSB_REG_MASK;
669 
670 	cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
671 				 HAL_ADDR_MSB_REG_SHIFT;
672 
673 	ret = ath11k_hal_srng_get_entrysize(ring_type);
674 	if (ret < 0)
675 		goto err_free;
676 
677 	ring_entry_sz = ret;
678 
679 	ring_entry_sz >>= 2;
680 	cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
681 				ring_entry_sz);
682 	cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
683 				 params.num_entries * ring_entry_sz);
684 	cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
685 				 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
686 	cmd->info1 |= FIELD_PREP(
687 			HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
688 			!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
689 	cmd->info1 |= FIELD_PREP(
690 			HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
691 			!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
692 	if (htt_ring_type == HTT_SW_TO_HW_RING)
693 		cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
694 
695 	cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
696 	cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
697 					      HAL_ADDR_MSB_REG_SHIFT;
698 
699 	cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
700 	cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
701 					      HAL_ADDR_MSB_REG_SHIFT;
702 
703 	cmd->ring_msi_addr_lo = 0;
704 	cmd->ring_msi_addr_hi = 0;
705 	cmd->msi_data = 0;
706 
707 	cmd->intr_info = FIELD_PREP(
708 			HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
709 			params.intr_batch_cntr_thres_entries * ring_entry_sz);
710 	cmd->intr_info |= FIELD_PREP(
711 			HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
712 			params.intr_timer_thres_us >> 3);
713 
714 	cmd->info2 = 0;
715 	if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
716 		cmd->info2 = FIELD_PREP(
717 				HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
718 				params.low_threshold);
719 	}
720 
721 	ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
722 	if (ret)
723 		goto err_free;
724 
725 	return 0;
726 
727 err_free:
728 	dev_kfree_skb_any(skb);
729 
730 	return ret;
731 }
732 
733 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
734 
735 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
736 {
737 	struct ath11k_dp *dp = &ab->dp;
738 	struct sk_buff *skb;
739 	struct htt_ver_req_cmd *cmd;
740 	int len = sizeof(*cmd);
741 	int ret;
742 
743 	init_completion(&dp->htt_tgt_version_received);
744 
745 	skb = ath11k_htc_alloc_skb(ab, len);
746 	if (!skb)
747 		return -ENOMEM;
748 
749 	skb_put(skb, len);
750 	cmd = (struct htt_ver_req_cmd *)skb->data;
751 	cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
752 				       HTT_H2T_MSG_TYPE_VERSION_REQ);
753 
754 	ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
755 	if (ret) {
756 		dev_kfree_skb_any(skb);
757 		return ret;
758 	}
759 
760 	ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
761 					  HTT_TARGET_VERSION_TIMEOUT_HZ);
762 	if (ret == 0) {
763 		ath11k_warn(ab, "htt target version request timed out\n");
764 		return -ETIMEDOUT;
765 	}
766 
767 	if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
768 		ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
769 			   dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
770 		return -ENOTSUPP;
771 	}
772 
773 	return 0;
774 }
775 
776 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
777 {
778 	struct ath11k_base *ab = ar->ab;
779 	struct ath11k_dp *dp = &ab->dp;
780 	struct sk_buff *skb;
781 	struct htt_ppdu_stats_cfg_cmd *cmd;
782 	int len = sizeof(*cmd);
783 	u8 pdev_mask;
784 	int ret;
785 
786 	skb = ath11k_htc_alloc_skb(ab, len);
787 	if (!skb)
788 		return -ENOMEM;
789 
790 	skb_put(skb, len);
791 	cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
792 	cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
793 			      HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
794 
795 	pdev_mask = 1 << (ar->pdev_idx);
796 	cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
797 	cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
798 
799 	ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
800 	if (ret) {
801 		dev_kfree_skb_any(skb);
802 		return ret;
803 	}
804 
805 	return 0;
806 }
807 
808 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
809 				     int mac_id, enum hal_ring_type ring_type,
810 				     int rx_buf_size,
811 				     struct htt_rx_ring_tlv_filter *tlv_filter)
812 {
813 	struct htt_rx_ring_selection_cfg_cmd *cmd;
814 	struct hal_srng *srng = &ab->hal.srng_list[ring_id];
815 	struct hal_srng_params params;
816 	struct sk_buff *skb;
817 	int len = sizeof(*cmd);
818 	enum htt_srng_ring_type htt_ring_type;
819 	enum htt_srng_ring_id htt_ring_id;
820 	int ret;
821 
822 	skb = ath11k_htc_alloc_skb(ab, len);
823 	if (!skb)
824 		return -ENOMEM;
825 
826 	memset(&params, 0, sizeof(params));
827 	ath11k_hal_srng_get_params(ab, srng, &params);
828 
829 	ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
830 					    ring_type, &htt_ring_type,
831 					    &htt_ring_id);
832 	if (ret)
833 		goto err_free;
834 
835 	skb_put(skb, len);
836 	cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
837 	cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
838 				HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
839 	if (htt_ring_type == HTT_SW_TO_HW_RING ||
840 	    htt_ring_type == HTT_HW_TO_SW_RING)
841 		cmd->info0 |=
842 			FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
843 				   DP_SW2HW_MACID(mac_id));
844 	else
845 		cmd->info0 |=
846 			FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
847 				   mac_id);
848 	cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
849 				 htt_ring_id);
850 	cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
851 				 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
852 	cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
853 				 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
854 
855 	cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
856 				rx_buf_size);
857 	cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
858 	cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
859 	cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
860 	cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
861 	cmd->rx_filter_tlv = tlv_filter->rx_filter;
862 
863 	ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
864 	if (ret)
865 		goto err_free;
866 
867 	return 0;
868 
869 err_free:
870 	dev_kfree_skb_any(skb);
871 
872 	return ret;
873 }
874 
875 int
876 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
877 				   struct htt_ext_stats_cfg_params *cfg_params,
878 				   u64 cookie)
879 {
880 	struct ath11k_base *ab = ar->ab;
881 	struct ath11k_dp *dp = &ab->dp;
882 	struct sk_buff *skb;
883 	struct htt_ext_stats_cfg_cmd *cmd;
884 	int len = sizeof(*cmd);
885 	int ret;
886 
887 	skb = ath11k_htc_alloc_skb(ab, len);
888 	if (!skb)
889 		return -ENOMEM;
890 
891 	skb_put(skb, len);
892 
893 	cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
894 	memset(cmd, 0, sizeof(*cmd));
895 	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
896 
897 	cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id;
898 
899 	cmd->hdr.stats_type = type;
900 	cmd->cfg_param0 = cfg_params->cfg0;
901 	cmd->cfg_param1 = cfg_params->cfg1;
902 	cmd->cfg_param2 = cfg_params->cfg2;
903 	cmd->cfg_param3 = cfg_params->cfg3;
904 	cmd->cookie_lsb = lower_32_bits(cookie);
905 	cmd->cookie_msb = upper_32_bits(cookie);
906 
907 	ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
908 	if (ret) {
909 		ath11k_warn(ab, "failed to send htt type stats request: %d",
910 			    ret);
911 		dev_kfree_skb_any(skb);
912 		return ret;
913 	}
914 
915 	return 0;
916 }
917 
918 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
919 {
920 	struct ath11k_pdev_dp *dp = &ar->dp;
921 	struct htt_rx_ring_tlv_filter tlv_filter = {0};
922 	int ret = 0, ring_id = 0;
923 
924 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
925 
926 	if (!reset) {
927 		tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
928 		tlv_filter.pkt_filter_flags0 =
929 					HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
930 					HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
931 		tlv_filter.pkt_filter_flags1 =
932 					HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
933 					HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
934 		tlv_filter.pkt_filter_flags2 =
935 					HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
936 					HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
937 		tlv_filter.pkt_filter_flags3 =
938 					HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
939 					HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
940 					HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
941 					HTT_RX_MON_MO_DATA_FILTER_FLASG3;
942 	}
943 
944 	ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
945 					       HAL_RXDMA_MONITOR_BUF,
946 					       DP_RXDMA_REFILL_RING_SIZE,
947 					       &tlv_filter);
948 	if (ret)
949 		return ret;
950 
951 	ring_id = dp->rx_mon_status_refill_ring.refill_buf_ring.ring_id;
952 	if (!reset)
953 		tlv_filter.rx_filter =
954 				HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
955 	else
956 		tlv_filter = ath11k_mac_mon_status_filter_default;
957 
958 	ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
959 					       HAL_RXDMA_MONITOR_STATUS,
960 					       DP_RXDMA_REFILL_RING_SIZE,
961 					       &tlv_filter);
962 	return ret;
963 }
964