1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 13 static enum hal_tcl_encap_type 14 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15 { 16 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17 struct ath11k_base *ab = arvif->ar->ab; 18 19 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20 return HAL_TCL_ENCAP_TYPE_RAW; 21 22 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23 return HAL_TCL_ENCAP_TYPE_ETHERNET; 24 25 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26 } 27 28 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29 { 30 struct ieee80211_hdr *hdr = (void *)skb->data; 31 u8 *qos_ctl; 32 33 if (!ieee80211_is_data_qos(hdr->frame_control)) 34 return; 35 36 qos_ctl = ieee80211_get_qos_ctl(hdr); 37 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38 skb->data, (void *)qos_ctl - (void *)skb->data); 39 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40 41 hdr = (void *)skb->data; 42 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43 } 44 45 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46 { 47 struct ieee80211_hdr *hdr = (void *)skb->data; 48 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49 50 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52 else if (!ieee80211_is_data_qos(hdr->frame_control)) 53 return HAL_DESC_REO_NON_QOS_TID; 54 else 55 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56 } 57 58 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59 { 60 switch (cipher) { 61 case WLAN_CIPHER_SUITE_WEP40: 62 return HAL_ENCRYPT_TYPE_WEP_40; 63 case WLAN_CIPHER_SUITE_WEP104: 64 return HAL_ENCRYPT_TYPE_WEP_104; 65 case WLAN_CIPHER_SUITE_TKIP: 66 return HAL_ENCRYPT_TYPE_TKIP_MIC; 67 case WLAN_CIPHER_SUITE_CCMP: 68 return HAL_ENCRYPT_TYPE_CCMP_128; 69 case WLAN_CIPHER_SUITE_CCMP_256: 70 return HAL_ENCRYPT_TYPE_CCMP_256; 71 case WLAN_CIPHER_SUITE_GCMP: 72 return HAL_ENCRYPT_TYPE_GCMP_128; 73 case WLAN_CIPHER_SUITE_GCMP_256: 74 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75 default: 76 return HAL_ENCRYPT_TYPE_OPEN; 77 } 78 } 79 80 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81 struct sk_buff *skb) 82 { 83 struct ath11k_base *ab = ar->ab; 84 struct ath11k_dp *dp = &ab->dp; 85 struct hal_tx_info ti = {0}; 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ieee80211_key_conf *key = info->control.hw_key; 88 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 89 struct hal_srng *tcl_ring; 90 struct ieee80211_hdr *hdr = (void *)skb->data; 91 struct dp_tx_ring *tx_ring; 92 void *hal_tcl_desc; 93 u8 pool_id; 94 u8 hal_ring_id; 95 int ret; 96 u8 ring_selector = 0, ring_map = 0; 97 bool tcl_ring_retry; 98 99 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 100 return -ESHUTDOWN; 101 102 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 103 !ieee80211_is_data(hdr->frame_control)) 104 return -ENOTSUPP; 105 106 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 107 108 /* Let the default ring selection be based on a round robin 109 * fashion where one of the 3 tcl rings are selected based on 110 * the tcl_ring_selector counter. In case that ring 111 * is full/busy, we resort to other available rings. 112 * If all rings are full, we drop the packet. 113 * //TODO Add throttling logic when all rings are full 114 */ 115 ring_selector = atomic_inc_return(&ab->tcl_ring_selector); 116 117 tcl_ring_sel: 118 tcl_ring_retry = false; 119 /* For some chip, it can only use tcl0 to tx */ 120 if (ar->ab->hw_params.tcl_0_only) 121 ti.ring_id = 0; 122 else 123 ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX; 124 125 ring_map |= BIT(ti.ring_id); 126 127 tx_ring = &dp->tx_ring[ti.ring_id]; 128 129 spin_lock_bh(&tx_ring->tx_idr_lock); 130 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 131 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 132 spin_unlock_bh(&tx_ring->tx_idr_lock); 133 134 if (ret < 0) { 135 if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) { 136 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 137 return -ENOSPC; 138 } 139 140 /* Check if the next ring is available */ 141 ring_selector++; 142 goto tcl_ring_sel; 143 } 144 145 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 146 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 147 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 148 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 149 ti.meta_data_flags = arvif->tcl_metadata; 150 151 if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) { 152 if (key) { 153 ti.encrypt_type = 154 ath11k_dp_tx_get_encrypt_type(key->cipher); 155 156 if (ieee80211_has_protected(hdr->frame_control)) 157 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 158 } else { 159 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 160 } 161 } 162 163 ti.addr_search_flags = arvif->hal_addr_search_flags; 164 ti.search_type = arvif->search_type; 165 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 166 ti.pkt_offset = 0; 167 ti.lmac_id = ar->lmac_id; 168 ti.bss_ast_hash = arvif->ast_hash; 169 ti.dscp_tid_tbl_idx = 0; 170 171 if (skb->ip_summed == CHECKSUM_PARTIAL && 172 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 173 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 174 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 175 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 176 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 177 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 178 } 179 180 if (ieee80211_vif_is_mesh(arvif->vif)) 181 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1); 182 183 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 184 185 ti.tid = ath11k_dp_tx_get_tid(skb); 186 187 switch (ti.encap_type) { 188 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 189 ath11k_dp_tx_encap_nwifi(skb); 190 break; 191 case HAL_TCL_ENCAP_TYPE_RAW: 192 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 193 ret = -EINVAL; 194 goto fail_remove_idr; 195 } 196 break; 197 case HAL_TCL_ENCAP_TYPE_ETHERNET: 198 /* no need to encap */ 199 break; 200 case HAL_TCL_ENCAP_TYPE_802_3: 201 default: 202 /* TODO: Take care of other encap modes as well */ 203 ret = -EINVAL; 204 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 205 goto fail_remove_idr; 206 } 207 208 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 209 if (dma_mapping_error(ab->dev, ti.paddr)) { 210 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 211 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 212 ret = -ENOMEM; 213 goto fail_remove_idr; 214 } 215 216 ti.data_len = skb->len; 217 skb_cb->paddr = ti.paddr; 218 skb_cb->vif = arvif->vif; 219 skb_cb->ar = ar; 220 221 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 222 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 223 224 spin_lock_bh(&tcl_ring->lock); 225 226 ath11k_hal_srng_access_begin(ab, tcl_ring); 227 228 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 229 if (!hal_tcl_desc) { 230 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 231 * desc because the desc is directly enqueued onto hw queue. 232 */ 233 ath11k_hal_srng_access_end(ab, tcl_ring); 234 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 235 spin_unlock_bh(&tcl_ring->lock); 236 ret = -ENOMEM; 237 238 /* Checking for available tcl descritors in another ring in 239 * case of failure due to full tcl ring now, is better than 240 * checking this ring earlier for each pkt tx. 241 * Restart ring selection if some rings are not checked yet. 242 */ 243 if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) && 244 !ar->ab->hw_params.tcl_0_only) { 245 tcl_ring_retry = true; 246 ring_selector++; 247 } 248 249 goto fail_unmap_dma; 250 } 251 252 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 253 sizeof(struct hal_tlv_hdr), &ti); 254 255 ath11k_hal_srng_access_end(ab, tcl_ring); 256 257 spin_unlock_bh(&tcl_ring->lock); 258 259 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 260 skb->data, skb->len); 261 262 atomic_inc(&ar->dp.num_tx_pending); 263 264 return 0; 265 266 fail_unmap_dma: 267 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 268 269 fail_remove_idr: 270 spin_lock_bh(&tx_ring->tx_idr_lock); 271 idr_remove(&tx_ring->txbuf_idr, 272 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 273 spin_unlock_bh(&tx_ring->tx_idr_lock); 274 275 if (tcl_ring_retry) 276 goto tcl_ring_sel; 277 278 return ret; 279 } 280 281 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 282 int msdu_id, 283 struct dp_tx_ring *tx_ring) 284 { 285 struct ath11k *ar; 286 struct sk_buff *msdu; 287 struct ath11k_skb_cb *skb_cb; 288 289 spin_lock_bh(&tx_ring->tx_idr_lock); 290 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 291 if (!msdu) { 292 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 293 msdu_id); 294 spin_unlock_bh(&tx_ring->tx_idr_lock); 295 return; 296 } 297 298 skb_cb = ATH11K_SKB_CB(msdu); 299 300 idr_remove(&tx_ring->txbuf_idr, msdu_id); 301 spin_unlock_bh(&tx_ring->tx_idr_lock); 302 303 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 304 dev_kfree_skb_any(msdu); 305 306 ar = ab->pdevs[mac_id].ar; 307 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 308 wake_up(&ar->dp.tx_empty_waitq); 309 } 310 311 static void 312 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 313 struct dp_tx_ring *tx_ring, 314 struct ath11k_dp_htt_wbm_tx_status *ts) 315 { 316 struct sk_buff *msdu; 317 struct ieee80211_tx_info *info; 318 struct ath11k_skb_cb *skb_cb; 319 struct ath11k *ar; 320 321 spin_lock_bh(&tx_ring->tx_idr_lock); 322 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 323 if (!msdu) { 324 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 325 ts->msdu_id); 326 spin_unlock_bh(&tx_ring->tx_idr_lock); 327 return; 328 } 329 330 skb_cb = ATH11K_SKB_CB(msdu); 331 info = IEEE80211_SKB_CB(msdu); 332 333 ar = skb_cb->ar; 334 335 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 336 spin_unlock_bh(&tx_ring->tx_idr_lock); 337 338 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 339 wake_up(&ar->dp.tx_empty_waitq); 340 341 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 342 343 memset(&info->status, 0, sizeof(info->status)); 344 345 if (ts->acked) { 346 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 347 info->flags |= IEEE80211_TX_STAT_ACK; 348 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 349 ts->ack_rssi; 350 info->status.is_valid_ack_signal = true; 351 } else { 352 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 353 } 354 } 355 356 ieee80211_tx_status(ar->hw, msdu); 357 } 358 359 static void 360 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 361 void *desc, u8 mac_id, 362 u32 msdu_id, struct dp_tx_ring *tx_ring) 363 { 364 struct htt_tx_wbm_completion *status_desc; 365 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 366 enum hal_wbm_htt_tx_comp_status wbm_status; 367 368 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 369 370 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 371 status_desc->info0); 372 switch (wbm_status) { 373 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 374 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 375 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 376 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 377 ts.msdu_id = msdu_id; 378 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 379 status_desc->info1); 380 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 381 break; 382 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 383 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 384 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 385 break; 386 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 387 /* This event is to be handled only when the driver decides to 388 * use WDS offload functionality. 389 */ 390 break; 391 default: 392 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 393 break; 394 } 395 } 396 397 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 398 struct sk_buff *msdu, 399 struct hal_tx_status *ts) 400 { 401 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 402 403 if (ts->try_cnt > 1) { 404 peer_stats->retry_pkts += ts->try_cnt - 1; 405 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 406 407 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 408 peer_stats->failed_pkts += 1; 409 peer_stats->failed_bytes += msdu->len; 410 } 411 } 412 } 413 414 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 415 struct sk_buff *msdu, 416 struct hal_tx_status *ts) 417 { 418 struct ath11k_base *ab = ar->ab; 419 struct ieee80211_tx_info *info; 420 struct ath11k_skb_cb *skb_cb; 421 422 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 423 /* Must not happen */ 424 return; 425 } 426 427 skb_cb = ATH11K_SKB_CB(msdu); 428 429 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 430 431 rcu_read_lock(); 432 433 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 434 dev_kfree_skb_any(msdu); 435 goto exit; 436 } 437 438 if (!skb_cb->vif) { 439 dev_kfree_skb_any(msdu); 440 goto exit; 441 } 442 443 info = IEEE80211_SKB_CB(msdu); 444 memset(&info->status, 0, sizeof(info->status)); 445 446 /* skip tx rate update from ieee80211_status*/ 447 info->status.rates[0].idx = -1; 448 449 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 450 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 451 info->flags |= IEEE80211_TX_STAT_ACK; 452 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 453 ts->ack_rssi; 454 info->status.is_valid_ack_signal = true; 455 } 456 457 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 458 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 459 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 460 461 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) { 462 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 463 if (ar->last_ppdu_id == 0) { 464 ar->last_ppdu_id = ts->ppdu_id; 465 } else if (ar->last_ppdu_id == ts->ppdu_id || 466 ar->cached_ppdu_id == ar->last_ppdu_id) { 467 ar->cached_ppdu_id = ar->last_ppdu_id; 468 ar->cached_stats.is_ampdu = true; 469 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 470 memset(&ar->cached_stats, 0, 471 sizeof(struct ath11k_per_peer_tx_stats)); 472 } else { 473 ar->cached_stats.is_ampdu = false; 474 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 475 memset(&ar->cached_stats, 0, 476 sizeof(struct ath11k_per_peer_tx_stats)); 477 } 478 ar->last_ppdu_id = ts->ppdu_id; 479 } 480 481 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 482 } 483 484 /* NOTE: Tx rate status reporting. Tx completion status does not have 485 * necessary information (for example nss) to build the tx rate. 486 * Might end up reporting it out-of-band from HTT stats. 487 */ 488 489 ieee80211_tx_status(ar->hw, msdu); 490 491 exit: 492 rcu_read_unlock(); 493 } 494 495 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 496 struct hal_wbm_release_ring *desc, 497 struct hal_tx_status *ts) 498 { 499 ts->buf_rel_source = 500 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 501 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 502 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 503 return; 504 505 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 506 return; 507 508 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 509 desc->info0); 510 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 511 desc->info1); 512 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 513 desc->info1); 514 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 515 desc->info2); 516 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 517 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 518 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 519 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 520 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 521 ts->rate_stats = desc->rate_stats.info0; 522 else 523 ts->rate_stats = 0; 524 } 525 526 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 527 { 528 struct ath11k *ar; 529 struct ath11k_dp *dp = &ab->dp; 530 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 531 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 532 struct sk_buff *msdu; 533 struct hal_tx_status ts = { 0 }; 534 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 535 u32 *desc; 536 u32 msdu_id; 537 u8 mac_id; 538 539 ath11k_hal_srng_access_begin(ab, status_ring); 540 541 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 542 tx_ring->tx_status_tail) && 543 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 544 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 545 desc, sizeof(struct hal_wbm_release_ring)); 546 tx_ring->tx_status_head = 547 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 548 } 549 550 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 551 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 552 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 553 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 554 } 555 556 ath11k_hal_srng_access_end(ab, status_ring); 557 558 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 559 struct hal_wbm_release_ring *tx_status; 560 u32 desc_id; 561 562 tx_ring->tx_status_tail = 563 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 564 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 565 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 566 567 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 568 tx_status->buf_addr_info.info1); 569 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 570 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 571 572 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 573 ath11k_dp_tx_process_htt_tx_complete(ab, 574 (void *)tx_status, 575 mac_id, msdu_id, 576 tx_ring); 577 continue; 578 } 579 580 spin_lock_bh(&tx_ring->tx_idr_lock); 581 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 582 if (!msdu) { 583 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 584 msdu_id); 585 spin_unlock_bh(&tx_ring->tx_idr_lock); 586 continue; 587 } 588 idr_remove(&tx_ring->txbuf_idr, msdu_id); 589 spin_unlock_bh(&tx_ring->tx_idr_lock); 590 591 ar = ab->pdevs[mac_id].ar; 592 593 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 594 wake_up(&ar->dp.tx_empty_waitq); 595 596 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 597 } 598 } 599 600 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 601 enum hal_reo_cmd_type type, 602 struct ath11k_hal_reo_cmd *cmd, 603 void (*cb)(struct ath11k_dp *, void *, 604 enum hal_reo_cmd_status)) 605 { 606 struct ath11k_dp *dp = &ab->dp; 607 struct dp_reo_cmd *dp_cmd; 608 struct hal_srng *cmd_ring; 609 int cmd_num; 610 611 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 612 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 613 614 /* cmd_num should start from 1, during failure return the error code */ 615 if (cmd_num < 0) 616 return cmd_num; 617 618 /* reo cmd ring descriptors has cmd_num starting from 1 */ 619 if (cmd_num == 0) 620 return -EINVAL; 621 622 if (!cb) 623 return 0; 624 625 /* Can this be optimized so that we keep the pending command list only 626 * for tid delete command to free up the resoruce on the command status 627 * indication? 628 */ 629 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 630 631 if (!dp_cmd) 632 return -ENOMEM; 633 634 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 635 dp_cmd->cmd_num = cmd_num; 636 dp_cmd->handler = cb; 637 638 spin_lock_bh(&dp->reo_cmd_lock); 639 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 640 spin_unlock_bh(&dp->reo_cmd_lock); 641 642 return 0; 643 } 644 645 static int 646 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 647 int mac_id, u32 ring_id, 648 enum hal_ring_type ring_type, 649 enum htt_srng_ring_type *htt_ring_type, 650 enum htt_srng_ring_id *htt_ring_id) 651 { 652 int lmac_ring_id_offset = 0; 653 int ret = 0; 654 655 switch (ring_type) { 656 case HAL_RXDMA_BUF: 657 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 658 659 /* for QCA6390, host fills rx buffer to fw and fw fills to 660 * rxbuf ring for each rxdma 661 */ 662 if (!ab->hw_params.rx_mac_buf_ring) { 663 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 664 lmac_ring_id_offset) || 665 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 666 lmac_ring_id_offset))) { 667 ret = -EINVAL; 668 } 669 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 670 *htt_ring_type = HTT_SW_TO_HW_RING; 671 } else { 672 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 673 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 674 *htt_ring_type = HTT_SW_TO_SW_RING; 675 } else { 676 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 677 *htt_ring_type = HTT_SW_TO_HW_RING; 678 } 679 } 680 break; 681 case HAL_RXDMA_DST: 682 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 683 *htt_ring_type = HTT_HW_TO_SW_RING; 684 break; 685 case HAL_RXDMA_MONITOR_BUF: 686 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 687 *htt_ring_type = HTT_SW_TO_HW_RING; 688 break; 689 case HAL_RXDMA_MONITOR_STATUS: 690 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 691 *htt_ring_type = HTT_SW_TO_HW_RING; 692 break; 693 case HAL_RXDMA_MONITOR_DST: 694 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 695 *htt_ring_type = HTT_HW_TO_SW_RING; 696 break; 697 case HAL_RXDMA_MONITOR_DESC: 698 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 699 *htt_ring_type = HTT_SW_TO_HW_RING; 700 break; 701 default: 702 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 703 ret = -EINVAL; 704 } 705 return ret; 706 } 707 708 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 709 int mac_id, enum hal_ring_type ring_type) 710 { 711 struct htt_srng_setup_cmd *cmd; 712 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 713 struct hal_srng_params params; 714 struct sk_buff *skb; 715 u32 ring_entry_sz; 716 int len = sizeof(*cmd); 717 dma_addr_t hp_addr, tp_addr; 718 enum htt_srng_ring_type htt_ring_type; 719 enum htt_srng_ring_id htt_ring_id; 720 int ret; 721 722 skb = ath11k_htc_alloc_skb(ab, len); 723 if (!skb) 724 return -ENOMEM; 725 726 memset(¶ms, 0, sizeof(params)); 727 ath11k_hal_srng_get_params(ab, srng, ¶ms); 728 729 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 730 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 731 732 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 733 ring_type, &htt_ring_type, 734 &htt_ring_id); 735 if (ret) 736 goto err_free; 737 738 skb_put(skb, len); 739 cmd = (struct htt_srng_setup_cmd *)skb->data; 740 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 741 HTT_H2T_MSG_TYPE_SRING_SETUP); 742 if (htt_ring_type == HTT_SW_TO_HW_RING || 743 htt_ring_type == HTT_HW_TO_SW_RING) 744 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 745 DP_SW2HW_MACID(mac_id)); 746 else 747 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 748 mac_id); 749 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 750 htt_ring_type); 751 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 752 753 cmd->ring_base_addr_lo = params.ring_base_paddr & 754 HAL_ADDR_LSB_REG_MASK; 755 756 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 757 HAL_ADDR_MSB_REG_SHIFT; 758 759 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 760 if (ret < 0) 761 goto err_free; 762 763 ring_entry_sz = ret; 764 765 ring_entry_sz >>= 2; 766 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 767 ring_entry_sz); 768 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 769 params.num_entries * ring_entry_sz); 770 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 771 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 772 cmd->info1 |= FIELD_PREP( 773 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 774 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 775 cmd->info1 |= FIELD_PREP( 776 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 777 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 778 if (htt_ring_type == HTT_SW_TO_HW_RING) 779 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 780 781 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 782 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 783 HAL_ADDR_MSB_REG_SHIFT; 784 785 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 786 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 787 HAL_ADDR_MSB_REG_SHIFT; 788 789 cmd->ring_msi_addr_lo = 0; 790 cmd->ring_msi_addr_hi = 0; 791 cmd->msi_data = 0; 792 793 cmd->intr_info = FIELD_PREP( 794 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 795 params.intr_batch_cntr_thres_entries * ring_entry_sz); 796 cmd->intr_info |= FIELD_PREP( 797 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 798 params.intr_timer_thres_us >> 3); 799 800 cmd->info2 = 0; 801 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 802 cmd->info2 = FIELD_PREP( 803 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 804 params.low_threshold); 805 } 806 807 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 808 if (ret) 809 goto err_free; 810 811 return 0; 812 813 err_free: 814 dev_kfree_skb_any(skb); 815 816 return ret; 817 } 818 819 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 820 821 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 822 { 823 struct ath11k_dp *dp = &ab->dp; 824 struct sk_buff *skb; 825 struct htt_ver_req_cmd *cmd; 826 int len = sizeof(*cmd); 827 int ret; 828 829 init_completion(&dp->htt_tgt_version_received); 830 831 skb = ath11k_htc_alloc_skb(ab, len); 832 if (!skb) 833 return -ENOMEM; 834 835 skb_put(skb, len); 836 cmd = (struct htt_ver_req_cmd *)skb->data; 837 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 838 HTT_H2T_MSG_TYPE_VERSION_REQ); 839 840 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 841 if (ret) { 842 dev_kfree_skb_any(skb); 843 return ret; 844 } 845 846 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 847 HTT_TARGET_VERSION_TIMEOUT_HZ); 848 if (ret == 0) { 849 ath11k_warn(ab, "htt target version request timed out\n"); 850 return -ETIMEDOUT; 851 } 852 853 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 854 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 855 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 856 return -ENOTSUPP; 857 } 858 859 return 0; 860 } 861 862 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 863 { 864 struct ath11k_base *ab = ar->ab; 865 struct ath11k_dp *dp = &ab->dp; 866 struct sk_buff *skb; 867 struct htt_ppdu_stats_cfg_cmd *cmd; 868 int len = sizeof(*cmd); 869 u8 pdev_mask; 870 int ret; 871 872 skb = ath11k_htc_alloc_skb(ab, len); 873 if (!skb) 874 return -ENOMEM; 875 876 skb_put(skb, len); 877 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 878 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 879 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 880 881 pdev_mask = 1 << (ar->pdev_idx); 882 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 883 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 884 885 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 886 if (ret) { 887 dev_kfree_skb_any(skb); 888 return ret; 889 } 890 891 return 0; 892 } 893 894 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 895 int mac_id, enum hal_ring_type ring_type, 896 int rx_buf_size, 897 struct htt_rx_ring_tlv_filter *tlv_filter) 898 { 899 struct htt_rx_ring_selection_cfg_cmd *cmd; 900 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 901 struct hal_srng_params params; 902 struct sk_buff *skb; 903 int len = sizeof(*cmd); 904 enum htt_srng_ring_type htt_ring_type; 905 enum htt_srng_ring_id htt_ring_id; 906 int ret; 907 908 skb = ath11k_htc_alloc_skb(ab, len); 909 if (!skb) 910 return -ENOMEM; 911 912 memset(¶ms, 0, sizeof(params)); 913 ath11k_hal_srng_get_params(ab, srng, ¶ms); 914 915 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 916 ring_type, &htt_ring_type, 917 &htt_ring_id); 918 if (ret) 919 goto err_free; 920 921 skb_put(skb, len); 922 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 923 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 924 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 925 if (htt_ring_type == HTT_SW_TO_HW_RING || 926 htt_ring_type == HTT_HW_TO_SW_RING) 927 cmd->info0 |= 928 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 929 DP_SW2HW_MACID(mac_id)); 930 else 931 cmd->info0 |= 932 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 933 mac_id); 934 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 935 htt_ring_id); 936 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 937 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 938 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 939 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 940 941 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 942 rx_buf_size); 943 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 944 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 945 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 946 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 947 cmd->rx_filter_tlv = tlv_filter->rx_filter; 948 949 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 950 if (ret) 951 goto err_free; 952 953 return 0; 954 955 err_free: 956 dev_kfree_skb_any(skb); 957 958 return ret; 959 } 960 961 int 962 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 963 struct htt_ext_stats_cfg_params *cfg_params, 964 u64 cookie) 965 { 966 struct ath11k_base *ab = ar->ab; 967 struct ath11k_dp *dp = &ab->dp; 968 struct sk_buff *skb; 969 struct htt_ext_stats_cfg_cmd *cmd; 970 int len = sizeof(*cmd); 971 int ret; 972 973 skb = ath11k_htc_alloc_skb(ab, len); 974 if (!skb) 975 return -ENOMEM; 976 977 skb_put(skb, len); 978 979 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 980 memset(cmd, 0, sizeof(*cmd)); 981 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 982 983 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 984 985 cmd->hdr.stats_type = type; 986 cmd->cfg_param0 = cfg_params->cfg0; 987 cmd->cfg_param1 = cfg_params->cfg1; 988 cmd->cfg_param2 = cfg_params->cfg2; 989 cmd->cfg_param3 = cfg_params->cfg3; 990 cmd->cookie_lsb = lower_32_bits(cookie); 991 cmd->cookie_msb = upper_32_bits(cookie); 992 993 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 994 if (ret) { 995 ath11k_warn(ab, "failed to send htt type stats request: %d", 996 ret); 997 dev_kfree_skb_any(skb); 998 return ret; 999 } 1000 1001 return 0; 1002 } 1003 1004 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1005 { 1006 struct ath11k_pdev_dp *dp = &ar->dp; 1007 struct ath11k_base *ab = ar->ab; 1008 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1009 int ret = 0, ring_id = 0, i; 1010 1011 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1012 1013 if (!reset) { 1014 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1015 tlv_filter.pkt_filter_flags0 = 1016 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1017 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1018 tlv_filter.pkt_filter_flags1 = 1019 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1020 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1021 tlv_filter.pkt_filter_flags2 = 1022 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1023 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1024 tlv_filter.pkt_filter_flags3 = 1025 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1026 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1027 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1028 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1029 } 1030 1031 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1032 HAL_RXDMA_MONITOR_BUF, 1033 DP_RXDMA_REFILL_RING_SIZE, 1034 &tlv_filter); 1035 if (ret) 1036 return ret; 1037 1038 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1039 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1040 if (!reset) 1041 tlv_filter.rx_filter = 1042 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1043 else 1044 tlv_filter = ath11k_mac_mon_status_filter_default; 1045 1046 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1047 dp->mac_id + i, 1048 HAL_RXDMA_MONITOR_STATUS, 1049 DP_RXDMA_REFILL_RING_SIZE, 1050 &tlv_filter); 1051 } 1052 1053 return ret; 1054 } 1055