1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 #include "mac.h" 13 14 static enum hal_tcl_encap_type 15 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 16 { 17 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 18 struct ath11k_base *ab = arvif->ar->ab; 19 20 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 21 return HAL_TCL_ENCAP_TYPE_RAW; 22 23 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 24 return HAL_TCL_ENCAP_TYPE_ETHERNET; 25 26 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 27 } 28 29 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 30 { 31 struct ieee80211_hdr *hdr = (void *)skb->data; 32 u8 *qos_ctl; 33 34 if (!ieee80211_is_data_qos(hdr->frame_control)) 35 return; 36 37 qos_ctl = ieee80211_get_qos_ctl(hdr); 38 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 39 skb->data, (void *)qos_ctl - (void *)skb->data); 40 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 41 42 hdr = (void *)skb->data; 43 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 44 } 45 46 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 47 { 48 struct ieee80211_hdr *hdr = (void *)skb->data; 49 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 50 51 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 52 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 53 else if (!ieee80211_is_data_qos(hdr->frame_control)) 54 return HAL_DESC_REO_NON_QOS_TID; 55 else 56 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 57 } 58 59 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 60 { 61 switch (cipher) { 62 case WLAN_CIPHER_SUITE_WEP40: 63 return HAL_ENCRYPT_TYPE_WEP_40; 64 case WLAN_CIPHER_SUITE_WEP104: 65 return HAL_ENCRYPT_TYPE_WEP_104; 66 case WLAN_CIPHER_SUITE_TKIP: 67 return HAL_ENCRYPT_TYPE_TKIP_MIC; 68 case WLAN_CIPHER_SUITE_CCMP: 69 return HAL_ENCRYPT_TYPE_CCMP_128; 70 case WLAN_CIPHER_SUITE_CCMP_256: 71 return HAL_ENCRYPT_TYPE_CCMP_256; 72 case WLAN_CIPHER_SUITE_GCMP: 73 return HAL_ENCRYPT_TYPE_GCMP_128; 74 case WLAN_CIPHER_SUITE_GCMP_256: 75 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 76 default: 77 return HAL_ENCRYPT_TYPE_OPEN; 78 } 79 } 80 81 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 82 struct ath11k_sta *arsta, struct sk_buff *skb) 83 { 84 struct ath11k_base *ab = ar->ab; 85 struct ath11k_dp *dp = &ab->dp; 86 struct hal_tx_info ti = {0}; 87 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 88 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 89 struct hal_srng *tcl_ring; 90 struct ieee80211_hdr *hdr = (void *)skb->data; 91 struct dp_tx_ring *tx_ring; 92 void *hal_tcl_desc; 93 u8 pool_id; 94 u8 hal_ring_id; 95 int ret; 96 u8 ring_selector = 0, ring_map = 0; 97 bool tcl_ring_retry; 98 99 if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) 100 return -ESHUTDOWN; 101 102 if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 103 !ieee80211_is_data(hdr->frame_control))) 104 return -ENOTSUPP; 105 106 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 107 108 /* Let the default ring selection be based on current processor 109 * number, where one of the 3 tcl rings are selected based on 110 * the smp_processor_id(). In case that ring 111 * is full/busy, we resort to other available rings. 112 * If all rings are full, we drop the packet. 113 * //TODO Add throttling logic when all rings are full 114 */ 115 ring_selector = smp_processor_id(); 116 117 tcl_ring_sel: 118 tcl_ring_retry = false; 119 120 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; 121 122 ring_map |= BIT(ti.ring_id); 123 124 tx_ring = &dp->tx_ring[ti.ring_id]; 125 126 spin_lock_bh(&tx_ring->tx_idr_lock); 127 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 128 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 129 spin_unlock_bh(&tx_ring->tx_idr_lock); 130 131 if (unlikely(ret < 0)) { 132 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) { 133 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 134 return -ENOSPC; 135 } 136 137 /* Check if the next ring is available */ 138 ring_selector++; 139 goto tcl_ring_sel; 140 } 141 142 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 143 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 144 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 145 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 146 147 if (ieee80211_has_a4(hdr->frame_control) && 148 is_multicast_ether_addr(hdr->addr3) && arsta && 149 arsta->use_4addr_set) { 150 ti.meta_data_flags = arsta->tcl_metadata; 151 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 152 } else { 153 ti.meta_data_flags = arvif->tcl_metadata; 154 } 155 156 if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) { 157 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 158 ti.encrypt_type = 159 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 160 161 if (ieee80211_has_protected(hdr->frame_control)) 162 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 163 } else { 164 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 165 } 166 } 167 168 ti.addr_search_flags = arvif->hal_addr_search_flags; 169 ti.search_type = arvif->search_type; 170 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 171 ti.pkt_offset = 0; 172 ti.lmac_id = ar->lmac_id; 173 ti.bss_ast_hash = arvif->ast_hash; 174 ti.bss_ast_idx = arvif->ast_idx; 175 ti.dscp_tid_tbl_idx = 0; 176 177 if (likely(skb->ip_summed == CHECKSUM_PARTIAL && 178 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) { 179 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 180 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 181 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 182 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 183 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 184 } 185 186 if (ieee80211_vif_is_mesh(arvif->vif)) 187 ti.enable_mesh = true; 188 189 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 190 191 ti.tid = ath11k_dp_tx_get_tid(skb); 192 193 switch (ti.encap_type) { 194 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 195 ath11k_dp_tx_encap_nwifi(skb); 196 break; 197 case HAL_TCL_ENCAP_TYPE_RAW: 198 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 199 ret = -EINVAL; 200 goto fail_remove_idr; 201 } 202 break; 203 case HAL_TCL_ENCAP_TYPE_ETHERNET: 204 /* no need to encap */ 205 break; 206 case HAL_TCL_ENCAP_TYPE_802_3: 207 default: 208 /* TODO: Take care of other encap modes as well */ 209 ret = -EINVAL; 210 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 211 goto fail_remove_idr; 212 } 213 214 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 215 if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { 216 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 217 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 218 ret = -ENOMEM; 219 goto fail_remove_idr; 220 } 221 222 ti.data_len = skb->len; 223 skb_cb->paddr = ti.paddr; 224 skb_cb->vif = arvif->vif; 225 skb_cb->ar = ar; 226 227 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 228 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 229 230 spin_lock_bh(&tcl_ring->lock); 231 232 ath11k_hal_srng_access_begin(ab, tcl_ring); 233 234 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 235 if (unlikely(!hal_tcl_desc)) { 236 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 237 * desc because the desc is directly enqueued onto hw queue. 238 */ 239 ath11k_hal_srng_access_end(ab, tcl_ring); 240 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 241 spin_unlock_bh(&tcl_ring->lock); 242 ret = -ENOMEM; 243 244 /* Checking for available tcl descritors in another ring in 245 * case of failure due to full tcl ring now, is better than 246 * checking this ring earlier for each pkt tx. 247 * Restart ring selection if some rings are not checked yet. 248 */ 249 if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) && 250 ab->hw_params.max_tx_ring > 1) { 251 tcl_ring_retry = true; 252 ring_selector++; 253 } 254 255 goto fail_unmap_dma; 256 } 257 258 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 259 sizeof(struct hal_tlv_hdr), &ti); 260 261 ath11k_hal_srng_access_end(ab, tcl_ring); 262 263 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 264 265 spin_unlock_bh(&tcl_ring->lock); 266 267 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 268 skb->data, skb->len); 269 270 atomic_inc(&ar->dp.num_tx_pending); 271 272 return 0; 273 274 fail_unmap_dma: 275 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 276 277 fail_remove_idr: 278 spin_lock_bh(&tx_ring->tx_idr_lock); 279 idr_remove(&tx_ring->txbuf_idr, 280 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 281 spin_unlock_bh(&tx_ring->tx_idr_lock); 282 283 if (tcl_ring_retry) 284 goto tcl_ring_sel; 285 286 return ret; 287 } 288 289 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 290 int msdu_id, 291 struct dp_tx_ring *tx_ring) 292 { 293 struct ath11k *ar; 294 struct sk_buff *msdu; 295 struct ath11k_skb_cb *skb_cb; 296 297 spin_lock(&tx_ring->tx_idr_lock); 298 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 299 spin_unlock(&tx_ring->tx_idr_lock); 300 301 if (unlikely(!msdu)) { 302 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 303 msdu_id); 304 return; 305 } 306 307 skb_cb = ATH11K_SKB_CB(msdu); 308 309 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 310 dev_kfree_skb_any(msdu); 311 312 ar = ab->pdevs[mac_id].ar; 313 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 314 wake_up(&ar->dp.tx_empty_waitq); 315 } 316 317 static void 318 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 319 struct dp_tx_ring *tx_ring, 320 struct ath11k_dp_htt_wbm_tx_status *ts) 321 { 322 struct sk_buff *msdu; 323 struct ieee80211_tx_info *info; 324 struct ath11k_skb_cb *skb_cb; 325 struct ath11k *ar; 326 327 spin_lock(&tx_ring->tx_idr_lock); 328 msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 329 spin_unlock(&tx_ring->tx_idr_lock); 330 331 if (unlikely(!msdu)) { 332 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 333 ts->msdu_id); 334 return; 335 } 336 337 skb_cb = ATH11K_SKB_CB(msdu); 338 info = IEEE80211_SKB_CB(msdu); 339 340 ar = skb_cb->ar; 341 342 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 343 wake_up(&ar->dp.tx_empty_waitq); 344 345 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 346 347 memset(&info->status, 0, sizeof(info->status)); 348 349 if (ts->acked) { 350 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 351 info->flags |= IEEE80211_TX_STAT_ACK; 352 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 353 ts->ack_rssi; 354 info->status.flags |= 355 IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 356 } else { 357 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 358 } 359 } 360 361 ieee80211_tx_status(ar->hw, msdu); 362 } 363 364 static void 365 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 366 void *desc, u8 mac_id, 367 u32 msdu_id, struct dp_tx_ring *tx_ring) 368 { 369 struct htt_tx_wbm_completion *status_desc; 370 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 371 enum hal_wbm_htt_tx_comp_status wbm_status; 372 373 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 374 375 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 376 status_desc->info0); 377 switch (wbm_status) { 378 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 379 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 380 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 381 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 382 ts.msdu_id = msdu_id; 383 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 384 status_desc->info1); 385 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 386 break; 387 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 388 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 389 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 390 break; 391 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 392 /* This event is to be handled only when the driver decides to 393 * use WDS offload functionality. 394 */ 395 break; 396 default: 397 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 398 break; 399 } 400 } 401 402 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 403 struct sk_buff *msdu, 404 struct hal_tx_status *ts) 405 { 406 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 407 408 if (ts->try_cnt > 1) { 409 peer_stats->retry_pkts += ts->try_cnt - 1; 410 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 411 412 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 413 peer_stats->failed_pkts += 1; 414 peer_stats->failed_bytes += msdu->len; 415 } 416 } 417 } 418 419 void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts) 420 { 421 struct ath11k_base *ab = ar->ab; 422 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 423 enum hal_tx_rate_stats_pkt_type pkt_type; 424 enum hal_tx_rate_stats_sgi sgi; 425 enum hal_tx_rate_stats_bw bw; 426 struct ath11k_peer *peer; 427 struct ath11k_sta *arsta; 428 struct ieee80211_sta *sta; 429 u16 rate, ru_tones; 430 u8 mcs, rate_idx, ofdma; 431 int ret; 432 433 spin_lock_bh(&ab->base_lock); 434 peer = ath11k_peer_find_by_id(ab, ts->peer_id); 435 if (!peer || !peer->sta) { 436 ath11k_dbg(ab, ATH11K_DBG_DP_TX, 437 "failed to find the peer by id %u\n", ts->peer_id); 438 goto err_out; 439 } 440 441 sta = peer->sta; 442 arsta = (struct ath11k_sta *)sta->drv_priv; 443 444 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 445 pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE, 446 ts->rate_stats); 447 mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS, 448 ts->rate_stats); 449 sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI, 450 ts->rate_stats); 451 bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats); 452 ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats); 453 ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats); 454 455 /* This is to prefer choose the real NSS value arsta->last_txrate.nss, 456 * if it is invalid, then choose the NSS value while assoc. 457 */ 458 if (arsta->last_txrate.nss) 459 arsta->txrate.nss = arsta->last_txrate.nss; 460 else 461 arsta->txrate.nss = arsta->peer_nss; 462 463 if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A || 464 pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) { 465 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 466 pkt_type, 467 &rate_idx, 468 &rate); 469 if (ret < 0) 470 goto err_out; 471 arsta->txrate.legacy = rate; 472 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) { 473 if (mcs > 7) { 474 ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs); 475 goto err_out; 476 } 477 478 if (arsta->txrate.nss != 0) 479 arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1); 480 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 481 if (sgi) 482 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 483 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) { 484 if (mcs > 9) { 485 ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs); 486 goto err_out; 487 } 488 489 arsta->txrate.mcs = mcs; 490 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 491 if (sgi) 492 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 493 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 494 if (mcs > 11) { 495 ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs); 496 goto err_out; 497 } 498 499 arsta->txrate.mcs = mcs; 500 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 501 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 502 } 503 504 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 505 if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 506 arsta->txrate.bw = RATE_INFO_BW_HE_RU; 507 arsta->txrate.he_ru_alloc = 508 ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 509 } 510 511 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 512 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 513 514 err_out: 515 spin_unlock_bh(&ab->base_lock); 516 } 517 518 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 519 struct sk_buff *msdu, 520 struct hal_tx_status *ts) 521 { 522 struct ath11k_base *ab = ar->ab; 523 struct ieee80211_tx_info *info; 524 struct ath11k_skb_cb *skb_cb; 525 526 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 527 /* Must not happen */ 528 return; 529 } 530 531 skb_cb = ATH11K_SKB_CB(msdu); 532 533 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 534 535 if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { 536 dev_kfree_skb_any(msdu); 537 return; 538 } 539 540 if (unlikely(!skb_cb->vif)) { 541 dev_kfree_skb_any(msdu); 542 return; 543 } 544 545 info = IEEE80211_SKB_CB(msdu); 546 memset(&info->status, 0, sizeof(info->status)); 547 548 /* skip tx rate update from ieee80211_status*/ 549 info->status.rates[0].idx = -1; 550 551 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 552 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 553 info->flags |= IEEE80211_TX_STAT_ACK; 554 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 555 ts->ack_rssi; 556 info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 557 } 558 559 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 560 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 561 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 562 563 if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) || 564 ab->hw_params.single_pdev_only) { 565 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 566 if (ar->last_ppdu_id == 0) { 567 ar->last_ppdu_id = ts->ppdu_id; 568 } else if (ar->last_ppdu_id == ts->ppdu_id || 569 ar->cached_ppdu_id == ar->last_ppdu_id) { 570 ar->cached_ppdu_id = ar->last_ppdu_id; 571 ar->cached_stats.is_ampdu = true; 572 ath11k_dp_tx_update_txcompl(ar, ts); 573 memset(&ar->cached_stats, 0, 574 sizeof(struct ath11k_per_peer_tx_stats)); 575 } else { 576 ar->cached_stats.is_ampdu = false; 577 ath11k_dp_tx_update_txcompl(ar, ts); 578 memset(&ar->cached_stats, 0, 579 sizeof(struct ath11k_per_peer_tx_stats)); 580 } 581 ar->last_ppdu_id = ts->ppdu_id; 582 } 583 584 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 585 } 586 587 /* NOTE: Tx rate status reporting. Tx completion status does not have 588 * necessary information (for example nss) to build the tx rate. 589 * Might end up reporting it out-of-band from HTT stats. 590 */ 591 592 ieee80211_tx_status(ar->hw, msdu); 593 } 594 595 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 596 struct hal_wbm_release_ring *desc, 597 struct hal_tx_status *ts) 598 { 599 ts->buf_rel_source = 600 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 601 if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 602 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) 603 return; 604 605 if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) 606 return; 607 608 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 609 desc->info0); 610 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 611 desc->info1); 612 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 613 desc->info1); 614 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 615 desc->info2); 616 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 617 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 618 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 619 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 620 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 621 ts->rate_stats = desc->rate_stats.info0; 622 else 623 ts->rate_stats = 0; 624 } 625 626 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 627 { 628 struct ath11k *ar; 629 struct ath11k_dp *dp = &ab->dp; 630 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 631 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 632 struct sk_buff *msdu; 633 struct hal_tx_status ts = { 0 }; 634 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 635 u32 *desc; 636 u32 msdu_id; 637 u8 mac_id; 638 639 spin_lock_bh(&status_ring->lock); 640 641 ath11k_hal_srng_access_begin(ab, status_ring); 642 643 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 644 tx_ring->tx_status_tail) && 645 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 646 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 647 desc, sizeof(struct hal_wbm_release_ring)); 648 tx_ring->tx_status_head = 649 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 650 } 651 652 if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 653 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == 654 tx_ring->tx_status_tail))) { 655 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 656 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 657 } 658 659 ath11k_hal_srng_access_end(ab, status_ring); 660 661 spin_unlock_bh(&status_ring->lock); 662 663 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 664 struct hal_wbm_release_ring *tx_status; 665 u32 desc_id; 666 667 tx_ring->tx_status_tail = 668 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 669 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 670 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 671 672 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 673 tx_status->buf_addr_info.info1); 674 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 675 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 676 677 if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { 678 ath11k_dp_tx_process_htt_tx_complete(ab, 679 (void *)tx_status, 680 mac_id, msdu_id, 681 tx_ring); 682 continue; 683 } 684 685 spin_lock(&tx_ring->tx_idr_lock); 686 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 687 if (unlikely(!msdu)) { 688 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 689 msdu_id); 690 spin_unlock(&tx_ring->tx_idr_lock); 691 continue; 692 } 693 694 spin_unlock(&tx_ring->tx_idr_lock); 695 696 ar = ab->pdevs[mac_id].ar; 697 698 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 699 wake_up(&ar->dp.tx_empty_waitq); 700 701 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 702 } 703 } 704 705 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 706 enum hal_reo_cmd_type type, 707 struct ath11k_hal_reo_cmd *cmd, 708 void (*cb)(struct ath11k_dp *, void *, 709 enum hal_reo_cmd_status)) 710 { 711 struct ath11k_dp *dp = &ab->dp; 712 struct dp_reo_cmd *dp_cmd; 713 struct hal_srng *cmd_ring; 714 int cmd_num; 715 716 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 717 return -ESHUTDOWN; 718 719 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 720 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 721 722 /* cmd_num should start from 1, during failure return the error code */ 723 if (cmd_num < 0) 724 return cmd_num; 725 726 /* reo cmd ring descriptors has cmd_num starting from 1 */ 727 if (cmd_num == 0) 728 return -EINVAL; 729 730 if (!cb) 731 return 0; 732 733 /* Can this be optimized so that we keep the pending command list only 734 * for tid delete command to free up the resoruce on the command status 735 * indication? 736 */ 737 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 738 739 if (!dp_cmd) 740 return -ENOMEM; 741 742 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 743 dp_cmd->cmd_num = cmd_num; 744 dp_cmd->handler = cb; 745 746 spin_lock_bh(&dp->reo_cmd_lock); 747 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 748 spin_unlock_bh(&dp->reo_cmd_lock); 749 750 return 0; 751 } 752 753 static int 754 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 755 int mac_id, u32 ring_id, 756 enum hal_ring_type ring_type, 757 enum htt_srng_ring_type *htt_ring_type, 758 enum htt_srng_ring_id *htt_ring_id) 759 { 760 int lmac_ring_id_offset = 0; 761 int ret = 0; 762 763 switch (ring_type) { 764 case HAL_RXDMA_BUF: 765 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 766 767 /* for QCA6390, host fills rx buffer to fw and fw fills to 768 * rxbuf ring for each rxdma 769 */ 770 if (!ab->hw_params.rx_mac_buf_ring) { 771 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 772 lmac_ring_id_offset) || 773 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 774 lmac_ring_id_offset))) { 775 ret = -EINVAL; 776 } 777 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 778 *htt_ring_type = HTT_SW_TO_HW_RING; 779 } else { 780 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 781 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 782 *htt_ring_type = HTT_SW_TO_SW_RING; 783 } else { 784 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 785 *htt_ring_type = HTT_SW_TO_HW_RING; 786 } 787 } 788 break; 789 case HAL_RXDMA_DST: 790 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 791 *htt_ring_type = HTT_HW_TO_SW_RING; 792 break; 793 case HAL_RXDMA_MONITOR_BUF: 794 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 795 *htt_ring_type = HTT_SW_TO_HW_RING; 796 break; 797 case HAL_RXDMA_MONITOR_STATUS: 798 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 799 *htt_ring_type = HTT_SW_TO_HW_RING; 800 break; 801 case HAL_RXDMA_MONITOR_DST: 802 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 803 *htt_ring_type = HTT_HW_TO_SW_RING; 804 break; 805 case HAL_RXDMA_MONITOR_DESC: 806 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 807 *htt_ring_type = HTT_SW_TO_HW_RING; 808 break; 809 default: 810 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 811 ret = -EINVAL; 812 } 813 return ret; 814 } 815 816 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 817 int mac_id, enum hal_ring_type ring_type) 818 { 819 struct htt_srng_setup_cmd *cmd; 820 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 821 struct hal_srng_params params; 822 struct sk_buff *skb; 823 u32 ring_entry_sz; 824 int len = sizeof(*cmd); 825 dma_addr_t hp_addr, tp_addr; 826 enum htt_srng_ring_type htt_ring_type; 827 enum htt_srng_ring_id htt_ring_id; 828 int ret; 829 830 skb = ath11k_htc_alloc_skb(ab, len); 831 if (!skb) 832 return -ENOMEM; 833 834 memset(¶ms, 0, sizeof(params)); 835 ath11k_hal_srng_get_params(ab, srng, ¶ms); 836 837 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 838 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 839 840 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 841 ring_type, &htt_ring_type, 842 &htt_ring_id); 843 if (ret) 844 goto err_free; 845 846 skb_put(skb, len); 847 cmd = (struct htt_srng_setup_cmd *)skb->data; 848 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 849 HTT_H2T_MSG_TYPE_SRING_SETUP); 850 if (htt_ring_type == HTT_SW_TO_HW_RING || 851 htt_ring_type == HTT_HW_TO_SW_RING) 852 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 853 DP_SW2HW_MACID(mac_id)); 854 else 855 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 856 mac_id); 857 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 858 htt_ring_type); 859 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 860 861 cmd->ring_base_addr_lo = params.ring_base_paddr & 862 HAL_ADDR_LSB_REG_MASK; 863 864 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 865 HAL_ADDR_MSB_REG_SHIFT; 866 867 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 868 if (ret < 0) 869 goto err_free; 870 871 ring_entry_sz = ret; 872 873 ring_entry_sz >>= 2; 874 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 875 ring_entry_sz); 876 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 877 params.num_entries * ring_entry_sz); 878 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 879 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 880 cmd->info1 |= FIELD_PREP( 881 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 882 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 883 cmd->info1 |= FIELD_PREP( 884 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 885 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 886 if (htt_ring_type == HTT_SW_TO_HW_RING) 887 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 888 889 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 890 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 891 HAL_ADDR_MSB_REG_SHIFT; 892 893 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 894 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 895 HAL_ADDR_MSB_REG_SHIFT; 896 897 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 898 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 899 cmd->msi_data = params.msi_data; 900 901 cmd->intr_info = FIELD_PREP( 902 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 903 params.intr_batch_cntr_thres_entries * ring_entry_sz); 904 cmd->intr_info |= FIELD_PREP( 905 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 906 params.intr_timer_thres_us >> 3); 907 908 cmd->info2 = 0; 909 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 910 cmd->info2 = FIELD_PREP( 911 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 912 params.low_threshold); 913 } 914 915 ath11k_dbg(ab, ATH11k_DBG_HAL, 916 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 917 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 918 cmd->msi_data); 919 920 ath11k_dbg(ab, ATH11k_DBG_HAL, 921 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 922 ring_id, ring_type, cmd->intr_info, cmd->info2); 923 924 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 925 if (ret) 926 goto err_free; 927 928 return 0; 929 930 err_free: 931 dev_kfree_skb_any(skb); 932 933 return ret; 934 } 935 936 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 937 938 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 939 { 940 struct ath11k_dp *dp = &ab->dp; 941 struct sk_buff *skb; 942 struct htt_ver_req_cmd *cmd; 943 int len = sizeof(*cmd); 944 int ret; 945 946 init_completion(&dp->htt_tgt_version_received); 947 948 skb = ath11k_htc_alloc_skb(ab, len); 949 if (!skb) 950 return -ENOMEM; 951 952 skb_put(skb, len); 953 cmd = (struct htt_ver_req_cmd *)skb->data; 954 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 955 HTT_H2T_MSG_TYPE_VERSION_REQ); 956 957 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 958 if (ret) { 959 dev_kfree_skb_any(skb); 960 return ret; 961 } 962 963 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 964 HTT_TARGET_VERSION_TIMEOUT_HZ); 965 if (ret == 0) { 966 ath11k_warn(ab, "htt target version request timed out\n"); 967 return -ETIMEDOUT; 968 } 969 970 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 971 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 972 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 973 return -ENOTSUPP; 974 } 975 976 return 0; 977 } 978 979 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 980 { 981 struct ath11k_base *ab = ar->ab; 982 struct ath11k_dp *dp = &ab->dp; 983 struct sk_buff *skb; 984 struct htt_ppdu_stats_cfg_cmd *cmd; 985 int len = sizeof(*cmd); 986 u8 pdev_mask; 987 int ret; 988 int i; 989 990 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 991 skb = ath11k_htc_alloc_skb(ab, len); 992 if (!skb) 993 return -ENOMEM; 994 995 skb_put(skb, len); 996 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 997 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 998 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 999 1000 pdev_mask = 1 << (ar->pdev_idx + i); 1001 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 1002 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 1003 1004 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1005 if (ret) { 1006 dev_kfree_skb_any(skb); 1007 return ret; 1008 } 1009 } 1010 1011 return 0; 1012 } 1013 1014 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 1015 int mac_id, enum hal_ring_type ring_type, 1016 int rx_buf_size, 1017 struct htt_rx_ring_tlv_filter *tlv_filter) 1018 { 1019 struct htt_rx_ring_selection_cfg_cmd *cmd; 1020 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1021 struct hal_srng_params params; 1022 struct sk_buff *skb; 1023 int len = sizeof(*cmd); 1024 enum htt_srng_ring_type htt_ring_type; 1025 enum htt_srng_ring_id htt_ring_id; 1026 int ret; 1027 1028 skb = ath11k_htc_alloc_skb(ab, len); 1029 if (!skb) 1030 return -ENOMEM; 1031 1032 memset(¶ms, 0, sizeof(params)); 1033 ath11k_hal_srng_get_params(ab, srng, ¶ms); 1034 1035 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1036 ring_type, &htt_ring_type, 1037 &htt_ring_id); 1038 if (ret) 1039 goto err_free; 1040 1041 skb_put(skb, len); 1042 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 1043 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 1044 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 1045 if (htt_ring_type == HTT_SW_TO_HW_RING || 1046 htt_ring_type == HTT_HW_TO_SW_RING) 1047 cmd->info0 |= 1048 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 1049 DP_SW2HW_MACID(mac_id)); 1050 else 1051 cmd->info0 |= 1052 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 1053 mac_id); 1054 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 1055 htt_ring_id); 1056 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 1057 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 1058 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 1059 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 1060 1061 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 1062 rx_buf_size); 1063 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 1064 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 1065 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 1066 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 1067 cmd->rx_filter_tlv = tlv_filter->rx_filter; 1068 1069 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 1070 if (ret) 1071 goto err_free; 1072 1073 return 0; 1074 1075 err_free: 1076 dev_kfree_skb_any(skb); 1077 1078 return ret; 1079 } 1080 1081 int 1082 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 1083 struct htt_ext_stats_cfg_params *cfg_params, 1084 u64 cookie) 1085 { 1086 struct ath11k_base *ab = ar->ab; 1087 struct ath11k_dp *dp = &ab->dp; 1088 struct sk_buff *skb; 1089 struct htt_ext_stats_cfg_cmd *cmd; 1090 u32 pdev_id; 1091 int len = sizeof(*cmd); 1092 int ret; 1093 1094 skb = ath11k_htc_alloc_skb(ab, len); 1095 if (!skb) 1096 return -ENOMEM; 1097 1098 skb_put(skb, len); 1099 1100 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1101 memset(cmd, 0, sizeof(*cmd)); 1102 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1103 1104 if (ab->hw_params.single_pdev_only) 1105 pdev_id = ath11k_mac_get_target_pdev_id(ar); 1106 else 1107 pdev_id = ar->pdev->pdev_id; 1108 1109 cmd->hdr.pdev_mask = 1 << pdev_id; 1110 1111 cmd->hdr.stats_type = type; 1112 cmd->cfg_param0 = cfg_params->cfg0; 1113 cmd->cfg_param1 = cfg_params->cfg1; 1114 cmd->cfg_param2 = cfg_params->cfg2; 1115 cmd->cfg_param3 = cfg_params->cfg3; 1116 cmd->cookie_lsb = lower_32_bits(cookie); 1117 cmd->cookie_msb = upper_32_bits(cookie); 1118 1119 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1120 if (ret) { 1121 ath11k_warn(ab, "failed to send htt type stats request: %d", 1122 ret); 1123 dev_kfree_skb_any(skb); 1124 return ret; 1125 } 1126 1127 return 0; 1128 } 1129 1130 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1131 { 1132 struct ath11k_pdev_dp *dp = &ar->dp; 1133 struct ath11k_base *ab = ar->ab; 1134 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1135 int ret = 0, ring_id = 0, i; 1136 1137 if (ab->hw_params.full_monitor_mode) { 1138 ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab, 1139 dp->mac_id, !reset); 1140 if (ret < 0) { 1141 ath11k_err(ab, "failed to setup full monitor %d\n", ret); 1142 return ret; 1143 } 1144 } 1145 1146 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1147 1148 if (!reset) { 1149 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1150 tlv_filter.pkt_filter_flags0 = 1151 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1152 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1153 tlv_filter.pkt_filter_flags1 = 1154 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1155 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1156 tlv_filter.pkt_filter_flags2 = 1157 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1158 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1159 tlv_filter.pkt_filter_flags3 = 1160 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1161 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1162 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1163 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1164 } 1165 1166 if (ab->hw_params.rxdma1_enable) { 1167 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1168 HAL_RXDMA_MONITOR_BUF, 1169 DP_RXDMA_REFILL_RING_SIZE, 1170 &tlv_filter); 1171 } else if (!reset) { 1172 /* set in monitor mode only */ 1173 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1174 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1175 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1176 dp->mac_id + i, 1177 HAL_RXDMA_BUF, 1178 1024, 1179 &tlv_filter); 1180 } 1181 } 1182 1183 if (ret) 1184 return ret; 1185 1186 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1187 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1188 if (!reset) { 1189 tlv_filter.rx_filter = 1190 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1191 } else { 1192 tlv_filter = ath11k_mac_mon_status_filter_default; 1193 1194 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1195 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1196 } 1197 1198 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1199 dp->mac_id + i, 1200 HAL_RXDMA_MONITOR_STATUS, 1201 DP_RXDMA_REFILL_RING_SIZE, 1202 &tlv_filter); 1203 } 1204 1205 if (!ar->ab->hw_params.rxdma1_enable) 1206 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1207 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1208 1209 return ret; 1210 } 1211 1212 int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id, 1213 bool config) 1214 { 1215 struct htt_rx_full_monitor_mode_cfg_cmd *cmd; 1216 struct sk_buff *skb; 1217 int ret, len = sizeof(*cmd); 1218 1219 skb = ath11k_htc_alloc_skb(ab, len); 1220 if (!skb) 1221 return -ENOMEM; 1222 1223 skb_put(skb, len); 1224 cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data; 1225 memset(cmd, 0, sizeof(*cmd)); 1226 cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE, 1227 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE); 1228 1229 cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id); 1230 1231 cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE | 1232 FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING, 1233 HTT_RX_MON_RING_SW); 1234 if (config) { 1235 cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END | 1236 HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END; 1237 } 1238 1239 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 1240 if (ret) 1241 goto err_free; 1242 1243 return 0; 1244 1245 err_free: 1246 dev_kfree_skb_any(skb); 1247 1248 return ret; 1249 } 1250