1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 13 static enum hal_tcl_encap_type 14 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15 { 16 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17 struct ath11k_base *ab = arvif->ar->ab; 18 19 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20 return HAL_TCL_ENCAP_TYPE_RAW; 21 22 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23 return HAL_TCL_ENCAP_TYPE_ETHERNET; 24 25 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26 } 27 28 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29 { 30 struct ieee80211_hdr *hdr = (void *)skb->data; 31 u8 *qos_ctl; 32 33 if (!ieee80211_is_data_qos(hdr->frame_control)) 34 return; 35 36 qos_ctl = ieee80211_get_qos_ctl(hdr); 37 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38 skb->data, (void *)qos_ctl - (void *)skb->data); 39 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40 41 hdr = (void *)skb->data; 42 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43 } 44 45 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46 { 47 struct ieee80211_hdr *hdr = (void *)skb->data; 48 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49 50 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52 else if (!ieee80211_is_data_qos(hdr->frame_control)) 53 return HAL_DESC_REO_NON_QOS_TID; 54 else 55 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56 } 57 58 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59 { 60 switch (cipher) { 61 case WLAN_CIPHER_SUITE_WEP40: 62 return HAL_ENCRYPT_TYPE_WEP_40; 63 case WLAN_CIPHER_SUITE_WEP104: 64 return HAL_ENCRYPT_TYPE_WEP_104; 65 case WLAN_CIPHER_SUITE_TKIP: 66 return HAL_ENCRYPT_TYPE_TKIP_MIC; 67 case WLAN_CIPHER_SUITE_CCMP: 68 return HAL_ENCRYPT_TYPE_CCMP_128; 69 case WLAN_CIPHER_SUITE_CCMP_256: 70 return HAL_ENCRYPT_TYPE_CCMP_256; 71 case WLAN_CIPHER_SUITE_GCMP: 72 return HAL_ENCRYPT_TYPE_GCMP_128; 73 case WLAN_CIPHER_SUITE_GCMP_256: 74 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75 default: 76 return HAL_ENCRYPT_TYPE_OPEN; 77 } 78 } 79 80 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81 struct ath11k_sta *arsta, struct sk_buff *skb) 82 { 83 struct ath11k_base *ab = ar->ab; 84 struct ath11k_dp *dp = &ab->dp; 85 struct hal_tx_info ti = {0}; 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 88 struct hal_srng *tcl_ring; 89 struct ieee80211_hdr *hdr = (void *)skb->data; 90 struct dp_tx_ring *tx_ring; 91 void *hal_tcl_desc; 92 u8 pool_id; 93 u8 hal_ring_id; 94 int ret; 95 u8 ring_selector = 0, ring_map = 0; 96 bool tcl_ring_retry; 97 98 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 99 return -ESHUTDOWN; 100 101 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 102 !ieee80211_is_data(hdr->frame_control)) 103 return -ENOTSUPP; 104 105 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 106 107 /* Let the default ring selection be based on current processor 108 * number, where one of the 3 tcl rings are selected based on 109 * the smp_processor_id(). In case that ring 110 * is full/busy, we resort to other available rings. 111 * If all rings are full, we drop the packet. 112 * //TODO Add throttling logic when all rings are full 113 */ 114 ring_selector = smp_processor_id(); 115 116 tcl_ring_sel: 117 tcl_ring_retry = false; 118 119 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; 120 121 ring_map |= BIT(ti.ring_id); 122 123 tx_ring = &dp->tx_ring[ti.ring_id]; 124 125 spin_lock_bh(&tx_ring->tx_idr_lock); 126 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 127 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 128 spin_unlock_bh(&tx_ring->tx_idr_lock); 129 130 if (ret < 0) { 131 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) { 132 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 133 return -ENOSPC; 134 } 135 136 /* Check if the next ring is available */ 137 ring_selector++; 138 goto tcl_ring_sel; 139 } 140 141 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 142 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 143 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 144 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 145 146 if (ieee80211_has_a4(hdr->frame_control) && 147 is_multicast_ether_addr(hdr->addr3) && arsta && 148 arsta->use_4addr_set) { 149 ti.meta_data_flags = arsta->tcl_metadata; 150 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 151 } else { 152 ti.meta_data_flags = arvif->tcl_metadata; 153 } 154 155 if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) { 156 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 157 ti.encrypt_type = 158 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 159 160 if (ieee80211_has_protected(hdr->frame_control)) 161 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 162 } else { 163 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 164 } 165 } 166 167 ti.addr_search_flags = arvif->hal_addr_search_flags; 168 ti.search_type = arvif->search_type; 169 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 170 ti.pkt_offset = 0; 171 ti.lmac_id = ar->lmac_id; 172 ti.bss_ast_hash = arvif->ast_hash; 173 ti.bss_ast_idx = arvif->ast_idx; 174 ti.dscp_tid_tbl_idx = 0; 175 176 if (skb->ip_summed == CHECKSUM_PARTIAL && 177 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 178 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 179 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 180 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 181 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 182 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 183 } 184 185 if (ieee80211_vif_is_mesh(arvif->vif)) 186 ti.enable_mesh = true; 187 188 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 189 190 ti.tid = ath11k_dp_tx_get_tid(skb); 191 192 switch (ti.encap_type) { 193 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 194 ath11k_dp_tx_encap_nwifi(skb); 195 break; 196 case HAL_TCL_ENCAP_TYPE_RAW: 197 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 198 ret = -EINVAL; 199 goto fail_remove_idr; 200 } 201 break; 202 case HAL_TCL_ENCAP_TYPE_ETHERNET: 203 /* no need to encap */ 204 break; 205 case HAL_TCL_ENCAP_TYPE_802_3: 206 default: 207 /* TODO: Take care of other encap modes as well */ 208 ret = -EINVAL; 209 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 210 goto fail_remove_idr; 211 } 212 213 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 214 if (dma_mapping_error(ab->dev, ti.paddr)) { 215 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 216 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 217 ret = -ENOMEM; 218 goto fail_remove_idr; 219 } 220 221 ti.data_len = skb->len; 222 skb_cb->paddr = ti.paddr; 223 skb_cb->vif = arvif->vif; 224 skb_cb->ar = ar; 225 226 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 227 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 228 229 spin_lock_bh(&tcl_ring->lock); 230 231 ath11k_hal_srng_access_begin(ab, tcl_ring); 232 233 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 234 if (!hal_tcl_desc) { 235 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 236 * desc because the desc is directly enqueued onto hw queue. 237 */ 238 ath11k_hal_srng_access_end(ab, tcl_ring); 239 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 240 spin_unlock_bh(&tcl_ring->lock); 241 ret = -ENOMEM; 242 243 /* Checking for available tcl descritors in another ring in 244 * case of failure due to full tcl ring now, is better than 245 * checking this ring earlier for each pkt tx. 246 * Restart ring selection if some rings are not checked yet. 247 */ 248 if (ring_map != (BIT(ab->hw_params.max_tx_ring) - 1) && 249 ab->hw_params.max_tx_ring > 1) { 250 tcl_ring_retry = true; 251 ring_selector++; 252 } 253 254 goto fail_unmap_dma; 255 } 256 257 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 258 sizeof(struct hal_tlv_hdr), &ti); 259 260 ath11k_hal_srng_access_end(ab, tcl_ring); 261 262 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 263 264 spin_unlock_bh(&tcl_ring->lock); 265 266 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 267 skb->data, skb->len); 268 269 atomic_inc(&ar->dp.num_tx_pending); 270 271 return 0; 272 273 fail_unmap_dma: 274 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 275 276 fail_remove_idr: 277 spin_lock_bh(&tx_ring->tx_idr_lock); 278 idr_remove(&tx_ring->txbuf_idr, 279 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 280 spin_unlock_bh(&tx_ring->tx_idr_lock); 281 282 if (tcl_ring_retry) 283 goto tcl_ring_sel; 284 285 return ret; 286 } 287 288 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 289 int msdu_id, 290 struct dp_tx_ring *tx_ring) 291 { 292 struct ath11k *ar; 293 struct sk_buff *msdu; 294 struct ath11k_skb_cb *skb_cb; 295 296 spin_lock_bh(&tx_ring->tx_idr_lock); 297 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 298 if (!msdu) { 299 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 300 msdu_id); 301 spin_unlock_bh(&tx_ring->tx_idr_lock); 302 return; 303 } 304 305 skb_cb = ATH11K_SKB_CB(msdu); 306 307 idr_remove(&tx_ring->txbuf_idr, msdu_id); 308 spin_unlock_bh(&tx_ring->tx_idr_lock); 309 310 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 311 dev_kfree_skb_any(msdu); 312 313 ar = ab->pdevs[mac_id].ar; 314 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 315 wake_up(&ar->dp.tx_empty_waitq); 316 } 317 318 static void 319 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 320 struct dp_tx_ring *tx_ring, 321 struct ath11k_dp_htt_wbm_tx_status *ts) 322 { 323 struct sk_buff *msdu; 324 struct ieee80211_tx_info *info; 325 struct ath11k_skb_cb *skb_cb; 326 struct ath11k *ar; 327 328 spin_lock_bh(&tx_ring->tx_idr_lock); 329 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 330 if (!msdu) { 331 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 332 ts->msdu_id); 333 spin_unlock_bh(&tx_ring->tx_idr_lock); 334 return; 335 } 336 337 skb_cb = ATH11K_SKB_CB(msdu); 338 info = IEEE80211_SKB_CB(msdu); 339 340 ar = skb_cb->ar; 341 342 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 343 spin_unlock_bh(&tx_ring->tx_idr_lock); 344 345 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 346 wake_up(&ar->dp.tx_empty_waitq); 347 348 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 349 350 memset(&info->status, 0, sizeof(info->status)); 351 352 if (ts->acked) { 353 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 354 info->flags |= IEEE80211_TX_STAT_ACK; 355 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 356 ts->ack_rssi; 357 info->status.is_valid_ack_signal = true; 358 } else { 359 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 360 } 361 } 362 363 ieee80211_tx_status(ar->hw, msdu); 364 } 365 366 static void 367 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 368 void *desc, u8 mac_id, 369 u32 msdu_id, struct dp_tx_ring *tx_ring) 370 { 371 struct htt_tx_wbm_completion *status_desc; 372 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 373 enum hal_wbm_htt_tx_comp_status wbm_status; 374 375 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 376 377 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 378 status_desc->info0); 379 switch (wbm_status) { 380 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 381 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 382 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 383 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 384 ts.msdu_id = msdu_id; 385 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 386 status_desc->info1); 387 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 388 break; 389 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 390 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 391 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 392 break; 393 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 394 /* This event is to be handled only when the driver decides to 395 * use WDS offload functionality. 396 */ 397 break; 398 default: 399 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 400 break; 401 } 402 } 403 404 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 405 struct sk_buff *msdu, 406 struct hal_tx_status *ts) 407 { 408 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 409 410 if (ts->try_cnt > 1) { 411 peer_stats->retry_pkts += ts->try_cnt - 1; 412 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 413 414 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 415 peer_stats->failed_pkts += 1; 416 peer_stats->failed_bytes += msdu->len; 417 } 418 } 419 } 420 421 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 422 struct sk_buff *msdu, 423 struct hal_tx_status *ts) 424 { 425 struct ath11k_base *ab = ar->ab; 426 struct ieee80211_tx_info *info; 427 struct ath11k_skb_cb *skb_cb; 428 429 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 430 /* Must not happen */ 431 return; 432 } 433 434 skb_cb = ATH11K_SKB_CB(msdu); 435 436 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 437 438 rcu_read_lock(); 439 440 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 441 dev_kfree_skb_any(msdu); 442 goto exit; 443 } 444 445 if (!skb_cb->vif) { 446 dev_kfree_skb_any(msdu); 447 goto exit; 448 } 449 450 info = IEEE80211_SKB_CB(msdu); 451 memset(&info->status, 0, sizeof(info->status)); 452 453 /* skip tx rate update from ieee80211_status*/ 454 info->status.rates[0].idx = -1; 455 456 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 457 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 458 info->flags |= IEEE80211_TX_STAT_ACK; 459 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 460 ts->ack_rssi; 461 info->status.is_valid_ack_signal = true; 462 } 463 464 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 465 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 466 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 467 468 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) { 469 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 470 if (ar->last_ppdu_id == 0) { 471 ar->last_ppdu_id = ts->ppdu_id; 472 } else if (ar->last_ppdu_id == ts->ppdu_id || 473 ar->cached_ppdu_id == ar->last_ppdu_id) { 474 ar->cached_ppdu_id = ar->last_ppdu_id; 475 ar->cached_stats.is_ampdu = true; 476 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 477 memset(&ar->cached_stats, 0, 478 sizeof(struct ath11k_per_peer_tx_stats)); 479 } else { 480 ar->cached_stats.is_ampdu = false; 481 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 482 memset(&ar->cached_stats, 0, 483 sizeof(struct ath11k_per_peer_tx_stats)); 484 } 485 ar->last_ppdu_id = ts->ppdu_id; 486 } 487 488 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 489 } 490 491 /* NOTE: Tx rate status reporting. Tx completion status does not have 492 * necessary information (for example nss) to build the tx rate. 493 * Might end up reporting it out-of-band from HTT stats. 494 */ 495 496 ieee80211_tx_status(ar->hw, msdu); 497 498 exit: 499 rcu_read_unlock(); 500 } 501 502 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 503 struct hal_wbm_release_ring *desc, 504 struct hal_tx_status *ts) 505 { 506 ts->buf_rel_source = 507 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 508 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 509 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 510 return; 511 512 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 513 return; 514 515 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 516 desc->info0); 517 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 518 desc->info1); 519 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 520 desc->info1); 521 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 522 desc->info2); 523 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 524 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 525 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 526 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 527 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 528 ts->rate_stats = desc->rate_stats.info0; 529 else 530 ts->rate_stats = 0; 531 } 532 533 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 534 { 535 struct ath11k *ar; 536 struct ath11k_dp *dp = &ab->dp; 537 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 538 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 539 struct sk_buff *msdu; 540 struct hal_tx_status ts = { 0 }; 541 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 542 u32 *desc; 543 u32 msdu_id; 544 u8 mac_id; 545 546 spin_lock_bh(&status_ring->lock); 547 548 ath11k_hal_srng_access_begin(ab, status_ring); 549 550 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 551 tx_ring->tx_status_tail) && 552 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 553 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 554 desc, sizeof(struct hal_wbm_release_ring)); 555 tx_ring->tx_status_head = 556 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 557 } 558 559 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 560 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 561 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 562 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 563 } 564 565 ath11k_hal_srng_access_end(ab, status_ring); 566 567 spin_unlock_bh(&status_ring->lock); 568 569 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 570 struct hal_wbm_release_ring *tx_status; 571 u32 desc_id; 572 573 tx_ring->tx_status_tail = 574 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 575 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 576 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 577 578 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 579 tx_status->buf_addr_info.info1); 580 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 581 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 582 583 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 584 ath11k_dp_tx_process_htt_tx_complete(ab, 585 (void *)tx_status, 586 mac_id, msdu_id, 587 tx_ring); 588 continue; 589 } 590 591 spin_lock_bh(&tx_ring->tx_idr_lock); 592 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 593 if (!msdu) { 594 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 595 msdu_id); 596 spin_unlock_bh(&tx_ring->tx_idr_lock); 597 continue; 598 } 599 idr_remove(&tx_ring->txbuf_idr, msdu_id); 600 spin_unlock_bh(&tx_ring->tx_idr_lock); 601 602 ar = ab->pdevs[mac_id].ar; 603 604 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 605 wake_up(&ar->dp.tx_empty_waitq); 606 607 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 608 } 609 } 610 611 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 612 enum hal_reo_cmd_type type, 613 struct ath11k_hal_reo_cmd *cmd, 614 void (*cb)(struct ath11k_dp *, void *, 615 enum hal_reo_cmd_status)) 616 { 617 struct ath11k_dp *dp = &ab->dp; 618 struct dp_reo_cmd *dp_cmd; 619 struct hal_srng *cmd_ring; 620 int cmd_num; 621 622 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 623 return -ESHUTDOWN; 624 625 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 626 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 627 628 /* cmd_num should start from 1, during failure return the error code */ 629 if (cmd_num < 0) 630 return cmd_num; 631 632 /* reo cmd ring descriptors has cmd_num starting from 1 */ 633 if (cmd_num == 0) 634 return -EINVAL; 635 636 if (!cb) 637 return 0; 638 639 /* Can this be optimized so that we keep the pending command list only 640 * for tid delete command to free up the resoruce on the command status 641 * indication? 642 */ 643 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 644 645 if (!dp_cmd) 646 return -ENOMEM; 647 648 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 649 dp_cmd->cmd_num = cmd_num; 650 dp_cmd->handler = cb; 651 652 spin_lock_bh(&dp->reo_cmd_lock); 653 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 654 spin_unlock_bh(&dp->reo_cmd_lock); 655 656 return 0; 657 } 658 659 static int 660 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 661 int mac_id, u32 ring_id, 662 enum hal_ring_type ring_type, 663 enum htt_srng_ring_type *htt_ring_type, 664 enum htt_srng_ring_id *htt_ring_id) 665 { 666 int lmac_ring_id_offset = 0; 667 int ret = 0; 668 669 switch (ring_type) { 670 case HAL_RXDMA_BUF: 671 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 672 673 /* for QCA6390, host fills rx buffer to fw and fw fills to 674 * rxbuf ring for each rxdma 675 */ 676 if (!ab->hw_params.rx_mac_buf_ring) { 677 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 678 lmac_ring_id_offset) || 679 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 680 lmac_ring_id_offset))) { 681 ret = -EINVAL; 682 } 683 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 684 *htt_ring_type = HTT_SW_TO_HW_RING; 685 } else { 686 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 687 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 688 *htt_ring_type = HTT_SW_TO_SW_RING; 689 } else { 690 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 691 *htt_ring_type = HTT_SW_TO_HW_RING; 692 } 693 } 694 break; 695 case HAL_RXDMA_DST: 696 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 697 *htt_ring_type = HTT_HW_TO_SW_RING; 698 break; 699 case HAL_RXDMA_MONITOR_BUF: 700 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 701 *htt_ring_type = HTT_SW_TO_HW_RING; 702 break; 703 case HAL_RXDMA_MONITOR_STATUS: 704 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 705 *htt_ring_type = HTT_SW_TO_HW_RING; 706 break; 707 case HAL_RXDMA_MONITOR_DST: 708 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 709 *htt_ring_type = HTT_HW_TO_SW_RING; 710 break; 711 case HAL_RXDMA_MONITOR_DESC: 712 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 713 *htt_ring_type = HTT_SW_TO_HW_RING; 714 break; 715 default: 716 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 717 ret = -EINVAL; 718 } 719 return ret; 720 } 721 722 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 723 int mac_id, enum hal_ring_type ring_type) 724 { 725 struct htt_srng_setup_cmd *cmd; 726 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 727 struct hal_srng_params params; 728 struct sk_buff *skb; 729 u32 ring_entry_sz; 730 int len = sizeof(*cmd); 731 dma_addr_t hp_addr, tp_addr; 732 enum htt_srng_ring_type htt_ring_type; 733 enum htt_srng_ring_id htt_ring_id; 734 int ret; 735 736 skb = ath11k_htc_alloc_skb(ab, len); 737 if (!skb) 738 return -ENOMEM; 739 740 memset(¶ms, 0, sizeof(params)); 741 ath11k_hal_srng_get_params(ab, srng, ¶ms); 742 743 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 744 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 745 746 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 747 ring_type, &htt_ring_type, 748 &htt_ring_id); 749 if (ret) 750 goto err_free; 751 752 skb_put(skb, len); 753 cmd = (struct htt_srng_setup_cmd *)skb->data; 754 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 755 HTT_H2T_MSG_TYPE_SRING_SETUP); 756 if (htt_ring_type == HTT_SW_TO_HW_RING || 757 htt_ring_type == HTT_HW_TO_SW_RING) 758 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 759 DP_SW2HW_MACID(mac_id)); 760 else 761 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 762 mac_id); 763 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 764 htt_ring_type); 765 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 766 767 cmd->ring_base_addr_lo = params.ring_base_paddr & 768 HAL_ADDR_LSB_REG_MASK; 769 770 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 771 HAL_ADDR_MSB_REG_SHIFT; 772 773 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 774 if (ret < 0) 775 goto err_free; 776 777 ring_entry_sz = ret; 778 779 ring_entry_sz >>= 2; 780 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 781 ring_entry_sz); 782 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 783 params.num_entries * ring_entry_sz); 784 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 785 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 786 cmd->info1 |= FIELD_PREP( 787 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 788 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 789 cmd->info1 |= FIELD_PREP( 790 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 791 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 792 if (htt_ring_type == HTT_SW_TO_HW_RING) 793 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 794 795 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 796 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 797 HAL_ADDR_MSB_REG_SHIFT; 798 799 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 800 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 801 HAL_ADDR_MSB_REG_SHIFT; 802 803 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 804 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 805 cmd->msi_data = params.msi_data; 806 807 cmd->intr_info = FIELD_PREP( 808 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 809 params.intr_batch_cntr_thres_entries * ring_entry_sz); 810 cmd->intr_info |= FIELD_PREP( 811 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 812 params.intr_timer_thres_us >> 3); 813 814 cmd->info2 = 0; 815 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 816 cmd->info2 = FIELD_PREP( 817 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 818 params.low_threshold); 819 } 820 821 ath11k_dbg(ab, ATH11k_DBG_HAL, 822 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 823 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 824 cmd->msi_data); 825 826 ath11k_dbg(ab, ATH11k_DBG_HAL, 827 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 828 ring_id, ring_type, cmd->intr_info, cmd->info2); 829 830 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 831 if (ret) 832 goto err_free; 833 834 return 0; 835 836 err_free: 837 dev_kfree_skb_any(skb); 838 839 return ret; 840 } 841 842 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 843 844 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 845 { 846 struct ath11k_dp *dp = &ab->dp; 847 struct sk_buff *skb; 848 struct htt_ver_req_cmd *cmd; 849 int len = sizeof(*cmd); 850 int ret; 851 852 init_completion(&dp->htt_tgt_version_received); 853 854 skb = ath11k_htc_alloc_skb(ab, len); 855 if (!skb) 856 return -ENOMEM; 857 858 skb_put(skb, len); 859 cmd = (struct htt_ver_req_cmd *)skb->data; 860 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 861 HTT_H2T_MSG_TYPE_VERSION_REQ); 862 863 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 864 if (ret) { 865 dev_kfree_skb_any(skb); 866 return ret; 867 } 868 869 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 870 HTT_TARGET_VERSION_TIMEOUT_HZ); 871 if (ret == 0) { 872 ath11k_warn(ab, "htt target version request timed out\n"); 873 return -ETIMEDOUT; 874 } 875 876 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 877 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 878 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 879 return -ENOTSUPP; 880 } 881 882 return 0; 883 } 884 885 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 886 { 887 struct ath11k_base *ab = ar->ab; 888 struct ath11k_dp *dp = &ab->dp; 889 struct sk_buff *skb; 890 struct htt_ppdu_stats_cfg_cmd *cmd; 891 int len = sizeof(*cmd); 892 u8 pdev_mask; 893 int ret; 894 int i; 895 896 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 897 skb = ath11k_htc_alloc_skb(ab, len); 898 if (!skb) 899 return -ENOMEM; 900 901 skb_put(skb, len); 902 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 903 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 904 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 905 906 pdev_mask = 1 << (i + 1); 907 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 908 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 909 910 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 911 if (ret) { 912 dev_kfree_skb_any(skb); 913 return ret; 914 } 915 } 916 917 return 0; 918 } 919 920 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 921 int mac_id, enum hal_ring_type ring_type, 922 int rx_buf_size, 923 struct htt_rx_ring_tlv_filter *tlv_filter) 924 { 925 struct htt_rx_ring_selection_cfg_cmd *cmd; 926 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 927 struct hal_srng_params params; 928 struct sk_buff *skb; 929 int len = sizeof(*cmd); 930 enum htt_srng_ring_type htt_ring_type; 931 enum htt_srng_ring_id htt_ring_id; 932 int ret; 933 934 skb = ath11k_htc_alloc_skb(ab, len); 935 if (!skb) 936 return -ENOMEM; 937 938 memset(¶ms, 0, sizeof(params)); 939 ath11k_hal_srng_get_params(ab, srng, ¶ms); 940 941 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 942 ring_type, &htt_ring_type, 943 &htt_ring_id); 944 if (ret) 945 goto err_free; 946 947 skb_put(skb, len); 948 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 949 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 950 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 951 if (htt_ring_type == HTT_SW_TO_HW_RING || 952 htt_ring_type == HTT_HW_TO_SW_RING) 953 cmd->info0 |= 954 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 955 DP_SW2HW_MACID(mac_id)); 956 else 957 cmd->info0 |= 958 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 959 mac_id); 960 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 961 htt_ring_id); 962 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 963 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 964 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 965 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 966 967 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 968 rx_buf_size); 969 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 970 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 971 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 972 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 973 cmd->rx_filter_tlv = tlv_filter->rx_filter; 974 975 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 976 if (ret) 977 goto err_free; 978 979 return 0; 980 981 err_free: 982 dev_kfree_skb_any(skb); 983 984 return ret; 985 } 986 987 int 988 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 989 struct htt_ext_stats_cfg_params *cfg_params, 990 u64 cookie) 991 { 992 struct ath11k_base *ab = ar->ab; 993 struct ath11k_dp *dp = &ab->dp; 994 struct sk_buff *skb; 995 struct htt_ext_stats_cfg_cmd *cmd; 996 int len = sizeof(*cmd); 997 int ret; 998 999 skb = ath11k_htc_alloc_skb(ab, len); 1000 if (!skb) 1001 return -ENOMEM; 1002 1003 skb_put(skb, len); 1004 1005 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1006 memset(cmd, 0, sizeof(*cmd)); 1007 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1008 1009 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1010 1011 cmd->hdr.stats_type = type; 1012 cmd->cfg_param0 = cfg_params->cfg0; 1013 cmd->cfg_param1 = cfg_params->cfg1; 1014 cmd->cfg_param2 = cfg_params->cfg2; 1015 cmd->cfg_param3 = cfg_params->cfg3; 1016 cmd->cookie_lsb = lower_32_bits(cookie); 1017 cmd->cookie_msb = upper_32_bits(cookie); 1018 1019 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1020 if (ret) { 1021 ath11k_warn(ab, "failed to send htt type stats request: %d", 1022 ret); 1023 dev_kfree_skb_any(skb); 1024 return ret; 1025 } 1026 1027 return 0; 1028 } 1029 1030 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1031 { 1032 struct ath11k_pdev_dp *dp = &ar->dp; 1033 struct ath11k_base *ab = ar->ab; 1034 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1035 int ret = 0, ring_id = 0, i; 1036 1037 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1038 1039 if (!reset) { 1040 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1041 tlv_filter.pkt_filter_flags0 = 1042 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1043 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1044 tlv_filter.pkt_filter_flags1 = 1045 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1046 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1047 tlv_filter.pkt_filter_flags2 = 1048 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1049 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1050 tlv_filter.pkt_filter_flags3 = 1051 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1052 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1053 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1054 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1055 } 1056 1057 if (ab->hw_params.rxdma1_enable) { 1058 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1059 HAL_RXDMA_MONITOR_BUF, 1060 DP_RXDMA_REFILL_RING_SIZE, 1061 &tlv_filter); 1062 } else if (!reset) { 1063 /* set in monitor mode only */ 1064 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1065 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1066 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1067 dp->mac_id + i, 1068 HAL_RXDMA_BUF, 1069 1024, 1070 &tlv_filter); 1071 } 1072 } 1073 1074 if (ret) 1075 return ret; 1076 1077 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1078 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1079 if (!reset) { 1080 tlv_filter.rx_filter = 1081 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1082 } else { 1083 tlv_filter = ath11k_mac_mon_status_filter_default; 1084 1085 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1086 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1087 } 1088 1089 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1090 dp->mac_id + i, 1091 HAL_RXDMA_MONITOR_STATUS, 1092 DP_RXDMA_REFILL_RING_SIZE, 1093 &tlv_filter); 1094 } 1095 1096 if (!ar->ab->hw_params.rxdma1_enable) 1097 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1098 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1099 1100 return ret; 1101 } 1102