1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 13 static enum hal_tcl_encap_type 14 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15 { 16 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17 struct ath11k_base *ab = arvif->ar->ab; 18 19 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20 return HAL_TCL_ENCAP_TYPE_RAW; 21 22 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23 return HAL_TCL_ENCAP_TYPE_ETHERNET; 24 25 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26 } 27 28 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29 { 30 struct ieee80211_hdr *hdr = (void *)skb->data; 31 u8 *qos_ctl; 32 33 if (!ieee80211_is_data_qos(hdr->frame_control)) 34 return; 35 36 qos_ctl = ieee80211_get_qos_ctl(hdr); 37 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38 skb->data, (void *)qos_ctl - (void *)skb->data); 39 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40 41 hdr = (void *)skb->data; 42 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43 } 44 45 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46 { 47 struct ieee80211_hdr *hdr = (void *)skb->data; 48 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49 50 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52 else if (!ieee80211_is_data_qos(hdr->frame_control)) 53 return HAL_DESC_REO_NON_QOS_TID; 54 else 55 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56 } 57 58 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59 { 60 switch (cipher) { 61 case WLAN_CIPHER_SUITE_WEP40: 62 return HAL_ENCRYPT_TYPE_WEP_40; 63 case WLAN_CIPHER_SUITE_WEP104: 64 return HAL_ENCRYPT_TYPE_WEP_104; 65 case WLAN_CIPHER_SUITE_TKIP: 66 return HAL_ENCRYPT_TYPE_TKIP_MIC; 67 case WLAN_CIPHER_SUITE_CCMP: 68 return HAL_ENCRYPT_TYPE_CCMP_128; 69 case WLAN_CIPHER_SUITE_CCMP_256: 70 return HAL_ENCRYPT_TYPE_CCMP_256; 71 case WLAN_CIPHER_SUITE_GCMP: 72 return HAL_ENCRYPT_TYPE_GCMP_128; 73 case WLAN_CIPHER_SUITE_GCMP_256: 74 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75 default: 76 return HAL_ENCRYPT_TYPE_OPEN; 77 } 78 } 79 80 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81 struct ath11k_sta *arsta, struct sk_buff *skb) 82 { 83 struct ath11k_base *ab = ar->ab; 84 struct ath11k_dp *dp = &ab->dp; 85 struct hal_tx_info ti = {0}; 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 88 struct hal_srng *tcl_ring; 89 struct ieee80211_hdr *hdr = (void *)skb->data; 90 struct dp_tx_ring *tx_ring; 91 void *hal_tcl_desc; 92 u8 pool_id; 93 u8 hal_ring_id; 94 int ret; 95 u8 ring_selector = 0, ring_map = 0; 96 bool tcl_ring_retry; 97 98 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 99 return -ESHUTDOWN; 100 101 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 102 !ieee80211_is_data(hdr->frame_control)) 103 return -ENOTSUPP; 104 105 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 106 107 /* Let the default ring selection be based on current processor 108 * number, where one of the 3 tcl rings are selected based on 109 * the smp_processor_id(). In case that ring 110 * is full/busy, we resort to other available rings. 111 * If all rings are full, we drop the packet. 112 * //TODO Add throttling logic when all rings are full 113 */ 114 ring_selector = smp_processor_id(); 115 116 tcl_ring_sel: 117 tcl_ring_retry = false; 118 /* For some chip, it can only use tcl0 to tx */ 119 if (ar->ab->hw_params.tcl_0_only) 120 ti.ring_id = 0; 121 else 122 ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX; 123 124 ring_map |= BIT(ti.ring_id); 125 126 tx_ring = &dp->tx_ring[ti.ring_id]; 127 128 spin_lock_bh(&tx_ring->tx_idr_lock); 129 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 130 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 131 spin_unlock_bh(&tx_ring->tx_idr_lock); 132 133 if (ret < 0) { 134 if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) { 135 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 136 return -ENOSPC; 137 } 138 139 /* Check if the next ring is available */ 140 ring_selector++; 141 goto tcl_ring_sel; 142 } 143 144 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 145 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 146 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 147 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 148 149 if (ieee80211_has_a4(hdr->frame_control) && 150 is_multicast_ether_addr(hdr->addr3) && arsta && 151 arsta->use_4addr_set) { 152 ti.meta_data_flags = arsta->tcl_metadata; 153 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 154 } else { 155 ti.meta_data_flags = arvif->tcl_metadata; 156 } 157 158 if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) { 159 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 160 ti.encrypt_type = 161 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 162 163 if (ieee80211_has_protected(hdr->frame_control)) 164 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 165 } else { 166 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 167 } 168 } 169 170 ti.addr_search_flags = arvif->hal_addr_search_flags; 171 ti.search_type = arvif->search_type; 172 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 173 ti.pkt_offset = 0; 174 ti.lmac_id = ar->lmac_id; 175 ti.bss_ast_hash = arvif->ast_hash; 176 ti.bss_ast_idx = arvif->ast_idx; 177 ti.dscp_tid_tbl_idx = 0; 178 179 if (skb->ip_summed == CHECKSUM_PARTIAL && 180 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 181 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 182 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 183 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 184 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 185 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 186 } 187 188 if (ieee80211_vif_is_mesh(arvif->vif)) 189 ti.enable_mesh = true; 190 191 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 192 193 ti.tid = ath11k_dp_tx_get_tid(skb); 194 195 switch (ti.encap_type) { 196 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 197 ath11k_dp_tx_encap_nwifi(skb); 198 break; 199 case HAL_TCL_ENCAP_TYPE_RAW: 200 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 201 ret = -EINVAL; 202 goto fail_remove_idr; 203 } 204 break; 205 case HAL_TCL_ENCAP_TYPE_ETHERNET: 206 /* no need to encap */ 207 break; 208 case HAL_TCL_ENCAP_TYPE_802_3: 209 default: 210 /* TODO: Take care of other encap modes as well */ 211 ret = -EINVAL; 212 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 213 goto fail_remove_idr; 214 } 215 216 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 217 if (dma_mapping_error(ab->dev, ti.paddr)) { 218 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 219 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 220 ret = -ENOMEM; 221 goto fail_remove_idr; 222 } 223 224 ti.data_len = skb->len; 225 skb_cb->paddr = ti.paddr; 226 skb_cb->vif = arvif->vif; 227 skb_cb->ar = ar; 228 229 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 230 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 231 232 spin_lock_bh(&tcl_ring->lock); 233 234 ath11k_hal_srng_access_begin(ab, tcl_ring); 235 236 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 237 if (!hal_tcl_desc) { 238 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 239 * desc because the desc is directly enqueued onto hw queue. 240 */ 241 ath11k_hal_srng_access_end(ab, tcl_ring); 242 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 243 spin_unlock_bh(&tcl_ring->lock); 244 ret = -ENOMEM; 245 246 /* Checking for available tcl descritors in another ring in 247 * case of failure due to full tcl ring now, is better than 248 * checking this ring earlier for each pkt tx. 249 * Restart ring selection if some rings are not checked yet. 250 */ 251 if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) && 252 !ar->ab->hw_params.tcl_0_only) { 253 tcl_ring_retry = true; 254 ring_selector++; 255 } 256 257 goto fail_unmap_dma; 258 } 259 260 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 261 sizeof(struct hal_tlv_hdr), &ti); 262 263 ath11k_hal_srng_access_end(ab, tcl_ring); 264 265 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 266 267 spin_unlock_bh(&tcl_ring->lock); 268 269 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 270 skb->data, skb->len); 271 272 atomic_inc(&ar->dp.num_tx_pending); 273 274 return 0; 275 276 fail_unmap_dma: 277 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 278 279 fail_remove_idr: 280 spin_lock_bh(&tx_ring->tx_idr_lock); 281 idr_remove(&tx_ring->txbuf_idr, 282 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 283 spin_unlock_bh(&tx_ring->tx_idr_lock); 284 285 if (tcl_ring_retry) 286 goto tcl_ring_sel; 287 288 return ret; 289 } 290 291 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 292 int msdu_id, 293 struct dp_tx_ring *tx_ring) 294 { 295 struct ath11k *ar; 296 struct sk_buff *msdu; 297 struct ath11k_skb_cb *skb_cb; 298 299 spin_lock_bh(&tx_ring->tx_idr_lock); 300 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 301 if (!msdu) { 302 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 303 msdu_id); 304 spin_unlock_bh(&tx_ring->tx_idr_lock); 305 return; 306 } 307 308 skb_cb = ATH11K_SKB_CB(msdu); 309 310 idr_remove(&tx_ring->txbuf_idr, msdu_id); 311 spin_unlock_bh(&tx_ring->tx_idr_lock); 312 313 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 314 dev_kfree_skb_any(msdu); 315 316 ar = ab->pdevs[mac_id].ar; 317 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 318 wake_up(&ar->dp.tx_empty_waitq); 319 } 320 321 static void 322 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 323 struct dp_tx_ring *tx_ring, 324 struct ath11k_dp_htt_wbm_tx_status *ts) 325 { 326 struct sk_buff *msdu; 327 struct ieee80211_tx_info *info; 328 struct ath11k_skb_cb *skb_cb; 329 struct ath11k *ar; 330 331 spin_lock_bh(&tx_ring->tx_idr_lock); 332 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 333 if (!msdu) { 334 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 335 ts->msdu_id); 336 spin_unlock_bh(&tx_ring->tx_idr_lock); 337 return; 338 } 339 340 skb_cb = ATH11K_SKB_CB(msdu); 341 info = IEEE80211_SKB_CB(msdu); 342 343 ar = skb_cb->ar; 344 345 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 346 spin_unlock_bh(&tx_ring->tx_idr_lock); 347 348 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 349 wake_up(&ar->dp.tx_empty_waitq); 350 351 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 352 353 memset(&info->status, 0, sizeof(info->status)); 354 355 if (ts->acked) { 356 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 357 info->flags |= IEEE80211_TX_STAT_ACK; 358 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 359 ts->ack_rssi; 360 info->status.is_valid_ack_signal = true; 361 } else { 362 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 363 } 364 } 365 366 ieee80211_tx_status(ar->hw, msdu); 367 } 368 369 static void 370 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 371 void *desc, u8 mac_id, 372 u32 msdu_id, struct dp_tx_ring *tx_ring) 373 { 374 struct htt_tx_wbm_completion *status_desc; 375 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 376 enum hal_wbm_htt_tx_comp_status wbm_status; 377 378 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 379 380 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 381 status_desc->info0); 382 switch (wbm_status) { 383 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 384 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 385 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 386 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 387 ts.msdu_id = msdu_id; 388 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 389 status_desc->info1); 390 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 391 break; 392 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 393 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 394 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 395 break; 396 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 397 /* This event is to be handled only when the driver decides to 398 * use WDS offload functionality. 399 */ 400 break; 401 default: 402 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 403 break; 404 } 405 } 406 407 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 408 struct sk_buff *msdu, 409 struct hal_tx_status *ts) 410 { 411 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 412 413 if (ts->try_cnt > 1) { 414 peer_stats->retry_pkts += ts->try_cnt - 1; 415 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 416 417 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 418 peer_stats->failed_pkts += 1; 419 peer_stats->failed_bytes += msdu->len; 420 } 421 } 422 } 423 424 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 425 struct sk_buff *msdu, 426 struct hal_tx_status *ts) 427 { 428 struct ath11k_base *ab = ar->ab; 429 struct ieee80211_tx_info *info; 430 struct ath11k_skb_cb *skb_cb; 431 432 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 433 /* Must not happen */ 434 return; 435 } 436 437 skb_cb = ATH11K_SKB_CB(msdu); 438 439 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 440 441 rcu_read_lock(); 442 443 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 444 dev_kfree_skb_any(msdu); 445 goto exit; 446 } 447 448 if (!skb_cb->vif) { 449 dev_kfree_skb_any(msdu); 450 goto exit; 451 } 452 453 info = IEEE80211_SKB_CB(msdu); 454 memset(&info->status, 0, sizeof(info->status)); 455 456 /* skip tx rate update from ieee80211_status*/ 457 info->status.rates[0].idx = -1; 458 459 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 460 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 461 info->flags |= IEEE80211_TX_STAT_ACK; 462 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 463 ts->ack_rssi; 464 info->status.is_valid_ack_signal = true; 465 } 466 467 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 468 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 469 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 470 471 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) { 472 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 473 if (ar->last_ppdu_id == 0) { 474 ar->last_ppdu_id = ts->ppdu_id; 475 } else if (ar->last_ppdu_id == ts->ppdu_id || 476 ar->cached_ppdu_id == ar->last_ppdu_id) { 477 ar->cached_ppdu_id = ar->last_ppdu_id; 478 ar->cached_stats.is_ampdu = true; 479 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 480 memset(&ar->cached_stats, 0, 481 sizeof(struct ath11k_per_peer_tx_stats)); 482 } else { 483 ar->cached_stats.is_ampdu = false; 484 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 485 memset(&ar->cached_stats, 0, 486 sizeof(struct ath11k_per_peer_tx_stats)); 487 } 488 ar->last_ppdu_id = ts->ppdu_id; 489 } 490 491 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 492 } 493 494 /* NOTE: Tx rate status reporting. Tx completion status does not have 495 * necessary information (for example nss) to build the tx rate. 496 * Might end up reporting it out-of-band from HTT stats. 497 */ 498 499 ieee80211_tx_status(ar->hw, msdu); 500 501 exit: 502 rcu_read_unlock(); 503 } 504 505 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 506 struct hal_wbm_release_ring *desc, 507 struct hal_tx_status *ts) 508 { 509 ts->buf_rel_source = 510 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 511 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 512 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 513 return; 514 515 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 516 return; 517 518 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 519 desc->info0); 520 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 521 desc->info1); 522 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 523 desc->info1); 524 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 525 desc->info2); 526 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 527 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 528 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 529 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 530 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 531 ts->rate_stats = desc->rate_stats.info0; 532 else 533 ts->rate_stats = 0; 534 } 535 536 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 537 { 538 struct ath11k *ar; 539 struct ath11k_dp *dp = &ab->dp; 540 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 541 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 542 struct sk_buff *msdu; 543 struct hal_tx_status ts = { 0 }; 544 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 545 u32 *desc; 546 u32 msdu_id; 547 u8 mac_id; 548 549 spin_lock_bh(&status_ring->lock); 550 551 ath11k_hal_srng_access_begin(ab, status_ring); 552 553 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 554 tx_ring->tx_status_tail) && 555 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 556 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 557 desc, sizeof(struct hal_wbm_release_ring)); 558 tx_ring->tx_status_head = 559 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 560 } 561 562 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 563 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 564 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 565 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 566 } 567 568 ath11k_hal_srng_access_end(ab, status_ring); 569 570 spin_unlock_bh(&status_ring->lock); 571 572 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 573 struct hal_wbm_release_ring *tx_status; 574 u32 desc_id; 575 576 tx_ring->tx_status_tail = 577 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 578 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 579 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 580 581 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 582 tx_status->buf_addr_info.info1); 583 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 584 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 585 586 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 587 ath11k_dp_tx_process_htt_tx_complete(ab, 588 (void *)tx_status, 589 mac_id, msdu_id, 590 tx_ring); 591 continue; 592 } 593 594 spin_lock_bh(&tx_ring->tx_idr_lock); 595 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 596 if (!msdu) { 597 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 598 msdu_id); 599 spin_unlock_bh(&tx_ring->tx_idr_lock); 600 continue; 601 } 602 idr_remove(&tx_ring->txbuf_idr, msdu_id); 603 spin_unlock_bh(&tx_ring->tx_idr_lock); 604 605 ar = ab->pdevs[mac_id].ar; 606 607 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 608 wake_up(&ar->dp.tx_empty_waitq); 609 610 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 611 } 612 } 613 614 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 615 enum hal_reo_cmd_type type, 616 struct ath11k_hal_reo_cmd *cmd, 617 void (*cb)(struct ath11k_dp *, void *, 618 enum hal_reo_cmd_status)) 619 { 620 struct ath11k_dp *dp = &ab->dp; 621 struct dp_reo_cmd *dp_cmd; 622 struct hal_srng *cmd_ring; 623 int cmd_num; 624 625 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 626 return -ESHUTDOWN; 627 628 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 629 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 630 631 /* cmd_num should start from 1, during failure return the error code */ 632 if (cmd_num < 0) 633 return cmd_num; 634 635 /* reo cmd ring descriptors has cmd_num starting from 1 */ 636 if (cmd_num == 0) 637 return -EINVAL; 638 639 if (!cb) 640 return 0; 641 642 /* Can this be optimized so that we keep the pending command list only 643 * for tid delete command to free up the resoruce on the command status 644 * indication? 645 */ 646 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 647 648 if (!dp_cmd) 649 return -ENOMEM; 650 651 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 652 dp_cmd->cmd_num = cmd_num; 653 dp_cmd->handler = cb; 654 655 spin_lock_bh(&dp->reo_cmd_lock); 656 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 657 spin_unlock_bh(&dp->reo_cmd_lock); 658 659 return 0; 660 } 661 662 static int 663 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 664 int mac_id, u32 ring_id, 665 enum hal_ring_type ring_type, 666 enum htt_srng_ring_type *htt_ring_type, 667 enum htt_srng_ring_id *htt_ring_id) 668 { 669 int lmac_ring_id_offset = 0; 670 int ret = 0; 671 672 switch (ring_type) { 673 case HAL_RXDMA_BUF: 674 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 675 676 /* for QCA6390, host fills rx buffer to fw and fw fills to 677 * rxbuf ring for each rxdma 678 */ 679 if (!ab->hw_params.rx_mac_buf_ring) { 680 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 681 lmac_ring_id_offset) || 682 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 683 lmac_ring_id_offset))) { 684 ret = -EINVAL; 685 } 686 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 687 *htt_ring_type = HTT_SW_TO_HW_RING; 688 } else { 689 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 690 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 691 *htt_ring_type = HTT_SW_TO_SW_RING; 692 } else { 693 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 694 *htt_ring_type = HTT_SW_TO_HW_RING; 695 } 696 } 697 break; 698 case HAL_RXDMA_DST: 699 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 700 *htt_ring_type = HTT_HW_TO_SW_RING; 701 break; 702 case HAL_RXDMA_MONITOR_BUF: 703 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 704 *htt_ring_type = HTT_SW_TO_HW_RING; 705 break; 706 case HAL_RXDMA_MONITOR_STATUS: 707 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 708 *htt_ring_type = HTT_SW_TO_HW_RING; 709 break; 710 case HAL_RXDMA_MONITOR_DST: 711 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 712 *htt_ring_type = HTT_HW_TO_SW_RING; 713 break; 714 case HAL_RXDMA_MONITOR_DESC: 715 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 716 *htt_ring_type = HTT_SW_TO_HW_RING; 717 break; 718 default: 719 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 720 ret = -EINVAL; 721 } 722 return ret; 723 } 724 725 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 726 int mac_id, enum hal_ring_type ring_type) 727 { 728 struct htt_srng_setup_cmd *cmd; 729 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 730 struct hal_srng_params params; 731 struct sk_buff *skb; 732 u32 ring_entry_sz; 733 int len = sizeof(*cmd); 734 dma_addr_t hp_addr, tp_addr; 735 enum htt_srng_ring_type htt_ring_type; 736 enum htt_srng_ring_id htt_ring_id; 737 int ret; 738 739 skb = ath11k_htc_alloc_skb(ab, len); 740 if (!skb) 741 return -ENOMEM; 742 743 memset(¶ms, 0, sizeof(params)); 744 ath11k_hal_srng_get_params(ab, srng, ¶ms); 745 746 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 747 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 748 749 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 750 ring_type, &htt_ring_type, 751 &htt_ring_id); 752 if (ret) 753 goto err_free; 754 755 skb_put(skb, len); 756 cmd = (struct htt_srng_setup_cmd *)skb->data; 757 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 758 HTT_H2T_MSG_TYPE_SRING_SETUP); 759 if (htt_ring_type == HTT_SW_TO_HW_RING || 760 htt_ring_type == HTT_HW_TO_SW_RING) 761 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 762 DP_SW2HW_MACID(mac_id)); 763 else 764 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 765 mac_id); 766 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 767 htt_ring_type); 768 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 769 770 cmd->ring_base_addr_lo = params.ring_base_paddr & 771 HAL_ADDR_LSB_REG_MASK; 772 773 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 774 HAL_ADDR_MSB_REG_SHIFT; 775 776 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 777 if (ret < 0) 778 goto err_free; 779 780 ring_entry_sz = ret; 781 782 ring_entry_sz >>= 2; 783 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 784 ring_entry_sz); 785 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 786 params.num_entries * ring_entry_sz); 787 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 788 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 789 cmd->info1 |= FIELD_PREP( 790 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 791 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 792 cmd->info1 |= FIELD_PREP( 793 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 794 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 795 if (htt_ring_type == HTT_SW_TO_HW_RING) 796 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 797 798 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 799 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 800 HAL_ADDR_MSB_REG_SHIFT; 801 802 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 803 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 804 HAL_ADDR_MSB_REG_SHIFT; 805 806 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 807 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 808 cmd->msi_data = params.msi_data; 809 810 cmd->intr_info = FIELD_PREP( 811 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 812 params.intr_batch_cntr_thres_entries * ring_entry_sz); 813 cmd->intr_info |= FIELD_PREP( 814 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 815 params.intr_timer_thres_us >> 3); 816 817 cmd->info2 = 0; 818 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 819 cmd->info2 = FIELD_PREP( 820 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 821 params.low_threshold); 822 } 823 824 ath11k_dbg(ab, ATH11k_DBG_HAL, 825 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 826 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 827 cmd->msi_data); 828 829 ath11k_dbg(ab, ATH11k_DBG_HAL, 830 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 831 ring_id, ring_type, cmd->intr_info, cmd->info2); 832 833 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 834 if (ret) 835 goto err_free; 836 837 return 0; 838 839 err_free: 840 dev_kfree_skb_any(skb); 841 842 return ret; 843 } 844 845 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 846 847 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 848 { 849 struct ath11k_dp *dp = &ab->dp; 850 struct sk_buff *skb; 851 struct htt_ver_req_cmd *cmd; 852 int len = sizeof(*cmd); 853 int ret; 854 855 init_completion(&dp->htt_tgt_version_received); 856 857 skb = ath11k_htc_alloc_skb(ab, len); 858 if (!skb) 859 return -ENOMEM; 860 861 skb_put(skb, len); 862 cmd = (struct htt_ver_req_cmd *)skb->data; 863 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 864 HTT_H2T_MSG_TYPE_VERSION_REQ); 865 866 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 867 if (ret) { 868 dev_kfree_skb_any(skb); 869 return ret; 870 } 871 872 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 873 HTT_TARGET_VERSION_TIMEOUT_HZ); 874 if (ret == 0) { 875 ath11k_warn(ab, "htt target version request timed out\n"); 876 return -ETIMEDOUT; 877 } 878 879 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 880 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 881 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 882 return -ENOTSUPP; 883 } 884 885 return 0; 886 } 887 888 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 889 { 890 struct ath11k_base *ab = ar->ab; 891 struct ath11k_dp *dp = &ab->dp; 892 struct sk_buff *skb; 893 struct htt_ppdu_stats_cfg_cmd *cmd; 894 int len = sizeof(*cmd); 895 u8 pdev_mask; 896 int ret; 897 int i; 898 899 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 900 skb = ath11k_htc_alloc_skb(ab, len); 901 if (!skb) 902 return -ENOMEM; 903 904 skb_put(skb, len); 905 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 906 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 907 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 908 909 pdev_mask = 1 << (i + 1); 910 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 911 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 912 913 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 914 if (ret) { 915 dev_kfree_skb_any(skb); 916 return ret; 917 } 918 } 919 920 return 0; 921 } 922 923 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 924 int mac_id, enum hal_ring_type ring_type, 925 int rx_buf_size, 926 struct htt_rx_ring_tlv_filter *tlv_filter) 927 { 928 struct htt_rx_ring_selection_cfg_cmd *cmd; 929 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 930 struct hal_srng_params params; 931 struct sk_buff *skb; 932 int len = sizeof(*cmd); 933 enum htt_srng_ring_type htt_ring_type; 934 enum htt_srng_ring_id htt_ring_id; 935 int ret; 936 937 skb = ath11k_htc_alloc_skb(ab, len); 938 if (!skb) 939 return -ENOMEM; 940 941 memset(¶ms, 0, sizeof(params)); 942 ath11k_hal_srng_get_params(ab, srng, ¶ms); 943 944 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 945 ring_type, &htt_ring_type, 946 &htt_ring_id); 947 if (ret) 948 goto err_free; 949 950 skb_put(skb, len); 951 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 952 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 953 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 954 if (htt_ring_type == HTT_SW_TO_HW_RING || 955 htt_ring_type == HTT_HW_TO_SW_RING) 956 cmd->info0 |= 957 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 958 DP_SW2HW_MACID(mac_id)); 959 else 960 cmd->info0 |= 961 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 962 mac_id); 963 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 964 htt_ring_id); 965 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 966 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 967 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 968 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 969 970 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 971 rx_buf_size); 972 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 973 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 974 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 975 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 976 cmd->rx_filter_tlv = tlv_filter->rx_filter; 977 978 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 979 if (ret) 980 goto err_free; 981 982 return 0; 983 984 err_free: 985 dev_kfree_skb_any(skb); 986 987 return ret; 988 } 989 990 int 991 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 992 struct htt_ext_stats_cfg_params *cfg_params, 993 u64 cookie) 994 { 995 struct ath11k_base *ab = ar->ab; 996 struct ath11k_dp *dp = &ab->dp; 997 struct sk_buff *skb; 998 struct htt_ext_stats_cfg_cmd *cmd; 999 int len = sizeof(*cmd); 1000 int ret; 1001 1002 skb = ath11k_htc_alloc_skb(ab, len); 1003 if (!skb) 1004 return -ENOMEM; 1005 1006 skb_put(skb, len); 1007 1008 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1009 memset(cmd, 0, sizeof(*cmd)); 1010 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1011 1012 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1013 1014 cmd->hdr.stats_type = type; 1015 cmd->cfg_param0 = cfg_params->cfg0; 1016 cmd->cfg_param1 = cfg_params->cfg1; 1017 cmd->cfg_param2 = cfg_params->cfg2; 1018 cmd->cfg_param3 = cfg_params->cfg3; 1019 cmd->cookie_lsb = lower_32_bits(cookie); 1020 cmd->cookie_msb = upper_32_bits(cookie); 1021 1022 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1023 if (ret) { 1024 ath11k_warn(ab, "failed to send htt type stats request: %d", 1025 ret); 1026 dev_kfree_skb_any(skb); 1027 return ret; 1028 } 1029 1030 return 0; 1031 } 1032 1033 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1034 { 1035 struct ath11k_pdev_dp *dp = &ar->dp; 1036 struct ath11k_base *ab = ar->ab; 1037 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1038 int ret = 0, ring_id = 0, i; 1039 1040 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1041 1042 if (!reset) { 1043 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1044 tlv_filter.pkt_filter_flags0 = 1045 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1046 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1047 tlv_filter.pkt_filter_flags1 = 1048 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1049 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1050 tlv_filter.pkt_filter_flags2 = 1051 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1052 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1053 tlv_filter.pkt_filter_flags3 = 1054 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1055 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1056 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1057 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1058 } 1059 1060 if (ab->hw_params.rxdma1_enable) { 1061 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1062 HAL_RXDMA_MONITOR_BUF, 1063 DP_RXDMA_REFILL_RING_SIZE, 1064 &tlv_filter); 1065 } else if (!reset) { 1066 /* set in monitor mode only */ 1067 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1068 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1069 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1070 dp->mac_id + i, 1071 HAL_RXDMA_BUF, 1072 1024, 1073 &tlv_filter); 1074 } 1075 } 1076 1077 if (ret) 1078 return ret; 1079 1080 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1081 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1082 if (!reset) { 1083 tlv_filter.rx_filter = 1084 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1085 } else { 1086 tlv_filter = ath11k_mac_mon_status_filter_default; 1087 1088 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1089 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1090 } 1091 1092 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1093 dp->mac_id + i, 1094 HAL_RXDMA_MONITOR_STATUS, 1095 DP_RXDMA_REFILL_RING_SIZE, 1096 &tlv_filter); 1097 } 1098 1099 if (!ar->ab->hw_params.rxdma1_enable) 1100 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1101 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1102 1103 return ret; 1104 } 1105