1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "hw.h" 10 11 /* NOTE: Any of the mapped ring id value must not exceed DP_TCL_NUM_RING_MAX */ 12 static const u8 13 ath11k_txq_tcl_ring_map[ATH11K_HW_MAX_QUEUES] = { 0x0, 0x1, 0x2, 0x2 }; 14 15 static enum hal_tcl_encap_type 16 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 17 { 18 /* TODO: Determine encap type based on vif_type and configuration */ 19 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 20 } 21 22 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 23 { 24 struct ieee80211_hdr *hdr = (void *)skb->data; 25 u8 *qos_ctl; 26 27 if (!ieee80211_is_data_qos(hdr->frame_control)) 28 return; 29 30 qos_ctl = ieee80211_get_qos_ctl(hdr); 31 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 32 skb->data, (void *)qos_ctl - (void *)skb->data); 33 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 34 35 hdr = (void *)skb->data; 36 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 37 } 38 39 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 40 { 41 struct ieee80211_hdr *hdr = (void *)skb->data; 42 43 if (!ieee80211_is_data_qos(hdr->frame_control)) 44 return HAL_DESC_REO_NON_QOS_TID; 45 else 46 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 47 } 48 49 static enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 50 { 51 switch (cipher) { 52 case WLAN_CIPHER_SUITE_WEP40: 53 return HAL_ENCRYPT_TYPE_WEP_40; 54 case WLAN_CIPHER_SUITE_WEP104: 55 return HAL_ENCRYPT_TYPE_WEP_104; 56 case WLAN_CIPHER_SUITE_TKIP: 57 return HAL_ENCRYPT_TYPE_TKIP_MIC; 58 case WLAN_CIPHER_SUITE_CCMP: 59 return HAL_ENCRYPT_TYPE_CCMP_128; 60 case WLAN_CIPHER_SUITE_CCMP_256: 61 return HAL_ENCRYPT_TYPE_CCMP_256; 62 case WLAN_CIPHER_SUITE_GCMP: 63 return HAL_ENCRYPT_TYPE_GCMP_128; 64 case WLAN_CIPHER_SUITE_GCMP_256: 65 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 66 default: 67 return HAL_ENCRYPT_TYPE_OPEN; 68 } 69 } 70 71 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 72 struct sk_buff *skb) 73 { 74 struct ath11k_base *ab = ar->ab; 75 struct ath11k_dp *dp = &ab->dp; 76 struct hal_tx_info ti = {0}; 77 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 78 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 79 struct hal_srng *tcl_ring; 80 struct ieee80211_hdr *hdr = (void *)skb->data; 81 struct dp_tx_ring *tx_ring; 82 u8 cached_desc[HAL_TCL_DESC_LEN]; 83 void *hal_tcl_desc; 84 u8 pool_id; 85 u8 hal_ring_id; 86 int ret; 87 88 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 89 return -ESHUTDOWN; 90 91 if (!ieee80211_is_data(hdr->frame_control)) 92 return -ENOTSUPP; 93 94 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 95 ti.ring_id = ath11k_txq_tcl_ring_map[pool_id]; 96 97 tx_ring = &dp->tx_ring[ti.ring_id]; 98 99 spin_lock_bh(&tx_ring->tx_idr_lock); 100 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 101 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 102 spin_unlock_bh(&tx_ring->tx_idr_lock); 103 104 if (ret < 0) 105 return -ENOSPC; 106 107 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 108 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 109 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 110 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 111 ti.meta_data_flags = arvif->tcl_metadata; 112 113 if (info->control.hw_key) 114 ti.encrypt_type = 115 ath11k_dp_tx_get_encrypt_type(info->control.hw_key->cipher); 116 else 117 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 118 119 ti.addr_search_flags = arvif->hal_addr_search_flags; 120 ti.search_type = arvif->search_type; 121 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 122 ti.pkt_offset = 0; 123 ti.lmac_id = ar->lmac_id; 124 ti.bss_ast_hash = arvif->ast_hash; 125 ti.dscp_tid_tbl_idx = 0; 126 127 if (skb->ip_summed == CHECKSUM_PARTIAL) { 128 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 129 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 130 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 131 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 132 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 133 } 134 135 if (ieee80211_vif_is_mesh(arvif->vif)) 136 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1); 137 138 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 139 140 ti.tid = ath11k_dp_tx_get_tid(skb); 141 142 switch (ti.encap_type) { 143 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 144 ath11k_dp_tx_encap_nwifi(skb); 145 break; 146 case HAL_TCL_ENCAP_TYPE_RAW: 147 /* TODO: for CHECKSUM_PARTIAL case in raw mode, HW checksum offload 148 * is not applicable, hence manual checksum calculation using 149 * skb_checksum_help() is needed 150 */ 151 case HAL_TCL_ENCAP_TYPE_ETHERNET: 152 case HAL_TCL_ENCAP_TYPE_802_3: 153 /* TODO: Take care of other encap modes as well */ 154 ret = -EINVAL; 155 goto fail_remove_idr; 156 } 157 158 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 159 if (dma_mapping_error(ab->dev, ti.paddr)) { 160 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 161 ret = -ENOMEM; 162 goto fail_remove_idr; 163 } 164 165 ti.data_len = skb->len; 166 skb_cb->paddr = ti.paddr; 167 skb_cb->vif = arvif->vif; 168 skb_cb->ar = ar; 169 170 memset(cached_desc, 0, HAL_TCL_DESC_LEN); 171 172 ath11k_hal_tx_cmd_desc_setup(ab, cached_desc, &ti); 173 174 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 175 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 176 177 spin_lock_bh(&tcl_ring->lock); 178 179 ath11k_hal_srng_access_begin(ab, tcl_ring); 180 181 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 182 if (!hal_tcl_desc) { 183 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 184 * desc because the desc is directly enqueued onto hw queue. 185 * So add tx packet throttling logic in future if required. 186 */ 187 ath11k_hal_srng_access_end(ab, tcl_ring); 188 spin_unlock_bh(&tcl_ring->lock); 189 ret = -ENOMEM; 190 goto fail_unmap_dma; 191 } 192 193 ath11k_hal_tx_desc_sync(cached_desc, hal_tcl_desc); 194 195 ath11k_hal_srng_access_end(ab, tcl_ring); 196 197 spin_unlock_bh(&tcl_ring->lock); 198 199 atomic_inc(&ar->dp.num_tx_pending); 200 201 return 0; 202 203 fail_unmap_dma: 204 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 205 206 fail_remove_idr: 207 spin_lock_bh(&tx_ring->tx_idr_lock); 208 idr_remove(&tx_ring->txbuf_idr, 209 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 210 spin_unlock_bh(&tx_ring->tx_idr_lock); 211 212 return ret; 213 } 214 215 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 216 int msdu_id, 217 struct dp_tx_ring *tx_ring) 218 { 219 struct ath11k *ar; 220 struct sk_buff *msdu; 221 struct ath11k_skb_cb *skb_cb; 222 223 spin_lock_bh(&tx_ring->tx_idr_lock); 224 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 225 if (!msdu) { 226 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 227 msdu_id); 228 spin_unlock_bh(&tx_ring->tx_idr_lock); 229 return; 230 } 231 232 skb_cb = ATH11K_SKB_CB(msdu); 233 234 idr_remove(&tx_ring->txbuf_idr, msdu_id); 235 spin_unlock_bh(&tx_ring->tx_idr_lock); 236 237 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 238 dev_kfree_skb_any(msdu); 239 240 ar = ab->pdevs[mac_id].ar; 241 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 242 wake_up(&ar->dp.tx_empty_waitq); 243 } 244 245 static void 246 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 247 struct dp_tx_ring *tx_ring, 248 struct ath11k_dp_htt_wbm_tx_status *ts) 249 { 250 struct sk_buff *msdu; 251 struct ieee80211_tx_info *info; 252 struct ath11k_skb_cb *skb_cb; 253 struct ath11k *ar; 254 255 spin_lock_bh(&tx_ring->tx_idr_lock); 256 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 257 if (!msdu) { 258 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 259 ts->msdu_id); 260 spin_unlock_bh(&tx_ring->tx_idr_lock); 261 return; 262 } 263 264 skb_cb = ATH11K_SKB_CB(msdu); 265 info = IEEE80211_SKB_CB(msdu); 266 267 ar = skb_cb->ar; 268 269 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 270 spin_unlock_bh(&tx_ring->tx_idr_lock); 271 272 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 273 wake_up(&ar->dp.tx_empty_waitq); 274 275 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 276 277 memset(&info->status, 0, sizeof(info->status)); 278 279 if (ts->acked) { 280 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 281 info->flags |= IEEE80211_TX_STAT_ACK; 282 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 283 ts->ack_rssi; 284 info->status.is_valid_ack_signal = true; 285 } else { 286 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 287 } 288 } 289 290 ieee80211_tx_status(ar->hw, msdu); 291 } 292 293 static void 294 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 295 void *desc, u8 mac_id, 296 u32 msdu_id, struct dp_tx_ring *tx_ring) 297 { 298 struct htt_tx_wbm_completion *status_desc; 299 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 300 enum hal_wbm_htt_tx_comp_status wbm_status; 301 302 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 303 304 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 305 status_desc->info0); 306 307 switch (wbm_status) { 308 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 309 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 310 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 311 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 312 ts.msdu_id = msdu_id; 313 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 314 status_desc->info1); 315 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 316 break; 317 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 318 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 319 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 320 break; 321 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 322 /* This event is to be handled only when the driver decides to 323 * use WDS offload functionality. 324 */ 325 break; 326 default: 327 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 328 break; 329 } 330 } 331 332 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 333 struct sk_buff *msdu, 334 struct hal_tx_status *ts) 335 { 336 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 337 338 if (ts->try_cnt > 1) { 339 peer_stats->retry_pkts += ts->try_cnt - 1; 340 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 341 342 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 343 peer_stats->failed_pkts += 1; 344 peer_stats->failed_bytes += msdu->len; 345 } 346 } 347 } 348 349 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 350 struct sk_buff *msdu, 351 struct hal_tx_status *ts) 352 { 353 struct ath11k_base *ab = ar->ab; 354 struct ieee80211_tx_info *info; 355 struct ath11k_skb_cb *skb_cb; 356 357 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 358 /* Must not happen */ 359 return; 360 } 361 362 skb_cb = ATH11K_SKB_CB(msdu); 363 364 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 365 366 rcu_read_lock(); 367 368 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 369 dev_kfree_skb_any(msdu); 370 goto exit; 371 } 372 373 if (!skb_cb->vif) { 374 dev_kfree_skb_any(msdu); 375 goto exit; 376 } 377 378 info = IEEE80211_SKB_CB(msdu); 379 memset(&info->status, 0, sizeof(info->status)); 380 381 /* skip tx rate update from ieee80211_status*/ 382 info->status.rates[0].idx = -1; 383 384 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 385 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 386 info->flags |= IEEE80211_TX_STAT_ACK; 387 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 388 ts->ack_rssi; 389 info->status.is_valid_ack_signal = true; 390 } 391 392 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 393 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 394 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 395 396 if (ath11k_debug_is_extd_tx_stats_enabled(ar)) { 397 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 398 if (ar->last_ppdu_id == 0) { 399 ar->last_ppdu_id = ts->ppdu_id; 400 } else if (ar->last_ppdu_id == ts->ppdu_id || 401 ar->cached_ppdu_id == ar->last_ppdu_id) { 402 ar->cached_ppdu_id = ar->last_ppdu_id; 403 ar->cached_stats.is_ampdu = true; 404 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts); 405 memset(&ar->cached_stats, 0, 406 sizeof(struct ath11k_per_peer_tx_stats)); 407 } else { 408 ar->cached_stats.is_ampdu = false; 409 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts); 410 memset(&ar->cached_stats, 0, 411 sizeof(struct ath11k_per_peer_tx_stats)); 412 } 413 ar->last_ppdu_id = ts->ppdu_id; 414 } 415 416 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 417 } 418 419 /* NOTE: Tx rate status reporting. Tx completion status does not have 420 * necessary information (for example nss) to build the tx rate. 421 * Might end up reporting it out-of-band from HTT stats. 422 */ 423 424 ieee80211_tx_status(ar->hw, msdu); 425 426 exit: 427 rcu_read_unlock(); 428 } 429 430 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 431 { 432 struct ath11k *ar; 433 struct ath11k_dp *dp = &ab->dp; 434 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 435 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 436 struct sk_buff *msdu; 437 struct hal_wbm_release_ring tx_status; 438 struct hal_tx_status ts; 439 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 440 u32 *desc; 441 u32 msdu_id; 442 u8 mac_id; 443 444 spin_lock_bh(&status_ring->lock); 445 446 ath11k_hal_srng_access_begin(ab, status_ring); 447 448 spin_lock_bh(&tx_ring->tx_status_lock); 449 while (!kfifo_is_full(&tx_ring->tx_status_fifo) && 450 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 451 ath11k_hal_tx_status_desc_sync((void *)desc, 452 (void *)&tx_status); 453 kfifo_put(&tx_ring->tx_status_fifo, tx_status); 454 } 455 456 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 457 kfifo_is_full(&tx_ring->tx_status_fifo)) { 458 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 459 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 460 } 461 462 spin_unlock_bh(&tx_ring->tx_status_lock); 463 464 ath11k_hal_srng_access_end(ab, status_ring); 465 spin_unlock_bh(&status_ring->lock); 466 467 spin_lock_bh(&tx_ring->tx_status_lock); 468 while (kfifo_get(&tx_ring->tx_status_fifo, &tx_status)) { 469 memset(&ts, 0, sizeof(ts)); 470 ath11k_hal_tx_status_parse(ab, &tx_status, &ts); 471 472 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, ts.desc_id); 473 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ts.desc_id); 474 475 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 476 ath11k_dp_tx_process_htt_tx_complete(ab, 477 (void *)&tx_status, 478 mac_id, msdu_id, 479 tx_ring); 480 continue; 481 } 482 483 spin_lock_bh(&tx_ring->tx_idr_lock); 484 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 485 if (!msdu) { 486 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 487 msdu_id); 488 spin_unlock_bh(&tx_ring->tx_idr_lock); 489 continue; 490 } 491 idr_remove(&tx_ring->txbuf_idr, msdu_id); 492 spin_unlock_bh(&tx_ring->tx_idr_lock); 493 494 ar = ab->pdevs[mac_id].ar; 495 496 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 497 wake_up(&ar->dp.tx_empty_waitq); 498 499 /* TODO: Locking optimization so that tx_completion for an msdu 500 * is not called with tx_status_lock acquired 501 */ 502 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 503 } 504 spin_unlock_bh(&tx_ring->tx_status_lock); 505 } 506 507 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 508 enum hal_reo_cmd_type type, 509 struct ath11k_hal_reo_cmd *cmd, 510 void (*cb)(struct ath11k_dp *, void *, 511 enum hal_reo_cmd_status)) 512 { 513 struct ath11k_dp *dp = &ab->dp; 514 struct dp_reo_cmd *dp_cmd; 515 struct hal_srng *cmd_ring; 516 int cmd_num; 517 518 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 519 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 520 521 /* reo cmd ring descriptors has cmd_num starting from 1 */ 522 if (cmd_num <= 0) 523 return -EINVAL; 524 525 if (!cb) 526 return 0; 527 528 /* Can this be optimized so that we keep the pending command list only 529 * for tid delete command to free up the resoruce on the command status 530 * indication? 531 */ 532 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 533 534 if (!dp_cmd) 535 return -ENOMEM; 536 537 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 538 dp_cmd->cmd_num = cmd_num; 539 dp_cmd->handler = cb; 540 541 spin_lock_bh(&dp->reo_cmd_lock); 542 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 543 spin_unlock_bh(&dp->reo_cmd_lock); 544 545 return 0; 546 } 547 548 static int 549 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 550 int mac_id, u32 ring_id, 551 enum hal_ring_type ring_type, 552 enum htt_srng_ring_type *htt_ring_type, 553 enum htt_srng_ring_id *htt_ring_id) 554 { 555 int lmac_ring_id_offset = 0; 556 int ret = 0; 557 558 switch (ring_type) { 559 case HAL_RXDMA_BUF: 560 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 561 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 562 lmac_ring_id_offset) || 563 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 564 lmac_ring_id_offset))) { 565 ret = -EINVAL; 566 } 567 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 568 *htt_ring_type = HTT_SW_TO_HW_RING; 569 break; 570 case HAL_RXDMA_DST: 571 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 572 *htt_ring_type = HTT_HW_TO_SW_RING; 573 break; 574 case HAL_RXDMA_MONITOR_BUF: 575 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 576 *htt_ring_type = HTT_SW_TO_HW_RING; 577 break; 578 case HAL_RXDMA_MONITOR_STATUS: 579 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 580 *htt_ring_type = HTT_SW_TO_HW_RING; 581 break; 582 case HAL_RXDMA_MONITOR_DST: 583 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 584 *htt_ring_type = HTT_HW_TO_SW_RING; 585 break; 586 case HAL_RXDMA_MONITOR_DESC: 587 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 588 *htt_ring_type = HTT_SW_TO_HW_RING; 589 break; 590 default: 591 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 592 ret = -EINVAL; 593 } 594 return ret; 595 } 596 597 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 598 int mac_id, enum hal_ring_type ring_type) 599 { 600 struct htt_srng_setup_cmd *cmd; 601 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 602 struct hal_srng_params params; 603 struct sk_buff *skb; 604 u32 ring_entry_sz; 605 int len = sizeof(*cmd); 606 dma_addr_t hp_addr, tp_addr; 607 enum htt_srng_ring_type htt_ring_type; 608 enum htt_srng_ring_id htt_ring_id; 609 int ret = 0; 610 611 skb = ath11k_htc_alloc_skb(ab, len); 612 if (!skb) 613 return -ENOMEM; 614 615 memset(¶ms, 0, sizeof(params)); 616 ath11k_hal_srng_get_params(ab, srng, ¶ms); 617 618 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 619 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 620 621 if (ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 622 ring_type, &htt_ring_type, 623 &htt_ring_id)) 624 goto err_free; 625 626 skb_put(skb, len); 627 cmd = (struct htt_srng_setup_cmd *)skb->data; 628 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 629 HTT_H2T_MSG_TYPE_SRING_SETUP); 630 if (htt_ring_type == HTT_SW_TO_HW_RING || 631 htt_ring_type == HTT_HW_TO_SW_RING) 632 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 633 DP_SW2HW_MACID(mac_id)); 634 else 635 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 636 mac_id); 637 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 638 htt_ring_type); 639 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 640 641 cmd->ring_base_addr_lo = params.ring_base_paddr & 642 HAL_ADDR_LSB_REG_MASK; 643 644 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 645 HAL_ADDR_MSB_REG_SHIFT; 646 647 ret = ath11k_hal_srng_get_entrysize(ring_type); 648 if (ret < 0) 649 return -EINVAL; 650 651 ring_entry_sz = ret; 652 653 ring_entry_sz >>= 2; 654 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 655 ring_entry_sz); 656 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 657 params.num_entries * ring_entry_sz); 658 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 659 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 660 cmd->info1 |= FIELD_PREP( 661 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 662 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 663 cmd->info1 |= FIELD_PREP( 664 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 665 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 666 if (htt_ring_type == HTT_SW_TO_HW_RING) 667 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 668 669 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 670 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 671 HAL_ADDR_MSB_REG_SHIFT; 672 673 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 674 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 675 HAL_ADDR_MSB_REG_SHIFT; 676 677 cmd->ring_msi_addr_lo = 0; 678 cmd->ring_msi_addr_hi = 0; 679 cmd->msi_data = 0; 680 681 cmd->intr_info = FIELD_PREP( 682 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 683 params.intr_batch_cntr_thres_entries * ring_entry_sz); 684 cmd->intr_info |= FIELD_PREP( 685 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 686 params.intr_timer_thres_us >> 3); 687 688 cmd->info2 = 0; 689 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 690 cmd->info2 = FIELD_PREP( 691 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 692 params.low_threshold); 693 } 694 695 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 696 if (ret) 697 goto err_free; 698 699 return 0; 700 701 err_free: 702 dev_kfree_skb_any(skb); 703 704 return ret; 705 } 706 707 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 708 709 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 710 { 711 struct ath11k_dp *dp = &ab->dp; 712 struct sk_buff *skb; 713 struct htt_ver_req_cmd *cmd; 714 int len = sizeof(*cmd); 715 int ret; 716 717 init_completion(&dp->htt_tgt_version_received); 718 719 skb = ath11k_htc_alloc_skb(ab, len); 720 if (!skb) 721 return -ENOMEM; 722 723 skb_put(skb, len); 724 cmd = (struct htt_ver_req_cmd *)skb->data; 725 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 726 HTT_H2T_MSG_TYPE_VERSION_REQ); 727 728 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 729 if (ret) { 730 dev_kfree_skb_any(skb); 731 return ret; 732 } 733 734 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 735 HTT_TARGET_VERSION_TIMEOUT_HZ); 736 if (ret == 0) { 737 ath11k_warn(ab, "htt target version request timed out\n"); 738 return -ETIMEDOUT; 739 } 740 741 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 742 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 743 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 744 return -ENOTSUPP; 745 } 746 747 return 0; 748 } 749 750 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 751 { 752 struct ath11k_base *ab = ar->ab; 753 struct ath11k_dp *dp = &ab->dp; 754 struct sk_buff *skb; 755 struct htt_ppdu_stats_cfg_cmd *cmd; 756 int len = sizeof(*cmd); 757 u8 pdev_mask; 758 int ret; 759 760 skb = ath11k_htc_alloc_skb(ab, len); 761 if (!skb) 762 return -ENOMEM; 763 764 skb_put(skb, len); 765 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 766 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 767 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 768 769 pdev_mask = 1 << (ar->pdev_idx); 770 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 771 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 772 773 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 774 if (ret) { 775 dev_kfree_skb_any(skb); 776 return ret; 777 } 778 779 return 0; 780 } 781 782 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 783 int mac_id, enum hal_ring_type ring_type, 784 int rx_buf_size, 785 struct htt_rx_ring_tlv_filter *tlv_filter) 786 { 787 struct htt_rx_ring_selection_cfg_cmd *cmd; 788 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 789 struct hal_srng_params params; 790 struct sk_buff *skb; 791 int len = sizeof(*cmd); 792 enum htt_srng_ring_type htt_ring_type; 793 enum htt_srng_ring_id htt_ring_id; 794 int ret = 0; 795 796 skb = ath11k_htc_alloc_skb(ab, len); 797 if (!skb) 798 return -ENOMEM; 799 800 memset(¶ms, 0, sizeof(params)); 801 ath11k_hal_srng_get_params(ab, srng, ¶ms); 802 803 if (ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 804 ring_type, &htt_ring_type, 805 &htt_ring_id)) 806 goto err_free; 807 808 skb_put(skb, len); 809 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 810 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 811 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 812 if (htt_ring_type == HTT_SW_TO_HW_RING || 813 htt_ring_type == HTT_HW_TO_SW_RING) 814 cmd->info0 |= 815 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 816 DP_SW2HW_MACID(mac_id)); 817 else 818 cmd->info0 |= 819 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 820 mac_id); 821 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 822 htt_ring_id); 823 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 824 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 825 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 826 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 827 828 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 829 rx_buf_size); 830 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 831 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 832 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 833 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 834 cmd->rx_filter_tlv = tlv_filter->rx_filter; 835 836 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 837 if (ret) 838 goto err_free; 839 840 return 0; 841 842 err_free: 843 dev_kfree_skb_any(skb); 844 845 return ret; 846 } 847 848 int 849 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 850 struct htt_ext_stats_cfg_params *cfg_params, 851 u64 cookie) 852 { 853 struct ath11k_base *ab = ar->ab; 854 struct ath11k_dp *dp = &ab->dp; 855 struct sk_buff *skb; 856 struct htt_ext_stats_cfg_cmd *cmd; 857 int len = sizeof(*cmd); 858 int ret; 859 860 skb = ath11k_htc_alloc_skb(ab, len); 861 if (!skb) 862 return -ENOMEM; 863 864 skb_put(skb, len); 865 866 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 867 memset(cmd, 0, sizeof(*cmd)); 868 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 869 870 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 871 872 cmd->hdr.stats_type = type; 873 cmd->cfg_param0 = cfg_params->cfg0; 874 cmd->cfg_param1 = cfg_params->cfg1; 875 cmd->cfg_param2 = cfg_params->cfg2; 876 cmd->cfg_param3 = cfg_params->cfg3; 877 cmd->cookie_lsb = lower_32_bits(cookie); 878 cmd->cookie_msb = upper_32_bits(cookie); 879 880 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 881 if (ret) { 882 ath11k_warn(ab, "failed to send htt type stats request: %d", 883 ret); 884 dev_kfree_skb_any(skb); 885 return ret; 886 } 887 888 return 0; 889 } 890 891 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 892 { 893 struct ath11k_pdev_dp *dp = &ar->dp; 894 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 895 int ret = 0, ring_id = 0; 896 897 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 898 899 if (!reset) { 900 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 901 tlv_filter.pkt_filter_flags0 = 902 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 903 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 904 tlv_filter.pkt_filter_flags1 = 905 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 906 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 907 tlv_filter.pkt_filter_flags2 = 908 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 909 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 910 tlv_filter.pkt_filter_flags3 = 911 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 912 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 913 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 914 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 915 } 916 917 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 918 HAL_RXDMA_MONITOR_BUF, 919 DP_RXDMA_REFILL_RING_SIZE, 920 &tlv_filter); 921 if (ret) 922 return ret; 923 924 ring_id = dp->rx_mon_status_refill_ring.refill_buf_ring.ring_id; 925 if (!reset) 926 tlv_filter.rx_filter = 927 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 928 else 929 tlv_filter = ath11k_mac_mon_status_filter_default; 930 931 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 932 HAL_RXDMA_MONITOR_STATUS, 933 DP_RXDMA_REFILL_RING_SIZE, 934 &tlv_filter); 935 return ret; 936 } 937