1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 #include "mac.h" 13 14 static enum hal_tcl_encap_type 15 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 16 { 17 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 18 struct ath11k_base *ab = arvif->ar->ab; 19 20 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 21 return HAL_TCL_ENCAP_TYPE_RAW; 22 23 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 24 return HAL_TCL_ENCAP_TYPE_ETHERNET; 25 26 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 27 } 28 29 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 30 { 31 struct ieee80211_hdr *hdr = (void *)skb->data; 32 u8 *qos_ctl; 33 34 if (!ieee80211_is_data_qos(hdr->frame_control)) 35 return; 36 37 qos_ctl = ieee80211_get_qos_ctl(hdr); 38 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 39 skb->data, (void *)qos_ctl - (void *)skb->data); 40 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 41 42 hdr = (void *)skb->data; 43 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 44 } 45 46 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 47 { 48 struct ieee80211_hdr *hdr = (void *)skb->data; 49 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 50 51 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 52 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 53 else if (!ieee80211_is_data_qos(hdr->frame_control)) 54 return HAL_DESC_REO_NON_QOS_TID; 55 else 56 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 57 } 58 59 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 60 { 61 switch (cipher) { 62 case WLAN_CIPHER_SUITE_WEP40: 63 return HAL_ENCRYPT_TYPE_WEP_40; 64 case WLAN_CIPHER_SUITE_WEP104: 65 return HAL_ENCRYPT_TYPE_WEP_104; 66 case WLAN_CIPHER_SUITE_TKIP: 67 return HAL_ENCRYPT_TYPE_TKIP_MIC; 68 case WLAN_CIPHER_SUITE_CCMP: 69 return HAL_ENCRYPT_TYPE_CCMP_128; 70 case WLAN_CIPHER_SUITE_CCMP_256: 71 return HAL_ENCRYPT_TYPE_CCMP_256; 72 case WLAN_CIPHER_SUITE_GCMP: 73 return HAL_ENCRYPT_TYPE_GCMP_128; 74 case WLAN_CIPHER_SUITE_GCMP_256: 75 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 76 default: 77 return HAL_ENCRYPT_TYPE_OPEN; 78 } 79 } 80 81 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 82 struct ath11k_sta *arsta, struct sk_buff *skb) 83 { 84 struct ath11k_base *ab = ar->ab; 85 struct ath11k_dp *dp = &ab->dp; 86 struct hal_tx_info ti = {0}; 87 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 88 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 89 struct hal_srng *tcl_ring; 90 struct ieee80211_hdr *hdr = (void *)skb->data; 91 struct dp_tx_ring *tx_ring; 92 void *hal_tcl_desc; 93 u8 pool_id; 94 u8 hal_ring_id; 95 int ret; 96 u8 ring_selector = 0, ring_map = 0; 97 bool tcl_ring_retry; 98 99 if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) 100 return -ESHUTDOWN; 101 102 if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 103 !ieee80211_is_data(hdr->frame_control))) 104 return -ENOTSUPP; 105 106 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 107 108 /* Let the default ring selection be based on current processor 109 * number, where one of the 3 tcl rings are selected based on 110 * the smp_processor_id(). In case that ring 111 * is full/busy, we resort to other available rings. 112 * If all rings are full, we drop the packet. 113 * //TODO Add throttling logic when all rings are full 114 */ 115 ring_selector = smp_processor_id(); 116 117 tcl_ring_sel: 118 tcl_ring_retry = false; 119 120 ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; 121 122 ring_map |= BIT(ti.ring_id); 123 124 tx_ring = &dp->tx_ring[ti.ring_id]; 125 126 spin_lock_bh(&tx_ring->tx_idr_lock); 127 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 128 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 129 spin_unlock_bh(&tx_ring->tx_idr_lock); 130 131 if (unlikely(ret < 0)) { 132 if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) { 133 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 134 return -ENOSPC; 135 } 136 137 /* Check if the next ring is available */ 138 ring_selector++; 139 goto tcl_ring_sel; 140 } 141 142 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 143 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 144 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 145 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 146 147 if (ieee80211_has_a4(hdr->frame_control) && 148 is_multicast_ether_addr(hdr->addr3) && arsta && 149 arsta->use_4addr_set) { 150 ti.meta_data_flags = arsta->tcl_metadata; 151 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 152 } else { 153 ti.meta_data_flags = arvif->tcl_metadata; 154 } 155 156 if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) { 157 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 158 ti.encrypt_type = 159 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 160 161 if (ieee80211_has_protected(hdr->frame_control)) 162 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 163 } else { 164 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 165 } 166 } 167 168 ti.addr_search_flags = arvif->hal_addr_search_flags; 169 ti.search_type = arvif->search_type; 170 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 171 ti.pkt_offset = 0; 172 ti.lmac_id = ar->lmac_id; 173 ti.bss_ast_hash = arvif->ast_hash; 174 ti.bss_ast_idx = arvif->ast_idx; 175 ti.dscp_tid_tbl_idx = 0; 176 177 if (likely(skb->ip_summed == CHECKSUM_PARTIAL && 178 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) { 179 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 180 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 181 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 182 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 183 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 184 } 185 186 if (ieee80211_vif_is_mesh(arvif->vif)) 187 ti.enable_mesh = true; 188 189 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 190 191 ti.tid = ath11k_dp_tx_get_tid(skb); 192 193 switch (ti.encap_type) { 194 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 195 ath11k_dp_tx_encap_nwifi(skb); 196 break; 197 case HAL_TCL_ENCAP_TYPE_RAW: 198 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 199 ret = -EINVAL; 200 goto fail_remove_idr; 201 } 202 break; 203 case HAL_TCL_ENCAP_TYPE_ETHERNET: 204 /* no need to encap */ 205 break; 206 case HAL_TCL_ENCAP_TYPE_802_3: 207 default: 208 /* TODO: Take care of other encap modes as well */ 209 ret = -EINVAL; 210 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 211 goto fail_remove_idr; 212 } 213 214 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 215 if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { 216 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 217 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 218 ret = -ENOMEM; 219 goto fail_remove_idr; 220 } 221 222 ti.data_len = skb->len; 223 skb_cb->paddr = ti.paddr; 224 skb_cb->vif = arvif->vif; 225 skb_cb->ar = ar; 226 227 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 228 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 229 230 spin_lock_bh(&tcl_ring->lock); 231 232 ath11k_hal_srng_access_begin(ab, tcl_ring); 233 234 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 235 if (unlikely(!hal_tcl_desc)) { 236 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 237 * desc because the desc is directly enqueued onto hw queue. 238 */ 239 ath11k_hal_srng_access_end(ab, tcl_ring); 240 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 241 spin_unlock_bh(&tcl_ring->lock); 242 ret = -ENOMEM; 243 244 /* Checking for available tcl descritors in another ring in 245 * case of failure due to full tcl ring now, is better than 246 * checking this ring earlier for each pkt tx. 247 * Restart ring selection if some rings are not checked yet. 248 */ 249 if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) && 250 ab->hw_params.max_tx_ring > 1) { 251 tcl_ring_retry = true; 252 ring_selector++; 253 } 254 255 goto fail_unmap_dma; 256 } 257 258 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 259 sizeof(struct hal_tlv_hdr), &ti); 260 261 ath11k_hal_srng_access_end(ab, tcl_ring); 262 263 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 264 265 spin_unlock_bh(&tcl_ring->lock); 266 267 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 268 skb->data, skb->len); 269 270 atomic_inc(&ar->dp.num_tx_pending); 271 272 return 0; 273 274 fail_unmap_dma: 275 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 276 277 fail_remove_idr: 278 spin_lock_bh(&tx_ring->tx_idr_lock); 279 idr_remove(&tx_ring->txbuf_idr, 280 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 281 spin_unlock_bh(&tx_ring->tx_idr_lock); 282 283 if (tcl_ring_retry) 284 goto tcl_ring_sel; 285 286 return ret; 287 } 288 289 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 290 int msdu_id, 291 struct dp_tx_ring *tx_ring) 292 { 293 struct ath11k *ar; 294 struct sk_buff *msdu; 295 struct ath11k_skb_cb *skb_cb; 296 297 spin_lock(&tx_ring->tx_idr_lock); 298 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 299 spin_unlock(&tx_ring->tx_idr_lock); 300 301 if (unlikely(!msdu)) { 302 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 303 msdu_id); 304 return; 305 } 306 307 skb_cb = ATH11K_SKB_CB(msdu); 308 309 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 310 dev_kfree_skb_any(msdu); 311 312 ar = ab->pdevs[mac_id].ar; 313 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 314 wake_up(&ar->dp.tx_empty_waitq); 315 } 316 317 static void 318 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 319 struct dp_tx_ring *tx_ring, 320 struct ath11k_dp_htt_wbm_tx_status *ts) 321 { 322 struct sk_buff *msdu; 323 struct ieee80211_tx_info *info; 324 struct ath11k_skb_cb *skb_cb; 325 struct ath11k *ar; 326 327 spin_lock(&tx_ring->tx_idr_lock); 328 msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 329 spin_unlock(&tx_ring->tx_idr_lock); 330 331 if (unlikely(!msdu)) { 332 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 333 ts->msdu_id); 334 return; 335 } 336 337 skb_cb = ATH11K_SKB_CB(msdu); 338 info = IEEE80211_SKB_CB(msdu); 339 340 ar = skb_cb->ar; 341 342 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 343 wake_up(&ar->dp.tx_empty_waitq); 344 345 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 346 347 memset(&info->status, 0, sizeof(info->status)); 348 349 if (ts->acked) { 350 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 351 info->flags |= IEEE80211_TX_STAT_ACK; 352 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 353 ts->ack_rssi; 354 info->status.is_valid_ack_signal = true; 355 } else { 356 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 357 } 358 } 359 360 ieee80211_tx_status(ar->hw, msdu); 361 } 362 363 static void 364 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 365 void *desc, u8 mac_id, 366 u32 msdu_id, struct dp_tx_ring *tx_ring) 367 { 368 struct htt_tx_wbm_completion *status_desc; 369 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 370 enum hal_wbm_htt_tx_comp_status wbm_status; 371 372 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 373 374 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 375 status_desc->info0); 376 switch (wbm_status) { 377 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 378 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 379 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 380 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 381 ts.msdu_id = msdu_id; 382 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 383 status_desc->info1); 384 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 385 break; 386 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 387 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 388 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 389 break; 390 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 391 /* This event is to be handled only when the driver decides to 392 * use WDS offload functionality. 393 */ 394 break; 395 default: 396 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 397 break; 398 } 399 } 400 401 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 402 struct sk_buff *msdu, 403 struct hal_tx_status *ts) 404 { 405 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 406 407 if (ts->try_cnt > 1) { 408 peer_stats->retry_pkts += ts->try_cnt - 1; 409 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 410 411 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 412 peer_stats->failed_pkts += 1; 413 peer_stats->failed_bytes += msdu->len; 414 } 415 } 416 } 417 418 void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts) 419 { 420 struct ath11k_base *ab = ar->ab; 421 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 422 enum hal_tx_rate_stats_pkt_type pkt_type; 423 enum hal_tx_rate_stats_sgi sgi; 424 enum hal_tx_rate_stats_bw bw; 425 struct ath11k_peer *peer; 426 struct ath11k_sta *arsta; 427 struct ieee80211_sta *sta; 428 u16 rate, ru_tones; 429 u8 mcs, rate_idx, ofdma; 430 int ret; 431 432 spin_lock_bh(&ab->base_lock); 433 peer = ath11k_peer_find_by_id(ab, ts->peer_id); 434 if (!peer || !peer->sta) { 435 ath11k_dbg(ab, ATH11K_DBG_DP_TX, 436 "failed to find the peer by id %u\n", ts->peer_id); 437 goto err_out; 438 } 439 440 sta = peer->sta; 441 arsta = (struct ath11k_sta *)sta->drv_priv; 442 443 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 444 pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE, 445 ts->rate_stats); 446 mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS, 447 ts->rate_stats); 448 sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI, 449 ts->rate_stats); 450 bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats); 451 ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats); 452 ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats); 453 454 /* This is to prefer choose the real NSS value arsta->last_txrate.nss, 455 * if it is invalid, then choose the NSS value while assoc. 456 */ 457 if (arsta->last_txrate.nss) 458 arsta->txrate.nss = arsta->last_txrate.nss; 459 else 460 arsta->txrate.nss = arsta->peer_nss; 461 462 if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A || 463 pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) { 464 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 465 pkt_type, 466 &rate_idx, 467 &rate); 468 if (ret < 0) 469 goto err_out; 470 arsta->txrate.legacy = rate; 471 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) { 472 if (mcs > 7) { 473 ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs); 474 goto err_out; 475 } 476 477 if (arsta->txrate.nss != 0) 478 arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1); 479 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 480 if (sgi) 481 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 482 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) { 483 if (mcs > 9) { 484 ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs); 485 goto err_out; 486 } 487 488 arsta->txrate.mcs = mcs; 489 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 490 if (sgi) 491 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 492 } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 493 if (mcs > 11) { 494 ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs); 495 goto err_out; 496 } 497 498 arsta->txrate.mcs = mcs; 499 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 500 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 501 } 502 503 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 504 if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { 505 arsta->txrate.bw = RATE_INFO_BW_HE_RU; 506 arsta->txrate.he_ru_alloc = 507 ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 508 } 509 510 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 511 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 512 513 err_out: 514 spin_unlock_bh(&ab->base_lock); 515 } 516 517 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 518 struct sk_buff *msdu, 519 struct hal_tx_status *ts) 520 { 521 struct ath11k_base *ab = ar->ab; 522 struct ieee80211_tx_info *info; 523 struct ath11k_skb_cb *skb_cb; 524 525 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 526 /* Must not happen */ 527 return; 528 } 529 530 skb_cb = ATH11K_SKB_CB(msdu); 531 532 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 533 534 if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { 535 dev_kfree_skb_any(msdu); 536 return; 537 } 538 539 if (unlikely(!skb_cb->vif)) { 540 dev_kfree_skb_any(msdu); 541 return; 542 } 543 544 info = IEEE80211_SKB_CB(msdu); 545 memset(&info->status, 0, sizeof(info->status)); 546 547 /* skip tx rate update from ieee80211_status*/ 548 info->status.rates[0].idx = -1; 549 550 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 551 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 552 info->flags |= IEEE80211_TX_STAT_ACK; 553 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 554 ts->ack_rssi; 555 info->status.is_valid_ack_signal = true; 556 } 557 558 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 559 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 560 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 561 562 if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) || 563 ab->hw_params.single_pdev_only) { 564 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 565 if (ar->last_ppdu_id == 0) { 566 ar->last_ppdu_id = ts->ppdu_id; 567 } else if (ar->last_ppdu_id == ts->ppdu_id || 568 ar->cached_ppdu_id == ar->last_ppdu_id) { 569 ar->cached_ppdu_id = ar->last_ppdu_id; 570 ar->cached_stats.is_ampdu = true; 571 ath11k_dp_tx_update_txcompl(ar, ts); 572 memset(&ar->cached_stats, 0, 573 sizeof(struct ath11k_per_peer_tx_stats)); 574 } else { 575 ar->cached_stats.is_ampdu = false; 576 ath11k_dp_tx_update_txcompl(ar, ts); 577 memset(&ar->cached_stats, 0, 578 sizeof(struct ath11k_per_peer_tx_stats)); 579 } 580 ar->last_ppdu_id = ts->ppdu_id; 581 } 582 583 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 584 } 585 586 /* NOTE: Tx rate status reporting. Tx completion status does not have 587 * necessary information (for example nss) to build the tx rate. 588 * Might end up reporting it out-of-band from HTT stats. 589 */ 590 591 ieee80211_tx_status(ar->hw, msdu); 592 } 593 594 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 595 struct hal_wbm_release_ring *desc, 596 struct hal_tx_status *ts) 597 { 598 ts->buf_rel_source = 599 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 600 if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 601 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) 602 return; 603 604 if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) 605 return; 606 607 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 608 desc->info0); 609 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 610 desc->info1); 611 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 612 desc->info1); 613 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 614 desc->info2); 615 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 616 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 617 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 618 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 619 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 620 ts->rate_stats = desc->rate_stats.info0; 621 else 622 ts->rate_stats = 0; 623 } 624 625 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 626 { 627 struct ath11k *ar; 628 struct ath11k_dp *dp = &ab->dp; 629 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 630 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 631 struct sk_buff *msdu; 632 struct hal_tx_status ts = { 0 }; 633 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 634 u32 *desc; 635 u32 msdu_id; 636 u8 mac_id; 637 638 spin_lock_bh(&status_ring->lock); 639 640 ath11k_hal_srng_access_begin(ab, status_ring); 641 642 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 643 tx_ring->tx_status_tail) && 644 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 645 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 646 desc, sizeof(struct hal_wbm_release_ring)); 647 tx_ring->tx_status_head = 648 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 649 } 650 651 if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 652 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == 653 tx_ring->tx_status_tail))) { 654 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 655 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 656 } 657 658 ath11k_hal_srng_access_end(ab, status_ring); 659 660 spin_unlock_bh(&status_ring->lock); 661 662 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 663 struct hal_wbm_release_ring *tx_status; 664 u32 desc_id; 665 666 tx_ring->tx_status_tail = 667 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 668 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 669 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 670 671 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 672 tx_status->buf_addr_info.info1); 673 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 674 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 675 676 if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { 677 ath11k_dp_tx_process_htt_tx_complete(ab, 678 (void *)tx_status, 679 mac_id, msdu_id, 680 tx_ring); 681 continue; 682 } 683 684 spin_lock(&tx_ring->tx_idr_lock); 685 msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 686 if (unlikely(!msdu)) { 687 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 688 msdu_id); 689 spin_unlock(&tx_ring->tx_idr_lock); 690 continue; 691 } 692 693 spin_unlock(&tx_ring->tx_idr_lock); 694 695 ar = ab->pdevs[mac_id].ar; 696 697 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 698 wake_up(&ar->dp.tx_empty_waitq); 699 700 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 701 } 702 } 703 704 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 705 enum hal_reo_cmd_type type, 706 struct ath11k_hal_reo_cmd *cmd, 707 void (*cb)(struct ath11k_dp *, void *, 708 enum hal_reo_cmd_status)) 709 { 710 struct ath11k_dp *dp = &ab->dp; 711 struct dp_reo_cmd *dp_cmd; 712 struct hal_srng *cmd_ring; 713 int cmd_num; 714 715 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 716 return -ESHUTDOWN; 717 718 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 719 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 720 721 /* cmd_num should start from 1, during failure return the error code */ 722 if (cmd_num < 0) 723 return cmd_num; 724 725 /* reo cmd ring descriptors has cmd_num starting from 1 */ 726 if (cmd_num == 0) 727 return -EINVAL; 728 729 if (!cb) 730 return 0; 731 732 /* Can this be optimized so that we keep the pending command list only 733 * for tid delete command to free up the resoruce on the command status 734 * indication? 735 */ 736 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 737 738 if (!dp_cmd) 739 return -ENOMEM; 740 741 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 742 dp_cmd->cmd_num = cmd_num; 743 dp_cmd->handler = cb; 744 745 spin_lock_bh(&dp->reo_cmd_lock); 746 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 747 spin_unlock_bh(&dp->reo_cmd_lock); 748 749 return 0; 750 } 751 752 static int 753 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 754 int mac_id, u32 ring_id, 755 enum hal_ring_type ring_type, 756 enum htt_srng_ring_type *htt_ring_type, 757 enum htt_srng_ring_id *htt_ring_id) 758 { 759 int lmac_ring_id_offset = 0; 760 int ret = 0; 761 762 switch (ring_type) { 763 case HAL_RXDMA_BUF: 764 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 765 766 /* for QCA6390, host fills rx buffer to fw and fw fills to 767 * rxbuf ring for each rxdma 768 */ 769 if (!ab->hw_params.rx_mac_buf_ring) { 770 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 771 lmac_ring_id_offset) || 772 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 773 lmac_ring_id_offset))) { 774 ret = -EINVAL; 775 } 776 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 777 *htt_ring_type = HTT_SW_TO_HW_RING; 778 } else { 779 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 780 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 781 *htt_ring_type = HTT_SW_TO_SW_RING; 782 } else { 783 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 784 *htt_ring_type = HTT_SW_TO_HW_RING; 785 } 786 } 787 break; 788 case HAL_RXDMA_DST: 789 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 790 *htt_ring_type = HTT_HW_TO_SW_RING; 791 break; 792 case HAL_RXDMA_MONITOR_BUF: 793 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 794 *htt_ring_type = HTT_SW_TO_HW_RING; 795 break; 796 case HAL_RXDMA_MONITOR_STATUS: 797 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 798 *htt_ring_type = HTT_SW_TO_HW_RING; 799 break; 800 case HAL_RXDMA_MONITOR_DST: 801 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 802 *htt_ring_type = HTT_HW_TO_SW_RING; 803 break; 804 case HAL_RXDMA_MONITOR_DESC: 805 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 806 *htt_ring_type = HTT_SW_TO_HW_RING; 807 break; 808 default: 809 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 810 ret = -EINVAL; 811 } 812 return ret; 813 } 814 815 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 816 int mac_id, enum hal_ring_type ring_type) 817 { 818 struct htt_srng_setup_cmd *cmd; 819 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 820 struct hal_srng_params params; 821 struct sk_buff *skb; 822 u32 ring_entry_sz; 823 int len = sizeof(*cmd); 824 dma_addr_t hp_addr, tp_addr; 825 enum htt_srng_ring_type htt_ring_type; 826 enum htt_srng_ring_id htt_ring_id; 827 int ret; 828 829 skb = ath11k_htc_alloc_skb(ab, len); 830 if (!skb) 831 return -ENOMEM; 832 833 memset(¶ms, 0, sizeof(params)); 834 ath11k_hal_srng_get_params(ab, srng, ¶ms); 835 836 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 837 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 838 839 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 840 ring_type, &htt_ring_type, 841 &htt_ring_id); 842 if (ret) 843 goto err_free; 844 845 skb_put(skb, len); 846 cmd = (struct htt_srng_setup_cmd *)skb->data; 847 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 848 HTT_H2T_MSG_TYPE_SRING_SETUP); 849 if (htt_ring_type == HTT_SW_TO_HW_RING || 850 htt_ring_type == HTT_HW_TO_SW_RING) 851 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 852 DP_SW2HW_MACID(mac_id)); 853 else 854 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 855 mac_id); 856 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 857 htt_ring_type); 858 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 859 860 cmd->ring_base_addr_lo = params.ring_base_paddr & 861 HAL_ADDR_LSB_REG_MASK; 862 863 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 864 HAL_ADDR_MSB_REG_SHIFT; 865 866 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 867 if (ret < 0) 868 goto err_free; 869 870 ring_entry_sz = ret; 871 872 ring_entry_sz >>= 2; 873 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 874 ring_entry_sz); 875 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 876 params.num_entries * ring_entry_sz); 877 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 878 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 879 cmd->info1 |= FIELD_PREP( 880 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 881 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 882 cmd->info1 |= FIELD_PREP( 883 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 884 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 885 if (htt_ring_type == HTT_SW_TO_HW_RING) 886 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 887 888 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 889 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 890 HAL_ADDR_MSB_REG_SHIFT; 891 892 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 893 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 894 HAL_ADDR_MSB_REG_SHIFT; 895 896 cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 897 cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 898 cmd->msi_data = params.msi_data; 899 900 cmd->intr_info = FIELD_PREP( 901 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 902 params.intr_batch_cntr_thres_entries * ring_entry_sz); 903 cmd->intr_info |= FIELD_PREP( 904 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 905 params.intr_timer_thres_us >> 3); 906 907 cmd->info2 = 0; 908 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 909 cmd->info2 = FIELD_PREP( 910 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 911 params.low_threshold); 912 } 913 914 ath11k_dbg(ab, ATH11k_DBG_HAL, 915 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 916 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 917 cmd->msi_data); 918 919 ath11k_dbg(ab, ATH11k_DBG_HAL, 920 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 921 ring_id, ring_type, cmd->intr_info, cmd->info2); 922 923 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 924 if (ret) 925 goto err_free; 926 927 return 0; 928 929 err_free: 930 dev_kfree_skb_any(skb); 931 932 return ret; 933 } 934 935 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 936 937 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 938 { 939 struct ath11k_dp *dp = &ab->dp; 940 struct sk_buff *skb; 941 struct htt_ver_req_cmd *cmd; 942 int len = sizeof(*cmd); 943 int ret; 944 945 init_completion(&dp->htt_tgt_version_received); 946 947 skb = ath11k_htc_alloc_skb(ab, len); 948 if (!skb) 949 return -ENOMEM; 950 951 skb_put(skb, len); 952 cmd = (struct htt_ver_req_cmd *)skb->data; 953 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 954 HTT_H2T_MSG_TYPE_VERSION_REQ); 955 956 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 957 if (ret) { 958 dev_kfree_skb_any(skb); 959 return ret; 960 } 961 962 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 963 HTT_TARGET_VERSION_TIMEOUT_HZ); 964 if (ret == 0) { 965 ath11k_warn(ab, "htt target version request timed out\n"); 966 return -ETIMEDOUT; 967 } 968 969 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 970 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 971 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 972 return -ENOTSUPP; 973 } 974 975 return 0; 976 } 977 978 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 979 { 980 struct ath11k_base *ab = ar->ab; 981 struct ath11k_dp *dp = &ab->dp; 982 struct sk_buff *skb; 983 struct htt_ppdu_stats_cfg_cmd *cmd; 984 int len = sizeof(*cmd); 985 u8 pdev_mask; 986 int ret; 987 int i; 988 989 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 990 skb = ath11k_htc_alloc_skb(ab, len); 991 if (!skb) 992 return -ENOMEM; 993 994 skb_put(skb, len); 995 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 996 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 997 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 998 999 pdev_mask = 1 << (ar->pdev_idx + i); 1000 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 1001 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 1002 1003 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1004 if (ret) { 1005 dev_kfree_skb_any(skb); 1006 return ret; 1007 } 1008 } 1009 1010 return 0; 1011 } 1012 1013 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 1014 int mac_id, enum hal_ring_type ring_type, 1015 int rx_buf_size, 1016 struct htt_rx_ring_tlv_filter *tlv_filter) 1017 { 1018 struct htt_rx_ring_selection_cfg_cmd *cmd; 1019 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1020 struct hal_srng_params params; 1021 struct sk_buff *skb; 1022 int len = sizeof(*cmd); 1023 enum htt_srng_ring_type htt_ring_type; 1024 enum htt_srng_ring_id htt_ring_id; 1025 int ret; 1026 1027 skb = ath11k_htc_alloc_skb(ab, len); 1028 if (!skb) 1029 return -ENOMEM; 1030 1031 memset(¶ms, 0, sizeof(params)); 1032 ath11k_hal_srng_get_params(ab, srng, ¶ms); 1033 1034 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1035 ring_type, &htt_ring_type, 1036 &htt_ring_id); 1037 if (ret) 1038 goto err_free; 1039 1040 skb_put(skb, len); 1041 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 1042 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 1043 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 1044 if (htt_ring_type == HTT_SW_TO_HW_RING || 1045 htt_ring_type == HTT_HW_TO_SW_RING) 1046 cmd->info0 |= 1047 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 1048 DP_SW2HW_MACID(mac_id)); 1049 else 1050 cmd->info0 |= 1051 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 1052 mac_id); 1053 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 1054 htt_ring_id); 1055 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 1056 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 1057 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 1058 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 1059 1060 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 1061 rx_buf_size); 1062 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 1063 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 1064 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 1065 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 1066 cmd->rx_filter_tlv = tlv_filter->rx_filter; 1067 1068 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 1069 if (ret) 1070 goto err_free; 1071 1072 return 0; 1073 1074 err_free: 1075 dev_kfree_skb_any(skb); 1076 1077 return ret; 1078 } 1079 1080 int 1081 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 1082 struct htt_ext_stats_cfg_params *cfg_params, 1083 u64 cookie) 1084 { 1085 struct ath11k_base *ab = ar->ab; 1086 struct ath11k_dp *dp = &ab->dp; 1087 struct sk_buff *skb; 1088 struct htt_ext_stats_cfg_cmd *cmd; 1089 u32 pdev_id; 1090 int len = sizeof(*cmd); 1091 int ret; 1092 1093 skb = ath11k_htc_alloc_skb(ab, len); 1094 if (!skb) 1095 return -ENOMEM; 1096 1097 skb_put(skb, len); 1098 1099 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1100 memset(cmd, 0, sizeof(*cmd)); 1101 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1102 1103 if (ab->hw_params.single_pdev_only) 1104 pdev_id = ath11k_mac_get_target_pdev_id(ar); 1105 else 1106 pdev_id = ar->pdev->pdev_id; 1107 1108 cmd->hdr.pdev_mask = 1 << pdev_id; 1109 1110 cmd->hdr.stats_type = type; 1111 cmd->cfg_param0 = cfg_params->cfg0; 1112 cmd->cfg_param1 = cfg_params->cfg1; 1113 cmd->cfg_param2 = cfg_params->cfg2; 1114 cmd->cfg_param3 = cfg_params->cfg3; 1115 cmd->cookie_lsb = lower_32_bits(cookie); 1116 cmd->cookie_msb = upper_32_bits(cookie); 1117 1118 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1119 if (ret) { 1120 ath11k_warn(ab, "failed to send htt type stats request: %d", 1121 ret); 1122 dev_kfree_skb_any(skb); 1123 return ret; 1124 } 1125 1126 return 0; 1127 } 1128 1129 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1130 { 1131 struct ath11k_pdev_dp *dp = &ar->dp; 1132 struct ath11k_base *ab = ar->ab; 1133 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1134 int ret = 0, ring_id = 0, i; 1135 1136 if (ab->hw_params.full_monitor_mode) { 1137 ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab, 1138 dp->mac_id, !reset); 1139 if (ret < 0) { 1140 ath11k_err(ab, "failed to setup full monitor %d\n", ret); 1141 return ret; 1142 } 1143 } 1144 1145 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1146 1147 if (!reset) { 1148 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1149 tlv_filter.pkt_filter_flags0 = 1150 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1151 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1152 tlv_filter.pkt_filter_flags1 = 1153 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1154 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1155 tlv_filter.pkt_filter_flags2 = 1156 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1157 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1158 tlv_filter.pkt_filter_flags3 = 1159 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1160 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1161 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1162 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1163 } 1164 1165 if (ab->hw_params.rxdma1_enable) { 1166 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1167 HAL_RXDMA_MONITOR_BUF, 1168 DP_RXDMA_REFILL_RING_SIZE, 1169 &tlv_filter); 1170 } else if (!reset) { 1171 /* set in monitor mode only */ 1172 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1173 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1174 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1175 dp->mac_id + i, 1176 HAL_RXDMA_BUF, 1177 1024, 1178 &tlv_filter); 1179 } 1180 } 1181 1182 if (ret) 1183 return ret; 1184 1185 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1186 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1187 if (!reset) { 1188 tlv_filter.rx_filter = 1189 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1190 } else { 1191 tlv_filter = ath11k_mac_mon_status_filter_default; 1192 1193 if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1194 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1195 } 1196 1197 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1198 dp->mac_id + i, 1199 HAL_RXDMA_MONITOR_STATUS, 1200 DP_RXDMA_REFILL_RING_SIZE, 1201 &tlv_filter); 1202 } 1203 1204 if (!ar->ab->hw_params.rxdma1_enable) 1205 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1206 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1207 1208 return ret; 1209 } 1210 1211 int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id, 1212 bool config) 1213 { 1214 struct htt_rx_full_monitor_mode_cfg_cmd *cmd; 1215 struct sk_buff *skb; 1216 int ret, len = sizeof(*cmd); 1217 1218 skb = ath11k_htc_alloc_skb(ab, len); 1219 if (!skb) 1220 return -ENOMEM; 1221 1222 skb_put(skb, len); 1223 cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data; 1224 memset(cmd, 0, sizeof(*cmd)); 1225 cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE, 1226 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE); 1227 1228 cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id); 1229 1230 cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE | 1231 FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING, 1232 HTT_RX_MON_RING_SW); 1233 if (config) { 1234 cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END | 1235 HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END; 1236 } 1237 1238 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 1239 if (ret) 1240 goto err_free; 1241 1242 return 0; 1243 1244 err_free: 1245 dev_kfree_skb_any(skb); 1246 1247 return ret; 1248 } 1249