1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "hw.h" 10 #include "peer.h" 11 12 static enum hal_tcl_encap_type 13 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 17 if (tx_info->control.flags & IEEE80211_TX_CTRL_HW_80211_ENCAP) 18 return HAL_TCL_ENCAP_TYPE_ETHERNET; 19 20 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 21 } 22 23 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 24 { 25 struct ieee80211_hdr *hdr = (void *)skb->data; 26 u8 *qos_ctl; 27 28 if (!ieee80211_is_data_qos(hdr->frame_control)) 29 return; 30 31 qos_ctl = ieee80211_get_qos_ctl(hdr); 32 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 33 skb->data, (void *)qos_ctl - (void *)skb->data); 34 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 35 36 hdr = (void *)skb->data; 37 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 38 } 39 40 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 41 { 42 struct ieee80211_hdr *hdr = (void *)skb->data; 43 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 44 45 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 46 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 47 else if (!ieee80211_is_data_qos(hdr->frame_control)) 48 return HAL_DESC_REO_NON_QOS_TID; 49 else 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 } 52 53 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 54 { 55 switch (cipher) { 56 case WLAN_CIPHER_SUITE_WEP40: 57 return HAL_ENCRYPT_TYPE_WEP_40; 58 case WLAN_CIPHER_SUITE_WEP104: 59 return HAL_ENCRYPT_TYPE_WEP_104; 60 case WLAN_CIPHER_SUITE_TKIP: 61 return HAL_ENCRYPT_TYPE_TKIP_MIC; 62 case WLAN_CIPHER_SUITE_CCMP: 63 return HAL_ENCRYPT_TYPE_CCMP_128; 64 case WLAN_CIPHER_SUITE_CCMP_256: 65 return HAL_ENCRYPT_TYPE_CCMP_256; 66 case WLAN_CIPHER_SUITE_GCMP: 67 return HAL_ENCRYPT_TYPE_GCMP_128; 68 case WLAN_CIPHER_SUITE_GCMP_256: 69 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 70 default: 71 return HAL_ENCRYPT_TYPE_OPEN; 72 } 73 } 74 75 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 76 struct sk_buff *skb) 77 { 78 struct ath11k_base *ab = ar->ab; 79 struct ath11k_dp *dp = &ab->dp; 80 struct hal_tx_info ti = {0}; 81 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 82 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 83 struct hal_srng *tcl_ring; 84 struct ieee80211_hdr *hdr = (void *)skb->data; 85 struct dp_tx_ring *tx_ring; 86 void *hal_tcl_desc; 87 u8 pool_id; 88 u8 hal_ring_id; 89 int ret; 90 u8 ring_selector = 0, ring_map = 0; 91 bool tcl_ring_retry; 92 93 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 94 return -ESHUTDOWN; 95 96 if (!(info->control.flags & IEEE80211_TX_CTRL_HW_80211_ENCAP) && 97 !ieee80211_is_data(hdr->frame_control)) 98 return -ENOTSUPP; 99 100 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 101 102 /* Let the default ring selection be based on a round robin 103 * fashion where one of the 3 tcl rings are selected based on 104 * the tcl_ring_selector counter. In case that ring 105 * is full/busy, we resort to other available rings. 106 * If all rings are full, we drop the packet. 107 * //TODO Add throttling logic when all rings are full 108 */ 109 ring_selector = atomic_inc_return(&ab->tcl_ring_selector); 110 111 tcl_ring_sel: 112 tcl_ring_retry = false; 113 /* For some chip, it can only use tcl0 to tx */ 114 if (ar->ab->hw_params.tcl_0_only) 115 ti.ring_id = 0; 116 else 117 ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX; 118 119 ring_map |= BIT(ti.ring_id); 120 121 tx_ring = &dp->tx_ring[ti.ring_id]; 122 123 spin_lock_bh(&tx_ring->tx_idr_lock); 124 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 125 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 126 spin_unlock_bh(&tx_ring->tx_idr_lock); 127 128 if (ret < 0) { 129 if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) { 130 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 131 return -ENOSPC; 132 } 133 134 /* Check if the next ring is available */ 135 ring_selector++; 136 goto tcl_ring_sel; 137 } 138 139 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 140 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 141 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 142 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 143 ti.meta_data_flags = arvif->tcl_metadata; 144 145 if (info->control.hw_key) 146 ti.encrypt_type = 147 ath11k_dp_tx_get_encrypt_type(info->control.hw_key->cipher); 148 else 149 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 150 151 ti.addr_search_flags = arvif->hal_addr_search_flags; 152 ti.search_type = arvif->search_type; 153 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 154 ti.pkt_offset = 0; 155 ti.lmac_id = ar->lmac_id; 156 ti.bss_ast_hash = arvif->ast_hash; 157 ti.dscp_tid_tbl_idx = 0; 158 159 if (skb->ip_summed == CHECKSUM_PARTIAL) { 160 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 161 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 162 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 163 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 164 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 165 } 166 167 if (ieee80211_vif_is_mesh(arvif->vif)) 168 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1); 169 170 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 171 172 ti.tid = ath11k_dp_tx_get_tid(skb); 173 174 switch (ti.encap_type) { 175 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 176 ath11k_dp_tx_encap_nwifi(skb); 177 break; 178 case HAL_TCL_ENCAP_TYPE_RAW: 179 /* TODO: for CHECKSUM_PARTIAL case in raw mode, HW checksum offload 180 * is not applicable, hence manual checksum calculation using 181 * skb_checksum_help() is needed 182 */ 183 case HAL_TCL_ENCAP_TYPE_ETHERNET: 184 /* no need to encap */ 185 break; 186 case HAL_TCL_ENCAP_TYPE_802_3: 187 default: 188 /* TODO: Take care of other encap modes as well */ 189 ret = -EINVAL; 190 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 191 goto fail_remove_idr; 192 } 193 194 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 195 if (dma_mapping_error(ab->dev, ti.paddr)) { 196 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 197 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 198 ret = -ENOMEM; 199 goto fail_remove_idr; 200 } 201 202 ti.data_len = skb->len; 203 skb_cb->paddr = ti.paddr; 204 skb_cb->vif = arvif->vif; 205 skb_cb->ar = ar; 206 207 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 208 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 209 210 spin_lock_bh(&tcl_ring->lock); 211 212 ath11k_hal_srng_access_begin(ab, tcl_ring); 213 214 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 215 if (!hal_tcl_desc) { 216 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 217 * desc because the desc is directly enqueued onto hw queue. 218 */ 219 ath11k_hal_srng_access_end(ab, tcl_ring); 220 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 221 spin_unlock_bh(&tcl_ring->lock); 222 ret = -ENOMEM; 223 224 /* Checking for available tcl descritors in another ring in 225 * case of failure due to full tcl ring now, is better than 226 * checking this ring earlier for each pkt tx. 227 * Restart ring selection if some rings are not checked yet. 228 */ 229 if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) && 230 !ar->ab->hw_params.tcl_0_only) { 231 tcl_ring_retry = true; 232 ring_selector++; 233 } 234 235 goto fail_unmap_dma; 236 } 237 238 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 239 sizeof(struct hal_tlv_hdr), &ti); 240 241 ath11k_hal_srng_access_end(ab, tcl_ring); 242 243 spin_unlock_bh(&tcl_ring->lock); 244 245 atomic_inc(&ar->dp.num_tx_pending); 246 247 return 0; 248 249 fail_unmap_dma: 250 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 251 252 fail_remove_idr: 253 spin_lock_bh(&tx_ring->tx_idr_lock); 254 idr_remove(&tx_ring->txbuf_idr, 255 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 256 spin_unlock_bh(&tx_ring->tx_idr_lock); 257 258 if (tcl_ring_retry) 259 goto tcl_ring_sel; 260 261 return ret; 262 } 263 264 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 265 int msdu_id, 266 struct dp_tx_ring *tx_ring) 267 { 268 struct ath11k *ar; 269 struct sk_buff *msdu; 270 struct ath11k_skb_cb *skb_cb; 271 272 spin_lock_bh(&tx_ring->tx_idr_lock); 273 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 274 if (!msdu) { 275 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 276 msdu_id); 277 spin_unlock_bh(&tx_ring->tx_idr_lock); 278 return; 279 } 280 281 skb_cb = ATH11K_SKB_CB(msdu); 282 283 idr_remove(&tx_ring->txbuf_idr, msdu_id); 284 spin_unlock_bh(&tx_ring->tx_idr_lock); 285 286 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 287 dev_kfree_skb_any(msdu); 288 289 ar = ab->pdevs[mac_id].ar; 290 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 291 wake_up(&ar->dp.tx_empty_waitq); 292 } 293 294 static void 295 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 296 struct dp_tx_ring *tx_ring, 297 struct ath11k_dp_htt_wbm_tx_status *ts) 298 { 299 struct sk_buff *msdu; 300 struct ieee80211_tx_info *info; 301 struct ath11k_skb_cb *skb_cb; 302 struct ath11k *ar; 303 304 spin_lock_bh(&tx_ring->tx_idr_lock); 305 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 306 if (!msdu) { 307 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 308 ts->msdu_id); 309 spin_unlock_bh(&tx_ring->tx_idr_lock); 310 return; 311 } 312 313 skb_cb = ATH11K_SKB_CB(msdu); 314 info = IEEE80211_SKB_CB(msdu); 315 316 ar = skb_cb->ar; 317 318 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 319 spin_unlock_bh(&tx_ring->tx_idr_lock); 320 321 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 322 wake_up(&ar->dp.tx_empty_waitq); 323 324 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 325 326 memset(&info->status, 0, sizeof(info->status)); 327 328 if (ts->acked) { 329 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 330 info->flags |= IEEE80211_TX_STAT_ACK; 331 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 332 ts->ack_rssi; 333 info->status.is_valid_ack_signal = true; 334 } else { 335 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 336 } 337 } 338 339 ieee80211_tx_status(ar->hw, msdu); 340 } 341 342 static void 343 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 344 void *desc, u8 mac_id, 345 u32 msdu_id, struct dp_tx_ring *tx_ring) 346 { 347 struct htt_tx_wbm_completion *status_desc; 348 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 349 enum hal_wbm_htt_tx_comp_status wbm_status; 350 351 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 352 353 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 354 status_desc->info0); 355 356 switch (wbm_status) { 357 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 358 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 359 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 360 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 361 ts.msdu_id = msdu_id; 362 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 363 status_desc->info1); 364 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 365 break; 366 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 367 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 368 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 369 break; 370 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 371 /* This event is to be handled only when the driver decides to 372 * use WDS offload functionality. 373 */ 374 break; 375 default: 376 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 377 break; 378 } 379 } 380 381 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 382 struct sk_buff *msdu, 383 struct hal_tx_status *ts) 384 { 385 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 386 387 if (ts->try_cnt > 1) { 388 peer_stats->retry_pkts += ts->try_cnt - 1; 389 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 390 391 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 392 peer_stats->failed_pkts += 1; 393 peer_stats->failed_bytes += msdu->len; 394 } 395 } 396 } 397 398 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 399 struct sk_buff *msdu, 400 struct hal_tx_status *ts) 401 { 402 struct ath11k_base *ab = ar->ab; 403 struct ieee80211_tx_info *info; 404 struct ath11k_skb_cb *skb_cb; 405 406 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 407 /* Must not happen */ 408 return; 409 } 410 411 skb_cb = ATH11K_SKB_CB(msdu); 412 413 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 414 415 rcu_read_lock(); 416 417 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 418 dev_kfree_skb_any(msdu); 419 goto exit; 420 } 421 422 if (!skb_cb->vif) { 423 dev_kfree_skb_any(msdu); 424 goto exit; 425 } 426 427 info = IEEE80211_SKB_CB(msdu); 428 memset(&info->status, 0, sizeof(info->status)); 429 430 /* skip tx rate update from ieee80211_status*/ 431 info->status.rates[0].idx = -1; 432 433 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 434 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 435 info->flags |= IEEE80211_TX_STAT_ACK; 436 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 437 ts->ack_rssi; 438 info->status.is_valid_ack_signal = true; 439 } 440 441 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 442 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 443 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 444 445 if (ath11k_debug_is_extd_tx_stats_enabled(ar)) { 446 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 447 if (ar->last_ppdu_id == 0) { 448 ar->last_ppdu_id = ts->ppdu_id; 449 } else if (ar->last_ppdu_id == ts->ppdu_id || 450 ar->cached_ppdu_id == ar->last_ppdu_id) { 451 ar->cached_ppdu_id = ar->last_ppdu_id; 452 ar->cached_stats.is_ampdu = true; 453 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts); 454 memset(&ar->cached_stats, 0, 455 sizeof(struct ath11k_per_peer_tx_stats)); 456 } else { 457 ar->cached_stats.is_ampdu = false; 458 ath11k_update_per_peer_stats_from_txcompl(ar, msdu, ts); 459 memset(&ar->cached_stats, 0, 460 sizeof(struct ath11k_per_peer_tx_stats)); 461 } 462 ar->last_ppdu_id = ts->ppdu_id; 463 } 464 465 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 466 } 467 468 /* NOTE: Tx rate status reporting. Tx completion status does not have 469 * necessary information (for example nss) to build the tx rate. 470 * Might end up reporting it out-of-band from HTT stats. 471 */ 472 473 ieee80211_tx_status(ar->hw, msdu); 474 475 exit: 476 rcu_read_unlock(); 477 } 478 479 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 480 struct hal_wbm_release_ring *desc, 481 struct hal_tx_status *ts) 482 { 483 ts->buf_rel_source = 484 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 485 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 486 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 487 return; 488 489 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 490 return; 491 492 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 493 desc->info0); 494 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 495 desc->info1); 496 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 497 desc->info1); 498 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 499 desc->info2); 500 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 501 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 502 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 503 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 504 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 505 ts->rate_stats = desc->rate_stats.info0; 506 else 507 ts->rate_stats = 0; 508 } 509 510 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 511 { 512 struct ath11k *ar; 513 struct ath11k_dp *dp = &ab->dp; 514 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 515 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 516 struct sk_buff *msdu; 517 struct hal_tx_status ts = { 0 }; 518 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 519 u32 *desc; 520 u32 msdu_id; 521 u8 mac_id; 522 523 ath11k_hal_srng_access_begin(ab, status_ring); 524 525 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 526 tx_ring->tx_status_tail) && 527 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 528 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 529 desc, sizeof(struct hal_wbm_release_ring)); 530 tx_ring->tx_status_head = 531 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 532 } 533 534 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 535 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 536 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 537 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 538 } 539 540 ath11k_hal_srng_access_end(ab, status_ring); 541 542 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 543 struct hal_wbm_release_ring *tx_status; 544 u32 desc_id; 545 546 tx_ring->tx_status_tail = 547 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 548 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 549 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 550 551 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 552 tx_status->buf_addr_info.info1); 553 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 554 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 555 556 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 557 ath11k_dp_tx_process_htt_tx_complete(ab, 558 (void *)tx_status, 559 mac_id, msdu_id, 560 tx_ring); 561 continue; 562 } 563 564 spin_lock_bh(&tx_ring->tx_idr_lock); 565 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 566 if (!msdu) { 567 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 568 msdu_id); 569 spin_unlock_bh(&tx_ring->tx_idr_lock); 570 continue; 571 } 572 idr_remove(&tx_ring->txbuf_idr, msdu_id); 573 spin_unlock_bh(&tx_ring->tx_idr_lock); 574 575 ar = ab->pdevs[mac_id].ar; 576 577 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 578 wake_up(&ar->dp.tx_empty_waitq); 579 580 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 581 } 582 } 583 584 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 585 enum hal_reo_cmd_type type, 586 struct ath11k_hal_reo_cmd *cmd, 587 void (*cb)(struct ath11k_dp *, void *, 588 enum hal_reo_cmd_status)) 589 { 590 struct ath11k_dp *dp = &ab->dp; 591 struct dp_reo_cmd *dp_cmd; 592 struct hal_srng *cmd_ring; 593 int cmd_num; 594 595 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 596 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 597 598 /* cmd_num should start from 1, during failure return the error code */ 599 if (cmd_num < 0) 600 return cmd_num; 601 602 /* reo cmd ring descriptors has cmd_num starting from 1 */ 603 if (cmd_num == 0) 604 return -EINVAL; 605 606 if (!cb) 607 return 0; 608 609 /* Can this be optimized so that we keep the pending command list only 610 * for tid delete command to free up the resoruce on the command status 611 * indication? 612 */ 613 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 614 615 if (!dp_cmd) 616 return -ENOMEM; 617 618 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 619 dp_cmd->cmd_num = cmd_num; 620 dp_cmd->handler = cb; 621 622 spin_lock_bh(&dp->reo_cmd_lock); 623 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 624 spin_unlock_bh(&dp->reo_cmd_lock); 625 626 return 0; 627 } 628 629 static int 630 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 631 int mac_id, u32 ring_id, 632 enum hal_ring_type ring_type, 633 enum htt_srng_ring_type *htt_ring_type, 634 enum htt_srng_ring_id *htt_ring_id) 635 { 636 int lmac_ring_id_offset = 0; 637 int ret = 0; 638 639 switch (ring_type) { 640 case HAL_RXDMA_BUF: 641 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 642 643 /* for QCA6390, host fills rx buffer to fw and fw fills to 644 * rxbuf ring for each rxdma 645 */ 646 if (!ab->hw_params.rx_mac_buf_ring) { 647 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 648 lmac_ring_id_offset) || 649 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 650 lmac_ring_id_offset))) { 651 ret = -EINVAL; 652 } 653 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 654 *htt_ring_type = HTT_SW_TO_HW_RING; 655 } else { 656 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 657 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 658 *htt_ring_type = HTT_SW_TO_SW_RING; 659 } else { 660 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 661 *htt_ring_type = HTT_SW_TO_HW_RING; 662 } 663 } 664 break; 665 case HAL_RXDMA_DST: 666 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 667 *htt_ring_type = HTT_HW_TO_SW_RING; 668 break; 669 case HAL_RXDMA_MONITOR_BUF: 670 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 671 *htt_ring_type = HTT_SW_TO_HW_RING; 672 break; 673 case HAL_RXDMA_MONITOR_STATUS: 674 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 675 *htt_ring_type = HTT_SW_TO_HW_RING; 676 break; 677 case HAL_RXDMA_MONITOR_DST: 678 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 679 *htt_ring_type = HTT_HW_TO_SW_RING; 680 break; 681 case HAL_RXDMA_MONITOR_DESC: 682 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 683 *htt_ring_type = HTT_SW_TO_HW_RING; 684 break; 685 default: 686 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 687 ret = -EINVAL; 688 } 689 return ret; 690 } 691 692 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 693 int mac_id, enum hal_ring_type ring_type) 694 { 695 struct htt_srng_setup_cmd *cmd; 696 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 697 struct hal_srng_params params; 698 struct sk_buff *skb; 699 u32 ring_entry_sz; 700 int len = sizeof(*cmd); 701 dma_addr_t hp_addr, tp_addr; 702 enum htt_srng_ring_type htt_ring_type; 703 enum htt_srng_ring_id htt_ring_id; 704 int ret; 705 706 skb = ath11k_htc_alloc_skb(ab, len); 707 if (!skb) 708 return -ENOMEM; 709 710 memset(¶ms, 0, sizeof(params)); 711 ath11k_hal_srng_get_params(ab, srng, ¶ms); 712 713 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 714 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 715 716 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 717 ring_type, &htt_ring_type, 718 &htt_ring_id); 719 if (ret) 720 goto err_free; 721 722 skb_put(skb, len); 723 cmd = (struct htt_srng_setup_cmd *)skb->data; 724 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 725 HTT_H2T_MSG_TYPE_SRING_SETUP); 726 if (htt_ring_type == HTT_SW_TO_HW_RING || 727 htt_ring_type == HTT_HW_TO_SW_RING) 728 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 729 DP_SW2HW_MACID(mac_id)); 730 else 731 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 732 mac_id); 733 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 734 htt_ring_type); 735 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 736 737 cmd->ring_base_addr_lo = params.ring_base_paddr & 738 HAL_ADDR_LSB_REG_MASK; 739 740 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 741 HAL_ADDR_MSB_REG_SHIFT; 742 743 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 744 if (ret < 0) 745 goto err_free; 746 747 ring_entry_sz = ret; 748 749 ring_entry_sz >>= 2; 750 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 751 ring_entry_sz); 752 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 753 params.num_entries * ring_entry_sz); 754 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 755 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 756 cmd->info1 |= FIELD_PREP( 757 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 758 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 759 cmd->info1 |= FIELD_PREP( 760 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 761 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 762 if (htt_ring_type == HTT_SW_TO_HW_RING) 763 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 764 765 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 766 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 767 HAL_ADDR_MSB_REG_SHIFT; 768 769 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 770 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 771 HAL_ADDR_MSB_REG_SHIFT; 772 773 cmd->ring_msi_addr_lo = 0; 774 cmd->ring_msi_addr_hi = 0; 775 cmd->msi_data = 0; 776 777 cmd->intr_info = FIELD_PREP( 778 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 779 params.intr_batch_cntr_thres_entries * ring_entry_sz); 780 cmd->intr_info |= FIELD_PREP( 781 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 782 params.intr_timer_thres_us >> 3); 783 784 cmd->info2 = 0; 785 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 786 cmd->info2 = FIELD_PREP( 787 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 788 params.low_threshold); 789 } 790 791 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 792 if (ret) 793 goto err_free; 794 795 return 0; 796 797 err_free: 798 dev_kfree_skb_any(skb); 799 800 return ret; 801 } 802 803 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 804 805 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 806 { 807 struct ath11k_dp *dp = &ab->dp; 808 struct sk_buff *skb; 809 struct htt_ver_req_cmd *cmd; 810 int len = sizeof(*cmd); 811 int ret; 812 813 init_completion(&dp->htt_tgt_version_received); 814 815 skb = ath11k_htc_alloc_skb(ab, len); 816 if (!skb) 817 return -ENOMEM; 818 819 skb_put(skb, len); 820 cmd = (struct htt_ver_req_cmd *)skb->data; 821 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 822 HTT_H2T_MSG_TYPE_VERSION_REQ); 823 824 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 825 if (ret) { 826 dev_kfree_skb_any(skb); 827 return ret; 828 } 829 830 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 831 HTT_TARGET_VERSION_TIMEOUT_HZ); 832 if (ret == 0) { 833 ath11k_warn(ab, "htt target version request timed out\n"); 834 return -ETIMEDOUT; 835 } 836 837 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 838 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 839 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 840 return -ENOTSUPP; 841 } 842 843 return 0; 844 } 845 846 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 847 { 848 struct ath11k_base *ab = ar->ab; 849 struct ath11k_dp *dp = &ab->dp; 850 struct sk_buff *skb; 851 struct htt_ppdu_stats_cfg_cmd *cmd; 852 int len = sizeof(*cmd); 853 u8 pdev_mask; 854 int ret; 855 856 skb = ath11k_htc_alloc_skb(ab, len); 857 if (!skb) 858 return -ENOMEM; 859 860 skb_put(skb, len); 861 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 862 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 863 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 864 865 pdev_mask = 1 << (ar->pdev_idx); 866 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 867 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 868 869 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 870 if (ret) { 871 dev_kfree_skb_any(skb); 872 return ret; 873 } 874 875 return 0; 876 } 877 878 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 879 int mac_id, enum hal_ring_type ring_type, 880 int rx_buf_size, 881 struct htt_rx_ring_tlv_filter *tlv_filter) 882 { 883 struct htt_rx_ring_selection_cfg_cmd *cmd; 884 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 885 struct hal_srng_params params; 886 struct sk_buff *skb; 887 int len = sizeof(*cmd); 888 enum htt_srng_ring_type htt_ring_type; 889 enum htt_srng_ring_id htt_ring_id; 890 int ret; 891 892 skb = ath11k_htc_alloc_skb(ab, len); 893 if (!skb) 894 return -ENOMEM; 895 896 memset(¶ms, 0, sizeof(params)); 897 ath11k_hal_srng_get_params(ab, srng, ¶ms); 898 899 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 900 ring_type, &htt_ring_type, 901 &htt_ring_id); 902 if (ret) 903 goto err_free; 904 905 skb_put(skb, len); 906 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 907 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 908 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 909 if (htt_ring_type == HTT_SW_TO_HW_RING || 910 htt_ring_type == HTT_HW_TO_SW_RING) 911 cmd->info0 |= 912 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 913 DP_SW2HW_MACID(mac_id)); 914 else 915 cmd->info0 |= 916 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 917 mac_id); 918 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 919 htt_ring_id); 920 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 921 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 922 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 923 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 924 925 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 926 rx_buf_size); 927 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 928 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 929 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 930 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 931 cmd->rx_filter_tlv = tlv_filter->rx_filter; 932 933 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 934 if (ret) 935 goto err_free; 936 937 return 0; 938 939 err_free: 940 dev_kfree_skb_any(skb); 941 942 return ret; 943 } 944 945 int 946 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 947 struct htt_ext_stats_cfg_params *cfg_params, 948 u64 cookie) 949 { 950 struct ath11k_base *ab = ar->ab; 951 struct ath11k_dp *dp = &ab->dp; 952 struct sk_buff *skb; 953 struct htt_ext_stats_cfg_cmd *cmd; 954 int len = sizeof(*cmd); 955 int ret; 956 957 skb = ath11k_htc_alloc_skb(ab, len); 958 if (!skb) 959 return -ENOMEM; 960 961 skb_put(skb, len); 962 963 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 964 memset(cmd, 0, sizeof(*cmd)); 965 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 966 967 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 968 969 cmd->hdr.stats_type = type; 970 cmd->cfg_param0 = cfg_params->cfg0; 971 cmd->cfg_param1 = cfg_params->cfg1; 972 cmd->cfg_param2 = cfg_params->cfg2; 973 cmd->cfg_param3 = cfg_params->cfg3; 974 cmd->cookie_lsb = lower_32_bits(cookie); 975 cmd->cookie_msb = upper_32_bits(cookie); 976 977 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 978 if (ret) { 979 ath11k_warn(ab, "failed to send htt type stats request: %d", 980 ret); 981 dev_kfree_skb_any(skb); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 989 { 990 struct ath11k_pdev_dp *dp = &ar->dp; 991 struct ath11k_base *ab = ar->ab; 992 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 993 int ret = 0, ring_id = 0, i; 994 995 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 996 997 if (!reset) { 998 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 999 tlv_filter.pkt_filter_flags0 = 1000 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1001 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1002 tlv_filter.pkt_filter_flags1 = 1003 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1004 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1005 tlv_filter.pkt_filter_flags2 = 1006 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1007 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1008 tlv_filter.pkt_filter_flags3 = 1009 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1010 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1011 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1012 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1013 } 1014 1015 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1016 HAL_RXDMA_MONITOR_BUF, 1017 DP_RXDMA_REFILL_RING_SIZE, 1018 &tlv_filter); 1019 if (ret) 1020 return ret; 1021 1022 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1023 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1024 if (!reset) 1025 tlv_filter.rx_filter = 1026 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1027 else 1028 tlv_filter = ath11k_mac_mon_status_filter_default; 1029 1030 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1031 dp->mac_id + i, 1032 HAL_RXDMA_MONITOR_STATUS, 1033 DP_RXDMA_REFILL_RING_SIZE, 1034 &tlv_filter); 1035 } 1036 1037 return ret; 1038 } 1039