1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "core.h" 7 #include "dp_tx.h" 8 #include "debug.h" 9 #include "debugfs_sta.h" 10 #include "hw.h" 11 #include "peer.h" 12 13 static enum hal_tcl_encap_type 14 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15 { 16 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17 struct ath11k_base *ab = arvif->ar->ab; 18 19 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20 return HAL_TCL_ENCAP_TYPE_RAW; 21 22 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23 return HAL_TCL_ENCAP_TYPE_ETHERNET; 24 25 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26 } 27 28 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29 { 30 struct ieee80211_hdr *hdr = (void *)skb->data; 31 u8 *qos_ctl; 32 33 if (!ieee80211_is_data_qos(hdr->frame_control)) 34 return; 35 36 qos_ctl = ieee80211_get_qos_ctl(hdr); 37 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38 skb->data, (void *)qos_ctl - (void *)skb->data); 39 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40 41 hdr = (void *)skb->data; 42 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43 } 44 45 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46 { 47 struct ieee80211_hdr *hdr = (void *)skb->data; 48 struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49 50 if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52 else if (!ieee80211_is_data_qos(hdr->frame_control)) 53 return HAL_DESC_REO_NON_QOS_TID; 54 else 55 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56 } 57 58 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59 { 60 switch (cipher) { 61 case WLAN_CIPHER_SUITE_WEP40: 62 return HAL_ENCRYPT_TYPE_WEP_40; 63 case WLAN_CIPHER_SUITE_WEP104: 64 return HAL_ENCRYPT_TYPE_WEP_104; 65 case WLAN_CIPHER_SUITE_TKIP: 66 return HAL_ENCRYPT_TYPE_TKIP_MIC; 67 case WLAN_CIPHER_SUITE_CCMP: 68 return HAL_ENCRYPT_TYPE_CCMP_128; 69 case WLAN_CIPHER_SUITE_CCMP_256: 70 return HAL_ENCRYPT_TYPE_CCMP_256; 71 case WLAN_CIPHER_SUITE_GCMP: 72 return HAL_ENCRYPT_TYPE_GCMP_128; 73 case WLAN_CIPHER_SUITE_GCMP_256: 74 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75 default: 76 return HAL_ENCRYPT_TYPE_OPEN; 77 } 78 } 79 80 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81 struct sk_buff *skb) 82 { 83 struct ath11k_base *ab = ar->ab; 84 struct ath11k_dp *dp = &ab->dp; 85 struct hal_tx_info ti = {0}; 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 88 struct hal_srng *tcl_ring; 89 struct ieee80211_hdr *hdr = (void *)skb->data; 90 struct dp_tx_ring *tx_ring; 91 void *hal_tcl_desc; 92 u8 pool_id; 93 u8 hal_ring_id; 94 int ret; 95 u8 ring_selector = 0, ring_map = 0; 96 bool tcl_ring_retry; 97 98 if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 99 return -ESHUTDOWN; 100 101 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 102 !ieee80211_is_data(hdr->frame_control)) 103 return -ENOTSUPP; 104 105 pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 106 107 /* Let the default ring selection be based on current processor 108 * number, where one of the 3 tcl rings are selected based on 109 * the smp_processor_id(). In case that ring 110 * is full/busy, we resort to other available rings. 111 * If all rings are full, we drop the packet. 112 * //TODO Add throttling logic when all rings are full 113 */ 114 ring_selector = smp_processor_id(); 115 116 tcl_ring_sel: 117 tcl_ring_retry = false; 118 /* For some chip, it can only use tcl0 to tx */ 119 if (ar->ab->hw_params.tcl_0_only) 120 ti.ring_id = 0; 121 else 122 ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX; 123 124 ring_map |= BIT(ti.ring_id); 125 126 tx_ring = &dp->tx_ring[ti.ring_id]; 127 128 spin_lock_bh(&tx_ring->tx_idr_lock); 129 ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 130 DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 131 spin_unlock_bh(&tx_ring->tx_idr_lock); 132 133 if (ret < 0) { 134 if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) { 135 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 136 return -ENOSPC; 137 } 138 139 /* Check if the next ring is available */ 140 ring_selector++; 141 goto tcl_ring_sel; 142 } 143 144 ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 145 FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 146 FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 147 ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 148 ti.meta_data_flags = arvif->tcl_metadata; 149 150 if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) { 151 if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 152 ti.encrypt_type = 153 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 154 155 if (ieee80211_has_protected(hdr->frame_control)) 156 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 157 } else { 158 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 159 } 160 } 161 162 ti.addr_search_flags = arvif->hal_addr_search_flags; 163 ti.search_type = arvif->search_type; 164 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 165 ti.pkt_offset = 0; 166 ti.lmac_id = ar->lmac_id; 167 ti.bss_ast_hash = arvif->ast_hash; 168 ti.dscp_tid_tbl_idx = 0; 169 170 if (skb->ip_summed == CHECKSUM_PARTIAL && 171 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 172 ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 173 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 174 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 175 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 176 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 177 } 178 179 if (ieee80211_vif_is_mesh(arvif->vif)) 180 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1); 181 182 ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 183 184 ti.tid = ath11k_dp_tx_get_tid(skb); 185 186 switch (ti.encap_type) { 187 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 188 ath11k_dp_tx_encap_nwifi(skb); 189 break; 190 case HAL_TCL_ENCAP_TYPE_RAW: 191 if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 192 ret = -EINVAL; 193 goto fail_remove_idr; 194 } 195 break; 196 case HAL_TCL_ENCAP_TYPE_ETHERNET: 197 /* no need to encap */ 198 break; 199 case HAL_TCL_ENCAP_TYPE_802_3: 200 default: 201 /* TODO: Take care of other encap modes as well */ 202 ret = -EINVAL; 203 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 204 goto fail_remove_idr; 205 } 206 207 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 208 if (dma_mapping_error(ab->dev, ti.paddr)) { 209 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 210 ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 211 ret = -ENOMEM; 212 goto fail_remove_idr; 213 } 214 215 ti.data_len = skb->len; 216 skb_cb->paddr = ti.paddr; 217 skb_cb->vif = arvif->vif; 218 skb_cb->ar = ar; 219 220 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 221 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 222 223 spin_lock_bh(&tcl_ring->lock); 224 225 ath11k_hal_srng_access_begin(ab, tcl_ring); 226 227 hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 228 if (!hal_tcl_desc) { 229 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 230 * desc because the desc is directly enqueued onto hw queue. 231 */ 232 ath11k_hal_srng_access_end(ab, tcl_ring); 233 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 234 spin_unlock_bh(&tcl_ring->lock); 235 ret = -ENOMEM; 236 237 /* Checking for available tcl descritors in another ring in 238 * case of failure due to full tcl ring now, is better than 239 * checking this ring earlier for each pkt tx. 240 * Restart ring selection if some rings are not checked yet. 241 */ 242 if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) && 243 !ar->ab->hw_params.tcl_0_only) { 244 tcl_ring_retry = true; 245 ring_selector++; 246 } 247 248 goto fail_unmap_dma; 249 } 250 251 ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 252 sizeof(struct hal_tlv_hdr), &ti); 253 254 ath11k_hal_srng_access_end(ab, tcl_ring); 255 256 ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 257 258 spin_unlock_bh(&tcl_ring->lock); 259 260 ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 261 skb->data, skb->len); 262 263 atomic_inc(&ar->dp.num_tx_pending); 264 265 return 0; 266 267 fail_unmap_dma: 268 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 269 270 fail_remove_idr: 271 spin_lock_bh(&tx_ring->tx_idr_lock); 272 idr_remove(&tx_ring->txbuf_idr, 273 FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 274 spin_unlock_bh(&tx_ring->tx_idr_lock); 275 276 if (tcl_ring_retry) 277 goto tcl_ring_sel; 278 279 return ret; 280 } 281 282 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 283 int msdu_id, 284 struct dp_tx_ring *tx_ring) 285 { 286 struct ath11k *ar; 287 struct sk_buff *msdu; 288 struct ath11k_skb_cb *skb_cb; 289 290 spin_lock_bh(&tx_ring->tx_idr_lock); 291 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 292 if (!msdu) { 293 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 294 msdu_id); 295 spin_unlock_bh(&tx_ring->tx_idr_lock); 296 return; 297 } 298 299 skb_cb = ATH11K_SKB_CB(msdu); 300 301 idr_remove(&tx_ring->txbuf_idr, msdu_id); 302 spin_unlock_bh(&tx_ring->tx_idr_lock); 303 304 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 305 dev_kfree_skb_any(msdu); 306 307 ar = ab->pdevs[mac_id].ar; 308 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 309 wake_up(&ar->dp.tx_empty_waitq); 310 } 311 312 static void 313 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 314 struct dp_tx_ring *tx_ring, 315 struct ath11k_dp_htt_wbm_tx_status *ts) 316 { 317 struct sk_buff *msdu; 318 struct ieee80211_tx_info *info; 319 struct ath11k_skb_cb *skb_cb; 320 struct ath11k *ar; 321 322 spin_lock_bh(&tx_ring->tx_idr_lock); 323 msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 324 if (!msdu) { 325 ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 326 ts->msdu_id); 327 spin_unlock_bh(&tx_ring->tx_idr_lock); 328 return; 329 } 330 331 skb_cb = ATH11K_SKB_CB(msdu); 332 info = IEEE80211_SKB_CB(msdu); 333 334 ar = skb_cb->ar; 335 336 idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 337 spin_unlock_bh(&tx_ring->tx_idr_lock); 338 339 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 340 wake_up(&ar->dp.tx_empty_waitq); 341 342 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 343 344 memset(&info->status, 0, sizeof(info->status)); 345 346 if (ts->acked) { 347 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 348 info->flags |= IEEE80211_TX_STAT_ACK; 349 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 350 ts->ack_rssi; 351 info->status.is_valid_ack_signal = true; 352 } else { 353 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 354 } 355 } 356 357 ieee80211_tx_status(ar->hw, msdu); 358 } 359 360 static void 361 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 362 void *desc, u8 mac_id, 363 u32 msdu_id, struct dp_tx_ring *tx_ring) 364 { 365 struct htt_tx_wbm_completion *status_desc; 366 struct ath11k_dp_htt_wbm_tx_status ts = {0}; 367 enum hal_wbm_htt_tx_comp_status wbm_status; 368 369 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 370 371 wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 372 status_desc->info0); 373 switch (wbm_status) { 374 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 375 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 376 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 377 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 378 ts.msdu_id = msdu_id; 379 ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 380 status_desc->info1); 381 ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 382 break; 383 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 384 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 385 ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 386 break; 387 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 388 /* This event is to be handled only when the driver decides to 389 * use WDS offload functionality. 390 */ 391 break; 392 default: 393 ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 394 break; 395 } 396 } 397 398 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 399 struct sk_buff *msdu, 400 struct hal_tx_status *ts) 401 { 402 struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 403 404 if (ts->try_cnt > 1) { 405 peer_stats->retry_pkts += ts->try_cnt - 1; 406 peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 407 408 if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 409 peer_stats->failed_pkts += 1; 410 peer_stats->failed_bytes += msdu->len; 411 } 412 } 413 } 414 415 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 416 struct sk_buff *msdu, 417 struct hal_tx_status *ts) 418 { 419 struct ath11k_base *ab = ar->ab; 420 struct ieee80211_tx_info *info; 421 struct ath11k_skb_cb *skb_cb; 422 423 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 424 /* Must not happen */ 425 return; 426 } 427 428 skb_cb = ATH11K_SKB_CB(msdu); 429 430 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 431 432 rcu_read_lock(); 433 434 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 435 dev_kfree_skb_any(msdu); 436 goto exit; 437 } 438 439 if (!skb_cb->vif) { 440 dev_kfree_skb_any(msdu); 441 goto exit; 442 } 443 444 info = IEEE80211_SKB_CB(msdu); 445 memset(&info->status, 0, sizeof(info->status)); 446 447 /* skip tx rate update from ieee80211_status*/ 448 info->status.rates[0].idx = -1; 449 450 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 451 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 452 info->flags |= IEEE80211_TX_STAT_ACK; 453 info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 454 ts->ack_rssi; 455 info->status.is_valid_ack_signal = true; 456 } 457 458 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 459 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 460 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 461 462 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) { 463 if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 464 if (ar->last_ppdu_id == 0) { 465 ar->last_ppdu_id = ts->ppdu_id; 466 } else if (ar->last_ppdu_id == ts->ppdu_id || 467 ar->cached_ppdu_id == ar->last_ppdu_id) { 468 ar->cached_ppdu_id = ar->last_ppdu_id; 469 ar->cached_stats.is_ampdu = true; 470 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 471 memset(&ar->cached_stats, 0, 472 sizeof(struct ath11k_per_peer_tx_stats)); 473 } else { 474 ar->cached_stats.is_ampdu = false; 475 ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 476 memset(&ar->cached_stats, 0, 477 sizeof(struct ath11k_per_peer_tx_stats)); 478 } 479 ar->last_ppdu_id = ts->ppdu_id; 480 } 481 482 ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 483 } 484 485 /* NOTE: Tx rate status reporting. Tx completion status does not have 486 * necessary information (for example nss) to build the tx rate. 487 * Might end up reporting it out-of-band from HTT stats. 488 */ 489 490 ieee80211_tx_status(ar->hw, msdu); 491 492 exit: 493 rcu_read_unlock(); 494 } 495 496 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 497 struct hal_wbm_release_ring *desc, 498 struct hal_tx_status *ts) 499 { 500 ts->buf_rel_source = 501 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 502 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 503 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 504 return; 505 506 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 507 return; 508 509 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 510 desc->info0); 511 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 512 desc->info1); 513 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 514 desc->info1); 515 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 516 desc->info2); 517 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 518 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 519 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 520 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 521 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 522 ts->rate_stats = desc->rate_stats.info0; 523 else 524 ts->rate_stats = 0; 525 } 526 527 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 528 { 529 struct ath11k *ar; 530 struct ath11k_dp *dp = &ab->dp; 531 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 532 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 533 struct sk_buff *msdu; 534 struct hal_tx_status ts = { 0 }; 535 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 536 u32 *desc; 537 u32 msdu_id; 538 u8 mac_id; 539 540 spin_lock_bh(&status_ring->lock); 541 542 ath11k_hal_srng_access_begin(ab, status_ring); 543 544 while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 545 tx_ring->tx_status_tail) && 546 (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 547 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 548 desc, sizeof(struct hal_wbm_release_ring)); 549 tx_ring->tx_status_head = 550 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 551 } 552 553 if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 554 (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 555 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 556 ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 557 } 558 559 ath11k_hal_srng_access_end(ab, status_ring); 560 561 spin_unlock_bh(&status_ring->lock); 562 563 while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 564 struct hal_wbm_release_ring *tx_status; 565 u32 desc_id; 566 567 tx_ring->tx_status_tail = 568 ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 569 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 570 ath11k_dp_tx_status_parse(ab, tx_status, &ts); 571 572 desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 573 tx_status->buf_addr_info.info1); 574 mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 575 msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 576 577 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 578 ath11k_dp_tx_process_htt_tx_complete(ab, 579 (void *)tx_status, 580 mac_id, msdu_id, 581 tx_ring); 582 continue; 583 } 584 585 spin_lock_bh(&tx_ring->tx_idr_lock); 586 msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 587 if (!msdu) { 588 ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 589 msdu_id); 590 spin_unlock_bh(&tx_ring->tx_idr_lock); 591 continue; 592 } 593 idr_remove(&tx_ring->txbuf_idr, msdu_id); 594 spin_unlock_bh(&tx_ring->tx_idr_lock); 595 596 ar = ab->pdevs[mac_id].ar; 597 598 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 599 wake_up(&ar->dp.tx_empty_waitq); 600 601 ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 602 } 603 } 604 605 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 606 enum hal_reo_cmd_type type, 607 struct ath11k_hal_reo_cmd *cmd, 608 void (*cb)(struct ath11k_dp *, void *, 609 enum hal_reo_cmd_status)) 610 { 611 struct ath11k_dp *dp = &ab->dp; 612 struct dp_reo_cmd *dp_cmd; 613 struct hal_srng *cmd_ring; 614 int cmd_num; 615 616 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 617 cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 618 619 /* cmd_num should start from 1, during failure return the error code */ 620 if (cmd_num < 0) 621 return cmd_num; 622 623 /* reo cmd ring descriptors has cmd_num starting from 1 */ 624 if (cmd_num == 0) 625 return -EINVAL; 626 627 if (!cb) 628 return 0; 629 630 /* Can this be optimized so that we keep the pending command list only 631 * for tid delete command to free up the resoruce on the command status 632 * indication? 633 */ 634 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 635 636 if (!dp_cmd) 637 return -ENOMEM; 638 639 memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 640 dp_cmd->cmd_num = cmd_num; 641 dp_cmd->handler = cb; 642 643 spin_lock_bh(&dp->reo_cmd_lock); 644 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 645 spin_unlock_bh(&dp->reo_cmd_lock); 646 647 return 0; 648 } 649 650 static int 651 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 652 int mac_id, u32 ring_id, 653 enum hal_ring_type ring_type, 654 enum htt_srng_ring_type *htt_ring_type, 655 enum htt_srng_ring_id *htt_ring_id) 656 { 657 int lmac_ring_id_offset = 0; 658 int ret = 0; 659 660 switch (ring_type) { 661 case HAL_RXDMA_BUF: 662 lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 663 664 /* for QCA6390, host fills rx buffer to fw and fw fills to 665 * rxbuf ring for each rxdma 666 */ 667 if (!ab->hw_params.rx_mac_buf_ring) { 668 if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 669 lmac_ring_id_offset) || 670 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 671 lmac_ring_id_offset))) { 672 ret = -EINVAL; 673 } 674 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 675 *htt_ring_type = HTT_SW_TO_HW_RING; 676 } else { 677 if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 678 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 679 *htt_ring_type = HTT_SW_TO_SW_RING; 680 } else { 681 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 682 *htt_ring_type = HTT_SW_TO_HW_RING; 683 } 684 } 685 break; 686 case HAL_RXDMA_DST: 687 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 688 *htt_ring_type = HTT_HW_TO_SW_RING; 689 break; 690 case HAL_RXDMA_MONITOR_BUF: 691 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 692 *htt_ring_type = HTT_SW_TO_HW_RING; 693 break; 694 case HAL_RXDMA_MONITOR_STATUS: 695 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 696 *htt_ring_type = HTT_SW_TO_HW_RING; 697 break; 698 case HAL_RXDMA_MONITOR_DST: 699 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 700 *htt_ring_type = HTT_HW_TO_SW_RING; 701 break; 702 case HAL_RXDMA_MONITOR_DESC: 703 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 704 *htt_ring_type = HTT_SW_TO_HW_RING; 705 break; 706 default: 707 ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 708 ret = -EINVAL; 709 } 710 return ret; 711 } 712 713 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 714 int mac_id, enum hal_ring_type ring_type) 715 { 716 struct htt_srng_setup_cmd *cmd; 717 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 718 struct hal_srng_params params; 719 struct sk_buff *skb; 720 u32 ring_entry_sz; 721 int len = sizeof(*cmd); 722 dma_addr_t hp_addr, tp_addr; 723 enum htt_srng_ring_type htt_ring_type; 724 enum htt_srng_ring_id htt_ring_id; 725 int ret; 726 727 skb = ath11k_htc_alloc_skb(ab, len); 728 if (!skb) 729 return -ENOMEM; 730 731 memset(¶ms, 0, sizeof(params)); 732 ath11k_hal_srng_get_params(ab, srng, ¶ms); 733 734 hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 735 tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 736 737 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 738 ring_type, &htt_ring_type, 739 &htt_ring_id); 740 if (ret) 741 goto err_free; 742 743 skb_put(skb, len); 744 cmd = (struct htt_srng_setup_cmd *)skb->data; 745 cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 746 HTT_H2T_MSG_TYPE_SRING_SETUP); 747 if (htt_ring_type == HTT_SW_TO_HW_RING || 748 htt_ring_type == HTT_HW_TO_SW_RING) 749 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 750 DP_SW2HW_MACID(mac_id)); 751 else 752 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 753 mac_id); 754 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 755 htt_ring_type); 756 cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 757 758 cmd->ring_base_addr_lo = params.ring_base_paddr & 759 HAL_ADDR_LSB_REG_MASK; 760 761 cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 762 HAL_ADDR_MSB_REG_SHIFT; 763 764 ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 765 if (ret < 0) 766 goto err_free; 767 768 ring_entry_sz = ret; 769 770 ring_entry_sz >>= 2; 771 cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 772 ring_entry_sz); 773 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 774 params.num_entries * ring_entry_sz); 775 cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 776 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 777 cmd->info1 |= FIELD_PREP( 778 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 779 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 780 cmd->info1 |= FIELD_PREP( 781 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 782 !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 783 if (htt_ring_type == HTT_SW_TO_HW_RING) 784 cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 785 786 cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 787 cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 788 HAL_ADDR_MSB_REG_SHIFT; 789 790 cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 791 cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 792 HAL_ADDR_MSB_REG_SHIFT; 793 794 cmd->ring_msi_addr_lo = params.msi_addr & 0xffffffff; 795 cmd->ring_msi_addr_hi = ((uint64_t)(params.msi_addr) >> 32) & 0xffffffff; 796 cmd->msi_data = params.msi_data; 797 798 cmd->intr_info = FIELD_PREP( 799 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 800 params.intr_batch_cntr_thres_entries * ring_entry_sz); 801 cmd->intr_info |= FIELD_PREP( 802 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 803 params.intr_timer_thres_us >> 3); 804 805 cmd->info2 = 0; 806 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 807 cmd->info2 = FIELD_PREP( 808 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 809 params.low_threshold); 810 } 811 812 ath11k_dbg(ab, ATH11k_DBG_HAL, 813 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 814 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 815 cmd->msi_data); 816 817 ath11k_dbg(ab, ATH11k_DBG_HAL, 818 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 819 ring_id, ring_type, cmd->intr_info, cmd->info2); 820 821 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 822 if (ret) 823 goto err_free; 824 825 return 0; 826 827 err_free: 828 dev_kfree_skb_any(skb); 829 830 return ret; 831 } 832 833 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 834 835 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 836 { 837 struct ath11k_dp *dp = &ab->dp; 838 struct sk_buff *skb; 839 struct htt_ver_req_cmd *cmd; 840 int len = sizeof(*cmd); 841 int ret; 842 843 init_completion(&dp->htt_tgt_version_received); 844 845 skb = ath11k_htc_alloc_skb(ab, len); 846 if (!skb) 847 return -ENOMEM; 848 849 skb_put(skb, len); 850 cmd = (struct htt_ver_req_cmd *)skb->data; 851 cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 852 HTT_H2T_MSG_TYPE_VERSION_REQ); 853 854 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 855 if (ret) { 856 dev_kfree_skb_any(skb); 857 return ret; 858 } 859 860 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 861 HTT_TARGET_VERSION_TIMEOUT_HZ); 862 if (ret == 0) { 863 ath11k_warn(ab, "htt target version request timed out\n"); 864 return -ETIMEDOUT; 865 } 866 867 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 868 ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 869 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 870 return -ENOTSUPP; 871 } 872 873 return 0; 874 } 875 876 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 877 { 878 struct ath11k_base *ab = ar->ab; 879 struct ath11k_dp *dp = &ab->dp; 880 struct sk_buff *skb; 881 struct htt_ppdu_stats_cfg_cmd *cmd; 882 int len = sizeof(*cmd); 883 u8 pdev_mask; 884 int ret; 885 int i; 886 887 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 888 skb = ath11k_htc_alloc_skb(ab, len); 889 if (!skb) 890 return -ENOMEM; 891 892 skb_put(skb, len); 893 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 894 cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 895 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 896 897 pdev_mask = 1 << (i + 1); 898 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 899 cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 900 901 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 902 if (ret) { 903 dev_kfree_skb_any(skb); 904 return ret; 905 } 906 } 907 908 return 0; 909 } 910 911 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 912 int mac_id, enum hal_ring_type ring_type, 913 int rx_buf_size, 914 struct htt_rx_ring_tlv_filter *tlv_filter) 915 { 916 struct htt_rx_ring_selection_cfg_cmd *cmd; 917 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 918 struct hal_srng_params params; 919 struct sk_buff *skb; 920 int len = sizeof(*cmd); 921 enum htt_srng_ring_type htt_ring_type; 922 enum htt_srng_ring_id htt_ring_id; 923 int ret; 924 925 skb = ath11k_htc_alloc_skb(ab, len); 926 if (!skb) 927 return -ENOMEM; 928 929 memset(¶ms, 0, sizeof(params)); 930 ath11k_hal_srng_get_params(ab, srng, ¶ms); 931 932 ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 933 ring_type, &htt_ring_type, 934 &htt_ring_id); 935 if (ret) 936 goto err_free; 937 938 skb_put(skb, len); 939 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 940 cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 941 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 942 if (htt_ring_type == HTT_SW_TO_HW_RING || 943 htt_ring_type == HTT_HW_TO_SW_RING) 944 cmd->info0 |= 945 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 946 DP_SW2HW_MACID(mac_id)); 947 else 948 cmd->info0 |= 949 FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 950 mac_id); 951 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 952 htt_ring_id); 953 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 954 !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 955 cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 956 !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 957 958 cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 959 rx_buf_size); 960 cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 961 cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 962 cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 963 cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 964 cmd->rx_filter_tlv = tlv_filter->rx_filter; 965 966 ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 967 if (ret) 968 goto err_free; 969 970 return 0; 971 972 err_free: 973 dev_kfree_skb_any(skb); 974 975 return ret; 976 } 977 978 int 979 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 980 struct htt_ext_stats_cfg_params *cfg_params, 981 u64 cookie) 982 { 983 struct ath11k_base *ab = ar->ab; 984 struct ath11k_dp *dp = &ab->dp; 985 struct sk_buff *skb; 986 struct htt_ext_stats_cfg_cmd *cmd; 987 int len = sizeof(*cmd); 988 int ret; 989 990 skb = ath11k_htc_alloc_skb(ab, len); 991 if (!skb) 992 return -ENOMEM; 993 994 skb_put(skb, len); 995 996 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 997 memset(cmd, 0, sizeof(*cmd)); 998 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 999 1000 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1001 1002 cmd->hdr.stats_type = type; 1003 cmd->cfg_param0 = cfg_params->cfg0; 1004 cmd->cfg_param1 = cfg_params->cfg1; 1005 cmd->cfg_param2 = cfg_params->cfg2; 1006 cmd->cfg_param3 = cfg_params->cfg3; 1007 cmd->cookie_lsb = lower_32_bits(cookie); 1008 cmd->cookie_msb = upper_32_bits(cookie); 1009 1010 ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1011 if (ret) { 1012 ath11k_warn(ab, "failed to send htt type stats request: %d", 1013 ret); 1014 dev_kfree_skb_any(skb); 1015 return ret; 1016 } 1017 1018 return 0; 1019 } 1020 1021 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1022 { 1023 struct ath11k_pdev_dp *dp = &ar->dp; 1024 struct ath11k_base *ab = ar->ab; 1025 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1026 int ret = 0, ring_id = 0, i; 1027 1028 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1029 1030 if (!reset) { 1031 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1032 tlv_filter.pkt_filter_flags0 = 1033 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1034 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1035 tlv_filter.pkt_filter_flags1 = 1036 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1037 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1038 tlv_filter.pkt_filter_flags2 = 1039 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1040 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1041 tlv_filter.pkt_filter_flags3 = 1042 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1043 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1044 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1045 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1046 } 1047 1048 if (ab->hw_params.rxdma1_enable) { 1049 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1050 HAL_RXDMA_MONITOR_BUF, 1051 DP_RXDMA_REFILL_RING_SIZE, 1052 &tlv_filter); 1053 } else if (!reset) { 1054 /* set in monitor mode only */ 1055 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1056 ring_id = dp->rx_mac_buf_ring[i].ring_id; 1057 ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1058 dp->mac_id + i, 1059 HAL_RXDMA_BUF, 1060 1024, 1061 &tlv_filter); 1062 } 1063 } 1064 1065 if (ret) 1066 return ret; 1067 1068 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1069 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1070 if (!reset) 1071 tlv_filter.rx_filter = 1072 HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1073 else 1074 tlv_filter = ath11k_mac_mon_status_filter_default; 1075 1076 ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 1077 dp->mac_id + i, 1078 HAL_RXDMA_MONITOR_STATUS, 1079 DP_RXDMA_REFILL_RING_SIZE, 1080 &tlv_filter); 1081 } 1082 1083 if (!ar->ab->hw_params.rxdma1_enable) 1084 mod_timer(&ar->ab->mon_reap_timer, jiffies + 1085 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1086 1087 return ret; 1088 } 1089