1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #include "core.h" 7d5c65159SKalle Valo #include "dp_tx.h" 8d5c65159SKalle Valo #include "debug.h" 9568f0603SKalle Valo #include "debugfs_sta.h" 10d5c65159SKalle Valo #include "hw.h" 116a0c3702SJohn Crispin #include "peer.h" 12d5c65159SKalle Valo 13d5c65159SKalle Valo static enum hal_tcl_encap_type 14d5c65159SKalle Valo ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 15d5c65159SKalle Valo { 16e7f33e0cSJohn Crispin struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 17aa2092a9SVenkateswara Naralasetty struct ath11k_base *ab = arvif->ar->ab; 18aa2092a9SVenkateswara Naralasetty 19aa2092a9SVenkateswara Naralasetty if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 20aa2092a9SVenkateswara Naralasetty return HAL_TCL_ENCAP_TYPE_RAW; 21e7f33e0cSJohn Crispin 22cc20ff2cSFelix Fietkau if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 23e7f33e0cSJohn Crispin return HAL_TCL_ENCAP_TYPE_ETHERNET; 24e7f33e0cSJohn Crispin 25d5c65159SKalle Valo return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 26d5c65159SKalle Valo } 27d5c65159SKalle Valo 28d5c65159SKalle Valo static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 29d5c65159SKalle Valo { 30d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 31d5c65159SKalle Valo u8 *qos_ctl; 32d5c65159SKalle Valo 33d5c65159SKalle Valo if (!ieee80211_is_data_qos(hdr->frame_control)) 34d5c65159SKalle Valo return; 35d5c65159SKalle Valo 36d5c65159SKalle Valo qos_ctl = ieee80211_get_qos_ctl(hdr); 37d5c65159SKalle Valo memmove(skb->data + IEEE80211_QOS_CTL_LEN, 38d5c65159SKalle Valo skb->data, (void *)qos_ctl - (void *)skb->data); 39d5c65159SKalle Valo skb_pull(skb, IEEE80211_QOS_CTL_LEN); 40d5c65159SKalle Valo 41d5c65159SKalle Valo hdr = (void *)skb->data; 42d5c65159SKalle Valo hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 43d5c65159SKalle Valo } 44d5c65159SKalle Valo 45d5c65159SKalle Valo static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 46d5c65159SKalle Valo { 47d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 48e7f33e0cSJohn Crispin struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 49d5c65159SKalle Valo 50e7f33e0cSJohn Crispin if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 51e7f33e0cSJohn Crispin return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 52e7f33e0cSJohn Crispin else if (!ieee80211_is_data_qos(hdr->frame_control)) 53d5c65159SKalle Valo return HAL_DESC_REO_NON_QOS_TID; 54d5c65159SKalle Valo else 55d5c65159SKalle Valo return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 56d5c65159SKalle Valo } 57d5c65159SKalle Valo 58acc79d98SSriram R enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 59d5c65159SKalle Valo { 60d5c65159SKalle Valo switch (cipher) { 61d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP40: 62d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_40; 63d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP104: 64d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_104; 65d5c65159SKalle Valo case WLAN_CIPHER_SUITE_TKIP: 66d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_TKIP_MIC; 67d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP: 68d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_128; 69d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP_256: 70d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_256; 71d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP: 72d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_GCMP_128; 73d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP_256: 74d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_AES_GCMP_256; 75d5c65159SKalle Valo default: 76d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN; 77d5c65159SKalle Valo } 78d5c65159SKalle Valo } 79d5c65159SKalle Valo 80d5c65159SKalle Valo int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 81d5c65159SKalle Valo struct sk_buff *skb) 82d5c65159SKalle Valo { 83d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 84d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 85d5c65159SKalle Valo struct hal_tx_info ti = {0}; 86d5c65159SKalle Valo struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 88d5c65159SKalle Valo struct hal_srng *tcl_ring; 89d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 90d5c65159SKalle Valo struct dp_tx_ring *tx_ring; 91d5c65159SKalle Valo void *hal_tcl_desc; 92d5c65159SKalle Valo u8 pool_id; 93d5c65159SKalle Valo u8 hal_ring_id; 94d5c65159SKalle Valo int ret; 95d687275bSSriram R u8 ring_selector = 0, ring_map = 0; 96d687275bSSriram R bool tcl_ring_retry; 97d5c65159SKalle Valo 98d5c65159SKalle Valo if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 99d5c65159SKalle Valo return -ESHUTDOWN; 100d5c65159SKalle Valo 101cc20ff2cSFelix Fietkau if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 102e7f33e0cSJohn Crispin !ieee80211_is_data(hdr->frame_control)) 103d5c65159SKalle Valo return -ENOTSUPP; 104d5c65159SKalle Valo 105d5c65159SKalle Valo pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 106d687275bSSriram R 1070eaa4c1dSP Praneesh /* Let the default ring selection be based on current processor 1080eaa4c1dSP Praneesh * number, where one of the 3 tcl rings are selected based on 1090eaa4c1dSP Praneesh * the smp_processor_id(). In case that ring 110d687275bSSriram R * is full/busy, we resort to other available rings. 111d687275bSSriram R * If all rings are full, we drop the packet. 112d687275bSSriram R * //TODO Add throttling logic when all rings are full 113d687275bSSriram R */ 1140eaa4c1dSP Praneesh ring_selector = smp_processor_id(); 115d687275bSSriram R 116d687275bSSriram R tcl_ring_sel: 117d687275bSSriram R tcl_ring_retry = false; 118065f5f68SCarl Huang /* For some chip, it can only use tcl0 to tx */ 119065f5f68SCarl Huang if (ar->ab->hw_params.tcl_0_only) 120065f5f68SCarl Huang ti.ring_id = 0; 121065f5f68SCarl Huang else 122d687275bSSriram R ti.ring_id = ring_selector % DP_TCL_NUM_RING_MAX; 123065f5f68SCarl Huang 124d687275bSSriram R ring_map |= BIT(ti.ring_id); 125d5c65159SKalle Valo 126d5c65159SKalle Valo tx_ring = &dp->tx_ring[ti.ring_id]; 127d5c65159SKalle Valo 128d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 129d5c65159SKalle Valo ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 130d5c65159SKalle Valo DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 131d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 132d5c65159SKalle Valo 133d687275bSSriram R if (ret < 0) { 1340dd6392aSSriram R if (ring_map == (BIT(DP_TCL_NUM_RING_MAX) - 1)) { 1350dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 136d5c65159SKalle Valo return -ENOSPC; 1370dd6392aSSriram R } 138d5c65159SKalle Valo 139d687275bSSriram R /* Check if the next ring is available */ 140d687275bSSriram R ring_selector++; 141d687275bSSriram R goto tcl_ring_sel; 142d687275bSSriram R } 143d687275bSSriram R 144d5c65159SKalle Valo ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 145d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 146d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 147d5c65159SKalle Valo ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 148d5c65159SKalle Valo ti.meta_data_flags = arvif->tcl_metadata; 149d5c65159SKalle Valo 150aa2092a9SVenkateswara Naralasetty if (ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW) { 151*f4d291b4SSven Eckelmann if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 152d5c65159SKalle Valo ti.encrypt_type = 153*f4d291b4SSven Eckelmann ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 154aa2092a9SVenkateswara Naralasetty 155aa2092a9SVenkateswara Naralasetty if (ieee80211_has_protected(hdr->frame_control)) 156aa2092a9SVenkateswara Naralasetty skb_put(skb, IEEE80211_CCMP_MIC_LEN); 157aa2092a9SVenkateswara Naralasetty } else { 158d5c65159SKalle Valo ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 159aa2092a9SVenkateswara Naralasetty } 160aa2092a9SVenkateswara Naralasetty } 161d5c65159SKalle Valo 162d5c65159SKalle Valo ti.addr_search_flags = arvif->hal_addr_search_flags; 163d5c65159SKalle Valo ti.search_type = arvif->search_type; 164d5c65159SKalle Valo ti.type = HAL_TCL_DESC_TYPE_BUFFER; 165d5c65159SKalle Valo ti.pkt_offset = 0; 166d5c65159SKalle Valo ti.lmac_id = ar->lmac_id; 167d5c65159SKalle Valo ti.bss_ast_hash = arvif->ast_hash; 168d5c65159SKalle Valo ti.dscp_tid_tbl_idx = 0; 169d5c65159SKalle Valo 170aa2092a9SVenkateswara Naralasetty if (skb->ip_summed == CHECKSUM_PARTIAL && 171aa2092a9SVenkateswara Naralasetty ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 172d5c65159SKalle Valo ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 173d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 174d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 175d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 176d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 177d5c65159SKalle Valo } 178d5c65159SKalle Valo 179d5c65159SKalle Valo if (ieee80211_vif_is_mesh(arvif->vif)) 180d5c65159SKalle Valo ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE, 1); 181d5c65159SKalle Valo 182d5c65159SKalle Valo ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 183d5c65159SKalle Valo 184d5c65159SKalle Valo ti.tid = ath11k_dp_tx_get_tid(skb); 185d5c65159SKalle Valo 186d5c65159SKalle Valo switch (ti.encap_type) { 187d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 188d5c65159SKalle Valo ath11k_dp_tx_encap_nwifi(skb); 189d5c65159SKalle Valo break; 190d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_RAW: 191aa2092a9SVenkateswara Naralasetty if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 192aa2092a9SVenkateswara Naralasetty ret = -EINVAL; 193aa2092a9SVenkateswara Naralasetty goto fail_remove_idr; 194aa2092a9SVenkateswara Naralasetty } 195aa2092a9SVenkateswara Naralasetty break; 196d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_ETHERNET: 197e7f33e0cSJohn Crispin /* no need to encap */ 198e7f33e0cSJohn Crispin break; 199d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_802_3: 200e7f33e0cSJohn Crispin default: 201d5c65159SKalle Valo /* TODO: Take care of other encap modes as well */ 202d5c65159SKalle Valo ret = -EINVAL; 2030dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 204d5c65159SKalle Valo goto fail_remove_idr; 205d5c65159SKalle Valo } 206d5c65159SKalle Valo 207d5c65159SKalle Valo ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 208d5c65159SKalle Valo if (dma_mapping_error(ab->dev, ti.paddr)) { 2090dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 210d5c65159SKalle Valo ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 211d5c65159SKalle Valo ret = -ENOMEM; 212d5c65159SKalle Valo goto fail_remove_idr; 213d5c65159SKalle Valo } 214d5c65159SKalle Valo 215d5c65159SKalle Valo ti.data_len = skb->len; 216d5c65159SKalle Valo skb_cb->paddr = ti.paddr; 217d5c65159SKalle Valo skb_cb->vif = arvif->vif; 218d5c65159SKalle Valo skb_cb->ar = ar; 219d5c65159SKalle Valo 220d5c65159SKalle Valo hal_ring_id = tx_ring->tcl_data_ring.ring_id; 221d5c65159SKalle Valo tcl_ring = &ab->hal.srng_list[hal_ring_id]; 222d5c65159SKalle Valo 223d5c65159SKalle Valo spin_lock_bh(&tcl_ring->lock); 224d5c65159SKalle Valo 225d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, tcl_ring); 226d5c65159SKalle Valo 227d5c65159SKalle Valo hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 228d5c65159SKalle Valo if (!hal_tcl_desc) { 229d5c65159SKalle Valo /* NOTE: It is highly unlikely we'll be running out of tcl_ring 230d5c65159SKalle Valo * desc because the desc is directly enqueued onto hw queue. 231d5c65159SKalle Valo */ 232d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring); 2330dd6392aSSriram R ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 234d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock); 235d5c65159SKalle Valo ret = -ENOMEM; 236d687275bSSriram R 237d687275bSSriram R /* Checking for available tcl descritors in another ring in 238d687275bSSriram R * case of failure due to full tcl ring now, is better than 239d687275bSSriram R * checking this ring earlier for each pkt tx. 240d687275bSSriram R * Restart ring selection if some rings are not checked yet. 241d687275bSSriram R */ 242065f5f68SCarl Huang if (ring_map != (BIT(DP_TCL_NUM_RING_MAX) - 1) && 243065f5f68SCarl Huang !ar->ab->hw_params.tcl_0_only) { 244d687275bSSriram R tcl_ring_retry = true; 245d687275bSSriram R ring_selector++; 246d687275bSSriram R } 247d687275bSSriram R 248d5c65159SKalle Valo goto fail_unmap_dma; 249d5c65159SKalle Valo } 250d5c65159SKalle Valo 251d0998eb8SJohn Crispin ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 252d0998eb8SJohn Crispin sizeof(struct hal_tlv_hdr), &ti); 253d5c65159SKalle Valo 254d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring); 255d5c65159SKalle Valo 2568ec5a6abSCarl Huang ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 2578ec5a6abSCarl Huang 258d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock); 259d5c65159SKalle Valo 260aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 261aa2092a9SVenkateswara Naralasetty skb->data, skb->len); 262aa2092a9SVenkateswara Naralasetty 263d5c65159SKalle Valo atomic_inc(&ar->dp.num_tx_pending); 264d5c65159SKalle Valo 265d5c65159SKalle Valo return 0; 266d5c65159SKalle Valo 267d5c65159SKalle Valo fail_unmap_dma: 268d5c65159SKalle Valo dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 269d5c65159SKalle Valo 270d5c65159SKalle Valo fail_remove_idr: 271d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 272d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr, 273d5c65159SKalle Valo FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 274d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 275d5c65159SKalle Valo 276d687275bSSriram R if (tcl_ring_retry) 277d687275bSSriram R goto tcl_ring_sel; 278d687275bSSriram R 279d5c65159SKalle Valo return ret; 280d5c65159SKalle Valo } 281d5c65159SKalle Valo 282d5c65159SKalle Valo static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 283d5c65159SKalle Valo int msdu_id, 284d5c65159SKalle Valo struct dp_tx_ring *tx_ring) 285d5c65159SKalle Valo { 286d5c65159SKalle Valo struct ath11k *ar; 287d5c65159SKalle Valo struct sk_buff *msdu; 288d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 289d5c65159SKalle Valo 290d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 291d5c65159SKalle Valo msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 292d5c65159SKalle Valo if (!msdu) { 293d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 294d5c65159SKalle Valo msdu_id); 295d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 296d5c65159SKalle Valo return; 297d5c65159SKalle Valo } 298d5c65159SKalle Valo 299d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 300d5c65159SKalle Valo 301d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr, msdu_id); 302d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 303d5c65159SKalle Valo 304d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 305d5c65159SKalle Valo dev_kfree_skb_any(msdu); 306d5c65159SKalle Valo 307d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 308d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 309d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 310d5c65159SKalle Valo } 311d5c65159SKalle Valo 312d5c65159SKalle Valo static void 313d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 314d5c65159SKalle Valo struct dp_tx_ring *tx_ring, 315d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status *ts) 316d5c65159SKalle Valo { 317d5c65159SKalle Valo struct sk_buff *msdu; 318d5c65159SKalle Valo struct ieee80211_tx_info *info; 319d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 320d5c65159SKalle Valo struct ath11k *ar; 321d5c65159SKalle Valo 322d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 323d5c65159SKalle Valo msdu = idr_find(&tx_ring->txbuf_idr, ts->msdu_id); 324d5c65159SKalle Valo if (!msdu) { 325d5c65159SKalle Valo ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 326d5c65159SKalle Valo ts->msdu_id); 327d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 328d5c65159SKalle Valo return; 329d5c65159SKalle Valo } 330d5c65159SKalle Valo 331d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 332d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu); 333d5c65159SKalle Valo 334d5c65159SKalle Valo ar = skb_cb->ar; 335d5c65159SKalle Valo 336d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 337d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 338d5c65159SKalle Valo 339d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 340d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 341d5c65159SKalle Valo 342d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 343d5c65159SKalle Valo 344d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status)); 345d5c65159SKalle Valo 346d5c65159SKalle Valo if (ts->acked) { 347d5c65159SKalle Valo if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 348d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK; 349d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 350d5c65159SKalle Valo ts->ack_rssi; 351d5c65159SKalle Valo info->status.is_valid_ack_signal = true; 352d5c65159SKalle Valo } else { 353d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 354d5c65159SKalle Valo } 355d5c65159SKalle Valo } 356d5c65159SKalle Valo 357d5c65159SKalle Valo ieee80211_tx_status(ar->hw, msdu); 358d5c65159SKalle Valo } 359d5c65159SKalle Valo 360d5c65159SKalle Valo static void 361d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 362d5c65159SKalle Valo void *desc, u8 mac_id, 363d5c65159SKalle Valo u32 msdu_id, struct dp_tx_ring *tx_ring) 364d5c65159SKalle Valo { 365d5c65159SKalle Valo struct htt_tx_wbm_completion *status_desc; 366d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status ts = {0}; 367d5c65159SKalle Valo enum hal_wbm_htt_tx_comp_status wbm_status; 368d5c65159SKalle Valo 369d5c65159SKalle Valo status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 370d5c65159SKalle Valo 371d5c65159SKalle Valo wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 372d5c65159SKalle Valo status_desc->info0); 373d5c65159SKalle Valo switch (wbm_status) { 374d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 375d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 376d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 377d5c65159SKalle Valo ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 378d5c65159SKalle Valo ts.msdu_id = msdu_id; 379d5c65159SKalle Valo ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 380d5c65159SKalle Valo status_desc->info1); 381d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 382d5c65159SKalle Valo break; 383d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 384d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 385d5c65159SKalle Valo ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 386d5c65159SKalle Valo break; 387d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 388d5c65159SKalle Valo /* This event is to be handled only when the driver decides to 389d5c65159SKalle Valo * use WDS offload functionality. 390d5c65159SKalle Valo */ 391d5c65159SKalle Valo break; 392d5c65159SKalle Valo default: 393d5c65159SKalle Valo ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 394d5c65159SKalle Valo break; 395d5c65159SKalle Valo } 396d5c65159SKalle Valo } 397d5c65159SKalle Valo 398d5c65159SKalle Valo static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 399d5c65159SKalle Valo struct sk_buff *msdu, 400d5c65159SKalle Valo struct hal_tx_status *ts) 401d5c65159SKalle Valo { 402d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 403d5c65159SKalle Valo 404d5c65159SKalle Valo if (ts->try_cnt > 1) { 405d5c65159SKalle Valo peer_stats->retry_pkts += ts->try_cnt - 1; 406d5c65159SKalle Valo peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 407d5c65159SKalle Valo 408d5c65159SKalle Valo if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 409d5c65159SKalle Valo peer_stats->failed_pkts += 1; 410d5c65159SKalle Valo peer_stats->failed_bytes += msdu->len; 411d5c65159SKalle Valo } 412d5c65159SKalle Valo } 413d5c65159SKalle Valo } 414d5c65159SKalle Valo 415d5c65159SKalle Valo static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 416d5c65159SKalle Valo struct sk_buff *msdu, 417d5c65159SKalle Valo struct hal_tx_status *ts) 418d5c65159SKalle Valo { 419d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 420d5c65159SKalle Valo struct ieee80211_tx_info *info; 421d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 422d5c65159SKalle Valo 423d5c65159SKalle Valo if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 424d5c65159SKalle Valo /* Must not happen */ 425d5c65159SKalle Valo return; 426d5c65159SKalle Valo } 427d5c65159SKalle Valo 428d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 429d5c65159SKalle Valo 430d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 431d5c65159SKalle Valo 432d5c65159SKalle Valo rcu_read_lock(); 433d5c65159SKalle Valo 434d5c65159SKalle Valo if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 435d5c65159SKalle Valo dev_kfree_skb_any(msdu); 436d5c65159SKalle Valo goto exit; 437d5c65159SKalle Valo } 438d5c65159SKalle Valo 439d5c65159SKalle Valo if (!skb_cb->vif) { 440d5c65159SKalle Valo dev_kfree_skb_any(msdu); 441d5c65159SKalle Valo goto exit; 442d5c65159SKalle Valo } 443d5c65159SKalle Valo 444d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu); 445d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status)); 446d5c65159SKalle Valo 447d5c65159SKalle Valo /* skip tx rate update from ieee80211_status*/ 448d5c65159SKalle Valo info->status.rates[0].idx = -1; 449d5c65159SKalle Valo 450d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 451d5c65159SKalle Valo !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 452d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK; 453d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 454d5c65159SKalle Valo ts->ack_rssi; 455d5c65159SKalle Valo info->status.is_valid_ack_signal = true; 456d5c65159SKalle Valo } 457d5c65159SKalle Valo 458d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 459d5c65159SKalle Valo (info->flags & IEEE80211_TX_CTL_NO_ACK)) 460d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 461d5c65159SKalle Valo 462cb4e57dbSKalle Valo if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) { 463d5c65159SKalle Valo if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 464d5c65159SKalle Valo if (ar->last_ppdu_id == 0) { 465d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id; 466d5c65159SKalle Valo } else if (ar->last_ppdu_id == ts->ppdu_id || 467d5c65159SKalle Valo ar->cached_ppdu_id == ar->last_ppdu_id) { 468d5c65159SKalle Valo ar->cached_ppdu_id = ar->last_ppdu_id; 469d5c65159SKalle Valo ar->cached_stats.is_ampdu = true; 470568f0603SKalle Valo ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 471d5c65159SKalle Valo memset(&ar->cached_stats, 0, 472d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats)); 473d5c65159SKalle Valo } else { 474d5c65159SKalle Valo ar->cached_stats.is_ampdu = false; 475568f0603SKalle Valo ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 476d5c65159SKalle Valo memset(&ar->cached_stats, 0, 477d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats)); 478d5c65159SKalle Valo } 479d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id; 480d5c65159SKalle Valo } 481d5c65159SKalle Valo 482d5c65159SKalle Valo ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 483d5c65159SKalle Valo } 484d5c65159SKalle Valo 485d5c65159SKalle Valo /* NOTE: Tx rate status reporting. Tx completion status does not have 486d5c65159SKalle Valo * necessary information (for example nss) to build the tx rate. 487d5c65159SKalle Valo * Might end up reporting it out-of-band from HTT stats. 488d5c65159SKalle Valo */ 489d5c65159SKalle Valo 490d5c65159SKalle Valo ieee80211_tx_status(ar->hw, msdu); 491d5c65159SKalle Valo 492d5c65159SKalle Valo exit: 493d5c65159SKalle Valo rcu_read_unlock(); 494d5c65159SKalle Valo } 495d5c65159SKalle Valo 4962ad578fdSJohn Crispin static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 4972ad578fdSJohn Crispin struct hal_wbm_release_ring *desc, 4982ad578fdSJohn Crispin struct hal_tx_status *ts) 4992ad578fdSJohn Crispin { 5002ad578fdSJohn Crispin ts->buf_rel_source = 5012ad578fdSJohn Crispin FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 5022ad578fdSJohn Crispin if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 5032ad578fdSJohn Crispin ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 5042ad578fdSJohn Crispin return; 5052ad578fdSJohn Crispin 5062ad578fdSJohn Crispin if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 5072ad578fdSJohn Crispin return; 5082ad578fdSJohn Crispin 5092ad578fdSJohn Crispin ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 5102ad578fdSJohn Crispin desc->info0); 5112ad578fdSJohn Crispin ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 5122ad578fdSJohn Crispin desc->info1); 5132ad578fdSJohn Crispin ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 5142ad578fdSJohn Crispin desc->info1); 5152ad578fdSJohn Crispin ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 5162ad578fdSJohn Crispin desc->info2); 5172ad578fdSJohn Crispin if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 5182ad578fdSJohn Crispin ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 5192ad578fdSJohn Crispin ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 5202ad578fdSJohn Crispin ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 5212ad578fdSJohn Crispin if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 5222ad578fdSJohn Crispin ts->rate_stats = desc->rate_stats.info0; 5232ad578fdSJohn Crispin else 5242ad578fdSJohn Crispin ts->rate_stats = 0; 5252ad578fdSJohn Crispin } 5262ad578fdSJohn Crispin 527d5c65159SKalle Valo void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 528d5c65159SKalle Valo { 529d5c65159SKalle Valo struct ath11k *ar; 530d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 531d5c65159SKalle Valo int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 532d5c65159SKalle Valo struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 533d5c65159SKalle Valo struct sk_buff *msdu; 534eefca584SColin Ian King struct hal_tx_status ts = { 0 }; 535d5c65159SKalle Valo struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 536d5c65159SKalle Valo u32 *desc; 537d5c65159SKalle Valo u32 msdu_id; 538d5c65159SKalle Valo u8 mac_id; 539d5c65159SKalle Valo 5402f588660SCarl Huang spin_lock_bh(&status_ring->lock); 5412f588660SCarl Huang 542d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, status_ring); 543d5c65159SKalle Valo 544d0998eb8SJohn Crispin while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 545d0998eb8SJohn Crispin tx_ring->tx_status_tail) && 546d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 547d0998eb8SJohn Crispin memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 548d0998eb8SJohn Crispin desc, sizeof(struct hal_wbm_release_ring)); 549d0998eb8SJohn Crispin tx_ring->tx_status_head = 550d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 551d5c65159SKalle Valo } 552d5c65159SKalle Valo 553d5c65159SKalle Valo if ((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 554d0998eb8SJohn Crispin (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 555d5c65159SKalle Valo /* TODO: Process pending tx_status messages when kfifo_is_full() */ 556d5c65159SKalle Valo ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 557d5c65159SKalle Valo } 558d5c65159SKalle Valo 559d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, status_ring); 560d5c65159SKalle Valo 5612f588660SCarl Huang spin_unlock_bh(&status_ring->lock); 5622f588660SCarl Huang 563d0998eb8SJohn Crispin while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 564d0998eb8SJohn Crispin struct hal_wbm_release_ring *tx_status; 5652ad578fdSJohn Crispin u32 desc_id; 566d0998eb8SJohn Crispin 567d0998eb8SJohn Crispin tx_ring->tx_status_tail = 568d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 569d0998eb8SJohn Crispin tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 5702ad578fdSJohn Crispin ath11k_dp_tx_status_parse(ab, tx_status, &ts); 571d5c65159SKalle Valo 5722ad578fdSJohn Crispin desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 5732ad578fdSJohn Crispin tx_status->buf_addr_info.info1); 5742ad578fdSJohn Crispin mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 5752ad578fdSJohn Crispin msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 576d5c65159SKalle Valo 577d5c65159SKalle Valo if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 578d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(ab, 579d0998eb8SJohn Crispin (void *)tx_status, 580d5c65159SKalle Valo mac_id, msdu_id, 581d5c65159SKalle Valo tx_ring); 582d5c65159SKalle Valo continue; 583d5c65159SKalle Valo } 584d5c65159SKalle Valo 585d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 586d5c65159SKalle Valo msdu = idr_find(&tx_ring->txbuf_idr, msdu_id); 587d5c65159SKalle Valo if (!msdu) { 588d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 589d5c65159SKalle Valo msdu_id); 590d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 591d5c65159SKalle Valo continue; 592d5c65159SKalle Valo } 593d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr, msdu_id); 594d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 595d5c65159SKalle Valo 596d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 597d5c65159SKalle Valo 598d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 599d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 600d5c65159SKalle Valo 601d5c65159SKalle Valo ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 602d5c65159SKalle Valo } 603d5c65159SKalle Valo } 604d5c65159SKalle Valo 605d5c65159SKalle Valo int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 606d5c65159SKalle Valo enum hal_reo_cmd_type type, 607d5c65159SKalle Valo struct ath11k_hal_reo_cmd *cmd, 608d5c65159SKalle Valo void (*cb)(struct ath11k_dp *, void *, 609d5c65159SKalle Valo enum hal_reo_cmd_status)) 610d5c65159SKalle Valo { 611d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 612d5c65159SKalle Valo struct dp_reo_cmd *dp_cmd; 613d5c65159SKalle Valo struct hal_srng *cmd_ring; 614d5c65159SKalle Valo int cmd_num; 615d5c65159SKalle Valo 616d5c65159SKalle Valo cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 617d5c65159SKalle Valo cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 618d5c65159SKalle Valo 619e190bc05SGovindaraj Saminathan /* cmd_num should start from 1, during failure return the error code */ 620e190bc05SGovindaraj Saminathan if (cmd_num < 0) 621e190bc05SGovindaraj Saminathan return cmd_num; 622e190bc05SGovindaraj Saminathan 623d5c65159SKalle Valo /* reo cmd ring descriptors has cmd_num starting from 1 */ 624e190bc05SGovindaraj Saminathan if (cmd_num == 0) 625d5c65159SKalle Valo return -EINVAL; 626d5c65159SKalle Valo 627d5c65159SKalle Valo if (!cb) 628d5c65159SKalle Valo return 0; 629d5c65159SKalle Valo 630d5c65159SKalle Valo /* Can this be optimized so that we keep the pending command list only 631d5c65159SKalle Valo * for tid delete command to free up the resoruce on the command status 632d5c65159SKalle Valo * indication? 633d5c65159SKalle Valo */ 634d5c65159SKalle Valo dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 635d5c65159SKalle Valo 636d5c65159SKalle Valo if (!dp_cmd) 637d5c65159SKalle Valo return -ENOMEM; 638d5c65159SKalle Valo 639d5c65159SKalle Valo memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 640d5c65159SKalle Valo dp_cmd->cmd_num = cmd_num; 641d5c65159SKalle Valo dp_cmd->handler = cb; 642d5c65159SKalle Valo 643d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 644d5c65159SKalle Valo list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 645d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 646d5c65159SKalle Valo 647d5c65159SKalle Valo return 0; 648d5c65159SKalle Valo } 649d5c65159SKalle Valo 650d5c65159SKalle Valo static int 651d5c65159SKalle Valo ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 652d5c65159SKalle Valo int mac_id, u32 ring_id, 653d5c65159SKalle Valo enum hal_ring_type ring_type, 654d5c65159SKalle Valo enum htt_srng_ring_type *htt_ring_type, 655d5c65159SKalle Valo enum htt_srng_ring_id *htt_ring_id) 656d5c65159SKalle Valo { 657d5c65159SKalle Valo int lmac_ring_id_offset = 0; 658d5c65159SKalle Valo int ret = 0; 659d5c65159SKalle Valo 660d5c65159SKalle Valo switch (ring_type) { 661d5c65159SKalle Valo case HAL_RXDMA_BUF: 662d5c65159SKalle Valo lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 6634152e420SCarl Huang 6644152e420SCarl Huang /* for QCA6390, host fills rx buffer to fw and fw fills to 6654152e420SCarl Huang * rxbuf ring for each rxdma 6664152e420SCarl Huang */ 6674152e420SCarl Huang if (!ab->hw_params.rx_mac_buf_ring) { 668d5c65159SKalle Valo if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 669d5c65159SKalle Valo lmac_ring_id_offset) || 670d5c65159SKalle Valo ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 671d5c65159SKalle Valo lmac_ring_id_offset))) { 672d5c65159SKalle Valo ret = -EINVAL; 673d5c65159SKalle Valo } 674d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 675d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 6764152e420SCarl Huang } else { 6774152e420SCarl Huang if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 6784152e420SCarl Huang *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 6794152e420SCarl Huang *htt_ring_type = HTT_SW_TO_SW_RING; 6804152e420SCarl Huang } else { 6814152e420SCarl Huang *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 6824152e420SCarl Huang *htt_ring_type = HTT_SW_TO_HW_RING; 6834152e420SCarl Huang } 6844152e420SCarl Huang } 685d5c65159SKalle Valo break; 686d5c65159SKalle Valo case HAL_RXDMA_DST: 687d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 688d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING; 689d5c65159SKalle Valo break; 690d5c65159SKalle Valo case HAL_RXDMA_MONITOR_BUF: 691d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 692d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 693d5c65159SKalle Valo break; 694d5c65159SKalle Valo case HAL_RXDMA_MONITOR_STATUS: 695d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 696d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 697d5c65159SKalle Valo break; 698d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DST: 699d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 700d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING; 701d5c65159SKalle Valo break; 702d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DESC: 703d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 704d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 705d5c65159SKalle Valo break; 706d5c65159SKalle Valo default: 707d5c65159SKalle Valo ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 708d5c65159SKalle Valo ret = -EINVAL; 709d5c65159SKalle Valo } 710d5c65159SKalle Valo return ret; 711d5c65159SKalle Valo } 712d5c65159SKalle Valo 713d5c65159SKalle Valo int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 714d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type) 715d5c65159SKalle Valo { 716d5c65159SKalle Valo struct htt_srng_setup_cmd *cmd; 717d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 718d5c65159SKalle Valo struct hal_srng_params params; 719d5c65159SKalle Valo struct sk_buff *skb; 720d5c65159SKalle Valo u32 ring_entry_sz; 721d5c65159SKalle Valo int len = sizeof(*cmd); 722d5c65159SKalle Valo dma_addr_t hp_addr, tp_addr; 723d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type; 724d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id; 7257195c874SDan Carpenter int ret; 726d5c65159SKalle Valo 727d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 728d5c65159SKalle Valo if (!skb) 729d5c65159SKalle Valo return -ENOMEM; 730d5c65159SKalle Valo 731d5c65159SKalle Valo memset(¶ms, 0, sizeof(params)); 732d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms); 733d5c65159SKalle Valo 734d5c65159SKalle Valo hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 735d5c65159SKalle Valo tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 736d5c65159SKalle Valo 7377195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 738d5c65159SKalle Valo ring_type, &htt_ring_type, 7397195c874SDan Carpenter &htt_ring_id); 7407195c874SDan Carpenter if (ret) 741d5c65159SKalle Valo goto err_free; 742d5c65159SKalle Valo 743d5c65159SKalle Valo skb_put(skb, len); 744d5c65159SKalle Valo cmd = (struct htt_srng_setup_cmd *)skb->data; 745d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 746d5c65159SKalle Valo HTT_H2T_MSG_TYPE_SRING_SETUP); 747d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING || 748d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING) 749d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 750d5c65159SKalle Valo DP_SW2HW_MACID(mac_id)); 751d5c65159SKalle Valo else 752d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 753d5c65159SKalle Valo mac_id); 754d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 755d5c65159SKalle Valo htt_ring_type); 756d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 757d5c65159SKalle Valo 758d5c65159SKalle Valo cmd->ring_base_addr_lo = params.ring_base_paddr & 759d5c65159SKalle Valo HAL_ADDR_LSB_REG_MASK; 760d5c65159SKalle Valo 761d5c65159SKalle Valo cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 762d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 763d5c65159SKalle Valo 764f7eb4b04SKalle Valo ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 7657195c874SDan Carpenter if (ret < 0) 7664358bcb5SColin Ian King goto err_free; 767d5c65159SKalle Valo 768d5c65159SKalle Valo ring_entry_sz = ret; 769d5c65159SKalle Valo 770d5c65159SKalle Valo ring_entry_sz >>= 2; 771d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 772d5c65159SKalle Valo ring_entry_sz); 773d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 774d5c65159SKalle Valo params.num_entries * ring_entry_sz); 775d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 776d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 777d5c65159SKalle Valo cmd->info1 |= FIELD_PREP( 778d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 779d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 780d5c65159SKalle Valo cmd->info1 |= FIELD_PREP( 781d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 782d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 783d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING) 784d5c65159SKalle Valo cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 785d5c65159SKalle Valo 786d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 787d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 788d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 789d5c65159SKalle Valo 790d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 791d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 792d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 793d5c65159SKalle Valo 794701e48a4SCarl Huang cmd->ring_msi_addr_lo = params.msi_addr & 0xffffffff; 795701e48a4SCarl Huang cmd->ring_msi_addr_hi = ((uint64_t)(params.msi_addr) >> 32) & 0xffffffff; 796701e48a4SCarl Huang cmd->msi_data = params.msi_data; 797d5c65159SKalle Valo 798d5c65159SKalle Valo cmd->intr_info = FIELD_PREP( 799d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 800d5c65159SKalle Valo params.intr_batch_cntr_thres_entries * ring_entry_sz); 801d5c65159SKalle Valo cmd->intr_info |= FIELD_PREP( 802d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 803d5c65159SKalle Valo params.intr_timer_thres_us >> 3); 804d5c65159SKalle Valo 805d5c65159SKalle Valo cmd->info2 = 0; 806d5c65159SKalle Valo if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 807d5c65159SKalle Valo cmd->info2 = FIELD_PREP( 808d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 809d5c65159SKalle Valo params.low_threshold); 810d5c65159SKalle Valo } 811d5c65159SKalle Valo 812701e48a4SCarl Huang ath11k_dbg(ab, ATH11k_DBG_HAL, 813701e48a4SCarl Huang "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 814701e48a4SCarl Huang __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 815701e48a4SCarl Huang cmd->msi_data); 816701e48a4SCarl Huang 817701e48a4SCarl Huang ath11k_dbg(ab, ATH11k_DBG_HAL, 818701e48a4SCarl Huang "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 819701e48a4SCarl Huang ring_id, ring_type, cmd->intr_info, cmd->info2); 820701e48a4SCarl Huang 821d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 822d5c65159SKalle Valo if (ret) 823d5c65159SKalle Valo goto err_free; 824d5c65159SKalle Valo 825d5c65159SKalle Valo return 0; 826d5c65159SKalle Valo 827d5c65159SKalle Valo err_free: 828d5c65159SKalle Valo dev_kfree_skb_any(skb); 829d5c65159SKalle Valo 830d5c65159SKalle Valo return ret; 831d5c65159SKalle Valo } 832d5c65159SKalle Valo 833d5c65159SKalle Valo #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 834d5c65159SKalle Valo 835d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 836d5c65159SKalle Valo { 837d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 838d5c65159SKalle Valo struct sk_buff *skb; 839d5c65159SKalle Valo struct htt_ver_req_cmd *cmd; 840d5c65159SKalle Valo int len = sizeof(*cmd); 841d5c65159SKalle Valo int ret; 842d5c65159SKalle Valo 843d5c65159SKalle Valo init_completion(&dp->htt_tgt_version_received); 844d5c65159SKalle Valo 845d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 846d5c65159SKalle Valo if (!skb) 847d5c65159SKalle Valo return -ENOMEM; 848d5c65159SKalle Valo 849d5c65159SKalle Valo skb_put(skb, len); 850d5c65159SKalle Valo cmd = (struct htt_ver_req_cmd *)skb->data; 851d5c65159SKalle Valo cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 852d5c65159SKalle Valo HTT_H2T_MSG_TYPE_VERSION_REQ); 853d5c65159SKalle Valo 854d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 855d5c65159SKalle Valo if (ret) { 856d5c65159SKalle Valo dev_kfree_skb_any(skb); 857d5c65159SKalle Valo return ret; 858d5c65159SKalle Valo } 859d5c65159SKalle Valo 860d5c65159SKalle Valo ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 861d5c65159SKalle Valo HTT_TARGET_VERSION_TIMEOUT_HZ); 862d5c65159SKalle Valo if (ret == 0) { 863d5c65159SKalle Valo ath11k_warn(ab, "htt target version request timed out\n"); 864d5c65159SKalle Valo return -ETIMEDOUT; 865d5c65159SKalle Valo } 866d5c65159SKalle Valo 867d5c65159SKalle Valo if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 868d5c65159SKalle Valo ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 869d5c65159SKalle Valo dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 870d5c65159SKalle Valo return -ENOTSUPP; 871d5c65159SKalle Valo } 872d5c65159SKalle Valo 873d5c65159SKalle Valo return 0; 874d5c65159SKalle Valo } 875d5c65159SKalle Valo 876d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 877d5c65159SKalle Valo { 878d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 879d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 880d5c65159SKalle Valo struct sk_buff *skb; 881d5c65159SKalle Valo struct htt_ppdu_stats_cfg_cmd *cmd; 882d5c65159SKalle Valo int len = sizeof(*cmd); 883d5c65159SKalle Valo u8 pdev_mask; 884d5c65159SKalle Valo int ret; 885701e48a4SCarl Huang int i; 886d5c65159SKalle Valo 887701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 888d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 889d5c65159SKalle Valo if (!skb) 890d5c65159SKalle Valo return -ENOMEM; 891d5c65159SKalle Valo 892d5c65159SKalle Valo skb_put(skb, len); 893d5c65159SKalle Valo cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 894d5c65159SKalle Valo cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 895d5c65159SKalle Valo HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 896d5c65159SKalle Valo 897701e48a4SCarl Huang pdev_mask = 1 << (i + 1); 898d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 899d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 900d5c65159SKalle Valo 901d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 902d5c65159SKalle Valo if (ret) { 903d5c65159SKalle Valo dev_kfree_skb_any(skb); 904d5c65159SKalle Valo return ret; 905d5c65159SKalle Valo } 906701e48a4SCarl Huang } 907d5c65159SKalle Valo 908d5c65159SKalle Valo return 0; 909d5c65159SKalle Valo } 910d5c65159SKalle Valo 911d5c65159SKalle Valo int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 912d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type, 913d5c65159SKalle Valo int rx_buf_size, 914d5c65159SKalle Valo struct htt_rx_ring_tlv_filter *tlv_filter) 915d5c65159SKalle Valo { 916d5c65159SKalle Valo struct htt_rx_ring_selection_cfg_cmd *cmd; 917d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 918d5c65159SKalle Valo struct hal_srng_params params; 919d5c65159SKalle Valo struct sk_buff *skb; 920d5c65159SKalle Valo int len = sizeof(*cmd); 921d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type; 922d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id; 9237195c874SDan Carpenter int ret; 924d5c65159SKalle Valo 925d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 926d5c65159SKalle Valo if (!skb) 927d5c65159SKalle Valo return -ENOMEM; 928d5c65159SKalle Valo 929d5c65159SKalle Valo memset(¶ms, 0, sizeof(params)); 930d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms); 931d5c65159SKalle Valo 9327195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 933d5c65159SKalle Valo ring_type, &htt_ring_type, 9347195c874SDan Carpenter &htt_ring_id); 9357195c874SDan Carpenter if (ret) 936d5c65159SKalle Valo goto err_free; 937d5c65159SKalle Valo 938d5c65159SKalle Valo skb_put(skb, len); 939d5c65159SKalle Valo cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 940d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 941d5c65159SKalle Valo HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 942d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING || 943d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING) 944d5c65159SKalle Valo cmd->info0 |= 945d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 946d5c65159SKalle Valo DP_SW2HW_MACID(mac_id)); 947d5c65159SKalle Valo else 948d5c65159SKalle Valo cmd->info0 |= 949d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 950d5c65159SKalle Valo mac_id); 951d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 952d5c65159SKalle Valo htt_ring_id); 953d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 954d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 955d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 956d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 957d5c65159SKalle Valo 958d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 959d5c65159SKalle Valo rx_buf_size); 960d5c65159SKalle Valo cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 961d5c65159SKalle Valo cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 962d5c65159SKalle Valo cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 963d5c65159SKalle Valo cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 964d5c65159SKalle Valo cmd->rx_filter_tlv = tlv_filter->rx_filter; 965d5c65159SKalle Valo 966d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 967d5c65159SKalle Valo if (ret) 968d5c65159SKalle Valo goto err_free; 969d5c65159SKalle Valo 970d5c65159SKalle Valo return 0; 971d5c65159SKalle Valo 972d5c65159SKalle Valo err_free: 973d5c65159SKalle Valo dev_kfree_skb_any(skb); 974d5c65159SKalle Valo 975d5c65159SKalle Valo return ret; 976d5c65159SKalle Valo } 977d5c65159SKalle Valo 978d5c65159SKalle Valo int 979d5c65159SKalle Valo ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 980d5c65159SKalle Valo struct htt_ext_stats_cfg_params *cfg_params, 981d5c65159SKalle Valo u64 cookie) 982d5c65159SKalle Valo { 983d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 984d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 985d5c65159SKalle Valo struct sk_buff *skb; 986d5c65159SKalle Valo struct htt_ext_stats_cfg_cmd *cmd; 987d5c65159SKalle Valo int len = sizeof(*cmd); 988d5c65159SKalle Valo int ret; 989d5c65159SKalle Valo 990d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 991d5c65159SKalle Valo if (!skb) 992d5c65159SKalle Valo return -ENOMEM; 993d5c65159SKalle Valo 994d5c65159SKalle Valo skb_put(skb, len); 995d5c65159SKalle Valo 996d5c65159SKalle Valo cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 997d5c65159SKalle Valo memset(cmd, 0, sizeof(*cmd)); 998d5c65159SKalle Valo cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 999d5c65159SKalle Valo 1000d5c65159SKalle Valo cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1001d5c65159SKalle Valo 1002d5c65159SKalle Valo cmd->hdr.stats_type = type; 1003d5c65159SKalle Valo cmd->cfg_param0 = cfg_params->cfg0; 1004d5c65159SKalle Valo cmd->cfg_param1 = cfg_params->cfg1; 1005d5c65159SKalle Valo cmd->cfg_param2 = cfg_params->cfg2; 1006d5c65159SKalle Valo cmd->cfg_param3 = cfg_params->cfg3; 1007d5c65159SKalle Valo cmd->cookie_lsb = lower_32_bits(cookie); 1008d5c65159SKalle Valo cmd->cookie_msb = upper_32_bits(cookie); 1009d5c65159SKalle Valo 1010d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1011d5c65159SKalle Valo if (ret) { 1012d5c65159SKalle Valo ath11k_warn(ab, "failed to send htt type stats request: %d", 1013d5c65159SKalle Valo ret); 1014d5c65159SKalle Valo dev_kfree_skb_any(skb); 1015d5c65159SKalle Valo return ret; 1016d5c65159SKalle Valo } 1017d5c65159SKalle Valo 1018d5c65159SKalle Valo return 0; 1019d5c65159SKalle Valo } 1020d5c65159SKalle Valo 1021d5c65159SKalle Valo int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1022d5c65159SKalle Valo { 1023d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 10244152e420SCarl Huang struct ath11k_base *ab = ar->ab; 1025d5c65159SKalle Valo struct htt_rx_ring_tlv_filter tlv_filter = {0}; 10264152e420SCarl Huang int ret = 0, ring_id = 0, i; 1027d5c65159SKalle Valo 1028d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1029d5c65159SKalle Valo 1030d5c65159SKalle Valo if (!reset) { 1031d5c65159SKalle Valo tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1032d5c65159SKalle Valo tlv_filter.pkt_filter_flags0 = 1033d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1034d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1035d5c65159SKalle Valo tlv_filter.pkt_filter_flags1 = 1036d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1037d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1038d5c65159SKalle Valo tlv_filter.pkt_filter_flags2 = 1039d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1040d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1041d5c65159SKalle Valo tlv_filter.pkt_filter_flags3 = 1042d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1043d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1044d5c65159SKalle Valo HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1045d5c65159SKalle Valo HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1046d5c65159SKalle Valo } 1047d5c65159SKalle Valo 1048701e48a4SCarl Huang if (ab->hw_params.rxdma1_enable) { 1049d5c65159SKalle Valo ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1050d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF, 1051d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE, 1052d5c65159SKalle Valo &tlv_filter); 1053701e48a4SCarl Huang } else if (!reset) { 1054701e48a4SCarl Huang /* set in monitor mode only */ 1055701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1056701e48a4SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id; 1057701e48a4SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1058701e48a4SCarl Huang dp->mac_id + i, 1059701e48a4SCarl Huang HAL_RXDMA_BUF, 1060701e48a4SCarl Huang 1024, 1061701e48a4SCarl Huang &tlv_filter); 1062701e48a4SCarl Huang } 1063701e48a4SCarl Huang } 1064701e48a4SCarl Huang 1065d5c65159SKalle Valo if (ret) 1066d5c65159SKalle Valo return ret; 1067d5c65159SKalle Valo 10684152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 10694152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1070d5c65159SKalle Valo if (!reset) 1071d5c65159SKalle Valo tlv_filter.rx_filter = 1072d5c65159SKalle Valo HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1073d5c65159SKalle Valo else 1074d5c65159SKalle Valo tlv_filter = ath11k_mac_mon_status_filter_default; 1075d5c65159SKalle Valo 10764152e420SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 10774152e420SCarl Huang dp->mac_id + i, 1078d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS, 1079d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE, 1080d5c65159SKalle Valo &tlv_filter); 10814152e420SCarl Huang } 10824152e420SCarl Huang 1083701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 1084701e48a4SCarl Huang mod_timer(&ar->ab->mon_reap_timer, jiffies + 1085701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1086701e48a4SCarl Huang 1087d5c65159SKalle Valo return ret; 1088d5c65159SKalle Valo } 1089