1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #include "core.h" 7d5c65159SKalle Valo #include "dp_tx.h" 8d5c65159SKalle Valo #include "debug.h" 9568f0603SKalle Valo #include "debugfs_sta.h" 10d5c65159SKalle Valo #include "hw.h" 116a0c3702SJohn Crispin #include "peer.h" 1213706340SWen Gong #include "mac.h" 13d5c65159SKalle Valo 14d5c65159SKalle Valo static enum hal_tcl_encap_type 15d5c65159SKalle Valo ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb) 16d5c65159SKalle Valo { 17e7f33e0cSJohn Crispin struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 18aa2092a9SVenkateswara Naralasetty struct ath11k_base *ab = arvif->ar->ab; 19aa2092a9SVenkateswara Naralasetty 20aa2092a9SVenkateswara Naralasetty if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 21aa2092a9SVenkateswara Naralasetty return HAL_TCL_ENCAP_TYPE_RAW; 22e7f33e0cSJohn Crispin 23cc20ff2cSFelix Fietkau if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 24e7f33e0cSJohn Crispin return HAL_TCL_ENCAP_TYPE_ETHERNET; 25e7f33e0cSJohn Crispin 26d5c65159SKalle Valo return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 27d5c65159SKalle Valo } 28d5c65159SKalle Valo 29d5c65159SKalle Valo static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb) 30d5c65159SKalle Valo { 31d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 32d5c65159SKalle Valo u8 *qos_ctl; 33d5c65159SKalle Valo 34d5c65159SKalle Valo if (!ieee80211_is_data_qos(hdr->frame_control)) 35d5c65159SKalle Valo return; 36d5c65159SKalle Valo 37d5c65159SKalle Valo qos_ctl = ieee80211_get_qos_ctl(hdr); 38d5c65159SKalle Valo memmove(skb->data + IEEE80211_QOS_CTL_LEN, 39d5c65159SKalle Valo skb->data, (void *)qos_ctl - (void *)skb->data); 40d5c65159SKalle Valo skb_pull(skb, IEEE80211_QOS_CTL_LEN); 41d5c65159SKalle Valo 42d5c65159SKalle Valo hdr = (void *)skb->data; 43d5c65159SKalle Valo hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 44d5c65159SKalle Valo } 45d5c65159SKalle Valo 46d5c65159SKalle Valo static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb) 47d5c65159SKalle Valo { 48d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 49e7f33e0cSJohn Crispin struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb); 50d5c65159SKalle Valo 51e7f33e0cSJohn Crispin if (cb->flags & ATH11K_SKB_HW_80211_ENCAP) 52e7f33e0cSJohn Crispin return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 53e7f33e0cSJohn Crispin else if (!ieee80211_is_data_qos(hdr->frame_control)) 54d5c65159SKalle Valo return HAL_DESC_REO_NON_QOS_TID; 55d5c65159SKalle Valo else 56d5c65159SKalle Valo return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 57d5c65159SKalle Valo } 58d5c65159SKalle Valo 59acc79d98SSriram R enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher) 60d5c65159SKalle Valo { 61d5c65159SKalle Valo switch (cipher) { 62d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP40: 63d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_40; 64d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP104: 65d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_104; 66d5c65159SKalle Valo case WLAN_CIPHER_SUITE_TKIP: 67d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_TKIP_MIC; 68d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP: 69d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_128; 70d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP_256: 71d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_256; 72d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP: 73d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_GCMP_128; 74d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP_256: 75d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_AES_GCMP_256; 76d5c65159SKalle Valo default: 77d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN; 78d5c65159SKalle Valo } 79d5c65159SKalle Valo } 80d5c65159SKalle Valo 81d5c65159SKalle Valo int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, 82e20cfa3bSKarthikeyan Periyasamy struct ath11k_sta *arsta, struct sk_buff *skb) 83d5c65159SKalle Valo { 84d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 85d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 86d5c65159SKalle Valo struct hal_tx_info ti = {0}; 87d5c65159SKalle Valo struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 88d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb); 89d5c65159SKalle Valo struct hal_srng *tcl_ring; 90d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data; 91d5c65159SKalle Valo struct dp_tx_ring *tx_ring; 92d5c65159SKalle Valo void *hal_tcl_desc; 93d5c65159SKalle Valo u8 pool_id; 94d5c65159SKalle Valo u8 hal_ring_id; 95d5c65159SKalle Valo int ret; 96d687275bSSriram R u8 ring_selector = 0, ring_map = 0; 97d687275bSSriram R bool tcl_ring_retry; 98d5c65159SKalle Valo 99bcef57eaSP Praneesh if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) 100d5c65159SKalle Valo return -ESHUTDOWN; 101d5c65159SKalle Valo 102bcef57eaSP Praneesh if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 103bcef57eaSP Praneesh !ieee80211_is_data(hdr->frame_control))) 104d5c65159SKalle Valo return -ENOTSUPP; 105d5c65159SKalle Valo 106d5c65159SKalle Valo pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1); 107d687275bSSriram R 1080eaa4c1dSP Praneesh /* Let the default ring selection be based on current processor 1090eaa4c1dSP Praneesh * number, where one of the 3 tcl rings are selected based on 1100eaa4c1dSP Praneesh * the smp_processor_id(). In case that ring 111d687275bSSriram R * is full/busy, we resort to other available rings. 112d687275bSSriram R * If all rings are full, we drop the packet. 113d687275bSSriram R * //TODO Add throttling logic when all rings are full 114d687275bSSriram R */ 1150eaa4c1dSP Praneesh ring_selector = smp_processor_id(); 116d687275bSSriram R 117d687275bSSriram R tcl_ring_sel: 118d687275bSSriram R tcl_ring_retry = false; 11931582373SBaochen Qiang 12031582373SBaochen Qiang ti.ring_id = ring_selector % ab->hw_params.max_tx_ring; 121065f5f68SCarl Huang 122d687275bSSriram R ring_map |= BIT(ti.ring_id); 123d5c65159SKalle Valo 124d5c65159SKalle Valo tx_ring = &dp->tx_ring[ti.ring_id]; 125d5c65159SKalle Valo 126d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 127d5c65159SKalle Valo ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0, 128d5c65159SKalle Valo DP_TX_IDR_SIZE - 1, GFP_ATOMIC); 129d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 130d5c65159SKalle Valo 131bcef57eaSP Praneesh if (unlikely(ret < 0)) { 13231582373SBaochen Qiang if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) { 1330dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 134d5c65159SKalle Valo return -ENOSPC; 1350dd6392aSSriram R } 136d5c65159SKalle Valo 137d687275bSSriram R /* Check if the next ring is available */ 138d687275bSSriram R ring_selector++; 139d687275bSSriram R goto tcl_ring_sel; 140d687275bSSriram R } 141d687275bSSriram R 142d5c65159SKalle Valo ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) | 143d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) | 144d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id); 145d5c65159SKalle Valo ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb); 146e20cfa3bSKarthikeyan Periyasamy 147e20cfa3bSKarthikeyan Periyasamy if (ieee80211_has_a4(hdr->frame_control) && 148e20cfa3bSKarthikeyan Periyasamy is_multicast_ether_addr(hdr->addr3) && arsta && 149e20cfa3bSKarthikeyan Periyasamy arsta->use_4addr_set) { 150e20cfa3bSKarthikeyan Periyasamy ti.meta_data_flags = arsta->tcl_metadata; 151e20cfa3bSKarthikeyan Periyasamy ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); 152e20cfa3bSKarthikeyan Periyasamy } else { 153d5c65159SKalle Valo ti.meta_data_flags = arvif->tcl_metadata; 154e20cfa3bSKarthikeyan Periyasamy } 155d5c65159SKalle Valo 156bcef57eaSP Praneesh if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) { 157f4d291b4SSven Eckelmann if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) { 158d5c65159SKalle Valo ti.encrypt_type = 159f4d291b4SSven Eckelmann ath11k_dp_tx_get_encrypt_type(skb_cb->cipher); 160aa2092a9SVenkateswara Naralasetty 161aa2092a9SVenkateswara Naralasetty if (ieee80211_has_protected(hdr->frame_control)) 162aa2092a9SVenkateswara Naralasetty skb_put(skb, IEEE80211_CCMP_MIC_LEN); 163aa2092a9SVenkateswara Naralasetty } else { 164d5c65159SKalle Valo ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 165aa2092a9SVenkateswara Naralasetty } 166aa2092a9SVenkateswara Naralasetty } 167d5c65159SKalle Valo 168d5c65159SKalle Valo ti.addr_search_flags = arvif->hal_addr_search_flags; 169d5c65159SKalle Valo ti.search_type = arvif->search_type; 170d5c65159SKalle Valo ti.type = HAL_TCL_DESC_TYPE_BUFFER; 171d5c65159SKalle Valo ti.pkt_offset = 0; 172d5c65159SKalle Valo ti.lmac_id = ar->lmac_id; 173d5c65159SKalle Valo ti.bss_ast_hash = arvif->ast_hash; 1744b965be5SKarthikeyan Periyasamy ti.bss_ast_idx = arvif->ast_idx; 175d5c65159SKalle Valo ti.dscp_tid_tbl_idx = 0; 176d5c65159SKalle Valo 177bcef57eaSP Praneesh if (likely(skb->ip_summed == CHECKSUM_PARTIAL && 178bcef57eaSP Praneesh ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) { 179d5c65159SKalle Valo ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) | 180d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) | 181d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) | 182d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) | 183d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1); 184d5c65159SKalle Valo } 185d5c65159SKalle Valo 186d5c65159SKalle Valo if (ieee80211_vif_is_mesh(arvif->vif)) 1876fe6f68fSKarthikeyan Periyasamy ti.enable_mesh = true; 188d5c65159SKalle Valo 189d5c65159SKalle Valo ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1); 190d5c65159SKalle Valo 191d5c65159SKalle Valo ti.tid = ath11k_dp_tx_get_tid(skb); 192d5c65159SKalle Valo 193d5c65159SKalle Valo switch (ti.encap_type) { 194d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 195d5c65159SKalle Valo ath11k_dp_tx_encap_nwifi(skb); 196d5c65159SKalle Valo break; 197d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_RAW: 198aa2092a9SVenkateswara Naralasetty if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) { 199aa2092a9SVenkateswara Naralasetty ret = -EINVAL; 200aa2092a9SVenkateswara Naralasetty goto fail_remove_idr; 201aa2092a9SVenkateswara Naralasetty } 202aa2092a9SVenkateswara Naralasetty break; 203d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_ETHERNET: 204e7f33e0cSJohn Crispin /* no need to encap */ 205e7f33e0cSJohn Crispin break; 206d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_802_3: 207e7f33e0cSJohn Crispin default: 208d5c65159SKalle Valo /* TODO: Take care of other encap modes as well */ 209d5c65159SKalle Valo ret = -EINVAL; 2100dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 211d5c65159SKalle Valo goto fail_remove_idr; 212d5c65159SKalle Valo } 213d5c65159SKalle Valo 214d5c65159SKalle Valo ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 215bcef57eaSP Praneesh if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { 2160dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail); 217d5c65159SKalle Valo ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); 218d5c65159SKalle Valo ret = -ENOMEM; 219d5c65159SKalle Valo goto fail_remove_idr; 220d5c65159SKalle Valo } 221d5c65159SKalle Valo 222d5c65159SKalle Valo ti.data_len = skb->len; 223d5c65159SKalle Valo skb_cb->paddr = ti.paddr; 224d5c65159SKalle Valo skb_cb->vif = arvif->vif; 225d5c65159SKalle Valo skb_cb->ar = ar; 226d5c65159SKalle Valo 227d5c65159SKalle Valo hal_ring_id = tx_ring->tcl_data_ring.ring_id; 228d5c65159SKalle Valo tcl_ring = &ab->hal.srng_list[hal_ring_id]; 229d5c65159SKalle Valo 230d5c65159SKalle Valo spin_lock_bh(&tcl_ring->lock); 231d5c65159SKalle Valo 232d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, tcl_ring); 233d5c65159SKalle Valo 234d5c65159SKalle Valo hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring); 235bcef57eaSP Praneesh if (unlikely(!hal_tcl_desc)) { 236d5c65159SKalle Valo /* NOTE: It is highly unlikely we'll be running out of tcl_ring 237d5c65159SKalle Valo * desc because the desc is directly enqueued onto hw queue. 238d5c65159SKalle Valo */ 239d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring); 2400dd6392aSSriram R ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 241d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock); 242d5c65159SKalle Valo ret = -ENOMEM; 243d687275bSSriram R 244d687275bSSriram R /* Checking for available tcl descritors in another ring in 245d687275bSSriram R * case of failure due to full tcl ring now, is better than 246d687275bSSriram R * checking this ring earlier for each pkt tx. 247d687275bSSriram R * Restart ring selection if some rings are not checked yet. 248d687275bSSriram R */ 249bcef57eaSP Praneesh if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) && 25031582373SBaochen Qiang ab->hw_params.max_tx_ring > 1) { 251d687275bSSriram R tcl_ring_retry = true; 252d687275bSSriram R ring_selector++; 253d687275bSSriram R } 254d687275bSSriram R 255d5c65159SKalle Valo goto fail_unmap_dma; 256d5c65159SKalle Valo } 257d5c65159SKalle Valo 258d0998eb8SJohn Crispin ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc + 259d0998eb8SJohn Crispin sizeof(struct hal_tlv_hdr), &ti); 260d5c65159SKalle Valo 261d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring); 262d5c65159SKalle Valo 2638ec5a6abSCarl Huang ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]); 2648ec5a6abSCarl Huang 265d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock); 266d5c65159SKalle Valo 267aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ", 268aa2092a9SVenkateswara Naralasetty skb->data, skb->len); 269aa2092a9SVenkateswara Naralasetty 270d5c65159SKalle Valo atomic_inc(&ar->dp.num_tx_pending); 271d5c65159SKalle Valo 272d5c65159SKalle Valo return 0; 273d5c65159SKalle Valo 274d5c65159SKalle Valo fail_unmap_dma: 275d5c65159SKalle Valo dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 276d5c65159SKalle Valo 277d5c65159SKalle Valo fail_remove_idr: 278d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock); 279d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr, 280d5c65159SKalle Valo FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id)); 281d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock); 282d5c65159SKalle Valo 283d687275bSSriram R if (tcl_ring_retry) 284d687275bSSriram R goto tcl_ring_sel; 285d687275bSSriram R 286d5c65159SKalle Valo return ret; 287d5c65159SKalle Valo } 288d5c65159SKalle Valo 289d5c65159SKalle Valo static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id, 290d5c65159SKalle Valo int msdu_id, 291d5c65159SKalle Valo struct dp_tx_ring *tx_ring) 292d5c65159SKalle Valo { 293d5c65159SKalle Valo struct ath11k *ar; 294d5c65159SKalle Valo struct sk_buff *msdu; 295d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 296d5c65159SKalle Valo 297be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock); 298be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 299be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock); 300be8867cbSP Praneesh 301be8867cbSP Praneesh if (unlikely(!msdu)) { 302d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 303d5c65159SKalle Valo msdu_id); 304d5c65159SKalle Valo return; 305d5c65159SKalle Valo } 306d5c65159SKalle Valo 307d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 308d5c65159SKalle Valo 309d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 310d5c65159SKalle Valo dev_kfree_skb_any(msdu); 311d5c65159SKalle Valo 312d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 313d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 314d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 315d5c65159SKalle Valo } 316d5c65159SKalle Valo 317d5c65159SKalle Valo static void 318d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab, 319d5c65159SKalle Valo struct dp_tx_ring *tx_ring, 320d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status *ts) 321d5c65159SKalle Valo { 322d5c65159SKalle Valo struct sk_buff *msdu; 323d5c65159SKalle Valo struct ieee80211_tx_info *info; 324d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 325d5c65159SKalle Valo struct ath11k *ar; 326d5c65159SKalle Valo 327be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock); 328be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id); 329be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock); 330be8867cbSP Praneesh 331bcef57eaSP Praneesh if (unlikely(!msdu)) { 332d5c65159SKalle Valo ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n", 333d5c65159SKalle Valo ts->msdu_id); 334d5c65159SKalle Valo return; 335d5c65159SKalle Valo } 336d5c65159SKalle Valo 337d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 338d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu); 339d5c65159SKalle Valo 340d5c65159SKalle Valo ar = skb_cb->ar; 341d5c65159SKalle Valo 342d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 343d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 344d5c65159SKalle Valo 345d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 346d5c65159SKalle Valo 347d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status)); 348d5c65159SKalle Valo 349d5c65159SKalle Valo if (ts->acked) { 350d5c65159SKalle Valo if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 351d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK; 352d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 353d5c65159SKalle Valo ts->ack_rssi; 354d5c65159SKalle Valo info->status.is_valid_ack_signal = true; 355d5c65159SKalle Valo } else { 356d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 357d5c65159SKalle Valo } 358d5c65159SKalle Valo } 359d5c65159SKalle Valo 360d5c65159SKalle Valo ieee80211_tx_status(ar->hw, msdu); 361d5c65159SKalle Valo } 362d5c65159SKalle Valo 363d5c65159SKalle Valo static void 364d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab, 365d5c65159SKalle Valo void *desc, u8 mac_id, 366d5c65159SKalle Valo u32 msdu_id, struct dp_tx_ring *tx_ring) 367d5c65159SKalle Valo { 368d5c65159SKalle Valo struct htt_tx_wbm_completion *status_desc; 369d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status ts = {0}; 370d5c65159SKalle Valo enum hal_wbm_htt_tx_comp_status wbm_status; 371d5c65159SKalle Valo 372d5c65159SKalle Valo status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 373d5c65159SKalle Valo 374d5c65159SKalle Valo wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, 375d5c65159SKalle Valo status_desc->info0); 376d5c65159SKalle Valo switch (wbm_status) { 377d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 378d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 379d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 380d5c65159SKalle Valo ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 381d5c65159SKalle Valo ts.msdu_id = msdu_id; 382d5c65159SKalle Valo ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI, 383d5c65159SKalle Valo status_desc->info1); 384d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts); 385d5c65159SKalle Valo break; 386d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 387d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 388d5c65159SKalle Valo ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring); 389d5c65159SKalle Valo break; 390d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 391d5c65159SKalle Valo /* This event is to be handled only when the driver decides to 392d5c65159SKalle Valo * use WDS offload functionality. 393d5c65159SKalle Valo */ 394d5c65159SKalle Valo break; 395d5c65159SKalle Valo default: 396d5c65159SKalle Valo ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 397d5c65159SKalle Valo break; 398d5c65159SKalle Valo } 399d5c65159SKalle Valo } 400d5c65159SKalle Valo 401d5c65159SKalle Valo static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar, 402d5c65159SKalle Valo struct sk_buff *msdu, 403d5c65159SKalle Valo struct hal_tx_status *ts) 404d5c65159SKalle Valo { 405d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats; 406d5c65159SKalle Valo 407d5c65159SKalle Valo if (ts->try_cnt > 1) { 408d5c65159SKalle Valo peer_stats->retry_pkts += ts->try_cnt - 1; 409d5c65159SKalle Valo peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; 410d5c65159SKalle Valo 411d5c65159SKalle Valo if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { 412d5c65159SKalle Valo peer_stats->failed_pkts += 1; 413d5c65159SKalle Valo peer_stats->failed_bytes += msdu->len; 414d5c65159SKalle Valo } 415d5c65159SKalle Valo } 416d5c65159SKalle Valo } 417d5c65159SKalle Valo 418d5c65159SKalle Valo static void ath11k_dp_tx_complete_msdu(struct ath11k *ar, 419d5c65159SKalle Valo struct sk_buff *msdu, 420d5c65159SKalle Valo struct hal_tx_status *ts) 421d5c65159SKalle Valo { 422d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 423d5c65159SKalle Valo struct ieee80211_tx_info *info; 424d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb; 425d5c65159SKalle Valo 426d5c65159SKalle Valo if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 427d5c65159SKalle Valo /* Must not happen */ 428d5c65159SKalle Valo return; 429d5c65159SKalle Valo } 430d5c65159SKalle Valo 431d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu); 432d5c65159SKalle Valo 433d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 434d5c65159SKalle Valo 435bcef57eaSP Praneesh if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { 436d5c65159SKalle Valo dev_kfree_skb_any(msdu); 437bcef57eaSP Praneesh return; 438d5c65159SKalle Valo } 439d5c65159SKalle Valo 440bcef57eaSP Praneesh if (unlikely(!skb_cb->vif)) { 441d5c65159SKalle Valo dev_kfree_skb_any(msdu); 442bcef57eaSP Praneesh return; 443d5c65159SKalle Valo } 444d5c65159SKalle Valo 445d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu); 446d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status)); 447d5c65159SKalle Valo 448d5c65159SKalle Valo /* skip tx rate update from ieee80211_status*/ 449d5c65159SKalle Valo info->status.rates[0].idx = -1; 450d5c65159SKalle Valo 451d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 452d5c65159SKalle Valo !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 453d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK; 454d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR + 455d5c65159SKalle Valo ts->ack_rssi; 456d5c65159SKalle Valo info->status.is_valid_ack_signal = true; 457d5c65159SKalle Valo } 458d5c65159SKalle Valo 459d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 460d5c65159SKalle Valo (info->flags & IEEE80211_TX_CTL_NO_ACK)) 461d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 462d5c65159SKalle Valo 463bcef57eaSP Praneesh if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar))) { 464d5c65159SKalle Valo if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { 465d5c65159SKalle Valo if (ar->last_ppdu_id == 0) { 466d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id; 467d5c65159SKalle Valo } else if (ar->last_ppdu_id == ts->ppdu_id || 468d5c65159SKalle Valo ar->cached_ppdu_id == ar->last_ppdu_id) { 469d5c65159SKalle Valo ar->cached_ppdu_id = ar->last_ppdu_id; 470d5c65159SKalle Valo ar->cached_stats.is_ampdu = true; 471568f0603SKalle Valo ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 472d5c65159SKalle Valo memset(&ar->cached_stats, 0, 473d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats)); 474d5c65159SKalle Valo } else { 475d5c65159SKalle Valo ar->cached_stats.is_ampdu = false; 476568f0603SKalle Valo ath11k_debugfs_sta_update_txcompl(ar, msdu, ts); 477d5c65159SKalle Valo memset(&ar->cached_stats, 0, 478d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats)); 479d5c65159SKalle Valo } 480d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id; 481d5c65159SKalle Valo } 482d5c65159SKalle Valo 483d5c65159SKalle Valo ath11k_dp_tx_cache_peer_stats(ar, msdu, ts); 484d5c65159SKalle Valo } 485d5c65159SKalle Valo 486d5c65159SKalle Valo /* NOTE: Tx rate status reporting. Tx completion status does not have 487d5c65159SKalle Valo * necessary information (for example nss) to build the tx rate. 488d5c65159SKalle Valo * Might end up reporting it out-of-band from HTT stats. 489d5c65159SKalle Valo */ 490d5c65159SKalle Valo 491d5c65159SKalle Valo ieee80211_tx_status(ar->hw, msdu); 492d5c65159SKalle Valo } 493d5c65159SKalle Valo 4942ad578fdSJohn Crispin static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab, 4952ad578fdSJohn Crispin struct hal_wbm_release_ring *desc, 4962ad578fdSJohn Crispin struct hal_tx_status *ts) 4972ad578fdSJohn Crispin { 4982ad578fdSJohn Crispin ts->buf_rel_source = 4992ad578fdSJohn Crispin FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 500bcef57eaSP Praneesh if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 501bcef57eaSP Praneesh ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) 5022ad578fdSJohn Crispin return; 5032ad578fdSJohn Crispin 504bcef57eaSP Praneesh if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) 5052ad578fdSJohn Crispin return; 5062ad578fdSJohn Crispin 5072ad578fdSJohn Crispin ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 5082ad578fdSJohn Crispin desc->info0); 5092ad578fdSJohn Crispin ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 5102ad578fdSJohn Crispin desc->info1); 5112ad578fdSJohn Crispin ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 5122ad578fdSJohn Crispin desc->info1); 5132ad578fdSJohn Crispin ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 5142ad578fdSJohn Crispin desc->info2); 5152ad578fdSJohn Crispin if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 5162ad578fdSJohn Crispin ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 5172ad578fdSJohn Crispin ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 5182ad578fdSJohn Crispin ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 5192ad578fdSJohn Crispin if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) 5202ad578fdSJohn Crispin ts->rate_stats = desc->rate_stats.info0; 5212ad578fdSJohn Crispin else 5222ad578fdSJohn Crispin ts->rate_stats = 0; 5232ad578fdSJohn Crispin } 5242ad578fdSJohn Crispin 525d5c65159SKalle Valo void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id) 526d5c65159SKalle Valo { 527d5c65159SKalle Valo struct ath11k *ar; 528d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 529d5c65159SKalle Valo int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 530d5c65159SKalle Valo struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 531d5c65159SKalle Valo struct sk_buff *msdu; 532eefca584SColin Ian King struct hal_tx_status ts = { 0 }; 533d5c65159SKalle Valo struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 534d5c65159SKalle Valo u32 *desc; 535d5c65159SKalle Valo u32 msdu_id; 536d5c65159SKalle Valo u8 mac_id; 537d5c65159SKalle Valo 5382f588660SCarl Huang spin_lock_bh(&status_ring->lock); 5392f588660SCarl Huang 540d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, status_ring); 541d5c65159SKalle Valo 542d0998eb8SJohn Crispin while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) != 543d0998eb8SJohn Crispin tx_ring->tx_status_tail) && 544d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) { 545d0998eb8SJohn Crispin memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 546d0998eb8SJohn Crispin desc, sizeof(struct hal_wbm_release_ring)); 547d0998eb8SJohn Crispin tx_ring->tx_status_head = 548d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head); 549d5c65159SKalle Valo } 550d5c65159SKalle Valo 551bcef57eaSP Praneesh if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) && 552bcef57eaSP Praneesh (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) == 553bcef57eaSP Praneesh tx_ring->tx_status_tail))) { 554d5c65159SKalle Valo /* TODO: Process pending tx_status messages when kfifo_is_full() */ 555d5c65159SKalle Valo ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 556d5c65159SKalle Valo } 557d5c65159SKalle Valo 558d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, status_ring); 559d5c65159SKalle Valo 5602f588660SCarl Huang spin_unlock_bh(&status_ring->lock); 5612f588660SCarl Huang 562d0998eb8SJohn Crispin while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 563d0998eb8SJohn Crispin struct hal_wbm_release_ring *tx_status; 5642ad578fdSJohn Crispin u32 desc_id; 565d0998eb8SJohn Crispin 566d0998eb8SJohn Crispin tx_ring->tx_status_tail = 567d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 568d0998eb8SJohn Crispin tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 5692ad578fdSJohn Crispin ath11k_dp_tx_status_parse(ab, tx_status, &ts); 570d5c65159SKalle Valo 5712ad578fdSJohn Crispin desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 5722ad578fdSJohn Crispin tx_status->buf_addr_info.info1); 5732ad578fdSJohn Crispin mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id); 5742ad578fdSJohn Crispin msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id); 575d5c65159SKalle Valo 576bcef57eaSP Praneesh if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { 577d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(ab, 578d0998eb8SJohn Crispin (void *)tx_status, 579d5c65159SKalle Valo mac_id, msdu_id, 580d5c65159SKalle Valo tx_ring); 581d5c65159SKalle Valo continue; 582d5c65159SKalle Valo } 583d5c65159SKalle Valo 584be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock); 585be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id); 586bcef57eaSP Praneesh if (unlikely(!msdu)) { 587d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n", 588d5c65159SKalle Valo msdu_id); 589be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock); 590d5c65159SKalle Valo continue; 591d5c65159SKalle Valo } 592be8867cbSP Praneesh 593be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock); 594d5c65159SKalle Valo 595d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 596d5c65159SKalle Valo 597d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 598d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq); 599d5c65159SKalle Valo 600d5c65159SKalle Valo ath11k_dp_tx_complete_msdu(ar, msdu, &ts); 601d5c65159SKalle Valo } 602d5c65159SKalle Valo } 603d5c65159SKalle Valo 604d5c65159SKalle Valo int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid, 605d5c65159SKalle Valo enum hal_reo_cmd_type type, 606d5c65159SKalle Valo struct ath11k_hal_reo_cmd *cmd, 607d5c65159SKalle Valo void (*cb)(struct ath11k_dp *, void *, 608d5c65159SKalle Valo enum hal_reo_cmd_status)) 609d5c65159SKalle Valo { 610d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 611d5c65159SKalle Valo struct dp_reo_cmd *dp_cmd; 612d5c65159SKalle Valo struct hal_srng *cmd_ring; 613d5c65159SKalle Valo int cmd_num; 614d5c65159SKalle Valo 6158ee8d38cSSriram R if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 6168ee8d38cSSriram R return -ESHUTDOWN; 6178ee8d38cSSriram R 618d5c65159SKalle Valo cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 619d5c65159SKalle Valo cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 620d5c65159SKalle Valo 621e190bc05SGovindaraj Saminathan /* cmd_num should start from 1, during failure return the error code */ 622e190bc05SGovindaraj Saminathan if (cmd_num < 0) 623e190bc05SGovindaraj Saminathan return cmd_num; 624e190bc05SGovindaraj Saminathan 625d5c65159SKalle Valo /* reo cmd ring descriptors has cmd_num starting from 1 */ 626e190bc05SGovindaraj Saminathan if (cmd_num == 0) 627d5c65159SKalle Valo return -EINVAL; 628d5c65159SKalle Valo 629d5c65159SKalle Valo if (!cb) 630d5c65159SKalle Valo return 0; 631d5c65159SKalle Valo 632d5c65159SKalle Valo /* Can this be optimized so that we keep the pending command list only 633d5c65159SKalle Valo * for tid delete command to free up the resoruce on the command status 634d5c65159SKalle Valo * indication? 635d5c65159SKalle Valo */ 636d5c65159SKalle Valo dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 637d5c65159SKalle Valo 638d5c65159SKalle Valo if (!dp_cmd) 639d5c65159SKalle Valo return -ENOMEM; 640d5c65159SKalle Valo 641d5c65159SKalle Valo memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid)); 642d5c65159SKalle Valo dp_cmd->cmd_num = cmd_num; 643d5c65159SKalle Valo dp_cmd->handler = cb; 644d5c65159SKalle Valo 645d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 646d5c65159SKalle Valo list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 647d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 648d5c65159SKalle Valo 649d5c65159SKalle Valo return 0; 650d5c65159SKalle Valo } 651d5c65159SKalle Valo 652d5c65159SKalle Valo static int 653d5c65159SKalle Valo ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab, 654d5c65159SKalle Valo int mac_id, u32 ring_id, 655d5c65159SKalle Valo enum hal_ring_type ring_type, 656d5c65159SKalle Valo enum htt_srng_ring_type *htt_ring_type, 657d5c65159SKalle Valo enum htt_srng_ring_id *htt_ring_id) 658d5c65159SKalle Valo { 659d5c65159SKalle Valo int lmac_ring_id_offset = 0; 660d5c65159SKalle Valo int ret = 0; 661d5c65159SKalle Valo 662d5c65159SKalle Valo switch (ring_type) { 663d5c65159SKalle Valo case HAL_RXDMA_BUF: 664d5c65159SKalle Valo lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC; 6654152e420SCarl Huang 6664152e420SCarl Huang /* for QCA6390, host fills rx buffer to fw and fw fills to 6674152e420SCarl Huang * rxbuf ring for each rxdma 6684152e420SCarl Huang */ 6694152e420SCarl Huang if (!ab->hw_params.rx_mac_buf_ring) { 670d5c65159SKalle Valo if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF + 671d5c65159SKalle Valo lmac_ring_id_offset) || 672d5c65159SKalle Valo ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF + 673d5c65159SKalle Valo lmac_ring_id_offset))) { 674d5c65159SKalle Valo ret = -EINVAL; 675d5c65159SKalle Valo } 676d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 677d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 6784152e420SCarl Huang } else { 6794152e420SCarl Huang if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) { 6804152e420SCarl Huang *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 6814152e420SCarl Huang *htt_ring_type = HTT_SW_TO_SW_RING; 6824152e420SCarl Huang } else { 6834152e420SCarl Huang *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 6844152e420SCarl Huang *htt_ring_type = HTT_SW_TO_HW_RING; 6854152e420SCarl Huang } 6864152e420SCarl Huang } 687d5c65159SKalle Valo break; 688d5c65159SKalle Valo case HAL_RXDMA_DST: 689d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 690d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING; 691d5c65159SKalle Valo break; 692d5c65159SKalle Valo case HAL_RXDMA_MONITOR_BUF: 693d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 694d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 695d5c65159SKalle Valo break; 696d5c65159SKalle Valo case HAL_RXDMA_MONITOR_STATUS: 697d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 698d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 699d5c65159SKalle Valo break; 700d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DST: 701d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 702d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING; 703d5c65159SKalle Valo break; 704d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DESC: 705d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 706d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING; 707d5c65159SKalle Valo break; 708d5c65159SKalle Valo default: 709d5c65159SKalle Valo ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 710d5c65159SKalle Valo ret = -EINVAL; 711d5c65159SKalle Valo } 712d5c65159SKalle Valo return ret; 713d5c65159SKalle Valo } 714d5c65159SKalle Valo 715d5c65159SKalle Valo int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 716d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type) 717d5c65159SKalle Valo { 718d5c65159SKalle Valo struct htt_srng_setup_cmd *cmd; 719d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 720d5c65159SKalle Valo struct hal_srng_params params; 721d5c65159SKalle Valo struct sk_buff *skb; 722d5c65159SKalle Valo u32 ring_entry_sz; 723d5c65159SKalle Valo int len = sizeof(*cmd); 724d5c65159SKalle Valo dma_addr_t hp_addr, tp_addr; 725d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type; 726d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id; 7277195c874SDan Carpenter int ret; 728d5c65159SKalle Valo 729d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 730d5c65159SKalle Valo if (!skb) 731d5c65159SKalle Valo return -ENOMEM; 732d5c65159SKalle Valo 733d5c65159SKalle Valo memset(¶ms, 0, sizeof(params)); 734d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms); 735d5c65159SKalle Valo 736d5c65159SKalle Valo hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng); 737d5c65159SKalle Valo tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng); 738d5c65159SKalle Valo 7397195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 740d5c65159SKalle Valo ring_type, &htt_ring_type, 7417195c874SDan Carpenter &htt_ring_id); 7427195c874SDan Carpenter if (ret) 743d5c65159SKalle Valo goto err_free; 744d5c65159SKalle Valo 745d5c65159SKalle Valo skb_put(skb, len); 746d5c65159SKalle Valo cmd = (struct htt_srng_setup_cmd *)skb->data; 747d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE, 748d5c65159SKalle Valo HTT_H2T_MSG_TYPE_SRING_SETUP); 749d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING || 750d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING) 751d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 752d5c65159SKalle Valo DP_SW2HW_MACID(mac_id)); 753d5c65159SKalle Valo else 754d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID, 755d5c65159SKalle Valo mac_id); 756d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE, 757d5c65159SKalle Valo htt_ring_type); 758d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id); 759d5c65159SKalle Valo 760d5c65159SKalle Valo cmd->ring_base_addr_lo = params.ring_base_paddr & 761d5c65159SKalle Valo HAL_ADDR_LSB_REG_MASK; 762d5c65159SKalle Valo 763d5c65159SKalle Valo cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >> 764d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 765d5c65159SKalle Valo 766f7eb4b04SKalle Valo ret = ath11k_hal_srng_get_entrysize(ab, ring_type); 7677195c874SDan Carpenter if (ret < 0) 7684358bcb5SColin Ian King goto err_free; 769d5c65159SKalle Valo 770d5c65159SKalle Valo ring_entry_sz = ret; 771d5c65159SKalle Valo 772d5c65159SKalle Valo ring_entry_sz >>= 2; 773d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE, 774d5c65159SKalle Valo ring_entry_sz); 775d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE, 776d5c65159SKalle Valo params.num_entries * ring_entry_sz); 777d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP, 778d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 779d5c65159SKalle Valo cmd->info1 |= FIELD_PREP( 780d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP, 781d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 782d5c65159SKalle Valo cmd->info1 |= FIELD_PREP( 783d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP, 784d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP)); 785d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING) 786d5c65159SKalle Valo cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS; 787d5c65159SKalle Valo 788d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK; 789d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >> 790d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 791d5c65159SKalle Valo 792d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK; 793d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >> 794d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT; 795d5c65159SKalle Valo 7967dc67af0SKarthikeyan Periyasamy cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr); 7977dc67af0SKarthikeyan Periyasamy cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr); 798701e48a4SCarl Huang cmd->msi_data = params.msi_data; 799d5c65159SKalle Valo 800d5c65159SKalle Valo cmd->intr_info = FIELD_PREP( 801d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH, 802d5c65159SKalle Valo params.intr_batch_cntr_thres_entries * ring_entry_sz); 803d5c65159SKalle Valo cmd->intr_info |= FIELD_PREP( 804d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH, 805d5c65159SKalle Valo params.intr_timer_thres_us >> 3); 806d5c65159SKalle Valo 807d5c65159SKalle Valo cmd->info2 = 0; 808d5c65159SKalle Valo if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 809d5c65159SKalle Valo cmd->info2 = FIELD_PREP( 810d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH, 811d5c65159SKalle Valo params.low_threshold); 812d5c65159SKalle Valo } 813d5c65159SKalle Valo 814701e48a4SCarl Huang ath11k_dbg(ab, ATH11k_DBG_HAL, 815701e48a4SCarl Huang "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 816701e48a4SCarl Huang __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 817701e48a4SCarl Huang cmd->msi_data); 818701e48a4SCarl Huang 819701e48a4SCarl Huang ath11k_dbg(ab, ATH11k_DBG_HAL, 820701e48a4SCarl Huang "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 821701e48a4SCarl Huang ring_id, ring_type, cmd->intr_info, cmd->info2); 822701e48a4SCarl Huang 823d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 824d5c65159SKalle Valo if (ret) 825d5c65159SKalle Valo goto err_free; 826d5c65159SKalle Valo 827d5c65159SKalle Valo return 0; 828d5c65159SKalle Valo 829d5c65159SKalle Valo err_free: 830d5c65159SKalle Valo dev_kfree_skb_any(skb); 831d5c65159SKalle Valo 832d5c65159SKalle Valo return ret; 833d5c65159SKalle Valo } 834d5c65159SKalle Valo 835d5c65159SKalle Valo #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 836d5c65159SKalle Valo 837d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab) 838d5c65159SKalle Valo { 839d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 840d5c65159SKalle Valo struct sk_buff *skb; 841d5c65159SKalle Valo struct htt_ver_req_cmd *cmd; 842d5c65159SKalle Valo int len = sizeof(*cmd); 843d5c65159SKalle Valo int ret; 844d5c65159SKalle Valo 845d5c65159SKalle Valo init_completion(&dp->htt_tgt_version_received); 846d5c65159SKalle Valo 847d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 848d5c65159SKalle Valo if (!skb) 849d5c65159SKalle Valo return -ENOMEM; 850d5c65159SKalle Valo 851d5c65159SKalle Valo skb_put(skb, len); 852d5c65159SKalle Valo cmd = (struct htt_ver_req_cmd *)skb->data; 853d5c65159SKalle Valo cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID, 854d5c65159SKalle Valo HTT_H2T_MSG_TYPE_VERSION_REQ); 855d5c65159SKalle Valo 856d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 857d5c65159SKalle Valo if (ret) { 858d5c65159SKalle Valo dev_kfree_skb_any(skb); 859d5c65159SKalle Valo return ret; 860d5c65159SKalle Valo } 861d5c65159SKalle Valo 862d5c65159SKalle Valo ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 863d5c65159SKalle Valo HTT_TARGET_VERSION_TIMEOUT_HZ); 864d5c65159SKalle Valo if (ret == 0) { 865d5c65159SKalle Valo ath11k_warn(ab, "htt target version request timed out\n"); 866d5c65159SKalle Valo return -ETIMEDOUT; 867d5c65159SKalle Valo } 868d5c65159SKalle Valo 869d5c65159SKalle Valo if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 870d5c65159SKalle Valo ath11k_err(ab, "unsupported htt major version %d supported version is %d\n", 871d5c65159SKalle Valo dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 872d5c65159SKalle Valo return -ENOTSUPP; 873d5c65159SKalle Valo } 874d5c65159SKalle Valo 875d5c65159SKalle Valo return 0; 876d5c65159SKalle Valo } 877d5c65159SKalle Valo 878d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask) 879d5c65159SKalle Valo { 880d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 881d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 882d5c65159SKalle Valo struct sk_buff *skb; 883d5c65159SKalle Valo struct htt_ppdu_stats_cfg_cmd *cmd; 884d5c65159SKalle Valo int len = sizeof(*cmd); 885d5c65159SKalle Valo u8 pdev_mask; 886d5c65159SKalle Valo int ret; 887701e48a4SCarl Huang int i; 888d5c65159SKalle Valo 889701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 890d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 891d5c65159SKalle Valo if (!skb) 892d5c65159SKalle Valo return -ENOMEM; 893d5c65159SKalle Valo 894d5c65159SKalle Valo skb_put(skb, len); 895d5c65159SKalle Valo cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 896d5c65159SKalle Valo cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE, 897d5c65159SKalle Valo HTT_H2T_MSG_TYPE_PPDU_STATS_CFG); 898d5c65159SKalle Valo 89916a2c3d5SRameshkumar Sundaram pdev_mask = 1 << (ar->pdev_idx + i); 900d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask); 901d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask); 902d5c65159SKalle Valo 903d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 904d5c65159SKalle Valo if (ret) { 905d5c65159SKalle Valo dev_kfree_skb_any(skb); 906d5c65159SKalle Valo return ret; 907d5c65159SKalle Valo } 908701e48a4SCarl Huang } 909d5c65159SKalle Valo 910d5c65159SKalle Valo return 0; 911d5c65159SKalle Valo } 912d5c65159SKalle Valo 913d5c65159SKalle Valo int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id, 914d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type, 915d5c65159SKalle Valo int rx_buf_size, 916d5c65159SKalle Valo struct htt_rx_ring_tlv_filter *tlv_filter) 917d5c65159SKalle Valo { 918d5c65159SKalle Valo struct htt_rx_ring_selection_cfg_cmd *cmd; 919d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 920d5c65159SKalle Valo struct hal_srng_params params; 921d5c65159SKalle Valo struct sk_buff *skb; 922d5c65159SKalle Valo int len = sizeof(*cmd); 923d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type; 924d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id; 9257195c874SDan Carpenter int ret; 926d5c65159SKalle Valo 927d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 928d5c65159SKalle Valo if (!skb) 929d5c65159SKalle Valo return -ENOMEM; 930d5c65159SKalle Valo 931d5c65159SKalle Valo memset(¶ms, 0, sizeof(params)); 932d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms); 933d5c65159SKalle Valo 9347195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 935d5c65159SKalle Valo ring_type, &htt_ring_type, 9367195c874SDan Carpenter &htt_ring_id); 9377195c874SDan Carpenter if (ret) 938d5c65159SKalle Valo goto err_free; 939d5c65159SKalle Valo 940d5c65159SKalle Valo skb_put(skb, len); 941d5c65159SKalle Valo cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 942d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE, 943d5c65159SKalle Valo HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG); 944d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING || 945d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING) 946d5c65159SKalle Valo cmd->info0 |= 947d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 948d5c65159SKalle Valo DP_SW2HW_MACID(mac_id)); 949d5c65159SKalle Valo else 950d5c65159SKalle Valo cmd->info0 |= 951d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID, 952d5c65159SKalle Valo mac_id); 953d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID, 954d5c65159SKalle Valo htt_ring_id); 955d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS, 956d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP)); 957d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS, 958d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP)); 959d5c65159SKalle Valo 960d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE, 961d5c65159SKalle Valo rx_buf_size); 962d5c65159SKalle Valo cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0; 963d5c65159SKalle Valo cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1; 964d5c65159SKalle Valo cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2; 965d5c65159SKalle Valo cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3; 966d5c65159SKalle Valo cmd->rx_filter_tlv = tlv_filter->rx_filter; 967d5c65159SKalle Valo 968d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 969d5c65159SKalle Valo if (ret) 970d5c65159SKalle Valo goto err_free; 971d5c65159SKalle Valo 972d5c65159SKalle Valo return 0; 973d5c65159SKalle Valo 974d5c65159SKalle Valo err_free: 975d5c65159SKalle Valo dev_kfree_skb_any(skb); 976d5c65159SKalle Valo 977d5c65159SKalle Valo return ret; 978d5c65159SKalle Valo } 979d5c65159SKalle Valo 980d5c65159SKalle Valo int 981d5c65159SKalle Valo ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type, 982d5c65159SKalle Valo struct htt_ext_stats_cfg_params *cfg_params, 983d5c65159SKalle Valo u64 cookie) 984d5c65159SKalle Valo { 985d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 986d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 987d5c65159SKalle Valo struct sk_buff *skb; 988d5c65159SKalle Valo struct htt_ext_stats_cfg_cmd *cmd; 98913706340SWen Gong u32 pdev_id; 990d5c65159SKalle Valo int len = sizeof(*cmd); 991d5c65159SKalle Valo int ret; 992d5c65159SKalle Valo 993d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len); 994d5c65159SKalle Valo if (!skb) 995d5c65159SKalle Valo return -ENOMEM; 996d5c65159SKalle Valo 997d5c65159SKalle Valo skb_put(skb, len); 998d5c65159SKalle Valo 999d5c65159SKalle Valo cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 1000d5c65159SKalle Valo memset(cmd, 0, sizeof(*cmd)); 1001d5c65159SKalle Valo cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 1002d5c65159SKalle Valo 100313706340SWen Gong if (ab->hw_params.single_pdev_only) 100413706340SWen Gong pdev_id = ath11k_mac_get_target_pdev_id(ar); 100513706340SWen Gong else 100613706340SWen Gong pdev_id = ar->pdev->pdev_id; 100713706340SWen Gong 100813706340SWen Gong cmd->hdr.pdev_mask = 1 << pdev_id; 1009d5c65159SKalle Valo 1010d5c65159SKalle Valo cmd->hdr.stats_type = type; 1011d5c65159SKalle Valo cmd->cfg_param0 = cfg_params->cfg0; 1012d5c65159SKalle Valo cmd->cfg_param1 = cfg_params->cfg1; 1013d5c65159SKalle Valo cmd->cfg_param2 = cfg_params->cfg2; 1014d5c65159SKalle Valo cmd->cfg_param3 = cfg_params->cfg3; 1015d5c65159SKalle Valo cmd->cookie_lsb = lower_32_bits(cookie); 1016d5c65159SKalle Valo cmd->cookie_msb = upper_32_bits(cookie); 1017d5c65159SKalle Valo 1018d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb); 1019d5c65159SKalle Valo if (ret) { 1020d5c65159SKalle Valo ath11k_warn(ab, "failed to send htt type stats request: %d", 1021d5c65159SKalle Valo ret); 1022d5c65159SKalle Valo dev_kfree_skb_any(skb); 1023d5c65159SKalle Valo return ret; 1024d5c65159SKalle Valo } 1025d5c65159SKalle Valo 1026d5c65159SKalle Valo return 0; 1027d5c65159SKalle Valo } 1028d5c65159SKalle Valo 1029d5c65159SKalle Valo int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset) 1030d5c65159SKalle Valo { 1031d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 10324152e420SCarl Huang struct ath11k_base *ab = ar->ab; 1033d5c65159SKalle Valo struct htt_rx_ring_tlv_filter tlv_filter = {0}; 10344152e420SCarl Huang int ret = 0, ring_id = 0, i; 1035d5c65159SKalle Valo 1036*5c1f74d2SAnilkumar Kolli if (ab->hw_params.full_monitor_mode) { 1037*5c1f74d2SAnilkumar Kolli ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab, 1038*5c1f74d2SAnilkumar Kolli dp->mac_id, !reset); 1039*5c1f74d2SAnilkumar Kolli if (ret < 0) { 1040*5c1f74d2SAnilkumar Kolli ath11k_err(ab, "failed to setup full monitor %d\n", ret); 1041*5c1f74d2SAnilkumar Kolli return ret; 1042*5c1f74d2SAnilkumar Kolli } 1043*5c1f74d2SAnilkumar Kolli } 1044*5c1f74d2SAnilkumar Kolli 1045d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1046d5c65159SKalle Valo 1047d5c65159SKalle Valo if (!reset) { 1048d5c65159SKalle Valo tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1049d5c65159SKalle Valo tlv_filter.pkt_filter_flags0 = 1050d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1051d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1052d5c65159SKalle Valo tlv_filter.pkt_filter_flags1 = 1053d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1054d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1055d5c65159SKalle Valo tlv_filter.pkt_filter_flags2 = 1056d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1057d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1058d5c65159SKalle Valo tlv_filter.pkt_filter_flags3 = 1059d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1060d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1061d5c65159SKalle Valo HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1062d5c65159SKalle Valo HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1063d5c65159SKalle Valo } 1064d5c65159SKalle Valo 1065701e48a4SCarl Huang if (ab->hw_params.rxdma1_enable) { 1066d5c65159SKalle Valo ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id, 1067d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF, 1068d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE, 1069d5c65159SKalle Valo &tlv_filter); 1070701e48a4SCarl Huang } else if (!reset) { 1071701e48a4SCarl Huang /* set in monitor mode only */ 1072701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 1073701e48a4SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id; 1074701e48a4SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 1075701e48a4SCarl Huang dp->mac_id + i, 1076701e48a4SCarl Huang HAL_RXDMA_BUF, 1077701e48a4SCarl Huang 1024, 1078701e48a4SCarl Huang &tlv_filter); 1079701e48a4SCarl Huang } 1080701e48a4SCarl Huang } 1081701e48a4SCarl Huang 1082d5c65159SKalle Valo if (ret) 1083d5c65159SKalle Valo return ret; 1084d5c65159SKalle Valo 10854152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 10864152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 1087689a5e6fSSeevalamuthu Mariappan if (!reset) { 1088d5c65159SKalle Valo tlv_filter.rx_filter = 1089d5c65159SKalle Valo HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING; 1090689a5e6fSSeevalamuthu Mariappan } else { 1091d5c65159SKalle Valo tlv_filter = ath11k_mac_mon_status_filter_default; 1092d5c65159SKalle Valo 1093689a5e6fSSeevalamuthu Mariappan if (ath11k_debugfs_is_extd_rx_stats_enabled(ar)) 1094689a5e6fSSeevalamuthu Mariappan tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar); 1095689a5e6fSSeevalamuthu Mariappan } 1096689a5e6fSSeevalamuthu Mariappan 10974152e420SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id, 10984152e420SCarl Huang dp->mac_id + i, 1099d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS, 1100d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE, 1101d5c65159SKalle Valo &tlv_filter); 11024152e420SCarl Huang } 11034152e420SCarl Huang 1104701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 1105701e48a4SCarl Huang mod_timer(&ar->ab->mon_reap_timer, jiffies + 1106701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 1107701e48a4SCarl Huang 1108d5c65159SKalle Valo return ret; 1109d5c65159SKalle Valo } 1110*5c1f74d2SAnilkumar Kolli 1111*5c1f74d2SAnilkumar Kolli int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id, 1112*5c1f74d2SAnilkumar Kolli bool config) 1113*5c1f74d2SAnilkumar Kolli { 1114*5c1f74d2SAnilkumar Kolli struct htt_rx_full_monitor_mode_cfg_cmd *cmd; 1115*5c1f74d2SAnilkumar Kolli struct sk_buff *skb; 1116*5c1f74d2SAnilkumar Kolli int ret, len = sizeof(*cmd); 1117*5c1f74d2SAnilkumar Kolli 1118*5c1f74d2SAnilkumar Kolli skb = ath11k_htc_alloc_skb(ab, len); 1119*5c1f74d2SAnilkumar Kolli if (!skb) 1120*5c1f74d2SAnilkumar Kolli return -ENOMEM; 1121*5c1f74d2SAnilkumar Kolli 1122*5c1f74d2SAnilkumar Kolli skb_put(skb, len); 1123*5c1f74d2SAnilkumar Kolli cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data; 1124*5c1f74d2SAnilkumar Kolli memset(cmd, 0, sizeof(*cmd)); 1125*5c1f74d2SAnilkumar Kolli cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE, 1126*5c1f74d2SAnilkumar Kolli HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE); 1127*5c1f74d2SAnilkumar Kolli 1128*5c1f74d2SAnilkumar Kolli cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id); 1129*5c1f74d2SAnilkumar Kolli 1130*5c1f74d2SAnilkumar Kolli cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE | 1131*5c1f74d2SAnilkumar Kolli FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING, 1132*5c1f74d2SAnilkumar Kolli HTT_RX_MON_RING_SW); 1133*5c1f74d2SAnilkumar Kolli if (config) { 1134*5c1f74d2SAnilkumar Kolli cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END | 1135*5c1f74d2SAnilkumar Kolli HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END; 1136*5c1f74d2SAnilkumar Kolli } 1137*5c1f74d2SAnilkumar Kolli 1138*5c1f74d2SAnilkumar Kolli ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb); 1139*5c1f74d2SAnilkumar Kolli if (ret) 1140*5c1f74d2SAnilkumar Kolli goto err_free; 1141*5c1f74d2SAnilkumar Kolli 1142*5c1f74d2SAnilkumar Kolli return 0; 1143*5c1f74d2SAnilkumar Kolli 1144*5c1f74d2SAnilkumar Kolli err_free: 1145*5c1f74d2SAnilkumar Kolli dev_kfree_skb_any(skb); 1146*5c1f74d2SAnilkumar Kolli 1147*5c1f74d2SAnilkumar Kolli return ret; 1148*5c1f74d2SAnilkumar Kolli } 1149