1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear
2d5c65159SKalle Valo /*
3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
47636c9a6SManikanta Pubbisetty * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5d5c65159SKalle Valo */
6d5c65159SKalle Valo
7d5c65159SKalle Valo #include "core.h"
8d5c65159SKalle Valo #include "dp_tx.h"
9d5c65159SKalle Valo #include "debug.h"
10568f0603SKalle Valo #include "debugfs_sta.h"
11d5c65159SKalle Valo #include "hw.h"
126a0c3702SJohn Crispin #include "peer.h"
1313706340SWen Gong #include "mac.h"
14d5c65159SKalle Valo
15d5c65159SKalle Valo static enum hal_tcl_encap_type
ath11k_dp_tx_get_encap_type(struct ath11k_vif * arvif,struct sk_buff * skb)16d5c65159SKalle Valo ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
17d5c65159SKalle Valo {
18e7f33e0cSJohn Crispin struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
19aa2092a9SVenkateswara Naralasetty struct ath11k_base *ab = arvif->ar->ab;
20aa2092a9SVenkateswara Naralasetty
21aa2092a9SVenkateswara Naralasetty if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
22aa2092a9SVenkateswara Naralasetty return HAL_TCL_ENCAP_TYPE_RAW;
23e7f33e0cSJohn Crispin
24cc20ff2cSFelix Fietkau if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
25e7f33e0cSJohn Crispin return HAL_TCL_ENCAP_TYPE_ETHERNET;
26e7f33e0cSJohn Crispin
27d5c65159SKalle Valo return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
28d5c65159SKalle Valo }
29d5c65159SKalle Valo
ath11k_dp_tx_encap_nwifi(struct sk_buff * skb)30d5c65159SKalle Valo static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
31d5c65159SKalle Valo {
32d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data;
33d5c65159SKalle Valo u8 *qos_ctl;
34d5c65159SKalle Valo
35d5c65159SKalle Valo if (!ieee80211_is_data_qos(hdr->frame_control))
36d5c65159SKalle Valo return;
37d5c65159SKalle Valo
38d5c65159SKalle Valo qos_ctl = ieee80211_get_qos_ctl(hdr);
39d5c65159SKalle Valo memmove(skb->data + IEEE80211_QOS_CTL_LEN,
40d5c65159SKalle Valo skb->data, (void *)qos_ctl - (void *)skb->data);
41d5c65159SKalle Valo skb_pull(skb, IEEE80211_QOS_CTL_LEN);
42d5c65159SKalle Valo
43d5c65159SKalle Valo hdr = (void *)skb->data;
44d5c65159SKalle Valo hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
45d5c65159SKalle Valo }
46d5c65159SKalle Valo
ath11k_dp_tx_get_tid(struct sk_buff * skb)47d5c65159SKalle Valo static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
48d5c65159SKalle Valo {
49d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data;
50e7f33e0cSJohn Crispin struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb);
51d5c65159SKalle Valo
52e7f33e0cSJohn Crispin if (cb->flags & ATH11K_SKB_HW_80211_ENCAP)
53e7f33e0cSJohn Crispin return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
54e7f33e0cSJohn Crispin else if (!ieee80211_is_data_qos(hdr->frame_control))
55d5c65159SKalle Valo return HAL_DESC_REO_NON_QOS_TID;
56d5c65159SKalle Valo else
57d5c65159SKalle Valo return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
58d5c65159SKalle Valo }
59d5c65159SKalle Valo
ath11k_dp_tx_get_encrypt_type(u32 cipher)60acc79d98SSriram R enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
61d5c65159SKalle Valo {
62d5c65159SKalle Valo switch (cipher) {
63d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP40:
64d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_40;
65d5c65159SKalle Valo case WLAN_CIPHER_SUITE_WEP104:
66d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_WEP_104;
67d5c65159SKalle Valo case WLAN_CIPHER_SUITE_TKIP:
68d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_TKIP_MIC;
69d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP:
70d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_128;
71d5c65159SKalle Valo case WLAN_CIPHER_SUITE_CCMP_256:
72d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_CCMP_256;
73d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP:
74d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_GCMP_128;
75d5c65159SKalle Valo case WLAN_CIPHER_SUITE_GCMP_256:
76d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_AES_GCMP_256;
77d5c65159SKalle Valo default:
78d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN;
79d5c65159SKalle Valo }
80d5c65159SKalle Valo }
81d5c65159SKalle Valo
ath11k_dp_tx(struct ath11k * ar,struct ath11k_vif * arvif,struct ath11k_sta * arsta,struct sk_buff * skb)82d5c65159SKalle Valo int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
83e20cfa3bSKarthikeyan Periyasamy struct ath11k_sta *arsta, struct sk_buff *skb)
84d5c65159SKalle Valo {
85d5c65159SKalle Valo struct ath11k_base *ab = ar->ab;
86d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
87d5c65159SKalle Valo struct hal_tx_info ti = {0};
88d5c65159SKalle Valo struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
89d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
90d5c65159SKalle Valo struct hal_srng *tcl_ring;
91d5c65159SKalle Valo struct ieee80211_hdr *hdr = (void *)skb->data;
92d5c65159SKalle Valo struct dp_tx_ring *tx_ring;
93d5c65159SKalle Valo void *hal_tcl_desc;
94d5c65159SKalle Valo u8 pool_id;
95d5c65159SKalle Valo u8 hal_ring_id;
96d5c65159SKalle Valo int ret;
977636c9a6SManikanta Pubbisetty u32 ring_selector = 0;
987636c9a6SManikanta Pubbisetty u8 ring_map = 0;
99d687275bSSriram R bool tcl_ring_retry;
100d5c65159SKalle Valo
101bcef57eaSP Praneesh if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)))
102d5c65159SKalle Valo return -ESHUTDOWN;
103d5c65159SKalle Valo
104bcef57eaSP Praneesh if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
105bcef57eaSP Praneesh !ieee80211_is_data(hdr->frame_control)))
106d5c65159SKalle Valo return -ENOTSUPP;
107d5c65159SKalle Valo
108d5c65159SKalle Valo pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
109d687275bSSriram R
1107636c9a6SManikanta Pubbisetty ring_selector = ab->hw_params.hw_ops->get_ring_selector(skb);
111d687275bSSriram R
112d687275bSSriram R tcl_ring_sel:
113d687275bSSriram R tcl_ring_retry = false;
11431582373SBaochen Qiang
11531582373SBaochen Qiang ti.ring_id = ring_selector % ab->hw_params.max_tx_ring;
1167636c9a6SManikanta Pubbisetty ti.rbm_id = ab->hw_params.hal_params->tcl2wbm_rbm_map[ti.ring_id].rbm_id;
117065f5f68SCarl Huang
118d687275bSSriram R ring_map |= BIT(ti.ring_id);
119d5c65159SKalle Valo
120d5c65159SKalle Valo tx_ring = &dp->tx_ring[ti.ring_id];
121d5c65159SKalle Valo
122d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock);
123d5c65159SKalle Valo ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
124d5c65159SKalle Valo DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
125d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock);
126d5c65159SKalle Valo
127bcef57eaSP Praneesh if (unlikely(ret < 0)) {
1287636c9a6SManikanta Pubbisetty if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1) ||
1297636c9a6SManikanta Pubbisetty !ab->hw_params.tcl_ring_retry) {
1300dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail);
131d5c65159SKalle Valo return -ENOSPC;
1320dd6392aSSriram R }
133d5c65159SKalle Valo
134d687275bSSriram R /* Check if the next ring is available */
135d687275bSSriram R ring_selector++;
136d687275bSSriram R goto tcl_ring_sel;
137d687275bSSriram R }
138d687275bSSriram R
139d5c65159SKalle Valo ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
140d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
141d5c65159SKalle Valo FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
142d5c65159SKalle Valo ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
143e20cfa3bSKarthikeyan Periyasamy
144e20cfa3bSKarthikeyan Periyasamy if (ieee80211_has_a4(hdr->frame_control) &&
145e20cfa3bSKarthikeyan Periyasamy is_multicast_ether_addr(hdr->addr3) && arsta &&
146e20cfa3bSKarthikeyan Periyasamy arsta->use_4addr_set) {
147e20cfa3bSKarthikeyan Periyasamy ti.meta_data_flags = arsta->tcl_metadata;
148e20cfa3bSKarthikeyan Periyasamy ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1);
149e20cfa3bSKarthikeyan Periyasamy } else {
150d5c65159SKalle Valo ti.meta_data_flags = arvif->tcl_metadata;
151e20cfa3bSKarthikeyan Periyasamy }
152d5c65159SKalle Valo
153bcef57eaSP Praneesh if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) {
154f4d291b4SSven Eckelmann if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) {
155d5c65159SKalle Valo ti.encrypt_type =
156f4d291b4SSven Eckelmann ath11k_dp_tx_get_encrypt_type(skb_cb->cipher);
157aa2092a9SVenkateswara Naralasetty
158aa2092a9SVenkateswara Naralasetty if (ieee80211_has_protected(hdr->frame_control))
159aa2092a9SVenkateswara Naralasetty skb_put(skb, IEEE80211_CCMP_MIC_LEN);
160aa2092a9SVenkateswara Naralasetty } else {
161d5c65159SKalle Valo ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
162aa2092a9SVenkateswara Naralasetty }
163aa2092a9SVenkateswara Naralasetty }
164d5c65159SKalle Valo
165d5c65159SKalle Valo ti.addr_search_flags = arvif->hal_addr_search_flags;
166d5c65159SKalle Valo ti.search_type = arvif->search_type;
167d5c65159SKalle Valo ti.type = HAL_TCL_DESC_TYPE_BUFFER;
168d5c65159SKalle Valo ti.pkt_offset = 0;
169d5c65159SKalle Valo ti.lmac_id = ar->lmac_id;
170d5c65159SKalle Valo ti.bss_ast_hash = arvif->ast_hash;
1714b965be5SKarthikeyan Periyasamy ti.bss_ast_idx = arvif->ast_idx;
172d5c65159SKalle Valo ti.dscp_tid_tbl_idx = 0;
173d5c65159SKalle Valo
174bcef57eaSP Praneesh if (likely(skb->ip_summed == CHECKSUM_PARTIAL &&
175bcef57eaSP Praneesh ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) {
176d5c65159SKalle Valo ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
177d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
178d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
179d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
180d5c65159SKalle Valo FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
181d5c65159SKalle Valo }
182d5c65159SKalle Valo
183d5c65159SKalle Valo if (ieee80211_vif_is_mesh(arvif->vif))
1846fe6f68fSKarthikeyan Periyasamy ti.enable_mesh = true;
185d5c65159SKalle Valo
186d5c65159SKalle Valo ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
187d5c65159SKalle Valo
188d5c65159SKalle Valo ti.tid = ath11k_dp_tx_get_tid(skb);
189d5c65159SKalle Valo
190d5c65159SKalle Valo switch (ti.encap_type) {
191d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
192d5c65159SKalle Valo ath11k_dp_tx_encap_nwifi(skb);
193d5c65159SKalle Valo break;
194d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_RAW:
195aa2092a9SVenkateswara Naralasetty if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
196aa2092a9SVenkateswara Naralasetty ret = -EINVAL;
197aa2092a9SVenkateswara Naralasetty goto fail_remove_idr;
198aa2092a9SVenkateswara Naralasetty }
199aa2092a9SVenkateswara Naralasetty break;
200d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_ETHERNET:
201e7f33e0cSJohn Crispin /* no need to encap */
202e7f33e0cSJohn Crispin break;
203d5c65159SKalle Valo case HAL_TCL_ENCAP_TYPE_802_3:
204e7f33e0cSJohn Crispin default:
205d5c65159SKalle Valo /* TODO: Take care of other encap modes as well */
206d5c65159SKalle Valo ret = -EINVAL;
2070dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail);
208d5c65159SKalle Valo goto fail_remove_idr;
209d5c65159SKalle Valo }
210d5c65159SKalle Valo
211d5c65159SKalle Valo ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
212bcef57eaSP Praneesh if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) {
2130dd6392aSSriram R atomic_inc(&ab->soc_stats.tx_err.misc_fail);
214d5c65159SKalle Valo ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
215d5c65159SKalle Valo ret = -ENOMEM;
216d5c65159SKalle Valo goto fail_remove_idr;
217d5c65159SKalle Valo }
218d5c65159SKalle Valo
219d5c65159SKalle Valo ti.data_len = skb->len;
220d5c65159SKalle Valo skb_cb->paddr = ti.paddr;
221d5c65159SKalle Valo skb_cb->vif = arvif->vif;
222d5c65159SKalle Valo skb_cb->ar = ar;
223d5c65159SKalle Valo
224d5c65159SKalle Valo hal_ring_id = tx_ring->tcl_data_ring.ring_id;
225d5c65159SKalle Valo tcl_ring = &ab->hal.srng_list[hal_ring_id];
226d5c65159SKalle Valo
227d5c65159SKalle Valo spin_lock_bh(&tcl_ring->lock);
228d5c65159SKalle Valo
229d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, tcl_ring);
230d5c65159SKalle Valo
231d5c65159SKalle Valo hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
232bcef57eaSP Praneesh if (unlikely(!hal_tcl_desc)) {
233d5c65159SKalle Valo /* NOTE: It is highly unlikely we'll be running out of tcl_ring
234d5c65159SKalle Valo * desc because the desc is directly enqueued onto hw queue.
235d5c65159SKalle Valo */
236d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring);
2370dd6392aSSriram R ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
238d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock);
239d5c65159SKalle Valo ret = -ENOMEM;
240d687275bSSriram R
241*d68a283bSJeff Johnson /* Checking for available tcl descriptors in another ring in
242d687275bSSriram R * case of failure due to full tcl ring now, is better than
243d687275bSSriram R * checking this ring earlier for each pkt tx.
244d687275bSSriram R * Restart ring selection if some rings are not checked yet.
245d687275bSSriram R */
246bcef57eaSP Praneesh if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) &&
2477636c9a6SManikanta Pubbisetty ab->hw_params.tcl_ring_retry && ab->hw_params.max_tx_ring > 1) {
248d687275bSSriram R tcl_ring_retry = true;
249d687275bSSriram R ring_selector++;
250d687275bSSriram R }
251d687275bSSriram R
252d5c65159SKalle Valo goto fail_unmap_dma;
253d5c65159SKalle Valo }
254d5c65159SKalle Valo
255d0998eb8SJohn Crispin ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
256d0998eb8SJohn Crispin sizeof(struct hal_tlv_hdr), &ti);
257d5c65159SKalle Valo
258d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, tcl_ring);
259d5c65159SKalle Valo
2608ec5a6abSCarl Huang ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]);
2618ec5a6abSCarl Huang
262d5c65159SKalle Valo spin_unlock_bh(&tcl_ring->lock);
263d5c65159SKalle Valo
264aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ",
265aa2092a9SVenkateswara Naralasetty skb->data, skb->len);
266aa2092a9SVenkateswara Naralasetty
267d5c65159SKalle Valo atomic_inc(&ar->dp.num_tx_pending);
268d5c65159SKalle Valo
269d5c65159SKalle Valo return 0;
270d5c65159SKalle Valo
271d5c65159SKalle Valo fail_unmap_dma:
272d5c65159SKalle Valo dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
273d5c65159SKalle Valo
274d5c65159SKalle Valo fail_remove_idr:
275d5c65159SKalle Valo spin_lock_bh(&tx_ring->tx_idr_lock);
276d5c65159SKalle Valo idr_remove(&tx_ring->txbuf_idr,
277d5c65159SKalle Valo FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
278d5c65159SKalle Valo spin_unlock_bh(&tx_ring->tx_idr_lock);
279d5c65159SKalle Valo
280d687275bSSriram R if (tcl_ring_retry)
281d687275bSSriram R goto tcl_ring_sel;
282d687275bSSriram R
283d5c65159SKalle Valo return ret;
284d5c65159SKalle Valo }
285d5c65159SKalle Valo
ath11k_dp_tx_free_txbuf(struct ath11k_base * ab,u8 mac_id,int msdu_id,struct dp_tx_ring * tx_ring)286d5c65159SKalle Valo static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
287d5c65159SKalle Valo int msdu_id,
288d5c65159SKalle Valo struct dp_tx_ring *tx_ring)
289d5c65159SKalle Valo {
290d5c65159SKalle Valo struct ath11k *ar;
291d5c65159SKalle Valo struct sk_buff *msdu;
292d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb;
293d5c65159SKalle Valo
294be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock);
295be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
296be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock);
297be8867cbSP Praneesh
298be8867cbSP Praneesh if (unlikely(!msdu)) {
299d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
300d5c65159SKalle Valo msdu_id);
301d5c65159SKalle Valo return;
302d5c65159SKalle Valo }
303d5c65159SKalle Valo
304d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu);
305d5c65159SKalle Valo
306d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
307d5c65159SKalle Valo dev_kfree_skb_any(msdu);
308d5c65159SKalle Valo
309d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar;
310d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending))
311d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq);
312d5c65159SKalle Valo }
313d5c65159SKalle Valo
314d5c65159SKalle Valo static void
ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base * ab,struct dp_tx_ring * tx_ring,struct ath11k_dp_htt_wbm_tx_status * ts)315d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
316d5c65159SKalle Valo struct dp_tx_ring *tx_ring,
317d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status *ts)
318d5c65159SKalle Valo {
3196257c702SPradeep Kumar Chitrapu struct ieee80211_tx_status status = { 0 };
320d5c65159SKalle Valo struct sk_buff *msdu;
321d5c65159SKalle Valo struct ieee80211_tx_info *info;
322d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb;
323d5c65159SKalle Valo struct ath11k *ar;
3246257c702SPradeep Kumar Chitrapu struct ath11k_peer *peer;
325d5c65159SKalle Valo
326be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock);
327be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
328be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock);
329be8867cbSP Praneesh
330bcef57eaSP Praneesh if (unlikely(!msdu)) {
331d5c65159SKalle Valo ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
332d5c65159SKalle Valo ts->msdu_id);
333d5c65159SKalle Valo return;
334d5c65159SKalle Valo }
335d5c65159SKalle Valo
336d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu);
337d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu);
338d5c65159SKalle Valo
339d5c65159SKalle Valo ar = skb_cb->ar;
340d5c65159SKalle Valo
341d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending))
342d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq);
343d5c65159SKalle Valo
344d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
345d5c65159SKalle Valo
3466257c702SPradeep Kumar Chitrapu if (!skb_cb->vif) {
34729d15589SSven Eckelmann ieee80211_free_txskb(ar->hw, msdu);
3486257c702SPradeep Kumar Chitrapu return;
3496257c702SPradeep Kumar Chitrapu }
3506257c702SPradeep Kumar Chitrapu
351d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status));
352d5c65159SKalle Valo
353d5c65159SKalle Valo if (ts->acked) {
354d5c65159SKalle Valo if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
355d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK;
356d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
357d5c65159SKalle Valo ts->ack_rssi;
358ea5907dbSAvraham Stern info->status.flags |=
359ea5907dbSAvraham Stern IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
360d5c65159SKalle Valo } else {
361d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
362d5c65159SKalle Valo }
363d5c65159SKalle Valo }
364d5c65159SKalle Valo
3656257c702SPradeep Kumar Chitrapu spin_lock_bh(&ab->base_lock);
3666257c702SPradeep Kumar Chitrapu peer = ath11k_peer_find_by_id(ab, ts->peer_id);
3676257c702SPradeep Kumar Chitrapu if (!peer || !peer->sta) {
3686257c702SPradeep Kumar Chitrapu ath11k_dbg(ab, ATH11K_DBG_DATA,
3696257c702SPradeep Kumar Chitrapu "dp_tx: failed to find the peer with peer_id %d\n",
3706257c702SPradeep Kumar Chitrapu ts->peer_id);
3716257c702SPradeep Kumar Chitrapu spin_unlock_bh(&ab->base_lock);
372400ece6cSSven Eckelmann ieee80211_free_txskb(ar->hw, msdu);
3736257c702SPradeep Kumar Chitrapu return;
3746257c702SPradeep Kumar Chitrapu }
3756257c702SPradeep Kumar Chitrapu spin_unlock_bh(&ab->base_lock);
3766257c702SPradeep Kumar Chitrapu
3776257c702SPradeep Kumar Chitrapu status.sta = peer->sta;
3786257c702SPradeep Kumar Chitrapu status.info = info;
3796257c702SPradeep Kumar Chitrapu status.skb = msdu;
3806257c702SPradeep Kumar Chitrapu
3816257c702SPradeep Kumar Chitrapu ieee80211_tx_status_ext(ar->hw, &status);
382d5c65159SKalle Valo }
383d5c65159SKalle Valo
384d5c65159SKalle Valo static void
ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base * ab,void * desc,u8 mac_id,u32 msdu_id,struct dp_tx_ring * tx_ring)385d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
386d5c65159SKalle Valo void *desc, u8 mac_id,
387d5c65159SKalle Valo u32 msdu_id, struct dp_tx_ring *tx_ring)
388d5c65159SKalle Valo {
389d5c65159SKalle Valo struct htt_tx_wbm_completion *status_desc;
390d5c65159SKalle Valo struct ath11k_dp_htt_wbm_tx_status ts = {0};
391d5c65159SKalle Valo enum hal_wbm_htt_tx_comp_status wbm_status;
392d5c65159SKalle Valo
393d5c65159SKalle Valo status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
394d5c65159SKalle Valo
395d5c65159SKalle Valo wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
396d5c65159SKalle Valo status_desc->info0);
397d5c65159SKalle Valo switch (wbm_status) {
398d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
399d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
400d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
401d5c65159SKalle Valo ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
402d5c65159SKalle Valo ts.msdu_id = msdu_id;
403d5c65159SKalle Valo ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
404d5c65159SKalle Valo status_desc->info1);
4056257c702SPradeep Kumar Chitrapu
4066257c702SPradeep Kumar Chitrapu if (FIELD_GET(HTT_TX_WBM_COMP_INFO2_VALID, status_desc->info2))
4076257c702SPradeep Kumar Chitrapu ts.peer_id = FIELD_GET(HTT_TX_WBM_COMP_INFO2_SW_PEER_ID,
4086257c702SPradeep Kumar Chitrapu status_desc->info2);
4096257c702SPradeep Kumar Chitrapu else
4106257c702SPradeep Kumar Chitrapu ts.peer_id = HTT_INVALID_PEER_ID;
4116257c702SPradeep Kumar Chitrapu
412d5c65159SKalle Valo ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
4136257c702SPradeep Kumar Chitrapu
414d5c65159SKalle Valo break;
415d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
416d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
417d5c65159SKalle Valo ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
418d5c65159SKalle Valo break;
419d5c65159SKalle Valo case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
420d5c65159SKalle Valo /* This event is to be handled only when the driver decides to
421d5c65159SKalle Valo * use WDS offload functionality.
422d5c65159SKalle Valo */
423d5c65159SKalle Valo break;
424d5c65159SKalle Valo default:
425d5c65159SKalle Valo ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
426d5c65159SKalle Valo break;
427d5c65159SKalle Valo }
428d5c65159SKalle Valo }
429d5c65159SKalle Valo
ath11k_dp_tx_cache_peer_stats(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)430d5c65159SKalle Valo static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
431d5c65159SKalle Valo struct sk_buff *msdu,
432d5c65159SKalle Valo struct hal_tx_status *ts)
433d5c65159SKalle Valo {
434d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
435d5c65159SKalle Valo
436d5c65159SKalle Valo if (ts->try_cnt > 1) {
437d5c65159SKalle Valo peer_stats->retry_pkts += ts->try_cnt - 1;
438d5c65159SKalle Valo peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
439d5c65159SKalle Valo
440d5c65159SKalle Valo if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
441d5c65159SKalle Valo peer_stats->failed_pkts += 1;
442d5c65159SKalle Valo peer_stats->failed_bytes += msdu->len;
443d5c65159SKalle Valo }
444d5c65159SKalle Valo }
445d5c65159SKalle Valo }
446d5c65159SKalle Valo
ath11k_dp_tx_update_txcompl(struct ath11k * ar,struct hal_tx_status * ts)4471b8bb94cSWen Gong void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts)
4481b8bb94cSWen Gong {
4491b8bb94cSWen Gong struct ath11k_base *ab = ar->ab;
4501b8bb94cSWen Gong struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
4511b8bb94cSWen Gong enum hal_tx_rate_stats_pkt_type pkt_type;
4521b8bb94cSWen Gong enum hal_tx_rate_stats_sgi sgi;
4531b8bb94cSWen Gong enum hal_tx_rate_stats_bw bw;
4541b8bb94cSWen Gong struct ath11k_peer *peer;
4551b8bb94cSWen Gong struct ath11k_sta *arsta;
4561b8bb94cSWen Gong struct ieee80211_sta *sta;
4571b8bb94cSWen Gong u16 rate, ru_tones;
4588c4c567fSWen Gong u8 mcs, rate_idx = 0, ofdma;
4591b8bb94cSWen Gong int ret;
4601b8bb94cSWen Gong
4611b8bb94cSWen Gong spin_lock_bh(&ab->base_lock);
4621b8bb94cSWen Gong peer = ath11k_peer_find_by_id(ab, ts->peer_id);
4631b8bb94cSWen Gong if (!peer || !peer->sta) {
4641b8bb94cSWen Gong ath11k_dbg(ab, ATH11K_DBG_DP_TX,
4651b8bb94cSWen Gong "failed to find the peer by id %u\n", ts->peer_id);
4661b8bb94cSWen Gong goto err_out;
4671b8bb94cSWen Gong }
4681b8bb94cSWen Gong
4691b8bb94cSWen Gong sta = peer->sta;
4701b8bb94cSWen Gong arsta = (struct ath11k_sta *)sta->drv_priv;
4711b8bb94cSWen Gong
4721b8bb94cSWen Gong memset(&arsta->txrate, 0, sizeof(arsta->txrate));
4731b8bb94cSWen Gong pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE,
4741b8bb94cSWen Gong ts->rate_stats);
4751b8bb94cSWen Gong mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS,
4761b8bb94cSWen Gong ts->rate_stats);
4771b8bb94cSWen Gong sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI,
4781b8bb94cSWen Gong ts->rate_stats);
4791b8bb94cSWen Gong bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats);
4801b8bb94cSWen Gong ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats);
4811b8bb94cSWen Gong ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats);
4821b8bb94cSWen Gong
4831b8bb94cSWen Gong /* This is to prefer choose the real NSS value arsta->last_txrate.nss,
4841b8bb94cSWen Gong * if it is invalid, then choose the NSS value while assoc.
4851b8bb94cSWen Gong */
4861b8bb94cSWen Gong if (arsta->last_txrate.nss)
4871b8bb94cSWen Gong arsta->txrate.nss = arsta->last_txrate.nss;
4881b8bb94cSWen Gong else
4891b8bb94cSWen Gong arsta->txrate.nss = arsta->peer_nss;
4901b8bb94cSWen Gong
4911b8bb94cSWen Gong if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A ||
4921b8bb94cSWen Gong pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) {
4931b8bb94cSWen Gong ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
4941b8bb94cSWen Gong pkt_type,
4951b8bb94cSWen Gong &rate_idx,
4961b8bb94cSWen Gong &rate);
4971b8bb94cSWen Gong if (ret < 0)
4981b8bb94cSWen Gong goto err_out;
4991b8bb94cSWen Gong arsta->txrate.legacy = rate;
5001b8bb94cSWen Gong } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) {
5011b8bb94cSWen Gong if (mcs > 7) {
5021b8bb94cSWen Gong ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs);
5031b8bb94cSWen Gong goto err_out;
5041b8bb94cSWen Gong }
5051b8bb94cSWen Gong
5061b8bb94cSWen Gong if (arsta->txrate.nss != 0)
5071b8bb94cSWen Gong arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1);
5081b8bb94cSWen Gong arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
5091b8bb94cSWen Gong if (sgi)
5101b8bb94cSWen Gong arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
5111b8bb94cSWen Gong } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) {
5121b8bb94cSWen Gong if (mcs > 9) {
5131b8bb94cSWen Gong ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs);
5141b8bb94cSWen Gong goto err_out;
5151b8bb94cSWen Gong }
5161b8bb94cSWen Gong
5171b8bb94cSWen Gong arsta->txrate.mcs = mcs;
5181b8bb94cSWen Gong arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
5191b8bb94cSWen Gong if (sgi)
5201b8bb94cSWen Gong arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
5211b8bb94cSWen Gong } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
5221b8bb94cSWen Gong if (mcs > 11) {
5231b8bb94cSWen Gong ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs);
5241b8bb94cSWen Gong goto err_out;
5251b8bb94cSWen Gong }
5261b8bb94cSWen Gong
5271b8bb94cSWen Gong arsta->txrate.mcs = mcs;
5281b8bb94cSWen Gong arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
5291b8bb94cSWen Gong arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
5301b8bb94cSWen Gong }
5311b8bb94cSWen Gong
5321b8bb94cSWen Gong arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
5331b8bb94cSWen Gong if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
5341b8bb94cSWen Gong arsta->txrate.bw = RATE_INFO_BW_HE_RU;
5351b8bb94cSWen Gong arsta->txrate.he_ru_alloc =
5361b8bb94cSWen Gong ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
5371b8bb94cSWen Gong }
5381b8bb94cSWen Gong
5391b8bb94cSWen Gong if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
5401b8bb94cSWen Gong ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
5411b8bb94cSWen Gong
5421b8bb94cSWen Gong err_out:
5431b8bb94cSWen Gong spin_unlock_bh(&ab->base_lock);
5441b8bb94cSWen Gong }
5451b8bb94cSWen Gong
ath11k_dp_tx_complete_msdu(struct ath11k * ar,struct sk_buff * msdu,struct hal_tx_status * ts)546d5c65159SKalle Valo static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
547d5c65159SKalle Valo struct sk_buff *msdu,
548d5c65159SKalle Valo struct hal_tx_status *ts)
549d5c65159SKalle Valo {
55094739d45SPradeep Kumar Chitrapu struct ieee80211_tx_status status = { 0 };
55144fa75f2SJonas Jelonek struct ieee80211_rate_status status_rate = { 0 };
552d5c65159SKalle Valo struct ath11k_base *ab = ar->ab;
553d5c65159SKalle Valo struct ieee80211_tx_info *info;
554d5c65159SKalle Valo struct ath11k_skb_cb *skb_cb;
55594739d45SPradeep Kumar Chitrapu struct ath11k_peer *peer;
55694739d45SPradeep Kumar Chitrapu struct ath11k_sta *arsta;
55794739d45SPradeep Kumar Chitrapu struct rate_info rate;
558d5c65159SKalle Valo
559d5c65159SKalle Valo if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
560d5c65159SKalle Valo /* Must not happen */
561d5c65159SKalle Valo return;
562d5c65159SKalle Valo }
563d5c65159SKalle Valo
564d5c65159SKalle Valo skb_cb = ATH11K_SKB_CB(msdu);
565d5c65159SKalle Valo
566d5c65159SKalle Valo dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
567d5c65159SKalle Valo
568bcef57eaSP Praneesh if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) {
56929d15589SSven Eckelmann ieee80211_free_txskb(ar->hw, msdu);
570bcef57eaSP Praneesh return;
571d5c65159SKalle Valo }
572d5c65159SKalle Valo
573bcef57eaSP Praneesh if (unlikely(!skb_cb->vif)) {
57429d15589SSven Eckelmann ieee80211_free_txskb(ar->hw, msdu);
575bcef57eaSP Praneesh return;
576d5c65159SKalle Valo }
577d5c65159SKalle Valo
578d5c65159SKalle Valo info = IEEE80211_SKB_CB(msdu);
579d5c65159SKalle Valo memset(&info->status, 0, sizeof(info->status));
580d5c65159SKalle Valo
581d5c65159SKalle Valo /* skip tx rate update from ieee80211_status*/
582d5c65159SKalle Valo info->status.rates[0].idx = -1;
583d5c65159SKalle Valo
584d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
585d5c65159SKalle Valo !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
586d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_ACK;
587d5c65159SKalle Valo info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
588d5c65159SKalle Valo ts->ack_rssi;
589ea5907dbSAvraham Stern info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
590d5c65159SKalle Valo }
591d5c65159SKalle Valo
592d5c65159SKalle Valo if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
593d5c65159SKalle Valo (info->flags & IEEE80211_TX_CTL_NO_ACK))
594d5c65159SKalle Valo info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
595d5c65159SKalle Valo
5961b8bb94cSWen Gong if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) ||
5971b8bb94cSWen Gong ab->hw_params.single_pdev_only) {
598d5c65159SKalle Valo if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
599d5c65159SKalle Valo if (ar->last_ppdu_id == 0) {
600d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id;
601d5c65159SKalle Valo } else if (ar->last_ppdu_id == ts->ppdu_id ||
602d5c65159SKalle Valo ar->cached_ppdu_id == ar->last_ppdu_id) {
603d5c65159SKalle Valo ar->cached_ppdu_id = ar->last_ppdu_id;
604d5c65159SKalle Valo ar->cached_stats.is_ampdu = true;
6051b8bb94cSWen Gong ath11k_dp_tx_update_txcompl(ar, ts);
606d5c65159SKalle Valo memset(&ar->cached_stats, 0,
607d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats));
608d5c65159SKalle Valo } else {
609d5c65159SKalle Valo ar->cached_stats.is_ampdu = false;
6101b8bb94cSWen Gong ath11k_dp_tx_update_txcompl(ar, ts);
611d5c65159SKalle Valo memset(&ar->cached_stats, 0,
612d5c65159SKalle Valo sizeof(struct ath11k_per_peer_tx_stats));
613d5c65159SKalle Valo }
614d5c65159SKalle Valo ar->last_ppdu_id = ts->ppdu_id;
615d5c65159SKalle Valo }
616d5c65159SKalle Valo
617d5c65159SKalle Valo ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
618d5c65159SKalle Valo }
619d5c65159SKalle Valo
62094739d45SPradeep Kumar Chitrapu spin_lock_bh(&ab->base_lock);
62194739d45SPradeep Kumar Chitrapu peer = ath11k_peer_find_by_id(ab, ts->peer_id);
62294739d45SPradeep Kumar Chitrapu if (!peer || !peer->sta) {
62394739d45SPradeep Kumar Chitrapu ath11k_dbg(ab, ATH11K_DBG_DATA,
62494739d45SPradeep Kumar Chitrapu "dp_tx: failed to find the peer with peer_id %d\n",
62594739d45SPradeep Kumar Chitrapu ts->peer_id);
62694739d45SPradeep Kumar Chitrapu spin_unlock_bh(&ab->base_lock);
627400ece6cSSven Eckelmann ieee80211_free_txskb(ar->hw, msdu);
62894739d45SPradeep Kumar Chitrapu return;
62994739d45SPradeep Kumar Chitrapu }
63094739d45SPradeep Kumar Chitrapu arsta = (struct ath11k_sta *)peer->sta->drv_priv;
63194739d45SPradeep Kumar Chitrapu status.sta = peer->sta;
63294739d45SPradeep Kumar Chitrapu status.skb = msdu;
63394739d45SPradeep Kumar Chitrapu status.info = info;
63494739d45SPradeep Kumar Chitrapu rate = arsta->last_txrate;
63544fa75f2SJonas Jelonek
63644fa75f2SJonas Jelonek status_rate.rate_idx = rate;
63744fa75f2SJonas Jelonek status_rate.try_count = 1;
63844fa75f2SJonas Jelonek
63944fa75f2SJonas Jelonek status.rates = &status_rate;
64044fa75f2SJonas Jelonek status.n_rates = 1;
641d5c65159SKalle Valo
64294739d45SPradeep Kumar Chitrapu spin_unlock_bh(&ab->base_lock);
64394739d45SPradeep Kumar Chitrapu
64494739d45SPradeep Kumar Chitrapu ieee80211_tx_status_ext(ar->hw, &status);
645d5c65159SKalle Valo }
646d5c65159SKalle Valo
ath11k_dp_tx_status_parse(struct ath11k_base * ab,struct hal_wbm_release_ring * desc,struct hal_tx_status * ts)6472ad578fdSJohn Crispin static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
6482ad578fdSJohn Crispin struct hal_wbm_release_ring *desc,
6492ad578fdSJohn Crispin struct hal_tx_status *ts)
6502ad578fdSJohn Crispin {
6512ad578fdSJohn Crispin ts->buf_rel_source =
6522ad578fdSJohn Crispin FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
653bcef57eaSP Praneesh if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
654bcef57eaSP Praneesh ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM))
6552ad578fdSJohn Crispin return;
6562ad578fdSJohn Crispin
657bcef57eaSP Praneesh if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW))
6582ad578fdSJohn Crispin return;
6592ad578fdSJohn Crispin
6602ad578fdSJohn Crispin ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
6612ad578fdSJohn Crispin desc->info0);
6622ad578fdSJohn Crispin ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
6632ad578fdSJohn Crispin desc->info1);
6642ad578fdSJohn Crispin ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
6652ad578fdSJohn Crispin desc->info1);
6662ad578fdSJohn Crispin ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
6672ad578fdSJohn Crispin desc->info2);
6682ad578fdSJohn Crispin if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
6692ad578fdSJohn Crispin ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
6702ad578fdSJohn Crispin ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
6712ad578fdSJohn Crispin ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
6722ad578fdSJohn Crispin if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
6732ad578fdSJohn Crispin ts->rate_stats = desc->rate_stats.info0;
6742ad578fdSJohn Crispin else
6752ad578fdSJohn Crispin ts->rate_stats = 0;
6762ad578fdSJohn Crispin }
6772ad578fdSJohn Crispin
ath11k_dp_tx_completion_handler(struct ath11k_base * ab,int ring_id)678d5c65159SKalle Valo void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
679d5c65159SKalle Valo {
680d5c65159SKalle Valo struct ath11k *ar;
681d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
682d5c65159SKalle Valo int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
683d5c65159SKalle Valo struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
684d5c65159SKalle Valo struct sk_buff *msdu;
685eefca584SColin Ian King struct hal_tx_status ts = { 0 };
686d5c65159SKalle Valo struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
687d5c65159SKalle Valo u32 *desc;
688d5c65159SKalle Valo u32 msdu_id;
689d5c65159SKalle Valo u8 mac_id;
690d5c65159SKalle Valo
6912f588660SCarl Huang spin_lock_bh(&status_ring->lock);
6922f588660SCarl Huang
693d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, status_ring);
694d5c65159SKalle Valo
695d0998eb8SJohn Crispin while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
696d0998eb8SJohn Crispin tx_ring->tx_status_tail) &&
697d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
698d0998eb8SJohn Crispin memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
699d0998eb8SJohn Crispin desc, sizeof(struct hal_wbm_release_ring));
700d0998eb8SJohn Crispin tx_ring->tx_status_head =
701d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
702d5c65159SKalle Valo }
703d5c65159SKalle Valo
704bcef57eaSP Praneesh if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
705bcef57eaSP Praneesh (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) ==
706bcef57eaSP Praneesh tx_ring->tx_status_tail))) {
707d5c65159SKalle Valo /* TODO: Process pending tx_status messages when kfifo_is_full() */
708d5c65159SKalle Valo ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
709d5c65159SKalle Valo }
710d5c65159SKalle Valo
711d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, status_ring);
712d5c65159SKalle Valo
7132f588660SCarl Huang spin_unlock_bh(&status_ring->lock);
7142f588660SCarl Huang
715d0998eb8SJohn Crispin while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
716d0998eb8SJohn Crispin struct hal_wbm_release_ring *tx_status;
7172ad578fdSJohn Crispin u32 desc_id;
718d0998eb8SJohn Crispin
719d0998eb8SJohn Crispin tx_ring->tx_status_tail =
720d0998eb8SJohn Crispin ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
721d0998eb8SJohn Crispin tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
7222ad578fdSJohn Crispin ath11k_dp_tx_status_parse(ab, tx_status, &ts);
723d5c65159SKalle Valo
7242ad578fdSJohn Crispin desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
7252ad578fdSJohn Crispin tx_status->buf_addr_info.info1);
7262ad578fdSJohn Crispin mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
7272ad578fdSJohn Crispin msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
728d5c65159SKalle Valo
729bcef57eaSP Praneesh if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) {
730d5c65159SKalle Valo ath11k_dp_tx_process_htt_tx_complete(ab,
731d0998eb8SJohn Crispin (void *)tx_status,
732d5c65159SKalle Valo mac_id, msdu_id,
733d5c65159SKalle Valo tx_ring);
734d5c65159SKalle Valo continue;
735d5c65159SKalle Valo }
736d5c65159SKalle Valo
737be8867cbSP Praneesh spin_lock(&tx_ring->tx_idr_lock);
738be8867cbSP Praneesh msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
739bcef57eaSP Praneesh if (unlikely(!msdu)) {
740d5c65159SKalle Valo ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
741d5c65159SKalle Valo msdu_id);
742be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock);
743d5c65159SKalle Valo continue;
744d5c65159SKalle Valo }
745be8867cbSP Praneesh
746be8867cbSP Praneesh spin_unlock(&tx_ring->tx_idr_lock);
747d5c65159SKalle Valo
748d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar;
749d5c65159SKalle Valo
750d5c65159SKalle Valo if (atomic_dec_and_test(&ar->dp.num_tx_pending))
751d5c65159SKalle Valo wake_up(&ar->dp.tx_empty_waitq);
752d5c65159SKalle Valo
753d5c65159SKalle Valo ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
754d5c65159SKalle Valo }
755d5c65159SKalle Valo }
756d5c65159SKalle Valo
ath11k_dp_tx_send_reo_cmd(struct ath11k_base * ab,struct dp_rx_tid * rx_tid,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd,void (* cb)(struct ath11k_dp *,void *,enum hal_reo_cmd_status))757d5c65159SKalle Valo int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
758d5c65159SKalle Valo enum hal_reo_cmd_type type,
759d5c65159SKalle Valo struct ath11k_hal_reo_cmd *cmd,
760d5c65159SKalle Valo void (*cb)(struct ath11k_dp *, void *,
761d5c65159SKalle Valo enum hal_reo_cmd_status))
762d5c65159SKalle Valo {
763d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
764d5c65159SKalle Valo struct dp_reo_cmd *dp_cmd;
765d5c65159SKalle Valo struct hal_srng *cmd_ring;
766d5c65159SKalle Valo int cmd_num;
767d5c65159SKalle Valo
7688ee8d38cSSriram R if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
7698ee8d38cSSriram R return -ESHUTDOWN;
7708ee8d38cSSriram R
771d5c65159SKalle Valo cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
772d5c65159SKalle Valo cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
773d5c65159SKalle Valo
774e190bc05SGovindaraj Saminathan /* cmd_num should start from 1, during failure return the error code */
775e190bc05SGovindaraj Saminathan if (cmd_num < 0)
776e190bc05SGovindaraj Saminathan return cmd_num;
777e190bc05SGovindaraj Saminathan
778d5c65159SKalle Valo /* reo cmd ring descriptors has cmd_num starting from 1 */
779e190bc05SGovindaraj Saminathan if (cmd_num == 0)
780d5c65159SKalle Valo return -EINVAL;
781d5c65159SKalle Valo
782d5c65159SKalle Valo if (!cb)
783d5c65159SKalle Valo return 0;
784d5c65159SKalle Valo
785d5c65159SKalle Valo /* Can this be optimized so that we keep the pending command list only
7863fecca0eSJeff Johnson * for tid delete command to free up the resource on the command status
787d5c65159SKalle Valo * indication?
788d5c65159SKalle Valo */
789d5c65159SKalle Valo dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
790d5c65159SKalle Valo
791d5c65159SKalle Valo if (!dp_cmd)
792d5c65159SKalle Valo return -ENOMEM;
793d5c65159SKalle Valo
794d5c65159SKalle Valo memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
795d5c65159SKalle Valo dp_cmd->cmd_num = cmd_num;
796d5c65159SKalle Valo dp_cmd->handler = cb;
797d5c65159SKalle Valo
798d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock);
799d5c65159SKalle Valo list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
800d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock);
801d5c65159SKalle Valo
802d5c65159SKalle Valo return 0;
803d5c65159SKalle Valo }
804d5c65159SKalle Valo
805d5c65159SKalle Valo static int
ath11k_dp_tx_get_ring_id_type(struct ath11k_base * ab,int mac_id,u32 ring_id,enum hal_ring_type ring_type,enum htt_srng_ring_type * htt_ring_type,enum htt_srng_ring_id * htt_ring_id)806d5c65159SKalle Valo ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
807d5c65159SKalle Valo int mac_id, u32 ring_id,
808d5c65159SKalle Valo enum hal_ring_type ring_type,
809d5c65159SKalle Valo enum htt_srng_ring_type *htt_ring_type,
810d5c65159SKalle Valo enum htt_srng_ring_id *htt_ring_id)
811d5c65159SKalle Valo {
812d5c65159SKalle Valo int lmac_ring_id_offset = 0;
813d5c65159SKalle Valo int ret = 0;
814d5c65159SKalle Valo
815d5c65159SKalle Valo switch (ring_type) {
816d5c65159SKalle Valo case HAL_RXDMA_BUF:
817d5c65159SKalle Valo lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
8184152e420SCarl Huang
8194152e420SCarl Huang /* for QCA6390, host fills rx buffer to fw and fw fills to
8204152e420SCarl Huang * rxbuf ring for each rxdma
8214152e420SCarl Huang */
8224152e420SCarl Huang if (!ab->hw_params.rx_mac_buf_ring) {
823d5c65159SKalle Valo if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
824d5c65159SKalle Valo lmac_ring_id_offset) ||
825d5c65159SKalle Valo ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
826d5c65159SKalle Valo lmac_ring_id_offset))) {
827d5c65159SKalle Valo ret = -EINVAL;
828d5c65159SKalle Valo }
829d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
830d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING;
8314152e420SCarl Huang } else {
8324152e420SCarl Huang if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) {
8334152e420SCarl Huang *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
8344152e420SCarl Huang *htt_ring_type = HTT_SW_TO_SW_RING;
8354152e420SCarl Huang } else {
8364152e420SCarl Huang *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
8374152e420SCarl Huang *htt_ring_type = HTT_SW_TO_HW_RING;
8384152e420SCarl Huang }
8394152e420SCarl Huang }
840d5c65159SKalle Valo break;
841d5c65159SKalle Valo case HAL_RXDMA_DST:
842d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
843d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING;
844d5c65159SKalle Valo break;
845d5c65159SKalle Valo case HAL_RXDMA_MONITOR_BUF:
846d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
847d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING;
848d5c65159SKalle Valo break;
849d5c65159SKalle Valo case HAL_RXDMA_MONITOR_STATUS:
850d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
851d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING;
852d5c65159SKalle Valo break;
853d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DST:
854d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
855d5c65159SKalle Valo *htt_ring_type = HTT_HW_TO_SW_RING;
856d5c65159SKalle Valo break;
857d5c65159SKalle Valo case HAL_RXDMA_MONITOR_DESC:
858d5c65159SKalle Valo *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
859d5c65159SKalle Valo *htt_ring_type = HTT_SW_TO_HW_RING;
860d5c65159SKalle Valo break;
861d5c65159SKalle Valo default:
862d5c65159SKalle Valo ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
863d5c65159SKalle Valo ret = -EINVAL;
864d5c65159SKalle Valo }
865d5c65159SKalle Valo return ret;
866d5c65159SKalle Valo }
867d5c65159SKalle Valo
ath11k_dp_tx_htt_srng_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type)868d5c65159SKalle Valo int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
869d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type)
870d5c65159SKalle Valo {
871d5c65159SKalle Valo struct htt_srng_setup_cmd *cmd;
872d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id];
873d5c65159SKalle Valo struct hal_srng_params params;
874d5c65159SKalle Valo struct sk_buff *skb;
875d5c65159SKalle Valo u32 ring_entry_sz;
876d5c65159SKalle Valo int len = sizeof(*cmd);
877d5c65159SKalle Valo dma_addr_t hp_addr, tp_addr;
878d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type;
879d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id;
8807195c874SDan Carpenter int ret;
881d5c65159SKalle Valo
882d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len);
883d5c65159SKalle Valo if (!skb)
884d5c65159SKalle Valo return -ENOMEM;
885d5c65159SKalle Valo
886d5c65159SKalle Valo memset(¶ms, 0, sizeof(params));
887d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms);
888d5c65159SKalle Valo
889d5c65159SKalle Valo hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
890d5c65159SKalle Valo tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
891d5c65159SKalle Valo
8927195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
893d5c65159SKalle Valo ring_type, &htt_ring_type,
8947195c874SDan Carpenter &htt_ring_id);
8957195c874SDan Carpenter if (ret)
896d5c65159SKalle Valo goto err_free;
897d5c65159SKalle Valo
898d5c65159SKalle Valo skb_put(skb, len);
899d5c65159SKalle Valo cmd = (struct htt_srng_setup_cmd *)skb->data;
900d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
901d5c65159SKalle Valo HTT_H2T_MSG_TYPE_SRING_SETUP);
902d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING ||
903d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING)
904d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
905d5c65159SKalle Valo DP_SW2HW_MACID(mac_id));
906d5c65159SKalle Valo else
907d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
908d5c65159SKalle Valo mac_id);
909d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
910d5c65159SKalle Valo htt_ring_type);
911d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
912d5c65159SKalle Valo
913d5c65159SKalle Valo cmd->ring_base_addr_lo = params.ring_base_paddr &
914d5c65159SKalle Valo HAL_ADDR_LSB_REG_MASK;
915d5c65159SKalle Valo
916d5c65159SKalle Valo cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
917d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT;
918d5c65159SKalle Valo
919f7eb4b04SKalle Valo ret = ath11k_hal_srng_get_entrysize(ab, ring_type);
9207195c874SDan Carpenter if (ret < 0)
9214358bcb5SColin Ian King goto err_free;
922d5c65159SKalle Valo
923d5c65159SKalle Valo ring_entry_sz = ret;
924d5c65159SKalle Valo
925d5c65159SKalle Valo ring_entry_sz >>= 2;
926d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
927d5c65159SKalle Valo ring_entry_sz);
928d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
929d5c65159SKalle Valo params.num_entries * ring_entry_sz);
930d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
931d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
932d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(
933d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
934d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
935d5c65159SKalle Valo cmd->info1 |= FIELD_PREP(
936d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
937d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
938d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING)
939d5c65159SKalle Valo cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
940d5c65159SKalle Valo
941d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
942d5c65159SKalle Valo cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
943d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT;
944d5c65159SKalle Valo
945d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
946d5c65159SKalle Valo cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
947d5c65159SKalle Valo HAL_ADDR_MSB_REG_SHIFT;
948d5c65159SKalle Valo
9497dc67af0SKarthikeyan Periyasamy cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr);
9507dc67af0SKarthikeyan Periyasamy cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr);
951701e48a4SCarl Huang cmd->msi_data = params.msi_data;
952d5c65159SKalle Valo
953d5c65159SKalle Valo cmd->intr_info = FIELD_PREP(
954d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
955d5c65159SKalle Valo params.intr_batch_cntr_thres_entries * ring_entry_sz);
956d5c65159SKalle Valo cmd->intr_info |= FIELD_PREP(
957d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
958d5c65159SKalle Valo params.intr_timer_thres_us >> 3);
959d5c65159SKalle Valo
960d5c65159SKalle Valo cmd->info2 = 0;
961d5c65159SKalle Valo if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
962d5c65159SKalle Valo cmd->info2 = FIELD_PREP(
963d5c65159SKalle Valo HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
964d5c65159SKalle Valo params.low_threshold);
965d5c65159SKalle Valo }
966d5c65159SKalle Valo
967947b5e22SKalle Valo ath11k_dbg(ab, ATH11K_DBG_DP_TX,
968947b5e22SKalle Valo "htt srng setup msi_addr_lo 0x%x msi_addr_hi 0x%x msi_data 0x%x ring_id %d ring_type %d intr_info 0x%x flags 0x%x\n",
969947b5e22SKalle Valo cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
970947b5e22SKalle Valo cmd->msi_data, ring_id, ring_type, cmd->intr_info, cmd->info2);
971701e48a4SCarl Huang
972d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
973d5c65159SKalle Valo if (ret)
974d5c65159SKalle Valo goto err_free;
975d5c65159SKalle Valo
976d5c65159SKalle Valo return 0;
977d5c65159SKalle Valo
978d5c65159SKalle Valo err_free:
979d5c65159SKalle Valo dev_kfree_skb_any(skb);
980d5c65159SKalle Valo
981d5c65159SKalle Valo return ret;
982d5c65159SKalle Valo }
983d5c65159SKalle Valo
984d5c65159SKalle Valo #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
985d5c65159SKalle Valo
ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base * ab)986d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
987d5c65159SKalle Valo {
988d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
989d5c65159SKalle Valo struct sk_buff *skb;
990d5c65159SKalle Valo struct htt_ver_req_cmd *cmd;
991d5c65159SKalle Valo int len = sizeof(*cmd);
992d5c65159SKalle Valo int ret;
993d5c65159SKalle Valo
994d5c65159SKalle Valo init_completion(&dp->htt_tgt_version_received);
995d5c65159SKalle Valo
996d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len);
997d5c65159SKalle Valo if (!skb)
998d5c65159SKalle Valo return -ENOMEM;
999d5c65159SKalle Valo
1000d5c65159SKalle Valo skb_put(skb, len);
1001d5c65159SKalle Valo cmd = (struct htt_ver_req_cmd *)skb->data;
1002d5c65159SKalle Valo cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
1003d5c65159SKalle Valo HTT_H2T_MSG_TYPE_VERSION_REQ);
1004d5c65159SKalle Valo
1005d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1006d5c65159SKalle Valo if (ret) {
1007d5c65159SKalle Valo dev_kfree_skb_any(skb);
1008d5c65159SKalle Valo return ret;
1009d5c65159SKalle Valo }
1010d5c65159SKalle Valo
1011d5c65159SKalle Valo ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
1012d5c65159SKalle Valo HTT_TARGET_VERSION_TIMEOUT_HZ);
1013d5c65159SKalle Valo if (ret == 0) {
1014d5c65159SKalle Valo ath11k_warn(ab, "htt target version request timed out\n");
1015d5c65159SKalle Valo return -ETIMEDOUT;
1016d5c65159SKalle Valo }
1017d5c65159SKalle Valo
1018d5c65159SKalle Valo if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
1019d5c65159SKalle Valo ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
1020d5c65159SKalle Valo dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
1021d5c65159SKalle Valo return -ENOTSUPP;
1022d5c65159SKalle Valo }
1023d5c65159SKalle Valo
1024d5c65159SKalle Valo return 0;
1025d5c65159SKalle Valo }
1026d5c65159SKalle Valo
ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k * ar,u32 mask)1027d5c65159SKalle Valo int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
1028d5c65159SKalle Valo {
1029d5c65159SKalle Valo struct ath11k_base *ab = ar->ab;
1030d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
1031d5c65159SKalle Valo struct sk_buff *skb;
1032d5c65159SKalle Valo struct htt_ppdu_stats_cfg_cmd *cmd;
1033d5c65159SKalle Valo int len = sizeof(*cmd);
1034d5c65159SKalle Valo u8 pdev_mask;
1035d5c65159SKalle Valo int ret;
1036701e48a4SCarl Huang int i;
1037d5c65159SKalle Valo
1038701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1039d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len);
1040d5c65159SKalle Valo if (!skb)
1041d5c65159SKalle Valo return -ENOMEM;
1042d5c65159SKalle Valo
1043d5c65159SKalle Valo skb_put(skb, len);
1044d5c65159SKalle Valo cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
1045d5c65159SKalle Valo cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
1046d5c65159SKalle Valo HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
1047d5c65159SKalle Valo
104816a2c3d5SRameshkumar Sundaram pdev_mask = 1 << (ar->pdev_idx + i);
1049d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
1050d5c65159SKalle Valo cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
1051d5c65159SKalle Valo
1052d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1053d5c65159SKalle Valo if (ret) {
1054d5c65159SKalle Valo dev_kfree_skb_any(skb);
1055d5c65159SKalle Valo return ret;
1056d5c65159SKalle Valo }
1057701e48a4SCarl Huang }
1058d5c65159SKalle Valo
1059d5c65159SKalle Valo return 0;
1060d5c65159SKalle Valo }
1061d5c65159SKalle Valo
ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base * ab,u32 ring_id,int mac_id,enum hal_ring_type ring_type,int rx_buf_size,struct htt_rx_ring_tlv_filter * tlv_filter)1062d5c65159SKalle Valo int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
1063d5c65159SKalle Valo int mac_id, enum hal_ring_type ring_type,
1064d5c65159SKalle Valo int rx_buf_size,
1065d5c65159SKalle Valo struct htt_rx_ring_tlv_filter *tlv_filter)
1066d5c65159SKalle Valo {
1067d5c65159SKalle Valo struct htt_rx_ring_selection_cfg_cmd *cmd;
1068d5c65159SKalle Valo struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1069d5c65159SKalle Valo struct hal_srng_params params;
1070d5c65159SKalle Valo struct sk_buff *skb;
1071d5c65159SKalle Valo int len = sizeof(*cmd);
1072d5c65159SKalle Valo enum htt_srng_ring_type htt_ring_type;
1073d5c65159SKalle Valo enum htt_srng_ring_id htt_ring_id;
10747195c874SDan Carpenter int ret;
1075d5c65159SKalle Valo
1076d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len);
1077d5c65159SKalle Valo if (!skb)
1078d5c65159SKalle Valo return -ENOMEM;
1079d5c65159SKalle Valo
1080d5c65159SKalle Valo memset(¶ms, 0, sizeof(params));
1081d5c65159SKalle Valo ath11k_hal_srng_get_params(ab, srng, ¶ms);
1082d5c65159SKalle Valo
10837195c874SDan Carpenter ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1084d5c65159SKalle Valo ring_type, &htt_ring_type,
10857195c874SDan Carpenter &htt_ring_id);
10867195c874SDan Carpenter if (ret)
1087d5c65159SKalle Valo goto err_free;
1088d5c65159SKalle Valo
1089d5c65159SKalle Valo skb_put(skb, len);
1090d5c65159SKalle Valo cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
1091d5c65159SKalle Valo cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
1092d5c65159SKalle Valo HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
1093d5c65159SKalle Valo if (htt_ring_type == HTT_SW_TO_HW_RING ||
1094d5c65159SKalle Valo htt_ring_type == HTT_HW_TO_SW_RING)
1095d5c65159SKalle Valo cmd->info0 |=
1096d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1097d5c65159SKalle Valo DP_SW2HW_MACID(mac_id));
1098d5c65159SKalle Valo else
1099d5c65159SKalle Valo cmd->info0 |=
1100d5c65159SKalle Valo FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1101d5c65159SKalle Valo mac_id);
1102d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
1103d5c65159SKalle Valo htt_ring_id);
1104d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
1105d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
1106d5c65159SKalle Valo cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
1107d5c65159SKalle Valo !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
1108d5c65159SKalle Valo
1109d5c65159SKalle Valo cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
1110d5c65159SKalle Valo rx_buf_size);
1111d5c65159SKalle Valo cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
1112d5c65159SKalle Valo cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
1113d5c65159SKalle Valo cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
1114d5c65159SKalle Valo cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
1115d5c65159SKalle Valo cmd->rx_filter_tlv = tlv_filter->rx_filter;
1116d5c65159SKalle Valo
1117d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
1118d5c65159SKalle Valo if (ret)
1119d5c65159SKalle Valo goto err_free;
1120d5c65159SKalle Valo
1121d5c65159SKalle Valo return 0;
1122d5c65159SKalle Valo
1123d5c65159SKalle Valo err_free:
1124d5c65159SKalle Valo dev_kfree_skb_any(skb);
1125d5c65159SKalle Valo
1126d5c65159SKalle Valo return ret;
1127d5c65159SKalle Valo }
1128d5c65159SKalle Valo
1129d5c65159SKalle Valo int
ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k * ar,u8 type,struct htt_ext_stats_cfg_params * cfg_params,u64 cookie)1130d5c65159SKalle Valo ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
1131d5c65159SKalle Valo struct htt_ext_stats_cfg_params *cfg_params,
1132d5c65159SKalle Valo u64 cookie)
1133d5c65159SKalle Valo {
1134d5c65159SKalle Valo struct ath11k_base *ab = ar->ab;
1135d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp;
1136d5c65159SKalle Valo struct sk_buff *skb;
1137d5c65159SKalle Valo struct htt_ext_stats_cfg_cmd *cmd;
113813706340SWen Gong u32 pdev_id;
1139d5c65159SKalle Valo int len = sizeof(*cmd);
1140d5c65159SKalle Valo int ret;
1141d5c65159SKalle Valo
1142d5c65159SKalle Valo skb = ath11k_htc_alloc_skb(ab, len);
1143d5c65159SKalle Valo if (!skb)
1144d5c65159SKalle Valo return -ENOMEM;
1145d5c65159SKalle Valo
1146d5c65159SKalle Valo skb_put(skb, len);
1147d5c65159SKalle Valo
1148d5c65159SKalle Valo cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
1149d5c65159SKalle Valo memset(cmd, 0, sizeof(*cmd));
1150d5c65159SKalle Valo cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1151d5c65159SKalle Valo
115213706340SWen Gong if (ab->hw_params.single_pdev_only)
115313706340SWen Gong pdev_id = ath11k_mac_get_target_pdev_id(ar);
115413706340SWen Gong else
115513706340SWen Gong pdev_id = ar->pdev->pdev_id;
115613706340SWen Gong
115713706340SWen Gong cmd->hdr.pdev_mask = 1 << pdev_id;
1158d5c65159SKalle Valo
1159d5c65159SKalle Valo cmd->hdr.stats_type = type;
1160d5c65159SKalle Valo cmd->cfg_param0 = cfg_params->cfg0;
1161d5c65159SKalle Valo cmd->cfg_param1 = cfg_params->cfg1;
1162d5c65159SKalle Valo cmd->cfg_param2 = cfg_params->cfg2;
1163d5c65159SKalle Valo cmd->cfg_param3 = cfg_params->cfg3;
1164d5c65159SKalle Valo cmd->cookie_lsb = lower_32_bits(cookie);
1165d5c65159SKalle Valo cmd->cookie_msb = upper_32_bits(cookie);
1166d5c65159SKalle Valo
1167d5c65159SKalle Valo ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1168d5c65159SKalle Valo if (ret) {
1169d5c65159SKalle Valo ath11k_warn(ab, "failed to send htt type stats request: %d",
1170d5c65159SKalle Valo ret);
1171d5c65159SKalle Valo dev_kfree_skb_any(skb);
1172d5c65159SKalle Valo return ret;
1173d5c65159SKalle Valo }
1174d5c65159SKalle Valo
1175d5c65159SKalle Valo return 0;
1176d5c65159SKalle Valo }
1177d5c65159SKalle Valo
ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k * ar,bool reset)1178d5c65159SKalle Valo int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
1179d5c65159SKalle Valo {
1180d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp;
11814152e420SCarl Huang struct ath11k_base *ab = ar->ab;
1182d5c65159SKalle Valo struct htt_rx_ring_tlv_filter tlv_filter = {0};
11834152e420SCarl Huang int ret = 0, ring_id = 0, i;
1184d5c65159SKalle Valo
11855c1f74d2SAnilkumar Kolli if (ab->hw_params.full_monitor_mode) {
11865c1f74d2SAnilkumar Kolli ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab,
11875c1f74d2SAnilkumar Kolli dp->mac_id, !reset);
11885c1f74d2SAnilkumar Kolli if (ret < 0) {
11895c1f74d2SAnilkumar Kolli ath11k_err(ab, "failed to setup full monitor %d\n", ret);
11905c1f74d2SAnilkumar Kolli return ret;
11915c1f74d2SAnilkumar Kolli }
11925c1f74d2SAnilkumar Kolli }
11935c1f74d2SAnilkumar Kolli
1194d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1195d5c65159SKalle Valo
1196d5c65159SKalle Valo if (!reset) {
1197d5c65159SKalle Valo tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1198d5c65159SKalle Valo tlv_filter.pkt_filter_flags0 =
1199d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1200d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1201d5c65159SKalle Valo tlv_filter.pkt_filter_flags1 =
1202d5c65159SKalle Valo HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1203d5c65159SKalle Valo HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1204d5c65159SKalle Valo tlv_filter.pkt_filter_flags2 =
1205d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1206d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1207d5c65159SKalle Valo tlv_filter.pkt_filter_flags3 =
1208d5c65159SKalle Valo HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1209d5c65159SKalle Valo HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1210d5c65159SKalle Valo HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1211d5c65159SKalle Valo HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1212d5c65159SKalle Valo }
1213d5c65159SKalle Valo
1214701e48a4SCarl Huang if (ab->hw_params.rxdma1_enable) {
1215d5c65159SKalle Valo ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
1216d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF,
1217d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE,
1218d5c65159SKalle Valo &tlv_filter);
1219701e48a4SCarl Huang } else if (!reset) {
1220701e48a4SCarl Huang /* set in monitor mode only */
1221701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1222701e48a4SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id;
1223701e48a4SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
1224701e48a4SCarl Huang dp->mac_id + i,
1225701e48a4SCarl Huang HAL_RXDMA_BUF,
1226701e48a4SCarl Huang 1024,
1227701e48a4SCarl Huang &tlv_filter);
1228701e48a4SCarl Huang }
1229701e48a4SCarl Huang }
1230701e48a4SCarl Huang
1231d5c65159SKalle Valo if (ret)
1232d5c65159SKalle Valo return ret;
1233d5c65159SKalle Valo
12344152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
12354152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
1236689a5e6fSSeevalamuthu Mariappan if (!reset) {
1237d5c65159SKalle Valo tlv_filter.rx_filter =
1238d5c65159SKalle Valo HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
1239689a5e6fSSeevalamuthu Mariappan } else {
1240d5c65159SKalle Valo tlv_filter = ath11k_mac_mon_status_filter_default;
1241d5c65159SKalle Valo
1242689a5e6fSSeevalamuthu Mariappan if (ath11k_debugfs_is_extd_rx_stats_enabled(ar))
1243689a5e6fSSeevalamuthu Mariappan tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar);
1244689a5e6fSSeevalamuthu Mariappan }
1245689a5e6fSSeevalamuthu Mariappan
12464152e420SCarl Huang ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id,
12474152e420SCarl Huang dp->mac_id + i,
1248d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS,
1249d5c65159SKalle Valo DP_RXDMA_REFILL_RING_SIZE,
1250d5c65159SKalle Valo &tlv_filter);
12514152e420SCarl Huang }
12524152e420SCarl Huang
1253701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable)
1254701e48a4SCarl Huang mod_timer(&ar->ab->mon_reap_timer, jiffies +
1255701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
1256701e48a4SCarl Huang
1257d5c65159SKalle Valo return ret;
1258d5c65159SKalle Valo }
12595c1f74d2SAnilkumar Kolli
ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base * ab,int mac_id,bool config)12605c1f74d2SAnilkumar Kolli int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
12615c1f74d2SAnilkumar Kolli bool config)
12625c1f74d2SAnilkumar Kolli {
12635c1f74d2SAnilkumar Kolli struct htt_rx_full_monitor_mode_cfg_cmd *cmd;
12645c1f74d2SAnilkumar Kolli struct sk_buff *skb;
12655c1f74d2SAnilkumar Kolli int ret, len = sizeof(*cmd);
12665c1f74d2SAnilkumar Kolli
12675c1f74d2SAnilkumar Kolli skb = ath11k_htc_alloc_skb(ab, len);
12685c1f74d2SAnilkumar Kolli if (!skb)
12695c1f74d2SAnilkumar Kolli return -ENOMEM;
12705c1f74d2SAnilkumar Kolli
12715c1f74d2SAnilkumar Kolli skb_put(skb, len);
12725c1f74d2SAnilkumar Kolli cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data;
12735c1f74d2SAnilkumar Kolli memset(cmd, 0, sizeof(*cmd));
12745c1f74d2SAnilkumar Kolli cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE,
12755c1f74d2SAnilkumar Kolli HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE);
12765c1f74d2SAnilkumar Kolli
12775c1f74d2SAnilkumar Kolli cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id);
12785c1f74d2SAnilkumar Kolli
12795c1f74d2SAnilkumar Kolli cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE |
12805c1f74d2SAnilkumar Kolli FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING,
12815c1f74d2SAnilkumar Kolli HTT_RX_MON_RING_SW);
12825c1f74d2SAnilkumar Kolli if (config) {
12835c1f74d2SAnilkumar Kolli cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END |
12845c1f74d2SAnilkumar Kolli HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END;
12855c1f74d2SAnilkumar Kolli }
12865c1f74d2SAnilkumar Kolli
12875c1f74d2SAnilkumar Kolli ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
12885c1f74d2SAnilkumar Kolli if (ret)
12895c1f74d2SAnilkumar Kolli goto err_free;
12905c1f74d2SAnilkumar Kolli
12915c1f74d2SAnilkumar Kolli return 0;
12925c1f74d2SAnilkumar Kolli
12935c1f74d2SAnilkumar Kolli err_free:
12945c1f74d2SAnilkumar Kolli dev_kfree_skb_any(skb);
12955c1f74d2SAnilkumar Kolli
12965c1f74d2SAnilkumar Kolli return ret;
12975c1f74d2SAnilkumar Kolli }
1298