1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/ieee80211.h> 7 #include <linux/kernel.h> 8 #include <linux/skbuff.h> 9 #include <crypto/hash.h> 10 #include "core.h" 11 #include "debug.h" 12 #include "debugfs_htt_stats.h" 13 #include "debugfs_sta.h" 14 #include "hal_desc.h" 15 #include "hw.h" 16 #include "dp_rx.h" 17 #include "hal_rx.h" 18 #include "dp_tx.h" 19 #include "peer.h" 20 21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static inline 24 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc) 25 { 26 return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); 27 } 28 29 static inline 30 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab, 31 struct hal_rx_desc *desc) 32 { 33 if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) 34 return HAL_ENCRYPT_TYPE_OPEN; 35 36 return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); 37 } 38 39 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab, 40 struct hal_rx_desc *desc) 41 { 42 return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); 43 } 44 45 static inline 46 bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab, 47 struct hal_rx_desc *desc) 48 { 49 return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc); 50 } 51 52 static inline 53 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab, 54 struct hal_rx_desc *desc) 55 { 56 return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); 57 } 58 59 static inline 60 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab, 61 struct hal_rx_desc *desc) 62 { 63 return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 64 } 65 66 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab, 67 struct hal_rx_desc *desc) 68 { 69 return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc); 70 } 71 72 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab, 73 struct sk_buff *skb) 74 { 75 struct ieee80211_hdr *hdr; 76 77 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 78 return ieee80211_has_morefrags(hdr->frame_control); 79 } 80 81 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab, 82 struct sk_buff *skb) 83 { 84 struct ieee80211_hdr *hdr; 85 86 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 87 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 88 } 89 90 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab, 91 struct hal_rx_desc *desc) 92 { 93 return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc); 94 } 95 96 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab, 97 struct hal_rx_desc *desc) 98 { 99 return ab->hw_params.hw_ops->rx_desc_get_attention(desc); 100 } 101 102 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn) 103 { 104 return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 105 __le32_to_cpu(attn->info2)); 106 } 107 108 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn) 109 { 110 return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 111 __le32_to_cpu(attn->info1)); 112 } 113 114 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn) 115 { 116 return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 117 __le32_to_cpu(attn->info1)); 118 } 119 120 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn) 121 { 122 return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 123 __le32_to_cpu(attn->info2)) == 124 RX_DESC_DECRYPT_STATUS_CODE_OK); 125 } 126 127 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn) 128 { 129 u32 info = __le32_to_cpu(attn->info1); 130 u32 errmap = 0; 131 132 if (info & RX_ATTENTION_INFO1_FCS_ERR) 133 errmap |= DP_RX_MPDU_ERR_FCS; 134 135 if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 136 errmap |= DP_RX_MPDU_ERR_DECRYPT; 137 138 if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 139 errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 140 141 if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 142 errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 143 144 if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 145 errmap |= DP_RX_MPDU_ERR_OVERFLOW; 146 147 if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 148 errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 149 150 if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 151 errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 152 153 return errmap; 154 } 155 156 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab, 157 struct hal_rx_desc *desc) 158 { 159 struct rx_attention *rx_attention; 160 u32 errmap; 161 162 rx_attention = ath11k_dp_rx_get_attention(ab, desc); 163 errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 164 165 return errmap & DP_RX_MPDU_ERR_MSDU_LEN; 166 } 167 168 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab, 169 struct hal_rx_desc *desc) 170 { 171 return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc); 172 } 173 174 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab, 175 struct hal_rx_desc *desc) 176 { 177 return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc); 178 } 179 180 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab, 181 struct hal_rx_desc *desc) 182 { 183 return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc); 184 } 185 186 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab, 187 struct hal_rx_desc *desc) 188 { 189 return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc); 190 } 191 192 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab, 193 struct hal_rx_desc *desc) 194 { 195 return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc); 196 } 197 198 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab, 199 struct hal_rx_desc *desc) 200 { 201 return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc); 202 } 203 204 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab, 205 struct hal_rx_desc *desc) 206 { 207 return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc)); 208 } 209 210 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab, 211 struct hal_rx_desc *desc) 212 { 213 return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc); 214 } 215 216 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab, 217 struct hal_rx_desc *desc) 218 { 219 return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc); 220 } 221 222 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab, 223 struct hal_rx_desc *desc) 224 { 225 return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc); 226 } 227 228 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab, 229 struct hal_rx_desc *desc) 230 { 231 return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc); 232 } 233 234 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab, 235 struct hal_rx_desc *desc) 236 { 237 return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc); 238 } 239 240 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab, 241 struct hal_rx_desc *fdesc, 242 struct hal_rx_desc *ldesc) 243 { 244 ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc); 245 } 246 247 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn) 248 { 249 return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 250 __le32_to_cpu(attn->info1)); 251 } 252 253 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab, 254 struct hal_rx_desc *rx_desc) 255 { 256 u8 *rx_pkt_hdr; 257 258 rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc); 259 260 return rx_pkt_hdr; 261 } 262 263 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab, 264 struct hal_rx_desc *rx_desc) 265 { 266 u32 tlv_tag; 267 268 tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc); 269 270 return tlv_tag == HAL_RX_MPDU_START; 271 } 272 273 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab, 274 struct hal_rx_desc *rx_desc) 275 { 276 return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 277 } 278 279 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab, 280 struct hal_rx_desc *desc, 281 u16 len) 282 { 283 ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len); 284 } 285 286 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab, 287 struct hal_rx_desc *desc) 288 { 289 struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc); 290 291 return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) && 292 (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST, 293 __le32_to_cpu(attn->info1))); 294 } 295 296 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab, 297 struct hal_rx_desc *desc) 298 { 299 return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc); 300 } 301 302 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab, 303 struct hal_rx_desc *desc) 304 { 305 return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc); 306 } 307 308 static void ath11k_dp_service_mon_ring(struct timer_list *t) 309 { 310 struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer); 311 int i; 312 313 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 314 ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET); 315 316 mod_timer(&ab->mon_reap_timer, jiffies + 317 msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 318 } 319 320 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab) 321 { 322 int i, reaped = 0; 323 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 324 325 do { 326 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 327 reaped += ath11k_dp_rx_process_mon_rings(ab, i, 328 NULL, 329 DP_MON_SERVICE_BUDGET); 330 331 /* nothing more to reap */ 332 if (reaped < DP_MON_SERVICE_BUDGET) 333 return 0; 334 335 } while (time_before(jiffies, timeout)); 336 337 ath11k_warn(ab, "dp mon ring purge timeout"); 338 339 return -ETIMEDOUT; 340 } 341 342 /* Returns number of Rx buffers replenished */ 343 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 344 struct dp_rxdma_ring *rx_ring, 345 int req_entries, 346 enum hal_rx_buf_return_buf_manager mgr) 347 { 348 struct hal_srng *srng; 349 u32 *desc; 350 struct sk_buff *skb; 351 int num_free; 352 int num_remain; 353 int buf_id; 354 u32 cookie; 355 dma_addr_t paddr; 356 357 req_entries = min(req_entries, rx_ring->bufs_max); 358 359 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 360 361 spin_lock_bh(&srng->lock); 362 363 ath11k_hal_srng_access_begin(ab, srng); 364 365 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 366 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 367 req_entries = num_free; 368 369 req_entries = min(num_free, req_entries); 370 num_remain = req_entries; 371 372 while (num_remain > 0) { 373 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 374 DP_RX_BUFFER_ALIGN_SIZE); 375 if (!skb) 376 break; 377 378 if (!IS_ALIGNED((unsigned long)skb->data, 379 DP_RX_BUFFER_ALIGN_SIZE)) { 380 skb_pull(skb, 381 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 382 skb->data); 383 } 384 385 paddr = dma_map_single(ab->dev, skb->data, 386 skb->len + skb_tailroom(skb), 387 DMA_FROM_DEVICE); 388 if (dma_mapping_error(ab->dev, paddr)) 389 goto fail_free_skb; 390 391 spin_lock_bh(&rx_ring->idr_lock); 392 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 393 rx_ring->bufs_max * 3, GFP_ATOMIC); 394 spin_unlock_bh(&rx_ring->idr_lock); 395 if (buf_id < 0) 396 goto fail_dma_unmap; 397 398 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 399 if (!desc) 400 goto fail_idr_remove; 401 402 ATH11K_SKB_RXCB(skb)->paddr = paddr; 403 404 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 405 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 406 407 num_remain--; 408 409 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 410 } 411 412 ath11k_hal_srng_access_end(ab, srng); 413 414 spin_unlock_bh(&srng->lock); 415 416 return req_entries - num_remain; 417 418 fail_idr_remove: 419 spin_lock_bh(&rx_ring->idr_lock); 420 idr_remove(&rx_ring->bufs_idr, buf_id); 421 spin_unlock_bh(&rx_ring->idr_lock); 422 fail_dma_unmap: 423 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 424 DMA_FROM_DEVICE); 425 fail_free_skb: 426 dev_kfree_skb_any(skb); 427 428 ath11k_hal_srng_access_end(ab, srng); 429 430 spin_unlock_bh(&srng->lock); 431 432 return req_entries - num_remain; 433 } 434 435 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 436 struct dp_rxdma_ring *rx_ring) 437 { 438 struct ath11k_pdev_dp *dp = &ar->dp; 439 struct sk_buff *skb; 440 int buf_id; 441 442 spin_lock_bh(&rx_ring->idr_lock); 443 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 444 idr_remove(&rx_ring->bufs_idr, buf_id); 445 /* TODO: Understand where internal driver does this dma_unmap 446 * of rxdma_buffer. 447 */ 448 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 449 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 450 dev_kfree_skb_any(skb); 451 } 452 453 idr_destroy(&rx_ring->bufs_idr); 454 spin_unlock_bh(&rx_ring->idr_lock); 455 456 /* if rxdma1_enable is false, mon_status_refill_ring 457 * isn't setup, so don't clean. 458 */ 459 if (!ar->ab->hw_params.rxdma1_enable) 460 return 0; 461 462 rx_ring = &dp->rx_mon_status_refill_ring[0]; 463 464 spin_lock_bh(&rx_ring->idr_lock); 465 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 466 idr_remove(&rx_ring->bufs_idr, buf_id); 467 /* XXX: Understand where internal driver does this dma_unmap 468 * of rxdma_buffer. 469 */ 470 dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 471 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); 472 dev_kfree_skb_any(skb); 473 } 474 475 idr_destroy(&rx_ring->bufs_idr); 476 spin_unlock_bh(&rx_ring->idr_lock); 477 478 return 0; 479 } 480 481 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 482 { 483 struct ath11k_pdev_dp *dp = &ar->dp; 484 struct ath11k_base *ab = ar->ab; 485 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 486 int i; 487 488 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 489 490 rx_ring = &dp->rxdma_mon_buf_ring; 491 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 492 493 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 494 rx_ring = &dp->rx_mon_status_refill_ring[i]; 495 ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 496 } 497 498 return 0; 499 } 500 501 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 502 struct dp_rxdma_ring *rx_ring, 503 u32 ringtype) 504 { 505 struct ath11k_pdev_dp *dp = &ar->dp; 506 int num_entries; 507 508 num_entries = rx_ring->refill_buf_ring.size / 509 ath11k_hal_srng_get_entrysize(ar->ab, ringtype); 510 511 rx_ring->bufs_max = num_entries; 512 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 513 ar->ab->hw_params.hal_params->rx_buf_rbm); 514 return 0; 515 } 516 517 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 518 { 519 struct ath11k_pdev_dp *dp = &ar->dp; 520 struct ath11k_base *ab = ar->ab; 521 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 522 int i; 523 524 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 525 526 if (ar->ab->hw_params.rxdma1_enable) { 527 rx_ring = &dp->rxdma_mon_buf_ring; 528 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 529 } 530 531 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 532 rx_ring = &dp->rx_mon_status_refill_ring[i]; 533 ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 534 } 535 536 return 0; 537 } 538 539 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 540 { 541 struct ath11k_pdev_dp *dp = &ar->dp; 542 struct ath11k_base *ab = ar->ab; 543 int i; 544 545 ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 546 547 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 548 if (ab->hw_params.rx_mac_buf_ring) 549 ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 550 551 ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 552 ath11k_dp_srng_cleanup(ab, 553 &dp->rx_mon_status_refill_ring[i].refill_buf_ring); 554 } 555 556 ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 557 } 558 559 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 560 { 561 struct ath11k_dp *dp = &ab->dp; 562 int i; 563 564 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 565 ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 566 } 567 568 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 569 { 570 struct ath11k_dp *dp = &ab->dp; 571 int ret; 572 int i; 573 574 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 575 ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 576 HAL_REO_DST, i, 0, 577 DP_REO_DST_RING_SIZE); 578 if (ret) { 579 ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 580 goto err_reo_cleanup; 581 } 582 } 583 584 return 0; 585 586 err_reo_cleanup: 587 ath11k_dp_pdev_reo_cleanup(ab); 588 589 return ret; 590 } 591 592 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 593 { 594 struct ath11k_pdev_dp *dp = &ar->dp; 595 struct ath11k_base *ab = ar->ab; 596 struct dp_srng *srng = NULL; 597 int i; 598 int ret; 599 600 ret = ath11k_dp_srng_setup(ar->ab, 601 &dp->rx_refill_buf_ring.refill_buf_ring, 602 HAL_RXDMA_BUF, 0, 603 dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 604 if (ret) { 605 ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 606 return ret; 607 } 608 609 if (ar->ab->hw_params.rx_mac_buf_ring) { 610 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 611 ret = ath11k_dp_srng_setup(ar->ab, 612 &dp->rx_mac_buf_ring[i], 613 HAL_RXDMA_BUF, 1, 614 dp->mac_id + i, 1024); 615 if (ret) { 616 ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n", 617 i); 618 return ret; 619 } 620 } 621 } 622 623 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 624 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i], 625 HAL_RXDMA_DST, 0, dp->mac_id + i, 626 DP_RXDMA_ERR_DST_RING_SIZE); 627 if (ret) { 628 ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i); 629 return ret; 630 } 631 } 632 633 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 634 srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 635 ret = ath11k_dp_srng_setup(ar->ab, 636 srng, 637 HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i, 638 DP_RXDMA_MON_STATUS_RING_SIZE); 639 if (ret) { 640 ath11k_warn(ar->ab, 641 "failed to setup rx_mon_status_refill_ring %d\n", i); 642 return ret; 643 } 644 } 645 646 /* if rxdma1_enable is false, then it doesn't need 647 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring 648 * and rxdma_mon_desc_ring. 649 * init reap timer for QCA6390. 650 */ 651 if (!ar->ab->hw_params.rxdma1_enable) { 652 //init mon status buffer reap timer 653 timer_setup(&ar->ab->mon_reap_timer, 654 ath11k_dp_service_mon_ring, 0); 655 return 0; 656 } 657 658 ret = ath11k_dp_srng_setup(ar->ab, 659 &dp->rxdma_mon_buf_ring.refill_buf_ring, 660 HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 661 DP_RXDMA_MONITOR_BUF_RING_SIZE); 662 if (ret) { 663 ath11k_warn(ar->ab, 664 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 665 return ret; 666 } 667 668 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 669 HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 670 DP_RXDMA_MONITOR_DST_RING_SIZE); 671 if (ret) { 672 ath11k_warn(ar->ab, 673 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 674 return ret; 675 } 676 677 ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 678 HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 679 DP_RXDMA_MONITOR_DESC_RING_SIZE); 680 if (ret) { 681 ath11k_warn(ar->ab, 682 "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 683 return ret; 684 } 685 686 return 0; 687 } 688 689 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 690 { 691 struct ath11k_dp *dp = &ab->dp; 692 struct dp_reo_cmd *cmd, *tmp; 693 struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 694 695 spin_lock_bh(&dp->reo_cmd_lock); 696 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 697 list_del(&cmd->list); 698 dma_unmap_single(ab->dev, cmd->data.paddr, 699 cmd->data.size, DMA_BIDIRECTIONAL); 700 kfree(cmd->data.vaddr); 701 kfree(cmd); 702 } 703 704 list_for_each_entry_safe(cmd_cache, tmp_cache, 705 &dp->reo_cmd_cache_flush_list, list) { 706 list_del(&cmd_cache->list); 707 dp->reo_cmd_cache_flush_count--; 708 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 709 cmd_cache->data.size, DMA_BIDIRECTIONAL); 710 kfree(cmd_cache->data.vaddr); 711 kfree(cmd_cache); 712 } 713 spin_unlock_bh(&dp->reo_cmd_lock); 714 } 715 716 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 717 enum hal_reo_cmd_status status) 718 { 719 struct dp_rx_tid *rx_tid = ctx; 720 721 if (status != HAL_REO_CMD_SUCCESS) 722 ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 723 rx_tid->tid, status); 724 725 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 726 DMA_BIDIRECTIONAL); 727 kfree(rx_tid->vaddr); 728 } 729 730 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 731 struct dp_rx_tid *rx_tid) 732 { 733 struct ath11k_hal_reo_cmd cmd = {0}; 734 unsigned long tot_desc_sz, desc_sz; 735 int ret; 736 737 tot_desc_sz = rx_tid->size; 738 desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 739 740 while (tot_desc_sz > desc_sz) { 741 tot_desc_sz -= desc_sz; 742 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 743 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 744 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 745 HAL_REO_CMD_FLUSH_CACHE, &cmd, 746 NULL); 747 if (ret) 748 ath11k_warn(ab, 749 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 750 rx_tid->tid, ret); 751 } 752 753 memset(&cmd, 0, sizeof(cmd)); 754 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 755 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 756 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 757 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 758 HAL_REO_CMD_FLUSH_CACHE, 759 &cmd, ath11k_dp_reo_cmd_free); 760 if (ret) { 761 ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 762 rx_tid->tid, ret); 763 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 764 DMA_BIDIRECTIONAL); 765 kfree(rx_tid->vaddr); 766 } 767 } 768 769 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 770 enum hal_reo_cmd_status status) 771 { 772 struct ath11k_base *ab = dp->ab; 773 struct dp_rx_tid *rx_tid = ctx; 774 struct dp_reo_cache_flush_elem *elem, *tmp; 775 776 if (status == HAL_REO_CMD_DRAIN) { 777 goto free_desc; 778 } else if (status != HAL_REO_CMD_SUCCESS) { 779 /* Shouldn't happen! Cleanup in case of other failure? */ 780 ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 781 rx_tid->tid, status); 782 return; 783 } 784 785 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 786 if (!elem) 787 goto free_desc; 788 789 elem->ts = jiffies; 790 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 791 792 spin_lock_bh(&dp->reo_cmd_lock); 793 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 794 dp->reo_cmd_cache_flush_count++; 795 796 /* Flush and invalidate aged REO desc from HW cache */ 797 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 798 list) { 799 if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 800 time_after(jiffies, elem->ts + 801 msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 802 list_del(&elem->list); 803 dp->reo_cmd_cache_flush_count--; 804 spin_unlock_bh(&dp->reo_cmd_lock); 805 806 ath11k_dp_reo_cache_flush(ab, &elem->data); 807 kfree(elem); 808 spin_lock_bh(&dp->reo_cmd_lock); 809 } 810 } 811 spin_unlock_bh(&dp->reo_cmd_lock); 812 813 return; 814 free_desc: 815 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 816 DMA_BIDIRECTIONAL); 817 kfree(rx_tid->vaddr); 818 } 819 820 void ath11k_peer_rx_tid_delete(struct ath11k *ar, 821 struct ath11k_peer *peer, u8 tid) 822 { 823 struct ath11k_hal_reo_cmd cmd = {0}; 824 struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 825 int ret; 826 827 if (!rx_tid->active) 828 return; 829 830 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 831 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 832 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 833 cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 834 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 835 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 836 ath11k_dp_rx_tid_del_func); 837 if (ret) { 838 if (ret != -ESHUTDOWN) 839 ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 840 tid, ret); 841 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 842 DMA_BIDIRECTIONAL); 843 kfree(rx_tid->vaddr); 844 } 845 846 rx_tid->active = false; 847 } 848 849 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 850 u32 *link_desc, 851 enum hal_wbm_rel_bm_act action) 852 { 853 struct ath11k_dp *dp = &ab->dp; 854 struct hal_srng *srng; 855 u32 *desc; 856 int ret = 0; 857 858 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 859 860 spin_lock_bh(&srng->lock); 861 862 ath11k_hal_srng_access_begin(ab, srng); 863 864 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 865 if (!desc) { 866 ret = -ENOBUFS; 867 goto exit; 868 } 869 870 ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 871 action); 872 873 exit: 874 ath11k_hal_srng_access_end(ab, srng); 875 876 spin_unlock_bh(&srng->lock); 877 878 return ret; 879 } 880 881 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 882 { 883 struct ath11k_base *ab = rx_tid->ab; 884 885 lockdep_assert_held(&ab->base_lock); 886 887 if (rx_tid->dst_ring_desc) { 888 if (rel_link_desc) 889 ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 890 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 891 kfree(rx_tid->dst_ring_desc); 892 rx_tid->dst_ring_desc = NULL; 893 } 894 895 rx_tid->cur_sn = 0; 896 rx_tid->last_frag_no = 0; 897 rx_tid->rx_frag_bitmap = 0; 898 __skb_queue_purge(&rx_tid->rx_frags); 899 } 900 901 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer) 902 { 903 struct dp_rx_tid *rx_tid; 904 int i; 905 906 lockdep_assert_held(&ar->ab->base_lock); 907 908 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 909 rx_tid = &peer->rx_tid[i]; 910 911 spin_unlock_bh(&ar->ab->base_lock); 912 del_timer_sync(&rx_tid->frag_timer); 913 spin_lock_bh(&ar->ab->base_lock); 914 915 ath11k_dp_rx_frags_cleanup(rx_tid, true); 916 } 917 } 918 919 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 920 { 921 struct dp_rx_tid *rx_tid; 922 int i; 923 924 lockdep_assert_held(&ar->ab->base_lock); 925 926 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 927 rx_tid = &peer->rx_tid[i]; 928 929 ath11k_peer_rx_tid_delete(ar, peer, i); 930 ath11k_dp_rx_frags_cleanup(rx_tid, true); 931 932 spin_unlock_bh(&ar->ab->base_lock); 933 del_timer_sync(&rx_tid->frag_timer); 934 spin_lock_bh(&ar->ab->base_lock); 935 } 936 } 937 938 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 939 struct ath11k_peer *peer, 940 struct dp_rx_tid *rx_tid, 941 u32 ba_win_sz, u16 ssn, 942 bool update_ssn) 943 { 944 struct ath11k_hal_reo_cmd cmd = {0}; 945 int ret; 946 947 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 948 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 949 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 950 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 951 cmd.ba_window_size = ba_win_sz; 952 953 if (update_ssn) { 954 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 955 cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 956 } 957 958 ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 959 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 960 NULL); 961 if (ret) { 962 ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 963 rx_tid->tid, ret); 964 return ret; 965 } 966 967 rx_tid->ba_win_sz = ba_win_sz; 968 969 return 0; 970 } 971 972 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 973 const u8 *peer_mac, int vdev_id, u8 tid) 974 { 975 struct ath11k_peer *peer; 976 struct dp_rx_tid *rx_tid; 977 978 spin_lock_bh(&ab->base_lock); 979 980 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 981 if (!peer) { 982 ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 983 goto unlock_exit; 984 } 985 986 rx_tid = &peer->rx_tid[tid]; 987 if (!rx_tid->active) 988 goto unlock_exit; 989 990 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 991 DMA_BIDIRECTIONAL); 992 kfree(rx_tid->vaddr); 993 994 rx_tid->active = false; 995 996 unlock_exit: 997 spin_unlock_bh(&ab->base_lock); 998 } 999 1000 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 1001 u8 tid, u32 ba_win_sz, u16 ssn, 1002 enum hal_pn_type pn_type) 1003 { 1004 struct ath11k_base *ab = ar->ab; 1005 struct ath11k_peer *peer; 1006 struct dp_rx_tid *rx_tid; 1007 u32 hw_desc_sz; 1008 u32 *addr_aligned; 1009 void *vaddr; 1010 dma_addr_t paddr; 1011 int ret; 1012 1013 spin_lock_bh(&ab->base_lock); 1014 1015 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 1016 if (!peer) { 1017 ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); 1018 spin_unlock_bh(&ab->base_lock); 1019 return -ENOENT; 1020 } 1021 1022 rx_tid = &peer->rx_tid[tid]; 1023 /* Update the tid queue if it is already setup */ 1024 if (rx_tid->active) { 1025 paddr = rx_tid->paddr; 1026 ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1027 ba_win_sz, ssn, true); 1028 spin_unlock_bh(&ab->base_lock); 1029 if (ret) { 1030 ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1031 return ret; 1032 } 1033 1034 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1035 peer_mac, paddr, 1036 tid, 1, ba_win_sz); 1037 if (ret) 1038 ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", 1039 tid, ret); 1040 return ret; 1041 } 1042 1043 rx_tid->tid = tid; 1044 1045 rx_tid->ba_win_sz = ba_win_sz; 1046 1047 /* TODO: Optimize the memory allocation for qos tid based on 1048 * the actual BA window size in REO tid update path. 1049 */ 1050 if (tid == HAL_DESC_REO_NON_QOS_TID) 1051 hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 1052 else 1053 hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1054 1055 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1056 if (!vaddr) { 1057 spin_unlock_bh(&ab->base_lock); 1058 return -ENOMEM; 1059 } 1060 1061 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1062 1063 ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1064 ssn, pn_type); 1065 1066 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1067 DMA_BIDIRECTIONAL); 1068 1069 ret = dma_mapping_error(ab->dev, paddr); 1070 if (ret) { 1071 spin_unlock_bh(&ab->base_lock); 1072 goto err_mem_free; 1073 } 1074 1075 rx_tid->vaddr = vaddr; 1076 rx_tid->paddr = paddr; 1077 rx_tid->size = hw_desc_sz; 1078 rx_tid->active = true; 1079 1080 spin_unlock_bh(&ab->base_lock); 1081 1082 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1083 paddr, tid, 1, ba_win_sz); 1084 if (ret) { 1085 ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", 1086 tid, ret); 1087 ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 1088 } 1089 1090 return ret; 1091 1092 err_mem_free: 1093 kfree(vaddr); 1094 1095 return ret; 1096 } 1097 1098 int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 1099 struct ieee80211_ampdu_params *params) 1100 { 1101 struct ath11k_base *ab = ar->ab; 1102 struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1103 int vdev_id = arsta->arvif->vdev_id; 1104 int ret; 1105 1106 ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 1107 params->tid, params->buf_size, 1108 params->ssn, arsta->pn_type); 1109 if (ret) 1110 ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 1111 1112 return ret; 1113 } 1114 1115 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 1116 struct ieee80211_ampdu_params *params) 1117 { 1118 struct ath11k_base *ab = ar->ab; 1119 struct ath11k_peer *peer; 1120 struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1121 int vdev_id = arsta->arvif->vdev_id; 1122 dma_addr_t paddr; 1123 bool active; 1124 int ret; 1125 1126 spin_lock_bh(&ab->base_lock); 1127 1128 peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 1129 if (!peer) { 1130 ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1131 spin_unlock_bh(&ab->base_lock); 1132 return -ENOENT; 1133 } 1134 1135 paddr = peer->rx_tid[params->tid].paddr; 1136 active = peer->rx_tid[params->tid].active; 1137 1138 if (!active) { 1139 spin_unlock_bh(&ab->base_lock); 1140 return 0; 1141 } 1142 1143 ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1144 spin_unlock_bh(&ab->base_lock); 1145 if (ret) { 1146 ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1147 params->tid, ret); 1148 return ret; 1149 } 1150 1151 ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1152 params->sta->addr, paddr, 1153 params->tid, 1, 1); 1154 if (ret) 1155 ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1156 ret); 1157 1158 return ret; 1159 } 1160 1161 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 1162 const u8 *peer_addr, 1163 enum set_key_cmd key_cmd, 1164 struct ieee80211_key_conf *key) 1165 { 1166 struct ath11k *ar = arvif->ar; 1167 struct ath11k_base *ab = ar->ab; 1168 struct ath11k_hal_reo_cmd cmd = {0}; 1169 struct ath11k_peer *peer; 1170 struct dp_rx_tid *rx_tid; 1171 u8 tid; 1172 int ret = 0; 1173 1174 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1175 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1176 * for now. 1177 */ 1178 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1179 return 0; 1180 1181 cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 1182 cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 1183 HAL_REO_CMD_UPD0_PN_SIZE | 1184 HAL_REO_CMD_UPD0_PN_VALID | 1185 HAL_REO_CMD_UPD0_PN_CHECK | 1186 HAL_REO_CMD_UPD0_SVLD; 1187 1188 switch (key->cipher) { 1189 case WLAN_CIPHER_SUITE_TKIP: 1190 case WLAN_CIPHER_SUITE_CCMP: 1191 case WLAN_CIPHER_SUITE_CCMP_256: 1192 case WLAN_CIPHER_SUITE_GCMP: 1193 case WLAN_CIPHER_SUITE_GCMP_256: 1194 if (key_cmd == SET_KEY) { 1195 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1196 cmd.pn_size = 48; 1197 } 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 spin_lock_bh(&ab->base_lock); 1204 1205 peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 1206 if (!peer) { 1207 ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 1208 spin_unlock_bh(&ab->base_lock); 1209 return -ENOENT; 1210 } 1211 1212 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1213 rx_tid = &peer->rx_tid[tid]; 1214 if (!rx_tid->active) 1215 continue; 1216 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1217 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1218 ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 1219 HAL_REO_CMD_UPDATE_RX_QUEUE, 1220 &cmd, NULL); 1221 if (ret) { 1222 ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 1223 tid, ret); 1224 break; 1225 } 1226 } 1227 1228 spin_unlock_bh(&ab->base_lock); 1229 1230 return ret; 1231 } 1232 1233 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1234 u16 peer_id) 1235 { 1236 int i; 1237 1238 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1239 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1240 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1241 return i; 1242 } else { 1243 return i; 1244 } 1245 } 1246 1247 return -EINVAL; 1248 } 1249 1250 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1251 u16 tag, u16 len, const void *ptr, 1252 void *data) 1253 { 1254 struct htt_ppdu_stats_info *ppdu_info; 1255 struct htt_ppdu_user_stats *user_stats; 1256 int cur_user; 1257 u16 peer_id; 1258 1259 ppdu_info = (struct htt_ppdu_stats_info *)data; 1260 1261 switch (tag) { 1262 case HTT_PPDU_STATS_TAG_COMMON: 1263 if (len < sizeof(struct htt_ppdu_stats_common)) { 1264 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1265 len, tag); 1266 return -EINVAL; 1267 } 1268 memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1269 sizeof(struct htt_ppdu_stats_common)); 1270 break; 1271 case HTT_PPDU_STATS_TAG_USR_RATE: 1272 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1273 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1274 len, tag); 1275 return -EINVAL; 1276 } 1277 1278 peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1279 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1280 peer_id); 1281 if (cur_user < 0) 1282 return -EINVAL; 1283 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1284 user_stats->peer_id = peer_id; 1285 user_stats->is_valid_peer_id = true; 1286 memcpy((void *)&user_stats->rate, ptr, 1287 sizeof(struct htt_ppdu_stats_user_rate)); 1288 user_stats->tlv_flags |= BIT(tag); 1289 break; 1290 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1291 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1292 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1293 len, tag); 1294 return -EINVAL; 1295 } 1296 1297 peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1298 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1299 peer_id); 1300 if (cur_user < 0) 1301 return -EINVAL; 1302 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1303 user_stats->peer_id = peer_id; 1304 user_stats->is_valid_peer_id = true; 1305 memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1306 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1307 user_stats->tlv_flags |= BIT(tag); 1308 break; 1309 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1310 if (len < 1311 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1312 ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1313 len, tag); 1314 return -EINVAL; 1315 } 1316 1317 peer_id = 1318 ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1319 cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1320 peer_id); 1321 if (cur_user < 0) 1322 return -EINVAL; 1323 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1324 user_stats->peer_id = peer_id; 1325 user_stats->is_valid_peer_id = true; 1326 memcpy((void *)&user_stats->ack_ba, ptr, 1327 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1328 user_stats->tlv_flags |= BIT(tag); 1329 break; 1330 } 1331 return 0; 1332 } 1333 1334 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1335 int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1336 const void *ptr, void *data), 1337 void *data) 1338 { 1339 const struct htt_tlv *tlv; 1340 const void *begin = ptr; 1341 u16 tlv_tag, tlv_len; 1342 int ret = -EINVAL; 1343 1344 while (len > 0) { 1345 if (len < sizeof(*tlv)) { 1346 ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1347 ptr - begin, len, sizeof(*tlv)); 1348 return -EINVAL; 1349 } 1350 tlv = (struct htt_tlv *)ptr; 1351 tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1352 tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1353 ptr += sizeof(*tlv); 1354 len -= sizeof(*tlv); 1355 1356 if (tlv_len > len) { 1357 ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1358 tlv_tag, ptr - begin, len, tlv_len); 1359 return -EINVAL; 1360 } 1361 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1362 if (ret == -ENOMEM) 1363 return ret; 1364 1365 ptr += tlv_len; 1366 len -= tlv_len; 1367 } 1368 return 0; 1369 } 1370 1371 static void 1372 ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1373 struct htt_ppdu_stats *ppdu_stats, u8 user) 1374 { 1375 struct ath11k_base *ab = ar->ab; 1376 struct ath11k_peer *peer; 1377 struct ieee80211_sta *sta; 1378 struct ath11k_sta *arsta; 1379 struct htt_ppdu_stats_user_rate *user_rate; 1380 struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1381 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1382 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1383 int ret; 1384 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1385 u32 succ_bytes = 0; 1386 u16 rate = 0, succ_pkts = 0; 1387 u32 tx_duration = 0; 1388 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1389 bool is_ampdu = false; 1390 1391 if (!usr_stats) 1392 return; 1393 1394 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1395 return; 1396 1397 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1398 is_ampdu = 1399 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1400 1401 if (usr_stats->tlv_flags & 1402 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1403 succ_bytes = usr_stats->ack_ba.success_bytes; 1404 succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1405 usr_stats->ack_ba.info); 1406 tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1407 usr_stats->ack_ba.info); 1408 } 1409 1410 if (common->fes_duration_us) 1411 tx_duration = common->fes_duration_us; 1412 1413 user_rate = &usr_stats->rate; 1414 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1415 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1416 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1417 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1418 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1419 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1420 1421 /* Note: If host configured fixed rates and in some other special 1422 * cases, the broadcast/management frames are sent in different rates. 1423 * Firmware rate's control to be skipped for this? 1424 */ 1425 1426 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 1427 ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1428 return; 1429 } 1430 1431 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1432 ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1433 return; 1434 } 1435 1436 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1437 ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1438 mcs, nss); 1439 return; 1440 } 1441 1442 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1443 ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1444 flags, 1445 &rate_idx, 1446 &rate); 1447 if (ret < 0) 1448 return; 1449 } 1450 1451 rcu_read_lock(); 1452 spin_lock_bh(&ab->base_lock); 1453 peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1454 1455 if (!peer || !peer->sta) { 1456 spin_unlock_bh(&ab->base_lock); 1457 rcu_read_unlock(); 1458 return; 1459 } 1460 1461 sta = peer->sta; 1462 arsta = (struct ath11k_sta *)sta->drv_priv; 1463 1464 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1465 1466 switch (flags) { 1467 case WMI_RATE_PREAMBLE_OFDM: 1468 arsta->txrate.legacy = rate; 1469 break; 1470 case WMI_RATE_PREAMBLE_CCK: 1471 arsta->txrate.legacy = rate; 1472 break; 1473 case WMI_RATE_PREAMBLE_HT: 1474 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1475 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1476 if (sgi) 1477 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1478 break; 1479 case WMI_RATE_PREAMBLE_VHT: 1480 arsta->txrate.mcs = mcs; 1481 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1482 if (sgi) 1483 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1484 break; 1485 case WMI_RATE_PREAMBLE_HE: 1486 arsta->txrate.mcs = mcs; 1487 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1488 arsta->txrate.he_dcm = dcm; 1489 arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 1490 arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc 1491 ((user_rate->ru_end - 1492 user_rate->ru_start) + 1); 1493 break; 1494 } 1495 1496 arsta->txrate.nss = nss; 1497 1498 arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1499 arsta->tx_duration += tx_duration; 1500 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1501 1502 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1503 * So skip peer stats update for mgmt packets. 1504 */ 1505 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1506 memset(peer_stats, 0, sizeof(*peer_stats)); 1507 peer_stats->succ_pkts = succ_pkts; 1508 peer_stats->succ_bytes = succ_bytes; 1509 peer_stats->is_ampdu = is_ampdu; 1510 peer_stats->duration = tx_duration; 1511 peer_stats->ba_fails = 1512 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1513 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1514 1515 if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 1516 ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 1517 } 1518 1519 spin_unlock_bh(&ab->base_lock); 1520 rcu_read_unlock(); 1521 } 1522 1523 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1524 struct htt_ppdu_stats *ppdu_stats) 1525 { 1526 u8 user; 1527 1528 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1529 ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1530 } 1531 1532 static 1533 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1534 u32 ppdu_id) 1535 { 1536 struct htt_ppdu_stats_info *ppdu_info; 1537 1538 spin_lock_bh(&ar->data_lock); 1539 if (!list_empty(&ar->ppdu_stats_info)) { 1540 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1541 if (ppdu_info->ppdu_id == ppdu_id) { 1542 spin_unlock_bh(&ar->data_lock); 1543 return ppdu_info; 1544 } 1545 } 1546 1547 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1548 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1549 typeof(*ppdu_info), list); 1550 list_del(&ppdu_info->list); 1551 ar->ppdu_stat_list_depth--; 1552 ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1553 kfree(ppdu_info); 1554 } 1555 } 1556 spin_unlock_bh(&ar->data_lock); 1557 1558 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1559 if (!ppdu_info) 1560 return NULL; 1561 1562 spin_lock_bh(&ar->data_lock); 1563 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1564 ar->ppdu_stat_list_depth++; 1565 spin_unlock_bh(&ar->data_lock); 1566 1567 return ppdu_info; 1568 } 1569 1570 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1571 struct sk_buff *skb) 1572 { 1573 struct ath11k_htt_ppdu_stats_msg *msg; 1574 struct htt_ppdu_stats_info *ppdu_info; 1575 struct ath11k *ar; 1576 int ret; 1577 u8 pdev_id; 1578 u32 ppdu_id, len; 1579 1580 msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1581 len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1582 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1583 ppdu_id = msg->ppdu_id; 1584 1585 rcu_read_lock(); 1586 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1587 if (!ar) { 1588 ret = -EINVAL; 1589 goto exit; 1590 } 1591 1592 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) 1593 trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1594 1595 ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1596 if (!ppdu_info) { 1597 ret = -EINVAL; 1598 goto exit; 1599 } 1600 1601 ppdu_info->ppdu_id = ppdu_id; 1602 ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1603 ath11k_htt_tlv_ppdu_stats_parse, 1604 (void *)ppdu_info); 1605 if (ret) { 1606 ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1607 goto exit; 1608 } 1609 1610 exit: 1611 rcu_read_unlock(); 1612 1613 return ret; 1614 } 1615 1616 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1617 { 1618 struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1619 struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1620 struct ath11k *ar; 1621 u8 pdev_id; 1622 1623 pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1624 ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1625 if (!ar) { 1626 ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1627 return; 1628 } 1629 1630 trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 1631 ar->ab->pktlog_defs_checksum); 1632 } 1633 1634 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1635 struct sk_buff *skb) 1636 { 1637 u32 *data = (u32 *)skb->data; 1638 u8 pdev_id, ring_type, ring_id, pdev_idx; 1639 u16 hp, tp; 1640 u32 backpressure_time; 1641 struct ath11k_bp_stats *bp_stats; 1642 1643 pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1644 ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1645 ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1646 ++data; 1647 1648 hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1649 tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1650 ++data; 1651 1652 backpressure_time = *data; 1653 1654 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1655 pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 1656 1657 if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { 1658 if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) 1659 return; 1660 1661 bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; 1662 } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { 1663 pdev_idx = DP_HW2SW_MACID(pdev_id); 1664 1665 if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) 1666 return; 1667 1668 bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; 1669 } else { 1670 ath11k_warn(ab, "unknown ring type received in htt bp event %d\n", 1671 ring_type); 1672 return; 1673 } 1674 1675 spin_lock_bh(&ab->base_lock); 1676 bp_stats->hp = hp; 1677 bp_stats->tp = tp; 1678 bp_stats->count++; 1679 bp_stats->jiffies = jiffies; 1680 spin_unlock_bh(&ab->base_lock); 1681 } 1682 1683 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1684 struct sk_buff *skb) 1685 { 1686 struct ath11k_dp *dp = &ab->dp; 1687 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1688 enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1689 u16 peer_id; 1690 u8 vdev_id; 1691 u8 mac_addr[ETH_ALEN]; 1692 u16 peer_mac_h16; 1693 u16 ast_hash; 1694 u16 hw_peer_id; 1695 1696 ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1697 1698 switch (type) { 1699 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1700 dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1701 resp->version_msg.version); 1702 dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1703 resp->version_msg.version); 1704 complete(&dp->htt_tgt_version_received); 1705 break; 1706 case HTT_T2H_MSG_TYPE_PEER_MAP: 1707 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1708 resp->peer_map_ev.info); 1709 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1710 resp->peer_map_ev.info); 1711 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1712 resp->peer_map_ev.info1); 1713 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1714 peer_mac_h16, mac_addr); 1715 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1716 break; 1717 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1718 vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1719 resp->peer_map_ev.info); 1720 peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1721 resp->peer_map_ev.info); 1722 peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1723 resp->peer_map_ev.info1); 1724 ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1725 peer_mac_h16, mac_addr); 1726 ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 1727 resp->peer_map_ev.info2); 1728 hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID, 1729 resp->peer_map_ev.info1); 1730 ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1731 hw_peer_id); 1732 break; 1733 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1734 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1735 peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1736 resp->peer_unmap_ev.info); 1737 ath11k_peer_unmap_event(ab, peer_id); 1738 break; 1739 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1740 ath11k_htt_pull_ppdu_stats(ab, skb); 1741 break; 1742 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1743 ath11k_debugfs_htt_ext_stats_handler(ab, skb); 1744 break; 1745 case HTT_T2H_MSG_TYPE_PKTLOG: 1746 ath11k_htt_pktlog(ab, skb); 1747 break; 1748 case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1749 ath11k_htt_backpressure_event_handler(ab, skb); 1750 break; 1751 default: 1752 ath11k_warn(ab, "htt event %d not handled\n", type); 1753 break; 1754 } 1755 1756 dev_kfree_skb_any(skb); 1757 } 1758 1759 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1760 struct sk_buff_head *msdu_list, 1761 struct sk_buff *first, struct sk_buff *last, 1762 u8 l3pad_bytes, int msdu_len) 1763 { 1764 struct ath11k_base *ab = ar->ab; 1765 struct sk_buff *skb; 1766 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1767 int buf_first_hdr_len, buf_first_len; 1768 struct hal_rx_desc *ldesc; 1769 int space_extra, rem_len, buf_len; 1770 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 1771 1772 /* As the msdu is spread across multiple rx buffers, 1773 * find the offset to the start of msdu for computing 1774 * the length of the msdu in the first buffer. 1775 */ 1776 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1777 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1778 1779 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1780 skb_put(first, buf_first_hdr_len + msdu_len); 1781 skb_pull(first, buf_first_hdr_len); 1782 return 0; 1783 } 1784 1785 ldesc = (struct hal_rx_desc *)last->data; 1786 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc); 1787 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc); 1788 1789 /* MSDU spans over multiple buffers because the length of the MSDU 1790 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1791 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1792 */ 1793 skb_put(first, DP_RX_BUFFER_SIZE); 1794 skb_pull(first, buf_first_hdr_len); 1795 1796 /* When an MSDU spread over multiple buffers attention, MSDU_END and 1797 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 1798 */ 1799 ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1800 1801 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1802 if (space_extra > 0 && 1803 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1804 /* Free up all buffers of the MSDU */ 1805 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1806 rxcb = ATH11K_SKB_RXCB(skb); 1807 if (!rxcb->is_continuation) { 1808 dev_kfree_skb_any(skb); 1809 break; 1810 } 1811 dev_kfree_skb_any(skb); 1812 } 1813 return -ENOMEM; 1814 } 1815 1816 rem_len = msdu_len - buf_first_len; 1817 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1818 rxcb = ATH11K_SKB_RXCB(skb); 1819 if (rxcb->is_continuation) 1820 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1821 else 1822 buf_len = rem_len; 1823 1824 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1825 WARN_ON_ONCE(1); 1826 dev_kfree_skb_any(skb); 1827 return -EINVAL; 1828 } 1829 1830 skb_put(skb, buf_len + hal_rx_desc_sz); 1831 skb_pull(skb, hal_rx_desc_sz); 1832 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1833 buf_len); 1834 dev_kfree_skb_any(skb); 1835 1836 rem_len -= buf_len; 1837 if (!rxcb->is_continuation) 1838 break; 1839 } 1840 1841 return 0; 1842 } 1843 1844 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1845 struct sk_buff *first) 1846 { 1847 struct sk_buff *skb; 1848 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1849 1850 if (!rxcb->is_continuation) 1851 return first; 1852 1853 skb_queue_walk(msdu_list, skb) { 1854 rxcb = ATH11K_SKB_RXCB(skb); 1855 if (!rxcb->is_continuation) 1856 return skb; 1857 } 1858 1859 return NULL; 1860 } 1861 1862 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu) 1863 { 1864 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1865 struct rx_attention *rx_attention; 1866 bool ip_csum_fail, l4_csum_fail; 1867 1868 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc); 1869 ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention); 1870 l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention); 1871 1872 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1873 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1874 } 1875 1876 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1877 enum hal_encrypt_type enctype) 1878 { 1879 switch (enctype) { 1880 case HAL_ENCRYPT_TYPE_OPEN: 1881 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1882 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1883 return 0; 1884 case HAL_ENCRYPT_TYPE_CCMP_128: 1885 return IEEE80211_CCMP_MIC_LEN; 1886 case HAL_ENCRYPT_TYPE_CCMP_256: 1887 return IEEE80211_CCMP_256_MIC_LEN; 1888 case HAL_ENCRYPT_TYPE_GCMP_128: 1889 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1890 return IEEE80211_GCMP_MIC_LEN; 1891 case HAL_ENCRYPT_TYPE_WEP_40: 1892 case HAL_ENCRYPT_TYPE_WEP_104: 1893 case HAL_ENCRYPT_TYPE_WEP_128: 1894 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1895 case HAL_ENCRYPT_TYPE_WAPI: 1896 break; 1897 } 1898 1899 ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1900 return 0; 1901 } 1902 1903 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1904 enum hal_encrypt_type enctype) 1905 { 1906 switch (enctype) { 1907 case HAL_ENCRYPT_TYPE_OPEN: 1908 return 0; 1909 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1910 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1911 return IEEE80211_TKIP_IV_LEN; 1912 case HAL_ENCRYPT_TYPE_CCMP_128: 1913 return IEEE80211_CCMP_HDR_LEN; 1914 case HAL_ENCRYPT_TYPE_CCMP_256: 1915 return IEEE80211_CCMP_256_HDR_LEN; 1916 case HAL_ENCRYPT_TYPE_GCMP_128: 1917 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1918 return IEEE80211_GCMP_HDR_LEN; 1919 case HAL_ENCRYPT_TYPE_WEP_40: 1920 case HAL_ENCRYPT_TYPE_WEP_104: 1921 case HAL_ENCRYPT_TYPE_WEP_128: 1922 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1923 case HAL_ENCRYPT_TYPE_WAPI: 1924 break; 1925 } 1926 1927 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1928 return 0; 1929 } 1930 1931 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1932 enum hal_encrypt_type enctype) 1933 { 1934 switch (enctype) { 1935 case HAL_ENCRYPT_TYPE_OPEN: 1936 case HAL_ENCRYPT_TYPE_CCMP_128: 1937 case HAL_ENCRYPT_TYPE_CCMP_256: 1938 case HAL_ENCRYPT_TYPE_GCMP_128: 1939 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1940 return 0; 1941 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1942 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1943 return IEEE80211_TKIP_ICV_LEN; 1944 case HAL_ENCRYPT_TYPE_WEP_40: 1945 case HAL_ENCRYPT_TYPE_WEP_104: 1946 case HAL_ENCRYPT_TYPE_WEP_128: 1947 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1948 case HAL_ENCRYPT_TYPE_WAPI: 1949 break; 1950 } 1951 1952 ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1953 return 0; 1954 } 1955 1956 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1957 struct sk_buff *msdu, 1958 u8 *first_hdr, 1959 enum hal_encrypt_type enctype, 1960 struct ieee80211_rx_status *status) 1961 { 1962 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1963 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1964 struct ieee80211_hdr *hdr; 1965 size_t hdr_len; 1966 u8 da[ETH_ALEN]; 1967 u8 sa[ETH_ALEN]; 1968 u16 qos_ctl = 0; 1969 u8 *qos; 1970 1971 /* copy SA & DA and pull decapped header */ 1972 hdr = (struct ieee80211_hdr *)msdu->data; 1973 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1974 ether_addr_copy(da, ieee80211_get_DA(hdr)); 1975 ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1976 skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1977 1978 if (rxcb->is_first_msdu) { 1979 /* original 802.11 header is valid for the first msdu 1980 * hence we can reuse the same header 1981 */ 1982 hdr = (struct ieee80211_hdr *)first_hdr; 1983 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1984 1985 /* Each A-MSDU subframe will be reported as a separate MSDU, 1986 * so strip the A-MSDU bit from QoS Ctl. 1987 */ 1988 if (ieee80211_is_data_qos(hdr->frame_control)) { 1989 qos = ieee80211_get_qos_ctl(hdr); 1990 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 1991 } 1992 } else { 1993 /* Rebuild qos header if this is a middle/last msdu */ 1994 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1995 1996 /* Reset the order bit as the HT_Control header is stripped */ 1997 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1998 1999 qos_ctl = rxcb->tid; 2000 2001 if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc)) 2002 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2003 2004 /* TODO Add other QoS ctl fields when required */ 2005 2006 /* copy decap header before overwriting for reuse below */ 2007 memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 2008 } 2009 2010 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2011 memcpy(skb_push(msdu, 2012 ath11k_dp_rx_crypto_param_len(ar, enctype)), 2013 (void *)hdr + hdr_len, 2014 ath11k_dp_rx_crypto_param_len(ar, enctype)); 2015 } 2016 2017 if (!rxcb->is_first_msdu) { 2018 memcpy(skb_push(msdu, 2019 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2020 IEEE80211_QOS_CTL_LEN); 2021 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2022 return; 2023 } 2024 2025 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2026 2027 /* original 802.11 header has a different DA and in 2028 * case of 4addr it may also have different SA 2029 */ 2030 hdr = (struct ieee80211_hdr *)msdu->data; 2031 ether_addr_copy(ieee80211_get_DA(hdr), da); 2032 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2033 } 2034 2035 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 2036 enum hal_encrypt_type enctype, 2037 struct ieee80211_rx_status *status, 2038 bool decrypted) 2039 { 2040 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2041 struct ieee80211_hdr *hdr; 2042 size_t hdr_len; 2043 size_t crypto_len; 2044 2045 if (!rxcb->is_first_msdu || 2046 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2047 WARN_ON_ONCE(1); 2048 return; 2049 } 2050 2051 skb_trim(msdu, msdu->len - FCS_LEN); 2052 2053 if (!decrypted) 2054 return; 2055 2056 hdr = (void *)msdu->data; 2057 2058 /* Tail */ 2059 if (status->flag & RX_FLAG_IV_STRIPPED) { 2060 skb_trim(msdu, msdu->len - 2061 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2062 2063 skb_trim(msdu, msdu->len - 2064 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2065 } else { 2066 /* MIC */ 2067 if (status->flag & RX_FLAG_MIC_STRIPPED) 2068 skb_trim(msdu, msdu->len - 2069 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2070 2071 /* ICV */ 2072 if (status->flag & RX_FLAG_ICV_STRIPPED) 2073 skb_trim(msdu, msdu->len - 2074 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2075 } 2076 2077 /* MMIC */ 2078 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2079 !ieee80211_has_morefrags(hdr->frame_control) && 2080 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2081 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2082 2083 /* Head */ 2084 if (status->flag & RX_FLAG_IV_STRIPPED) { 2085 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2086 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2087 2088 memmove((void *)msdu->data + crypto_len, 2089 (void *)msdu->data, hdr_len); 2090 skb_pull(msdu, crypto_len); 2091 } 2092 } 2093 2094 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 2095 struct sk_buff *msdu, 2096 enum hal_encrypt_type enctype) 2097 { 2098 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2099 struct ieee80211_hdr *hdr; 2100 size_t hdr_len, crypto_len; 2101 void *rfc1042; 2102 bool is_amsdu; 2103 2104 is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 2105 hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc); 2106 rfc1042 = hdr; 2107 2108 if (rxcb->is_first_msdu) { 2109 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2110 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2111 2112 rfc1042 += hdr_len + crypto_len; 2113 } 2114 2115 if (is_amsdu) 2116 rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 2117 2118 return rfc1042; 2119 } 2120 2121 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 2122 struct sk_buff *msdu, 2123 u8 *first_hdr, 2124 enum hal_encrypt_type enctype, 2125 struct ieee80211_rx_status *status) 2126 { 2127 struct ieee80211_hdr *hdr; 2128 struct ethhdr *eth; 2129 size_t hdr_len; 2130 u8 da[ETH_ALEN]; 2131 u8 sa[ETH_ALEN]; 2132 void *rfc1042; 2133 2134 rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 2135 if (WARN_ON_ONCE(!rfc1042)) 2136 return; 2137 2138 /* pull decapped header and copy SA & DA */ 2139 eth = (struct ethhdr *)msdu->data; 2140 ether_addr_copy(da, eth->h_dest); 2141 ether_addr_copy(sa, eth->h_source); 2142 skb_pull(msdu, sizeof(struct ethhdr)); 2143 2144 /* push rfc1042/llc/snap */ 2145 memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 2146 sizeof(struct ath11k_dp_rfc1042_hdr)); 2147 2148 /* push original 802.11 header */ 2149 hdr = (struct ieee80211_hdr *)first_hdr; 2150 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2151 2152 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2153 memcpy(skb_push(msdu, 2154 ath11k_dp_rx_crypto_param_len(ar, enctype)), 2155 (void *)hdr + hdr_len, 2156 ath11k_dp_rx_crypto_param_len(ar, enctype)); 2157 } 2158 2159 memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2160 2161 /* original 802.11 header has a different DA and in 2162 * case of 4addr it may also have different SA 2163 */ 2164 hdr = (struct ieee80211_hdr *)msdu->data; 2165 ether_addr_copy(ieee80211_get_DA(hdr), da); 2166 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2167 } 2168 2169 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 2170 struct hal_rx_desc *rx_desc, 2171 enum hal_encrypt_type enctype, 2172 struct ieee80211_rx_status *status, 2173 bool decrypted) 2174 { 2175 u8 *first_hdr; 2176 u8 decap; 2177 struct ethhdr *ehdr; 2178 2179 first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 2180 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc); 2181 2182 switch (decap) { 2183 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2184 ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2185 enctype, status); 2186 break; 2187 case DP_RX_DECAP_TYPE_RAW: 2188 ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2189 decrypted); 2190 break; 2191 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2192 ehdr = (struct ethhdr *)msdu->data; 2193 2194 /* mac80211 allows fast path only for authorized STA */ 2195 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2196 ATH11K_SKB_RXCB(msdu)->is_eapol = true; 2197 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2198 enctype, status); 2199 break; 2200 } 2201 2202 /* PN for mcast packets will be validated in mac80211; 2203 * remove eth header and add 802.11 header. 2204 */ 2205 if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2206 ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2207 enctype, status); 2208 break; 2209 case DP_RX_DECAP_TYPE_8023: 2210 /* TODO: Handle undecap for these formats */ 2211 break; 2212 } 2213 } 2214 2215 static struct ath11k_peer * 2216 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu) 2217 { 2218 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2219 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2220 struct ath11k_peer *peer = NULL; 2221 2222 lockdep_assert_held(&ab->base_lock); 2223 2224 if (rxcb->peer_id) 2225 peer = ath11k_peer_find_by_id(ab, rxcb->peer_id); 2226 2227 if (peer) 2228 return peer; 2229 2230 if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2231 return NULL; 2232 2233 peer = ath11k_peer_find_by_addr(ab, 2234 ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc)); 2235 return peer; 2236 } 2237 2238 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2239 struct sk_buff *msdu, 2240 struct hal_rx_desc *rx_desc, 2241 struct ieee80211_rx_status *rx_status) 2242 { 2243 bool fill_crypto_hdr; 2244 enum hal_encrypt_type enctype; 2245 bool is_decrypted = false; 2246 struct ath11k_skb_rxcb *rxcb; 2247 struct ieee80211_hdr *hdr; 2248 struct ath11k_peer *peer; 2249 struct rx_attention *rx_attention; 2250 u32 err_bitmap; 2251 2252 /* PN for multicast packets will be checked in mac80211 */ 2253 rxcb = ATH11K_SKB_RXCB(msdu); 2254 fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 2255 rxcb->is_mcbc = fill_crypto_hdr; 2256 2257 if (rxcb->is_mcbc) { 2258 rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 2259 rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 2260 } 2261 2262 spin_lock_bh(&ar->ab->base_lock); 2263 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2264 if (peer) { 2265 if (rxcb->is_mcbc) 2266 enctype = peer->sec_type_grp; 2267 else 2268 enctype = peer->sec_type; 2269 } else { 2270 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 2271 } 2272 spin_unlock_bh(&ar->ab->base_lock); 2273 2274 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 2275 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 2276 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2277 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 2278 2279 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2280 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2281 RX_FLAG_MMIC_ERROR | 2282 RX_FLAG_DECRYPTED | 2283 RX_FLAG_IV_STRIPPED | 2284 RX_FLAG_MMIC_STRIPPED); 2285 2286 if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2287 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2288 if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2289 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2290 2291 if (is_decrypted) { 2292 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2293 2294 if (fill_crypto_hdr) 2295 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2296 RX_FLAG_ICV_STRIPPED; 2297 else 2298 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2299 RX_FLAG_PN_VALIDATED; 2300 } 2301 2302 ath11k_dp_rx_h_csum_offload(ar, msdu); 2303 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2304 enctype, rx_status, is_decrypted); 2305 2306 if (!is_decrypted || fill_crypto_hdr) 2307 return; 2308 2309 if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) != 2310 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2311 hdr = (void *)msdu->data; 2312 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2313 } 2314 } 2315 2316 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2317 struct ieee80211_rx_status *rx_status) 2318 { 2319 struct ieee80211_supported_band *sband; 2320 enum rx_msdu_start_pkt_type pkt_type; 2321 u8 bw; 2322 u8 rate_mcs, nss; 2323 u8 sgi; 2324 bool is_cck, is_ldpc; 2325 2326 pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc); 2327 bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc); 2328 rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc); 2329 nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc); 2330 sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc); 2331 2332 switch (pkt_type) { 2333 case RX_MSDU_START_PKT_TYPE_11A: 2334 case RX_MSDU_START_PKT_TYPE_11B: 2335 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2336 sband = &ar->mac.sbands[rx_status->band]; 2337 rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2338 is_cck); 2339 break; 2340 case RX_MSDU_START_PKT_TYPE_11N: 2341 rx_status->encoding = RX_ENC_HT; 2342 if (rate_mcs > ATH11K_HT_MCS_MAX) { 2343 ath11k_warn(ar->ab, 2344 "Received with invalid mcs in HT mode %d\n", 2345 rate_mcs); 2346 break; 2347 } 2348 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2349 if (sgi) 2350 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2351 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2352 break; 2353 case RX_MSDU_START_PKT_TYPE_11AC: 2354 rx_status->encoding = RX_ENC_VHT; 2355 rx_status->rate_idx = rate_mcs; 2356 if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2357 ath11k_warn(ar->ab, 2358 "Received with invalid mcs in VHT mode %d\n", 2359 rate_mcs); 2360 break; 2361 } 2362 rx_status->nss = nss; 2363 if (sgi) 2364 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2365 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2366 is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc); 2367 if (is_ldpc) 2368 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2369 break; 2370 case RX_MSDU_START_PKT_TYPE_11AX: 2371 rx_status->rate_idx = rate_mcs; 2372 if (rate_mcs > ATH11K_HE_MCS_MAX) { 2373 ath11k_warn(ar->ab, 2374 "Received with invalid mcs in HE mode %d\n", 2375 rate_mcs); 2376 break; 2377 } 2378 rx_status->encoding = RX_ENC_HE; 2379 rx_status->nss = nss; 2380 rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 2381 rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2382 break; 2383 } 2384 } 2385 2386 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2387 struct ieee80211_rx_status *rx_status) 2388 { 2389 u8 channel_num; 2390 u32 center_freq, meta_data; 2391 struct ieee80211_channel *channel; 2392 2393 rx_status->freq = 0; 2394 rx_status->rate_idx = 0; 2395 rx_status->nss = 0; 2396 rx_status->encoding = RX_ENC_LEGACY; 2397 rx_status->bw = RATE_INFO_BW_20; 2398 2399 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2400 2401 meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc); 2402 channel_num = meta_data; 2403 center_freq = meta_data >> 16; 2404 2405 if (center_freq >= ATH11K_MIN_6G_FREQ && 2406 center_freq <= ATH11K_MAX_6G_FREQ) { 2407 rx_status->band = NL80211_BAND_6GHZ; 2408 rx_status->freq = center_freq; 2409 } else if (channel_num >= 1 && channel_num <= 14) { 2410 rx_status->band = NL80211_BAND_2GHZ; 2411 } else if (channel_num >= 36 && channel_num <= 173) { 2412 rx_status->band = NL80211_BAND_5GHZ; 2413 } else { 2414 spin_lock_bh(&ar->data_lock); 2415 channel = ar->rx_channel; 2416 if (channel) { 2417 rx_status->band = channel->band; 2418 channel_num = 2419 ieee80211_frequency_to_channel(channel->center_freq); 2420 } 2421 spin_unlock_bh(&ar->data_lock); 2422 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2423 rx_desc, sizeof(struct hal_rx_desc)); 2424 } 2425 2426 if (rx_status->band != NL80211_BAND_6GHZ) 2427 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2428 rx_status->band); 2429 2430 ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2431 } 2432 2433 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 2434 struct sk_buff *msdu, 2435 struct ieee80211_rx_status *status) 2436 { 2437 static const struct ieee80211_radiotap_he known = { 2438 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2439 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2440 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2441 }; 2442 struct ieee80211_rx_status *rx_status; 2443 struct ieee80211_radiotap_he *he = NULL; 2444 struct ieee80211_sta *pubsta = NULL; 2445 struct ath11k_peer *peer; 2446 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2447 u8 decap = DP_RX_DECAP_TYPE_RAW; 2448 bool is_mcbc = rxcb->is_mcbc; 2449 bool is_eapol = rxcb->is_eapol; 2450 2451 if (status->encoding == RX_ENC_HE && 2452 !(status->flag & RX_FLAG_RADIOTAP_HE) && 2453 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2454 he = skb_push(msdu, sizeof(known)); 2455 memcpy(he, &known, sizeof(known)); 2456 status->flag |= RX_FLAG_RADIOTAP_HE; 2457 } 2458 2459 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2460 decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc); 2461 2462 spin_lock_bh(&ar->ab->base_lock); 2463 peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2464 if (peer && peer->sta) 2465 pubsta = peer->sta; 2466 spin_unlock_bh(&ar->ab->base_lock); 2467 2468 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 2469 "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2470 msdu, 2471 msdu->len, 2472 peer ? peer->addr : NULL, 2473 rxcb->tid, 2474 is_mcbc ? "mcast" : "ucast", 2475 rxcb->seq_no, 2476 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2477 (status->encoding == RX_ENC_HT) ? "ht" : "", 2478 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2479 (status->encoding == RX_ENC_HE) ? "he" : "", 2480 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2481 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2482 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2483 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2484 status->rate_idx, 2485 status->nss, 2486 status->freq, 2487 status->band, status->flag, 2488 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2489 !!(status->flag & RX_FLAG_MMIC_ERROR), 2490 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2491 2492 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ", 2493 msdu->data, msdu->len); 2494 2495 rx_status = IEEE80211_SKB_RXCB(msdu); 2496 *rx_status = *status; 2497 2498 /* TODO: trace rx packet */ 2499 2500 /* PN for multicast packets are not validate in HW, 2501 * so skip 802.3 rx path 2502 * Also, fast_rx expectes the STA to be authorized, hence 2503 * eapol packets are sent in slow path. 2504 */ 2505 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2506 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2507 rx_status->flag |= RX_FLAG_8023; 2508 2509 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 2510 } 2511 2512 static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2513 struct sk_buff *msdu, 2514 struct sk_buff_head *msdu_list, 2515 struct ieee80211_rx_status *rx_status) 2516 { 2517 struct ath11k_base *ab = ar->ab; 2518 struct hal_rx_desc *rx_desc, *lrx_desc; 2519 struct rx_attention *rx_attention; 2520 struct ath11k_skb_rxcb *rxcb; 2521 struct sk_buff *last_buf; 2522 u8 l3_pad_bytes; 2523 u8 *hdr_status; 2524 u16 msdu_len; 2525 int ret; 2526 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 2527 2528 last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2529 if (!last_buf) { 2530 ath11k_warn(ab, 2531 "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2532 ret = -EIO; 2533 goto free_out; 2534 } 2535 2536 rx_desc = (struct hal_rx_desc *)msdu->data; 2537 if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) { 2538 ath11k_warn(ar->ab, "msdu len not valid\n"); 2539 ret = -EIO; 2540 goto free_out; 2541 } 2542 2543 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2544 rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc); 2545 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 2546 ath11k_warn(ab, "msdu_done bit in attention is not set\n"); 2547 ret = -EIO; 2548 goto free_out; 2549 } 2550 2551 rxcb = ATH11K_SKB_RXCB(msdu); 2552 rxcb->rx_desc = rx_desc; 2553 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc); 2554 l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc); 2555 2556 if (rxcb->is_frag) { 2557 skb_pull(msdu, hal_rx_desc_sz); 2558 } else if (!rxcb->is_continuation) { 2559 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2560 hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc); 2561 ret = -EINVAL; 2562 ath11k_warn(ab, "invalid msdu len %u\n", msdu_len); 2563 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2564 sizeof(struct ieee80211_hdr)); 2565 ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2566 sizeof(struct hal_rx_desc)); 2567 goto free_out; 2568 } 2569 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2570 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2571 } else { 2572 ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2573 msdu, last_buf, 2574 l3_pad_bytes, msdu_len); 2575 if (ret) { 2576 ath11k_warn(ab, 2577 "failed to coalesce msdu rx buffer%d\n", ret); 2578 goto free_out; 2579 } 2580 } 2581 2582 ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2583 ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2584 2585 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2586 2587 return 0; 2588 2589 free_out: 2590 return ret; 2591 } 2592 2593 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2594 struct napi_struct *napi, 2595 struct sk_buff_head *msdu_list, 2596 int mac_id) 2597 { 2598 struct sk_buff *msdu; 2599 struct ath11k *ar; 2600 struct ieee80211_rx_status rx_status = {0}; 2601 int ret; 2602 2603 if (skb_queue_empty(msdu_list)) 2604 return; 2605 2606 if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) { 2607 __skb_queue_purge(msdu_list); 2608 return; 2609 } 2610 2611 ar = ab->pdevs[mac_id].ar; 2612 if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) { 2613 __skb_queue_purge(msdu_list); 2614 return; 2615 } 2616 2617 while ((msdu = __skb_dequeue(msdu_list))) { 2618 ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2619 if (unlikely(ret)) { 2620 ath11k_dbg(ab, ATH11K_DBG_DATA, 2621 "Unable to process msdu %d", ret); 2622 dev_kfree_skb_any(msdu); 2623 continue; 2624 } 2625 2626 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2627 } 2628 } 2629 2630 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2631 struct napi_struct *napi, int budget) 2632 { 2633 struct ath11k_dp *dp = &ab->dp; 2634 struct dp_rxdma_ring *rx_ring; 2635 int num_buffs_reaped[MAX_RADIOS] = {0}; 2636 struct sk_buff_head msdu_list[MAX_RADIOS]; 2637 struct ath11k_skb_rxcb *rxcb; 2638 int total_msdu_reaped = 0; 2639 struct hal_srng *srng; 2640 struct sk_buff *msdu; 2641 bool done = false; 2642 int buf_id, mac_id; 2643 struct ath11k *ar; 2644 struct hal_reo_dest_ring *desc; 2645 enum hal_reo_dest_ring_push_reason push_reason; 2646 u32 cookie; 2647 int i; 2648 2649 for (i = 0; i < MAX_RADIOS; i++) 2650 __skb_queue_head_init(&msdu_list[i]); 2651 2652 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2653 2654 spin_lock_bh(&srng->lock); 2655 2656 try_again: 2657 ath11k_hal_srng_access_begin(ab, srng); 2658 2659 while (likely(desc = 2660 (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab, 2661 srng))) { 2662 cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 2663 desc->buf_addr_info.info1); 2664 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2665 cookie); 2666 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2667 2668 ar = ab->pdevs[mac_id].ar; 2669 rx_ring = &ar->dp.rx_refill_buf_ring; 2670 spin_lock_bh(&rx_ring->idr_lock); 2671 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 2672 if (unlikely(!msdu)) { 2673 ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2674 buf_id); 2675 spin_unlock_bh(&rx_ring->idr_lock); 2676 continue; 2677 } 2678 2679 idr_remove(&rx_ring->bufs_idr, buf_id); 2680 spin_unlock_bh(&rx_ring->idr_lock); 2681 2682 rxcb = ATH11K_SKB_RXCB(msdu); 2683 dma_unmap_single(ab->dev, rxcb->paddr, 2684 msdu->len + skb_tailroom(msdu), 2685 DMA_FROM_DEVICE); 2686 2687 num_buffs_reaped[mac_id]++; 2688 2689 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 2690 desc->info0); 2691 if (unlikely(push_reason != 2692 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) { 2693 dev_kfree_skb_any(msdu); 2694 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2695 continue; 2696 } 2697 2698 rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 & 2699 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2700 rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 & 2701 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2702 rxcb->is_continuation = !!(desc->rx_msdu_info.info0 & 2703 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2704 rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID, 2705 desc->rx_mpdu_info.meta_data); 2706 rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM, 2707 desc->rx_mpdu_info.info0); 2708 rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 2709 desc->info0); 2710 2711 rxcb->mac_id = mac_id; 2712 __skb_queue_tail(&msdu_list[mac_id], msdu); 2713 2714 if (rxcb->is_continuation) { 2715 done = false; 2716 } else { 2717 total_msdu_reaped++; 2718 done = true; 2719 } 2720 2721 if (total_msdu_reaped >= budget) 2722 break; 2723 } 2724 2725 /* Hw might have updated the head pointer after we cached it. 2726 * In this case, even though there are entries in the ring we'll 2727 * get rx_desc NULL. Give the read another try with updated cached 2728 * head pointer so that we can reap complete MPDU in the current 2729 * rx processing. 2730 */ 2731 if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) { 2732 ath11k_hal_srng_access_end(ab, srng); 2733 goto try_again; 2734 } 2735 2736 ath11k_hal_srng_access_end(ab, srng); 2737 2738 spin_unlock_bh(&srng->lock); 2739 2740 if (unlikely(!total_msdu_reaped)) 2741 goto exit; 2742 2743 for (i = 0; i < ab->num_radios; i++) { 2744 if (!num_buffs_reaped[i]) 2745 continue; 2746 2747 ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i); 2748 2749 ar = ab->pdevs[i].ar; 2750 rx_ring = &ar->dp.rx_refill_buf_ring; 2751 2752 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 2753 ab->hw_params.hal_params->rx_buf_rbm); 2754 } 2755 exit: 2756 return total_msdu_reaped; 2757 } 2758 2759 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2760 struct hal_rx_mon_ppdu_info *ppdu_info) 2761 { 2762 struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2763 u32 num_msdu; 2764 int i; 2765 2766 if (!rx_stats) 2767 return; 2768 2769 arsta->rssi_comb = ppdu_info->rssi_comb; 2770 ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb); 2771 2772 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2773 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2774 2775 rx_stats->num_msdu += num_msdu; 2776 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2777 ppdu_info->tcp_ack_msdu_count; 2778 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2779 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2780 2781 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2782 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2783 ppdu_info->nss = 1; 2784 ppdu_info->mcs = HAL_RX_MAX_MCS; 2785 ppdu_info->tid = IEEE80211_NUM_TIDS; 2786 } 2787 2788 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2789 rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2790 2791 if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2792 rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2793 2794 if (ppdu_info->gi < HAL_RX_GI_MAX) 2795 rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2796 2797 if (ppdu_info->bw < HAL_RX_BW_MAX) 2798 rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2799 2800 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2801 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2802 2803 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2804 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2805 2806 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2807 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2808 2809 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2810 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2811 2812 if (ppdu_info->is_stbc) 2813 rx_stats->stbc_count += num_msdu; 2814 2815 if (ppdu_info->beamformed) 2816 rx_stats->beamformed_count += num_msdu; 2817 2818 if (ppdu_info->num_mpdu_fcs_ok > 1) 2819 rx_stats->ampdu_msdu_count += num_msdu; 2820 else 2821 rx_stats->non_ampdu_msdu_count += num_msdu; 2822 2823 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2824 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2825 rx_stats->dcm_count += ppdu_info->dcm; 2826 rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2827 2828 arsta->rssi_comb = ppdu_info->rssi_comb; 2829 2830 BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) > 2831 ARRAY_SIZE(ppdu_info->rssi_chain_pri20)); 2832 2833 for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++) 2834 arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i]; 2835 2836 rx_stats->rx_duration += ppdu_info->rx_duration; 2837 arsta->rx_duration = rx_stats->rx_duration; 2838 } 2839 2840 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2841 struct dp_rxdma_ring *rx_ring, 2842 int *buf_id) 2843 { 2844 struct sk_buff *skb; 2845 dma_addr_t paddr; 2846 2847 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2848 DP_RX_BUFFER_ALIGN_SIZE); 2849 2850 if (!skb) 2851 goto fail_alloc_skb; 2852 2853 if (!IS_ALIGNED((unsigned long)skb->data, 2854 DP_RX_BUFFER_ALIGN_SIZE)) { 2855 skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2856 skb->data); 2857 } 2858 2859 paddr = dma_map_single(ab->dev, skb->data, 2860 skb->len + skb_tailroom(skb), 2861 DMA_FROM_DEVICE); 2862 if (unlikely(dma_mapping_error(ab->dev, paddr))) 2863 goto fail_free_skb; 2864 2865 spin_lock_bh(&rx_ring->idr_lock); 2866 *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 2867 rx_ring->bufs_max, GFP_ATOMIC); 2868 spin_unlock_bh(&rx_ring->idr_lock); 2869 if (*buf_id < 0) 2870 goto fail_dma_unmap; 2871 2872 ATH11K_SKB_RXCB(skb)->paddr = paddr; 2873 return skb; 2874 2875 fail_dma_unmap: 2876 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2877 DMA_FROM_DEVICE); 2878 fail_free_skb: 2879 dev_kfree_skb_any(skb); 2880 fail_alloc_skb: 2881 return NULL; 2882 } 2883 2884 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2885 struct dp_rxdma_ring *rx_ring, 2886 int req_entries, 2887 enum hal_rx_buf_return_buf_manager mgr) 2888 { 2889 struct hal_srng *srng; 2890 u32 *desc; 2891 struct sk_buff *skb; 2892 int num_free; 2893 int num_remain; 2894 int buf_id; 2895 u32 cookie; 2896 dma_addr_t paddr; 2897 2898 req_entries = min(req_entries, rx_ring->bufs_max); 2899 2900 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2901 2902 spin_lock_bh(&srng->lock); 2903 2904 ath11k_hal_srng_access_begin(ab, srng); 2905 2906 num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2907 2908 req_entries = min(num_free, req_entries); 2909 num_remain = req_entries; 2910 2911 while (num_remain > 0) { 2912 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 2913 &buf_id); 2914 if (!skb) 2915 break; 2916 paddr = ATH11K_SKB_RXCB(skb)->paddr; 2917 2918 desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2919 if (!desc) 2920 goto fail_desc_get; 2921 2922 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2923 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2924 2925 num_remain--; 2926 2927 ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2928 } 2929 2930 ath11k_hal_srng_access_end(ab, srng); 2931 2932 spin_unlock_bh(&srng->lock); 2933 2934 return req_entries - num_remain; 2935 2936 fail_desc_get: 2937 spin_lock_bh(&rx_ring->idr_lock); 2938 idr_remove(&rx_ring->bufs_idr, buf_id); 2939 spin_unlock_bh(&rx_ring->idr_lock); 2940 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2941 DMA_FROM_DEVICE); 2942 dev_kfree_skb_any(skb); 2943 ath11k_hal_srng_access_end(ab, srng); 2944 spin_unlock_bh(&srng->lock); 2945 2946 return req_entries - num_remain; 2947 } 2948 2949 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535 2950 2951 static void 2952 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon, 2953 struct hal_tlv_hdr *tlv) 2954 { 2955 struct hal_rx_ppdu_start *ppdu_start; 2956 u16 ppdu_id_diff, ppdu_id, tlv_len; 2957 u8 *ptr; 2958 2959 /* PPDU id is part of second tlv, move ptr to second tlv */ 2960 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 2961 ptr = (u8 *)tlv; 2962 ptr += sizeof(*tlv) + tlv_len; 2963 tlv = (struct hal_tlv_hdr *)ptr; 2964 2965 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START) 2966 return; 2967 2968 ptr += sizeof(*tlv); 2969 ppdu_start = (struct hal_rx_ppdu_start *)ptr; 2970 ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 2971 __le32_to_cpu(ppdu_start->info0)); 2972 2973 if (pmon->sw_mon_entries.ppdu_id < ppdu_id) { 2974 pmon->buf_state = DP_MON_STATUS_LEAD; 2975 ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id; 2976 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 2977 pmon->buf_state = DP_MON_STATUS_LAG; 2978 } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) { 2979 pmon->buf_state = DP_MON_STATUS_LAG; 2980 ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id; 2981 if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 2982 pmon->buf_state = DP_MON_STATUS_LEAD; 2983 } 2984 } 2985 2986 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2987 int *budget, struct sk_buff_head *skb_list) 2988 { 2989 struct ath11k *ar; 2990 const struct ath11k_hw_hal_params *hal_params; 2991 struct ath11k_pdev_dp *dp; 2992 struct dp_rxdma_ring *rx_ring; 2993 struct ath11k_mon_data *pmon; 2994 struct hal_srng *srng; 2995 void *rx_mon_status_desc; 2996 struct sk_buff *skb; 2997 struct ath11k_skb_rxcb *rxcb; 2998 struct hal_tlv_hdr *tlv; 2999 u32 cookie; 3000 int buf_id, srng_id; 3001 dma_addr_t paddr; 3002 u8 rbm; 3003 int num_buffs_reaped = 0; 3004 3005 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 3006 dp = &ar->dp; 3007 pmon = &dp->mon_data; 3008 srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id); 3009 rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 3010 3011 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 3012 3013 spin_lock_bh(&srng->lock); 3014 3015 ath11k_hal_srng_access_begin(ab, srng); 3016 while (*budget) { 3017 *budget -= 1; 3018 rx_mon_status_desc = 3019 ath11k_hal_srng_src_peek(ab, srng); 3020 if (!rx_mon_status_desc) { 3021 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3022 break; 3023 } 3024 3025 ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 3026 &cookie, &rbm); 3027 if (paddr) { 3028 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 3029 3030 spin_lock_bh(&rx_ring->idr_lock); 3031 skb = idr_find(&rx_ring->bufs_idr, buf_id); 3032 if (!skb) { 3033 ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 3034 buf_id); 3035 spin_unlock_bh(&rx_ring->idr_lock); 3036 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3037 goto move_next; 3038 } 3039 3040 idr_remove(&rx_ring->bufs_idr, buf_id); 3041 spin_unlock_bh(&rx_ring->idr_lock); 3042 3043 rxcb = ATH11K_SKB_RXCB(skb); 3044 3045 dma_unmap_single(ab->dev, rxcb->paddr, 3046 skb->len + skb_tailroom(skb), 3047 DMA_FROM_DEVICE); 3048 3049 tlv = (struct hal_tlv_hdr *)skb->data; 3050 if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 3051 HAL_RX_STATUS_BUFFER_DONE) { 3052 ath11k_warn(ab, "mon status DONE not set %lx\n", 3053 FIELD_GET(HAL_TLV_HDR_TAG, 3054 tlv->tl)); 3055 dev_kfree_skb_any(skb); 3056 pmon->buf_state = DP_MON_STATUS_NO_DMA; 3057 goto move_next; 3058 } 3059 3060 if (ab->hw_params.full_monitor_mode) { 3061 ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv); 3062 if (paddr == pmon->mon_status_paddr) 3063 pmon->buf_state = DP_MON_STATUS_MATCH; 3064 } 3065 __skb_queue_tail(skb_list, skb); 3066 } else { 3067 pmon->buf_state = DP_MON_STATUS_REPLINISH; 3068 } 3069 move_next: 3070 skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 3071 &buf_id); 3072 3073 if (!skb) { 3074 hal_params = ab->hw_params.hal_params; 3075 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 3076 hal_params->rx_buf_rbm); 3077 num_buffs_reaped++; 3078 break; 3079 } 3080 rxcb = ATH11K_SKB_RXCB(skb); 3081 3082 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 3083 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3084 3085 ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 3086 cookie, 3087 ab->hw_params.hal_params->rx_buf_rbm); 3088 ath11k_hal_srng_src_get_next_entry(ab, srng); 3089 num_buffs_reaped++; 3090 } 3091 ath11k_hal_srng_access_end(ab, srng); 3092 spin_unlock_bh(&srng->lock); 3093 3094 return num_buffs_reaped; 3095 } 3096 3097 static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 3098 { 3099 struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 3100 3101 spin_lock_bh(&rx_tid->ab->base_lock); 3102 if (rx_tid->last_frag_no && 3103 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 3104 spin_unlock_bh(&rx_tid->ab->base_lock); 3105 return; 3106 } 3107 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3108 spin_unlock_bh(&rx_tid->ab->base_lock); 3109 } 3110 3111 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 3112 { 3113 struct ath11k_base *ab = ar->ab; 3114 struct crypto_shash *tfm; 3115 struct ath11k_peer *peer; 3116 struct dp_rx_tid *rx_tid; 3117 int i; 3118 3119 tfm = crypto_alloc_shash("michael_mic", 0, 0); 3120 if (IS_ERR(tfm)) 3121 return PTR_ERR(tfm); 3122 3123 spin_lock_bh(&ab->base_lock); 3124 3125 peer = ath11k_peer_find(ab, vdev_id, peer_mac); 3126 if (!peer) { 3127 ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 3128 spin_unlock_bh(&ab->base_lock); 3129 return -ENOENT; 3130 } 3131 3132 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3133 rx_tid = &peer->rx_tid[i]; 3134 rx_tid->ab = ab; 3135 timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 3136 skb_queue_head_init(&rx_tid->rx_frags); 3137 } 3138 3139 peer->tfm_mmic = tfm; 3140 spin_unlock_bh(&ab->base_lock); 3141 3142 return 0; 3143 } 3144 3145 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3146 struct ieee80211_hdr *hdr, u8 *data, 3147 size_t data_len, u8 *mic) 3148 { 3149 SHASH_DESC_ON_STACK(desc, tfm); 3150 u8 mic_hdr[16] = {0}; 3151 u8 tid = 0; 3152 int ret; 3153 3154 if (!tfm) 3155 return -EINVAL; 3156 3157 desc->tfm = tfm; 3158 3159 ret = crypto_shash_setkey(tfm, key, 8); 3160 if (ret) 3161 goto out; 3162 3163 ret = crypto_shash_init(desc); 3164 if (ret) 3165 goto out; 3166 3167 /* TKIP MIC header */ 3168 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3169 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3170 if (ieee80211_is_data_qos(hdr->frame_control)) 3171 tid = ieee80211_get_tid(hdr); 3172 mic_hdr[12] = tid; 3173 3174 ret = crypto_shash_update(desc, mic_hdr, 16); 3175 if (ret) 3176 goto out; 3177 ret = crypto_shash_update(desc, data, data_len); 3178 if (ret) 3179 goto out; 3180 ret = crypto_shash_final(desc, mic); 3181 out: 3182 shash_desc_zero(desc); 3183 return ret; 3184 } 3185 3186 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 3187 struct sk_buff *msdu) 3188 { 3189 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3190 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3191 struct ieee80211_key_conf *key_conf; 3192 struct ieee80211_hdr *hdr; 3193 u8 mic[IEEE80211_CCMP_MIC_LEN]; 3194 int head_len, tail_len, ret; 3195 size_t data_len; 3196 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3197 u8 *key, *data; 3198 u8 key_idx; 3199 3200 if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) != 3201 HAL_ENCRYPT_TYPE_TKIP_MIC) 3202 return 0; 3203 3204 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3205 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3206 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3207 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3208 3209 if (!is_multicast_ether_addr(hdr->addr1)) 3210 key_idx = peer->ucast_keyidx; 3211 else 3212 key_idx = peer->mcast_keyidx; 3213 3214 key_conf = peer->keys[key_idx]; 3215 3216 data = msdu->data + head_len; 3217 data_len = msdu->len - head_len - tail_len; 3218 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3219 3220 ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3221 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3222 goto mic_fail; 3223 3224 return 0; 3225 3226 mic_fail: 3227 (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 3228 (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 3229 3230 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3231 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3232 skb_pull(msdu, hal_rx_desc_sz); 3233 3234 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 3235 ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 3236 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3237 ieee80211_rx(ar->hw, msdu); 3238 return -EINVAL; 3239 } 3240 3241 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 3242 enum hal_encrypt_type enctype, u32 flags) 3243 { 3244 struct ieee80211_hdr *hdr; 3245 size_t hdr_len; 3246 size_t crypto_len; 3247 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3248 3249 if (!flags) 3250 return; 3251 3252 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3253 3254 if (flags & RX_FLAG_MIC_STRIPPED) 3255 skb_trim(msdu, msdu->len - 3256 ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3257 3258 if (flags & RX_FLAG_ICV_STRIPPED) 3259 skb_trim(msdu, msdu->len - 3260 ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3261 3262 if (flags & RX_FLAG_IV_STRIPPED) { 3263 hdr_len = ieee80211_hdrlen(hdr->frame_control); 3264 crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3265 3266 memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len, 3267 (void *)msdu->data + hal_rx_desc_sz, hdr_len); 3268 skb_pull(msdu, crypto_len); 3269 } 3270 } 3271 3272 static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3273 struct ath11k_peer *peer, 3274 struct dp_rx_tid *rx_tid, 3275 struct sk_buff **defrag_skb) 3276 { 3277 struct hal_rx_desc *rx_desc; 3278 struct sk_buff *skb, *first_frag, *last_frag; 3279 struct ieee80211_hdr *hdr; 3280 struct rx_attention *rx_attention; 3281 enum hal_encrypt_type enctype; 3282 bool is_decrypted = false; 3283 int msdu_len = 0; 3284 int extra_space; 3285 u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3286 3287 first_frag = skb_peek(&rx_tid->rx_frags); 3288 last_frag = skb_peek_tail(&rx_tid->rx_frags); 3289 3290 skb_queue_walk(&rx_tid->rx_frags, skb) { 3291 flags = 0; 3292 rx_desc = (struct hal_rx_desc *)skb->data; 3293 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3294 3295 enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 3296 if (enctype != HAL_ENCRYPT_TYPE_OPEN) { 3297 rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 3298 is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 3299 } 3300 3301 if (is_decrypted) { 3302 if (skb != first_frag) 3303 flags |= RX_FLAG_IV_STRIPPED; 3304 if (skb != last_frag) 3305 flags |= RX_FLAG_ICV_STRIPPED | 3306 RX_FLAG_MIC_STRIPPED; 3307 } 3308 3309 /* RX fragments are always raw packets */ 3310 if (skb != last_frag) 3311 skb_trim(skb, skb->len - FCS_LEN); 3312 ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3313 3314 if (skb != first_frag) 3315 skb_pull(skb, hal_rx_desc_sz + 3316 ieee80211_hdrlen(hdr->frame_control)); 3317 msdu_len += skb->len; 3318 } 3319 3320 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3321 if (extra_space > 0 && 3322 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3323 return -ENOMEM; 3324 3325 __skb_unlink(first_frag, &rx_tid->rx_frags); 3326 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3327 skb_put_data(first_frag, skb->data, skb->len); 3328 dev_kfree_skb_any(skb); 3329 } 3330 3331 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3332 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3333 ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3334 3335 if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3336 first_frag = NULL; 3337 3338 *defrag_skb = first_frag; 3339 return 0; 3340 } 3341 3342 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3343 struct sk_buff *defrag_skb) 3344 { 3345 struct ath11k_base *ab = ar->ab; 3346 struct ath11k_pdev_dp *dp = &ar->dp; 3347 struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3348 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3349 struct hal_reo_entrance_ring *reo_ent_ring; 3350 struct hal_reo_dest_ring *reo_dest_ring; 3351 struct dp_link_desc_bank *link_desc_banks; 3352 struct hal_rx_msdu_link *msdu_link; 3353 struct hal_rx_msdu_details *msdu0; 3354 struct hal_srng *srng; 3355 dma_addr_t paddr; 3356 u32 desc_bank, msdu_info, mpdu_info; 3357 u32 dst_idx, cookie, hal_rx_desc_sz; 3358 int ret, buf_id; 3359 3360 hal_rx_desc_sz = ab->hw_params.hal_desc_sz; 3361 link_desc_banks = ab->dp.link_desc_banks; 3362 reo_dest_ring = rx_tid->dst_ring_desc; 3363 3364 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3365 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3366 (paddr - link_desc_banks[desc_bank].paddr)); 3367 msdu0 = &msdu_link->msdu_link[0]; 3368 dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3369 memset(msdu0, 0, sizeof(*msdu0)); 3370 3371 msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3372 FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3373 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3374 FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3375 defrag_skb->len - hal_rx_desc_sz) | 3376 FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3377 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3378 FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3379 msdu0->rx_msdu_info.info0 = msdu_info; 3380 3381 /* change msdu len in hal rx desc */ 3382 ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3383 3384 paddr = dma_map_single(ab->dev, defrag_skb->data, 3385 defrag_skb->len + skb_tailroom(defrag_skb), 3386 DMA_TO_DEVICE); 3387 if (dma_mapping_error(ab->dev, paddr)) 3388 return -ENOMEM; 3389 3390 spin_lock_bh(&rx_refill_ring->idr_lock); 3391 buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3392 rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3393 spin_unlock_bh(&rx_refill_ring->idr_lock); 3394 if (buf_id < 0) { 3395 ret = -ENOMEM; 3396 goto err_unmap_dma; 3397 } 3398 3399 ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3400 cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3401 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3402 3403 ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, 3404 ab->hw_params.hal_params->rx_buf_rbm); 3405 3406 /* Fill mpdu details into reo entrace ring */ 3407 srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3408 3409 spin_lock_bh(&srng->lock); 3410 ath11k_hal_srng_access_begin(ab, srng); 3411 3412 reo_ent_ring = (struct hal_reo_entrance_ring *) 3413 ath11k_hal_srng_src_get_next_entry(ab, srng); 3414 if (!reo_ent_ring) { 3415 ath11k_hal_srng_access_end(ab, srng); 3416 spin_unlock_bh(&srng->lock); 3417 ret = -ENOSPC; 3418 goto err_free_idr; 3419 } 3420 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3421 3422 ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3423 ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3424 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3425 3426 mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3427 FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3428 FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3429 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3430 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3431 FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3432 FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3433 3434 reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3435 reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3436 reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3437 reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3438 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3439 reo_dest_ring->info0)) | 3440 FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3441 ath11k_hal_srng_access_end(ab, srng); 3442 spin_unlock_bh(&srng->lock); 3443 3444 return 0; 3445 3446 err_free_idr: 3447 spin_lock_bh(&rx_refill_ring->idr_lock); 3448 idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3449 spin_unlock_bh(&rx_refill_ring->idr_lock); 3450 err_unmap_dma: 3451 dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3452 DMA_TO_DEVICE); 3453 return ret; 3454 } 3455 3456 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar, 3457 struct sk_buff *a, struct sk_buff *b) 3458 { 3459 int frag1, frag2; 3460 3461 frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a); 3462 frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b); 3463 3464 return frag1 - frag2; 3465 } 3466 3467 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar, 3468 struct sk_buff_head *frag_list, 3469 struct sk_buff *cur_frag) 3470 { 3471 struct sk_buff *skb; 3472 int cmp; 3473 3474 skb_queue_walk(frag_list, skb) { 3475 cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag); 3476 if (cmp < 0) 3477 continue; 3478 __skb_queue_before(frag_list, skb, cur_frag); 3479 return; 3480 } 3481 __skb_queue_tail(frag_list, cur_frag); 3482 } 3483 3484 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb) 3485 { 3486 struct ieee80211_hdr *hdr; 3487 u64 pn = 0; 3488 u8 *ehdr; 3489 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3490 3491 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3492 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3493 3494 pn = ehdr[0]; 3495 pn |= (u64)ehdr[1] << 8; 3496 pn |= (u64)ehdr[4] << 16; 3497 pn |= (u64)ehdr[5] << 24; 3498 pn |= (u64)ehdr[6] << 32; 3499 pn |= (u64)ehdr[7] << 40; 3500 3501 return pn; 3502 } 3503 3504 static bool 3505 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3506 { 3507 enum hal_encrypt_type encrypt_type; 3508 struct sk_buff *first_frag, *skb; 3509 struct hal_rx_desc *desc; 3510 u64 last_pn; 3511 u64 cur_pn; 3512 3513 first_frag = skb_peek(&rx_tid->rx_frags); 3514 desc = (struct hal_rx_desc *)first_frag->data; 3515 3516 encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc); 3517 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3518 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3519 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3520 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3521 return true; 3522 3523 last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag); 3524 skb_queue_walk(&rx_tid->rx_frags, skb) { 3525 if (skb == first_frag) 3526 continue; 3527 3528 cur_pn = ath11k_dp_rx_h_get_pn(ar, skb); 3529 if (cur_pn != last_pn + 1) 3530 return false; 3531 last_pn = cur_pn; 3532 } 3533 return true; 3534 } 3535 3536 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3537 struct sk_buff *msdu, 3538 u32 *ring_desc) 3539 { 3540 struct ath11k_base *ab = ar->ab; 3541 struct hal_rx_desc *rx_desc; 3542 struct ath11k_peer *peer; 3543 struct dp_rx_tid *rx_tid; 3544 struct sk_buff *defrag_skb = NULL; 3545 u32 peer_id; 3546 u16 seqno, frag_no; 3547 u8 tid; 3548 int ret = 0; 3549 bool more_frags; 3550 bool is_mcbc; 3551 3552 rx_desc = (struct hal_rx_desc *)msdu->data; 3553 peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 3554 tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc); 3555 seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 3556 frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu); 3557 more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu); 3558 is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 3559 3560 /* Multicast/Broadcast fragments are not expected */ 3561 if (is_mcbc) 3562 return -EINVAL; 3563 3564 if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) || 3565 !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) || 3566 tid > IEEE80211_NUM_TIDS) 3567 return -EINVAL; 3568 3569 /* received unfragmented packet in reo 3570 * exception ring, this shouldn't happen 3571 * as these packets typically come from 3572 * reo2sw srngs. 3573 */ 3574 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3575 return -EINVAL; 3576 3577 spin_lock_bh(&ab->base_lock); 3578 peer = ath11k_peer_find_by_id(ab, peer_id); 3579 if (!peer) { 3580 ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3581 peer_id); 3582 ret = -ENOENT; 3583 goto out_unlock; 3584 } 3585 rx_tid = &peer->rx_tid[tid]; 3586 3587 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3588 skb_queue_empty(&rx_tid->rx_frags)) { 3589 /* Flush stored fragments and start a new sequence */ 3590 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3591 rx_tid->cur_sn = seqno; 3592 } 3593 3594 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3595 /* Fragment already present */ 3596 ret = -EINVAL; 3597 goto out_unlock; 3598 } 3599 3600 if (frag_no > __fls(rx_tid->rx_frag_bitmap)) 3601 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3602 else 3603 ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu); 3604 3605 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3606 if (!more_frags) 3607 rx_tid->last_frag_no = frag_no; 3608 3609 if (frag_no == 0) { 3610 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3611 sizeof(*rx_tid->dst_ring_desc), 3612 GFP_ATOMIC); 3613 if (!rx_tid->dst_ring_desc) { 3614 ret = -ENOMEM; 3615 goto out_unlock; 3616 } 3617 } else { 3618 ath11k_dp_rx_link_desc_return(ab, ring_desc, 3619 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3620 } 3621 3622 if (!rx_tid->last_frag_no || 3623 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3624 mod_timer(&rx_tid->frag_timer, jiffies + 3625 ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3626 goto out_unlock; 3627 } 3628 3629 spin_unlock_bh(&ab->base_lock); 3630 del_timer_sync(&rx_tid->frag_timer); 3631 spin_lock_bh(&ab->base_lock); 3632 3633 peer = ath11k_peer_find_by_id(ab, peer_id); 3634 if (!peer) 3635 goto err_frags_cleanup; 3636 3637 if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3638 goto err_frags_cleanup; 3639 3640 if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3641 goto err_frags_cleanup; 3642 3643 if (!defrag_skb) 3644 goto err_frags_cleanup; 3645 3646 if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3647 goto err_frags_cleanup; 3648 3649 ath11k_dp_rx_frags_cleanup(rx_tid, false); 3650 goto out_unlock; 3651 3652 err_frags_cleanup: 3653 dev_kfree_skb_any(defrag_skb); 3654 ath11k_dp_rx_frags_cleanup(rx_tid, true); 3655 out_unlock: 3656 spin_unlock_bh(&ab->base_lock); 3657 return ret; 3658 } 3659 3660 static int 3661 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3662 { 3663 struct ath11k_pdev_dp *dp = &ar->dp; 3664 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3665 struct sk_buff *msdu; 3666 struct ath11k_skb_rxcb *rxcb; 3667 struct hal_rx_desc *rx_desc; 3668 u8 *hdr_status; 3669 u16 msdu_len; 3670 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3671 3672 spin_lock_bh(&rx_ring->idr_lock); 3673 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3674 if (!msdu) { 3675 ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3676 buf_id); 3677 spin_unlock_bh(&rx_ring->idr_lock); 3678 return -EINVAL; 3679 } 3680 3681 idr_remove(&rx_ring->bufs_idr, buf_id); 3682 spin_unlock_bh(&rx_ring->idr_lock); 3683 3684 rxcb = ATH11K_SKB_RXCB(msdu); 3685 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3686 msdu->len + skb_tailroom(msdu), 3687 DMA_FROM_DEVICE); 3688 3689 if (drop) { 3690 dev_kfree_skb_any(msdu); 3691 return 0; 3692 } 3693 3694 rcu_read_lock(); 3695 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3696 dev_kfree_skb_any(msdu); 3697 goto exit; 3698 } 3699 3700 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3701 dev_kfree_skb_any(msdu); 3702 goto exit; 3703 } 3704 3705 rx_desc = (struct hal_rx_desc *)msdu->data; 3706 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc); 3707 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3708 hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 3709 ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3710 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3711 sizeof(struct ieee80211_hdr)); 3712 ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3713 sizeof(struct hal_rx_desc)); 3714 dev_kfree_skb_any(msdu); 3715 goto exit; 3716 } 3717 3718 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3719 3720 if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3721 dev_kfree_skb_any(msdu); 3722 ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3723 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3724 } 3725 exit: 3726 rcu_read_unlock(); 3727 return 0; 3728 } 3729 3730 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3731 int budget) 3732 { 3733 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3734 struct dp_link_desc_bank *link_desc_banks; 3735 enum hal_rx_buf_return_buf_manager rbm; 3736 int tot_n_bufs_reaped, quota, ret, i; 3737 int n_bufs_reaped[MAX_RADIOS] = {0}; 3738 struct dp_rxdma_ring *rx_ring; 3739 struct dp_srng *reo_except; 3740 u32 desc_bank, num_msdus; 3741 struct hal_srng *srng; 3742 struct ath11k_dp *dp; 3743 void *link_desc_va; 3744 int buf_id, mac_id; 3745 struct ath11k *ar; 3746 dma_addr_t paddr; 3747 u32 *desc; 3748 bool is_frag; 3749 u8 drop = 0; 3750 3751 tot_n_bufs_reaped = 0; 3752 quota = budget; 3753 3754 dp = &ab->dp; 3755 reo_except = &dp->reo_except_ring; 3756 link_desc_banks = dp->link_desc_banks; 3757 3758 srng = &ab->hal.srng_list[reo_except->ring_id]; 3759 3760 spin_lock_bh(&srng->lock); 3761 3762 ath11k_hal_srng_access_begin(ab, srng); 3763 3764 while (budget && 3765 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3766 struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3767 3768 ab->soc_stats.err_ring_pkts++; 3769 ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3770 &desc_bank); 3771 if (ret) { 3772 ath11k_warn(ab, "failed to parse error reo desc %d\n", 3773 ret); 3774 continue; 3775 } 3776 link_desc_va = link_desc_banks[desc_bank].vaddr + 3777 (paddr - link_desc_banks[desc_bank].paddr); 3778 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3779 &rbm); 3780 if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 3781 rbm != HAL_RX_BUF_RBM_SW3_BM) { 3782 ab->soc_stats.invalid_rbm++; 3783 ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3784 ath11k_dp_rx_link_desc_return(ab, desc, 3785 HAL_WBM_REL_BM_ACT_REL_MSDU); 3786 continue; 3787 } 3788 3789 is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3790 3791 /* Process only rx fragments with one msdu per link desc below, and drop 3792 * msdu's indicated due to error reasons. 3793 */ 3794 if (!is_frag || num_msdus > 1) { 3795 drop = 1; 3796 /* Return the link desc back to wbm idle list */ 3797 ath11k_dp_rx_link_desc_return(ab, desc, 3798 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3799 } 3800 3801 for (i = 0; i < num_msdus; i++) { 3802 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3803 msdu_cookies[i]); 3804 3805 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3806 msdu_cookies[i]); 3807 3808 ar = ab->pdevs[mac_id].ar; 3809 3810 if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3811 n_bufs_reaped[mac_id]++; 3812 tot_n_bufs_reaped++; 3813 } 3814 } 3815 3816 if (tot_n_bufs_reaped >= quota) { 3817 tot_n_bufs_reaped = quota; 3818 goto exit; 3819 } 3820 3821 budget = quota - tot_n_bufs_reaped; 3822 } 3823 3824 exit: 3825 ath11k_hal_srng_access_end(ab, srng); 3826 3827 spin_unlock_bh(&srng->lock); 3828 3829 for (i = 0; i < ab->num_radios; i++) { 3830 if (!n_bufs_reaped[i]) 3831 continue; 3832 3833 ar = ab->pdevs[i].ar; 3834 rx_ring = &ar->dp.rx_refill_buf_ring; 3835 3836 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 3837 ab->hw_params.hal_params->rx_buf_rbm); 3838 } 3839 3840 return tot_n_bufs_reaped; 3841 } 3842 3843 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3844 int msdu_len, 3845 struct sk_buff_head *msdu_list) 3846 { 3847 struct sk_buff *skb, *tmp; 3848 struct ath11k_skb_rxcb *rxcb; 3849 int n_buffs; 3850 3851 n_buffs = DIV_ROUND_UP(msdu_len, 3852 (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz)); 3853 3854 skb_queue_walk_safe(msdu_list, skb, tmp) { 3855 rxcb = ATH11K_SKB_RXCB(skb); 3856 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3857 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3858 if (!n_buffs) 3859 break; 3860 __skb_unlink(skb, msdu_list); 3861 dev_kfree_skb_any(skb); 3862 n_buffs--; 3863 } 3864 } 3865 } 3866 3867 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3868 struct ieee80211_rx_status *status, 3869 struct sk_buff_head *msdu_list) 3870 { 3871 u16 msdu_len; 3872 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3873 struct rx_attention *rx_attention; 3874 u8 l3pad_bytes; 3875 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3876 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3877 3878 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3879 3880 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3881 /* First buffer will be freed by the caller, so deduct it's length */ 3882 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3883 ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3884 return -EINVAL; 3885 } 3886 3887 rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc); 3888 if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 3889 ath11k_warn(ar->ab, 3890 "msdu_done bit not set in null_q_des processing\n"); 3891 __skb_queue_purge(msdu_list); 3892 return -EIO; 3893 } 3894 3895 /* Handle NULL queue descriptor violations arising out a missing 3896 * REO queue for a given peer or a given TID. This typically 3897 * may happen if a packet is received on a QOS enabled TID before the 3898 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3899 * it may also happen for MC/BC frames if they are not routed to the 3900 * non-QOS TID queue, in the absence of any other default TID queue. 3901 * This error can show up both in a REO destination or WBM release ring. 3902 */ 3903 3904 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3905 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3906 3907 if (rxcb->is_frag) { 3908 skb_pull(msdu, hal_rx_desc_sz); 3909 } else { 3910 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3911 3912 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3913 return -EINVAL; 3914 3915 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3916 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3917 } 3918 ath11k_dp_rx_h_ppdu(ar, desc, status); 3919 3920 ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3921 3922 rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc); 3923 3924 /* Please note that caller will having the access to msdu and completing 3925 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3926 */ 3927 3928 return 0; 3929 } 3930 3931 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3932 struct ieee80211_rx_status *status, 3933 struct sk_buff_head *msdu_list) 3934 { 3935 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3936 bool drop = false; 3937 3938 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3939 3940 switch (rxcb->err_code) { 3941 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3942 if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3943 drop = true; 3944 break; 3945 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3946 /* TODO: Do not drop PN failed packets in the driver; 3947 * instead, it is good to drop such packets in mac80211 3948 * after incrementing the replay counters. 3949 */ 3950 fallthrough; 3951 default: 3952 /* TODO: Review other errors and process them to mac80211 3953 * as appropriate. 3954 */ 3955 drop = true; 3956 break; 3957 } 3958 3959 return drop; 3960 } 3961 3962 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3963 struct ieee80211_rx_status *status) 3964 { 3965 u16 msdu_len; 3966 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3967 u8 l3pad_bytes; 3968 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3969 u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3970 3971 rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3972 rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3973 3974 l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3975 msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3976 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3977 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3978 3979 ath11k_dp_rx_h_ppdu(ar, desc, status); 3980 3981 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3982 RX_FLAG_DECRYPTED); 3983 3984 ath11k_dp_rx_h_undecap(ar, msdu, desc, 3985 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3986 } 3987 3988 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 3989 struct ieee80211_rx_status *status) 3990 { 3991 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3992 bool drop = false; 3993 3994 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3995 3996 switch (rxcb->err_code) { 3997 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3998 ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3999 break; 4000 default: 4001 /* TODO: Review other rxdma error code to check if anything is 4002 * worth reporting to mac80211 4003 */ 4004 drop = true; 4005 break; 4006 } 4007 4008 return drop; 4009 } 4010 4011 static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 4012 struct napi_struct *napi, 4013 struct sk_buff *msdu, 4014 struct sk_buff_head *msdu_list) 4015 { 4016 struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4017 struct ieee80211_rx_status rxs = {0}; 4018 bool drop = true; 4019 4020 switch (rxcb->err_rel_src) { 4021 case HAL_WBM_REL_SRC_MODULE_REO: 4022 drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 4023 break; 4024 case HAL_WBM_REL_SRC_MODULE_RXDMA: 4025 drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 4026 break; 4027 default: 4028 /* msdu will get freed */ 4029 break; 4030 } 4031 4032 if (drop) { 4033 dev_kfree_skb_any(msdu); 4034 return; 4035 } 4036 4037 ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 4038 } 4039 4040 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 4041 struct napi_struct *napi, int budget) 4042 { 4043 struct ath11k *ar; 4044 struct ath11k_dp *dp = &ab->dp; 4045 struct dp_rxdma_ring *rx_ring; 4046 struct hal_rx_wbm_rel_info err_info; 4047 struct hal_srng *srng; 4048 struct sk_buff *msdu; 4049 struct sk_buff_head msdu_list[MAX_RADIOS]; 4050 struct ath11k_skb_rxcb *rxcb; 4051 u32 *rx_desc; 4052 int buf_id, mac_id; 4053 int num_buffs_reaped[MAX_RADIOS] = {0}; 4054 int total_num_buffs_reaped = 0; 4055 int ret, i; 4056 4057 for (i = 0; i < ab->num_radios; i++) 4058 __skb_queue_head_init(&msdu_list[i]); 4059 4060 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4061 4062 spin_lock_bh(&srng->lock); 4063 4064 ath11k_hal_srng_access_begin(ab, srng); 4065 4066 while (budget) { 4067 rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 4068 if (!rx_desc) 4069 break; 4070 4071 ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4072 if (ret) { 4073 ath11k_warn(ab, 4074 "failed to parse rx error in wbm_rel ring desc %d\n", 4075 ret); 4076 continue; 4077 } 4078 4079 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 4080 mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 4081 4082 ar = ab->pdevs[mac_id].ar; 4083 rx_ring = &ar->dp.rx_refill_buf_ring; 4084 4085 spin_lock_bh(&rx_ring->idr_lock); 4086 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4087 if (!msdu) { 4088 ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 4089 buf_id, mac_id); 4090 spin_unlock_bh(&rx_ring->idr_lock); 4091 continue; 4092 } 4093 4094 idr_remove(&rx_ring->bufs_idr, buf_id); 4095 spin_unlock_bh(&rx_ring->idr_lock); 4096 4097 rxcb = ATH11K_SKB_RXCB(msdu); 4098 dma_unmap_single(ab->dev, rxcb->paddr, 4099 msdu->len + skb_tailroom(msdu), 4100 DMA_FROM_DEVICE); 4101 4102 num_buffs_reaped[mac_id]++; 4103 total_num_buffs_reaped++; 4104 budget--; 4105 4106 if (err_info.push_reason != 4107 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4108 dev_kfree_skb_any(msdu); 4109 continue; 4110 } 4111 4112 rxcb->err_rel_src = err_info.err_rel_src; 4113 rxcb->err_code = err_info.err_code; 4114 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 4115 __skb_queue_tail(&msdu_list[mac_id], msdu); 4116 } 4117 4118 ath11k_hal_srng_access_end(ab, srng); 4119 4120 spin_unlock_bh(&srng->lock); 4121 4122 if (!total_num_buffs_reaped) 4123 goto done; 4124 4125 for (i = 0; i < ab->num_radios; i++) { 4126 if (!num_buffs_reaped[i]) 4127 continue; 4128 4129 ar = ab->pdevs[i].ar; 4130 rx_ring = &ar->dp.rx_refill_buf_ring; 4131 4132 ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 4133 ab->hw_params.hal_params->rx_buf_rbm); 4134 } 4135 4136 rcu_read_lock(); 4137 for (i = 0; i < ab->num_radios; i++) { 4138 if (!rcu_dereference(ab->pdevs_active[i])) { 4139 __skb_queue_purge(&msdu_list[i]); 4140 continue; 4141 } 4142 4143 ar = ab->pdevs[i].ar; 4144 4145 if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 4146 __skb_queue_purge(&msdu_list[i]); 4147 continue; 4148 } 4149 4150 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 4151 ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 4152 } 4153 rcu_read_unlock(); 4154 done: 4155 return total_num_buffs_reaped; 4156 } 4157 4158 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 4159 { 4160 struct ath11k *ar; 4161 struct dp_srng *err_ring; 4162 struct dp_rxdma_ring *rx_ring; 4163 struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 4164 struct hal_srng *srng; 4165 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 4166 enum hal_rx_buf_return_buf_manager rbm; 4167 enum hal_reo_entr_rxdma_ecode rxdma_err_code; 4168 struct ath11k_skb_rxcb *rxcb; 4169 struct sk_buff *skb; 4170 struct hal_reo_entrance_ring *entr_ring; 4171 void *desc; 4172 int num_buf_freed = 0; 4173 int quota = budget; 4174 dma_addr_t paddr; 4175 u32 desc_bank; 4176 void *link_desc_va; 4177 int num_msdus; 4178 int i; 4179 int buf_id; 4180 4181 ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 4182 err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params, 4183 mac_id)]; 4184 rx_ring = &ar->dp.rx_refill_buf_ring; 4185 4186 srng = &ab->hal.srng_list[err_ring->ring_id]; 4187 4188 spin_lock_bh(&srng->lock); 4189 4190 ath11k_hal_srng_access_begin(ab, srng); 4191 4192 while (quota-- && 4193 (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4194 ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 4195 4196 entr_ring = (struct hal_reo_entrance_ring *)desc; 4197 rxdma_err_code = 4198 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4199 entr_ring->info1); 4200 ab->soc_stats.rxdma_error[rxdma_err_code]++; 4201 4202 link_desc_va = link_desc_banks[desc_bank].vaddr + 4203 (paddr - link_desc_banks[desc_bank].paddr); 4204 ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 4205 msdu_cookies, &rbm); 4206 4207 for (i = 0; i < num_msdus; i++) { 4208 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4209 msdu_cookies[i]); 4210 4211 spin_lock_bh(&rx_ring->idr_lock); 4212 skb = idr_find(&rx_ring->bufs_idr, buf_id); 4213 if (!skb) { 4214 ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 4215 buf_id); 4216 spin_unlock_bh(&rx_ring->idr_lock); 4217 continue; 4218 } 4219 4220 idr_remove(&rx_ring->bufs_idr, buf_id); 4221 spin_unlock_bh(&rx_ring->idr_lock); 4222 4223 rxcb = ATH11K_SKB_RXCB(skb); 4224 dma_unmap_single(ab->dev, rxcb->paddr, 4225 skb->len + skb_tailroom(skb), 4226 DMA_FROM_DEVICE); 4227 dev_kfree_skb_any(skb); 4228 4229 num_buf_freed++; 4230 } 4231 4232 ath11k_dp_rx_link_desc_return(ab, desc, 4233 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4234 } 4235 4236 ath11k_hal_srng_access_end(ab, srng); 4237 4238 spin_unlock_bh(&srng->lock); 4239 4240 if (num_buf_freed) 4241 ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 4242 ab->hw_params.hal_params->rx_buf_rbm); 4243 4244 return budget - quota; 4245 } 4246 4247 void ath11k_dp_process_reo_status(struct ath11k_base *ab) 4248 { 4249 struct ath11k_dp *dp = &ab->dp; 4250 struct hal_srng *srng; 4251 struct dp_reo_cmd *cmd, *tmp; 4252 bool found = false; 4253 u32 *reo_desc; 4254 u16 tag; 4255 struct hal_reo_status reo_status; 4256 4257 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4258 4259 memset(&reo_status, 0, sizeof(reo_status)); 4260 4261 spin_lock_bh(&srng->lock); 4262 4263 ath11k_hal_srng_access_begin(ab, srng); 4264 4265 while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4266 tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 4267 4268 switch (tag) { 4269 case HAL_REO_GET_QUEUE_STATS_STATUS: 4270 ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4271 &reo_status); 4272 break; 4273 case HAL_REO_FLUSH_QUEUE_STATUS: 4274 ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4275 &reo_status); 4276 break; 4277 case HAL_REO_FLUSH_CACHE_STATUS: 4278 ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4279 &reo_status); 4280 break; 4281 case HAL_REO_UNBLOCK_CACHE_STATUS: 4282 ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4283 &reo_status); 4284 break; 4285 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4286 ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4287 &reo_status); 4288 break; 4289 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4290 ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4291 &reo_status); 4292 break; 4293 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4294 ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4295 &reo_status); 4296 break; 4297 default: 4298 ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4299 continue; 4300 } 4301 4302 spin_lock_bh(&dp->reo_cmd_lock); 4303 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4304 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4305 found = true; 4306 list_del(&cmd->list); 4307 break; 4308 } 4309 } 4310 spin_unlock_bh(&dp->reo_cmd_lock); 4311 4312 if (found) { 4313 cmd->handler(dp, (void *)&cmd->data, 4314 reo_status.uniform_hdr.cmd_status); 4315 kfree(cmd); 4316 } 4317 4318 found = false; 4319 } 4320 4321 ath11k_hal_srng_access_end(ab, srng); 4322 4323 spin_unlock_bh(&srng->lock); 4324 } 4325 4326 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4327 { 4328 struct ath11k *ar = ab->pdevs[mac_id].ar; 4329 4330 ath11k_dp_rx_pdev_srng_free(ar); 4331 ath11k_dp_rxdma_pdev_buf_free(ar); 4332 } 4333 4334 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4335 { 4336 struct ath11k *ar = ab->pdevs[mac_id].ar; 4337 struct ath11k_pdev_dp *dp = &ar->dp; 4338 u32 ring_id; 4339 int i; 4340 int ret; 4341 4342 ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4343 if (ret) { 4344 ath11k_warn(ab, "failed to setup rx srngs\n"); 4345 return ret; 4346 } 4347 4348 ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4349 if (ret) { 4350 ath11k_warn(ab, "failed to setup rxdma ring\n"); 4351 return ret; 4352 } 4353 4354 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4355 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4356 if (ret) { 4357 ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4358 ret); 4359 return ret; 4360 } 4361 4362 if (ab->hw_params.rx_mac_buf_ring) { 4363 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4364 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4365 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4366 mac_id + i, HAL_RXDMA_BUF); 4367 if (ret) { 4368 ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4369 i, ret); 4370 return ret; 4371 } 4372 } 4373 } 4374 4375 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4376 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4377 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4378 mac_id + i, HAL_RXDMA_DST); 4379 if (ret) { 4380 ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4381 i, ret); 4382 return ret; 4383 } 4384 } 4385 4386 if (!ab->hw_params.rxdma1_enable) 4387 goto config_refill_ring; 4388 4389 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4390 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4391 mac_id, HAL_RXDMA_MONITOR_BUF); 4392 if (ret) { 4393 ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4394 ret); 4395 return ret; 4396 } 4397 ret = ath11k_dp_tx_htt_srng_setup(ab, 4398 dp->rxdma_mon_dst_ring.ring_id, 4399 mac_id, HAL_RXDMA_MONITOR_DST); 4400 if (ret) { 4401 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4402 ret); 4403 return ret; 4404 } 4405 ret = ath11k_dp_tx_htt_srng_setup(ab, 4406 dp->rxdma_mon_desc_ring.ring_id, 4407 mac_id, HAL_RXDMA_MONITOR_DESC); 4408 if (ret) { 4409 ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4410 ret); 4411 return ret; 4412 } 4413 4414 config_refill_ring: 4415 for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4416 ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 4417 ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, 4418 HAL_RXDMA_MONITOR_STATUS); 4419 if (ret) { 4420 ath11k_warn(ab, 4421 "failed to configure mon_status_refill_ring%d %d\n", 4422 i, ret); 4423 return ret; 4424 } 4425 } 4426 4427 return 0; 4428 } 4429 4430 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4431 { 4432 if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4433 *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4434 *total_len -= *frag_len; 4435 } else { 4436 *frag_len = *total_len; 4437 *total_len = 0; 4438 } 4439 } 4440 4441 static 4442 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4443 void *p_last_buf_addr_info, 4444 u8 mac_id) 4445 { 4446 struct ath11k_pdev_dp *dp = &ar->dp; 4447 struct dp_srng *dp_srng; 4448 void *hal_srng; 4449 void *src_srng_desc; 4450 int ret = 0; 4451 4452 if (ar->ab->hw_params.rxdma1_enable) { 4453 dp_srng = &dp->rxdma_mon_desc_ring; 4454 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4455 } else { 4456 dp_srng = &ar->ab->dp.wbm_desc_rel_ring; 4457 hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4458 } 4459 4460 ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4461 4462 src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4463 4464 if (src_srng_desc) { 4465 struct ath11k_buffer_addr *src_desc = 4466 (struct ath11k_buffer_addr *)src_srng_desc; 4467 4468 *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4469 } else { 4470 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4471 "Monitor Link Desc Ring %d Full", mac_id); 4472 ret = -ENOMEM; 4473 } 4474 4475 ath11k_hal_srng_access_end(ar->ab, hal_srng); 4476 return ret; 4477 } 4478 4479 static 4480 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4481 dma_addr_t *paddr, u32 *sw_cookie, 4482 u8 *rbm, 4483 void **pp_buf_addr_info) 4484 { 4485 struct hal_rx_msdu_link *msdu_link = 4486 (struct hal_rx_msdu_link *)rx_msdu_link_desc; 4487 struct ath11k_buffer_addr *buf_addr_info; 4488 4489 buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4490 4491 ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 4492 4493 *pp_buf_addr_info = (void *)buf_addr_info; 4494 } 4495 4496 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4497 { 4498 if (skb->len > len) { 4499 skb_trim(skb, len); 4500 } else { 4501 if (skb_tailroom(skb) < len - skb->len) { 4502 if ((pskb_expand_head(skb, 0, 4503 len - skb->len - skb_tailroom(skb), 4504 GFP_ATOMIC))) { 4505 dev_kfree_skb_any(skb); 4506 return -ENOMEM; 4507 } 4508 } 4509 skb_put(skb, (len - skb->len)); 4510 } 4511 return 0; 4512 } 4513 4514 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4515 void *msdu_link_desc, 4516 struct hal_rx_msdu_list *msdu_list, 4517 u16 *num_msdus) 4518 { 4519 struct hal_rx_msdu_details *msdu_details = NULL; 4520 struct rx_msdu_desc *msdu_desc_info = NULL; 4521 struct hal_rx_msdu_link *msdu_link = NULL; 4522 int i; 4523 u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4524 u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4525 u8 tmp = 0; 4526 4527 msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc; 4528 msdu_details = &msdu_link->msdu_link[0]; 4529 4530 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4531 if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4532 msdu_details[i].buf_addr_info.info0) == 0) { 4533 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4534 msdu_desc_info->info0 |= last; 4535 ; 4536 break; 4537 } 4538 msdu_desc_info = &msdu_details[i].rx_msdu_info; 4539 4540 if (!i) 4541 msdu_desc_info->info0 |= first; 4542 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4543 msdu_desc_info->info0 |= last; 4544 msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4545 msdu_list->msdu_info[i].msdu_len = 4546 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4547 msdu_list->sw_cookie[i] = 4548 FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4549 msdu_details[i].buf_addr_info.info1); 4550 tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4551 msdu_details[i].buf_addr_info.info1); 4552 msdu_list->rbm[i] = tmp; 4553 } 4554 *num_msdus = i; 4555 } 4556 4557 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4558 u32 *rx_bufs_used) 4559 { 4560 u32 ret = 0; 4561 4562 if ((*ppdu_id < msdu_ppdu_id) && 4563 ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4564 *ppdu_id = msdu_ppdu_id; 4565 ret = msdu_ppdu_id; 4566 } else if ((*ppdu_id > msdu_ppdu_id) && 4567 ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4568 /* mon_dst is behind than mon_status 4569 * skip dst_ring and free it 4570 */ 4571 *rx_bufs_used += 1; 4572 *ppdu_id = msdu_ppdu_id; 4573 ret = msdu_ppdu_id; 4574 } 4575 return ret; 4576 } 4577 4578 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4579 bool *is_frag, u32 *total_len, 4580 u32 *frag_len, u32 *msdu_cnt) 4581 { 4582 if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4583 if (!*is_frag) { 4584 *total_len = info->msdu_len; 4585 *is_frag = true; 4586 } 4587 ath11k_dp_mon_set_frag_len(total_len, 4588 frag_len); 4589 } else { 4590 if (*is_frag) { 4591 ath11k_dp_mon_set_frag_len(total_len, 4592 frag_len); 4593 } else { 4594 *frag_len = info->msdu_len; 4595 } 4596 *is_frag = false; 4597 *msdu_cnt -= 1; 4598 } 4599 } 4600 4601 static u32 4602 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id, 4603 void *ring_entry, struct sk_buff **head_msdu, 4604 struct sk_buff **tail_msdu, u32 *npackets, 4605 u32 *ppdu_id) 4606 { 4607 struct ath11k_pdev_dp *dp = &ar->dp; 4608 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4609 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4610 struct sk_buff *msdu = NULL, *last = NULL; 4611 struct hal_rx_msdu_list msdu_list; 4612 void *p_buf_addr_info, *p_last_buf_addr_info; 4613 struct hal_rx_desc *rx_desc; 4614 void *rx_msdu_link_desc; 4615 dma_addr_t paddr; 4616 u16 num_msdus = 0; 4617 u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4618 u32 rx_bufs_used = 0, i = 0; 4619 u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4620 u32 total_len = 0, frag_len = 0; 4621 bool is_frag, is_first_msdu; 4622 bool drop_mpdu = false; 4623 struct ath11k_skb_rxcb *rxcb; 4624 struct hal_reo_entrance_ring *ent_desc = 4625 (struct hal_reo_entrance_ring *)ring_entry; 4626 int buf_id; 4627 u32 rx_link_buf_info[2]; 4628 u8 rbm; 4629 4630 if (!ar->ab->hw_params.rxdma1_enable) 4631 rx_ring = &dp->rx_refill_buf_ring; 4632 4633 ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4634 &sw_cookie, 4635 &p_last_buf_addr_info, &rbm, 4636 &msdu_cnt); 4637 4638 if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4639 ent_desc->info1) == 4640 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4641 u8 rxdma_err = 4642 FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4643 ent_desc->info1); 4644 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4645 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4646 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4647 drop_mpdu = true; 4648 pmon->rx_mon_stats.dest_mpdu_drop++; 4649 } 4650 } 4651 4652 is_frag = false; 4653 is_first_msdu = true; 4654 4655 do { 4656 if (pmon->mon_last_linkdesc_paddr == paddr) { 4657 pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4658 return rx_bufs_used; 4659 } 4660 4661 if (ar->ab->hw_params.rxdma1_enable) 4662 rx_msdu_link_desc = 4663 (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4664 (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4665 else 4666 rx_msdu_link_desc = 4667 (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr + 4668 (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr); 4669 4670 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4671 &num_msdus); 4672 4673 for (i = 0; i < num_msdus; i++) { 4674 u32 l2_hdr_offset; 4675 4676 if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4677 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4678 "i %d last_cookie %d is same\n", 4679 i, pmon->mon_last_buf_cookie); 4680 drop_mpdu = true; 4681 pmon->rx_mon_stats.dup_mon_buf_cnt++; 4682 continue; 4683 } 4684 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4685 msdu_list.sw_cookie[i]); 4686 4687 spin_lock_bh(&rx_ring->idr_lock); 4688 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4689 spin_unlock_bh(&rx_ring->idr_lock); 4690 if (!msdu) { 4691 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4692 "msdu_pop: invalid buf_id %d\n", buf_id); 4693 break; 4694 } 4695 rxcb = ATH11K_SKB_RXCB(msdu); 4696 if (!rxcb->unmapped) { 4697 dma_unmap_single(ar->ab->dev, rxcb->paddr, 4698 msdu->len + 4699 skb_tailroom(msdu), 4700 DMA_FROM_DEVICE); 4701 rxcb->unmapped = 1; 4702 } 4703 if (drop_mpdu) { 4704 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4705 "i %d drop msdu %p *ppdu_id %x\n", 4706 i, msdu, *ppdu_id); 4707 dev_kfree_skb_any(msdu); 4708 msdu = NULL; 4709 goto next_msdu; 4710 } 4711 4712 rx_desc = (struct hal_rx_desc *)msdu->data; 4713 4714 rx_pkt_offset = sizeof(struct hal_rx_desc); 4715 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 4716 4717 if (is_first_msdu) { 4718 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 4719 drop_mpdu = true; 4720 dev_kfree_skb_any(msdu); 4721 msdu = NULL; 4722 pmon->mon_last_linkdesc_paddr = paddr; 4723 goto next_msdu; 4724 } 4725 4726 msdu_ppdu_id = 4727 ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc); 4728 4729 if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4730 ppdu_id, 4731 &rx_bufs_used)) { 4732 if (rx_bufs_used) { 4733 drop_mpdu = true; 4734 dev_kfree_skb_any(msdu); 4735 msdu = NULL; 4736 goto next_msdu; 4737 } 4738 return rx_bufs_used; 4739 } 4740 pmon->mon_last_linkdesc_paddr = paddr; 4741 is_first_msdu = false; 4742 } 4743 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4744 &is_frag, &total_len, 4745 &frag_len, &msdu_cnt); 4746 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4747 4748 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4749 4750 if (!(*head_msdu)) 4751 *head_msdu = msdu; 4752 else if (last) 4753 last->next = msdu; 4754 4755 last = msdu; 4756 next_msdu: 4757 pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4758 rx_bufs_used++; 4759 spin_lock_bh(&rx_ring->idr_lock); 4760 idr_remove(&rx_ring->bufs_idr, buf_id); 4761 spin_unlock_bh(&rx_ring->idr_lock); 4762 } 4763 4764 ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm); 4765 4766 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4767 &sw_cookie, &rbm, 4768 &p_buf_addr_info); 4769 4770 if (ar->ab->hw_params.rxdma1_enable) { 4771 if (ath11k_dp_rx_monitor_link_desc_return(ar, 4772 p_last_buf_addr_info, 4773 dp->mac_id)) 4774 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4775 "dp_rx_monitor_link_desc_return failed"); 4776 } else { 4777 ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info, 4778 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4779 } 4780 4781 p_last_buf_addr_info = p_buf_addr_info; 4782 4783 } while (paddr && msdu_cnt); 4784 4785 if (last) 4786 last->next = NULL; 4787 4788 *tail_msdu = msdu; 4789 4790 if (msdu_cnt == 0) 4791 *npackets = 1; 4792 4793 return rx_bufs_used; 4794 } 4795 4796 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu) 4797 { 4798 u32 rx_pkt_offset, l2_hdr_offset; 4799 4800 rx_pkt_offset = ar->ab->hw_params.hal_desc_sz; 4801 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, 4802 (struct hal_rx_desc *)msdu->data); 4803 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4804 } 4805 4806 static struct sk_buff * 4807 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4808 u32 mac_id, struct sk_buff *head_msdu, 4809 struct sk_buff *last_msdu, 4810 struct ieee80211_rx_status *rxs, bool *fcs_err) 4811 { 4812 struct ath11k_base *ab = ar->ab; 4813 struct sk_buff *msdu, *prev_buf; 4814 struct hal_rx_desc *rx_desc; 4815 char *hdr_desc; 4816 u8 *dest, decap_format; 4817 struct ieee80211_hdr_3addr *wh; 4818 struct rx_attention *rx_attention; 4819 u32 err_bitmap; 4820 4821 if (!head_msdu) 4822 goto err_merge_fail; 4823 4824 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4825 rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc); 4826 err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 4827 4828 if (err_bitmap & DP_RX_MPDU_ERR_FCS) 4829 *fcs_err = true; 4830 4831 if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention)) 4832 return NULL; 4833 4834 decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc); 4835 4836 ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4837 4838 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4839 ath11k_dp_rx_msdus_set_payload(ar, head_msdu); 4840 4841 prev_buf = head_msdu; 4842 msdu = head_msdu->next; 4843 4844 while (msdu) { 4845 ath11k_dp_rx_msdus_set_payload(ar, msdu); 4846 4847 prev_buf = msdu; 4848 msdu = msdu->next; 4849 } 4850 4851 prev_buf->next = NULL; 4852 4853 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4854 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4855 u8 qos_pkt = 0; 4856 4857 rx_desc = (struct hal_rx_desc *)head_msdu->data; 4858 hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc); 4859 4860 /* Base size */ 4861 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4862 4863 if (ieee80211_is_data_qos(wh->frame_control)) 4864 qos_pkt = 1; 4865 4866 msdu = head_msdu; 4867 4868 while (msdu) { 4869 ath11k_dp_rx_msdus_set_payload(ar, msdu); 4870 if (qos_pkt) { 4871 dest = skb_push(msdu, sizeof(__le16)); 4872 if (!dest) 4873 goto err_merge_fail; 4874 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 4875 } 4876 prev_buf = msdu; 4877 msdu = msdu->next; 4878 } 4879 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4880 if (!dest) 4881 goto err_merge_fail; 4882 4883 ath11k_dbg(ab, ATH11K_DBG_DATA, 4884 "mpdu_buf %pK mpdu_buf->len %u", 4885 prev_buf, prev_buf->len); 4886 } else { 4887 ath11k_dbg(ab, ATH11K_DBG_DATA, 4888 "decap format %d is not supported!\n", 4889 decap_format); 4890 goto err_merge_fail; 4891 } 4892 4893 return head_msdu; 4894 4895 err_merge_fail: 4896 return NULL; 4897 } 4898 4899 static void 4900 ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 4901 u8 *rtap_buf) 4902 { 4903 u32 rtap_len = 0; 4904 4905 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 4906 rtap_len += 2; 4907 4908 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 4909 rtap_len += 2; 4910 4911 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 4912 rtap_len += 2; 4913 4914 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 4915 rtap_len += 2; 4916 4917 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 4918 rtap_len += 2; 4919 4920 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 4921 } 4922 4923 static void 4924 ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 4925 u8 *rtap_buf) 4926 { 4927 u32 rtap_len = 0; 4928 4929 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 4930 rtap_len += 2; 4931 4932 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 4933 rtap_len += 2; 4934 4935 rtap_buf[rtap_len] = rx_status->he_RU[0]; 4936 rtap_len += 1; 4937 4938 rtap_buf[rtap_len] = rx_status->he_RU[1]; 4939 rtap_len += 1; 4940 4941 rtap_buf[rtap_len] = rx_status->he_RU[2]; 4942 rtap_len += 1; 4943 4944 rtap_buf[rtap_len] = rx_status->he_RU[3]; 4945 } 4946 4947 static void ath11k_update_radiotap(struct ath11k *ar, 4948 struct hal_rx_mon_ppdu_info *ppduinfo, 4949 struct sk_buff *mon_skb, 4950 struct ieee80211_rx_status *rxs) 4951 { 4952 struct ieee80211_supported_band *sband; 4953 u8 *ptr = NULL; 4954 4955 rxs->flag |= RX_FLAG_MACTIME_START; 4956 rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR; 4957 4958 if (ppduinfo->nss) 4959 rxs->nss = ppduinfo->nss; 4960 4961 if (ppduinfo->he_mu_flags) { 4962 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 4963 rxs->encoding = RX_ENC_HE; 4964 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 4965 ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr); 4966 } else if (ppduinfo->he_flags) { 4967 rxs->flag |= RX_FLAG_RADIOTAP_HE; 4968 rxs->encoding = RX_ENC_HE; 4969 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 4970 ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr); 4971 rxs->rate_idx = ppduinfo->rate; 4972 } else if (ppduinfo->vht_flags) { 4973 rxs->encoding = RX_ENC_VHT; 4974 rxs->rate_idx = ppduinfo->rate; 4975 } else if (ppduinfo->ht_flags) { 4976 rxs->encoding = RX_ENC_HT; 4977 rxs->rate_idx = ppduinfo->rate; 4978 } else { 4979 rxs->encoding = RX_ENC_LEGACY; 4980 sband = &ar->mac.sbands[rxs->band]; 4981 rxs->rate_idx = ath11k_mac_hw_rate_to_idx(sband, ppduinfo->rate, 4982 ppduinfo->cck_flag); 4983 } 4984 4985 rxs->mactime = ppduinfo->tsft; 4986 } 4987 4988 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 4989 struct sk_buff *head_msdu, 4990 struct hal_rx_mon_ppdu_info *ppduinfo, 4991 struct sk_buff *tail_msdu, 4992 struct napi_struct *napi) 4993 { 4994 struct ath11k_pdev_dp *dp = &ar->dp; 4995 struct sk_buff *mon_skb, *skb_next, *header; 4996 struct ieee80211_rx_status *rxs = &dp->rx_status; 4997 bool fcs_err = false; 4998 4999 mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 5000 tail_msdu, rxs, &fcs_err); 5001 5002 if (!mon_skb) 5003 goto mon_deliver_fail; 5004 5005 header = mon_skb; 5006 5007 rxs->flag = 0; 5008 5009 if (fcs_err) 5010 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 5011 5012 do { 5013 skb_next = mon_skb->next; 5014 if (!skb_next) 5015 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 5016 else 5017 rxs->flag |= RX_FLAG_AMSDU_MORE; 5018 5019 if (mon_skb == header) { 5020 header = NULL; 5021 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 5022 } else { 5023 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 5024 } 5025 ath11k_update_radiotap(ar, ppduinfo, mon_skb, rxs); 5026 5027 ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs); 5028 mon_skb = skb_next; 5029 } while (mon_skb); 5030 rxs->flag = 0; 5031 5032 return 0; 5033 5034 mon_deliver_fail: 5035 mon_skb = head_msdu; 5036 while (mon_skb) { 5037 skb_next = mon_skb->next; 5038 dev_kfree_skb_any(mon_skb); 5039 mon_skb = skb_next; 5040 } 5041 return -EINVAL; 5042 } 5043 5044 /* The destination ring processing is stuck if the destination is not 5045 * moving while status ring moves 16 PPDU. The destination ring processing 5046 * skips this destination ring PPDU as a workaround. 5047 */ 5048 #define MON_DEST_RING_STUCK_MAX_CNT 16 5049 5050 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id, 5051 u32 quota, struct napi_struct *napi) 5052 { 5053 struct ath11k_pdev_dp *dp = &ar->dp; 5054 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5055 const struct ath11k_hw_hal_params *hal_params; 5056 void *ring_entry; 5057 void *mon_dst_srng; 5058 u32 ppdu_id; 5059 u32 rx_bufs_used; 5060 u32 ring_id; 5061 struct ath11k_pdev_mon_stats *rx_mon_stats; 5062 u32 npackets = 0; 5063 u32 mpdu_rx_bufs_used; 5064 5065 if (ar->ab->hw_params.rxdma1_enable) 5066 ring_id = dp->rxdma_mon_dst_ring.ring_id; 5067 else 5068 ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 5069 5070 mon_dst_srng = &ar->ab->hal.srng_list[ring_id]; 5071 5072 if (!mon_dst_srng) { 5073 ath11k_warn(ar->ab, 5074 "HAL Monitor Destination Ring Init Failed -- %pK", 5075 mon_dst_srng); 5076 return; 5077 } 5078 5079 spin_lock_bh(&pmon->mon_lock); 5080 5081 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5082 5083 ppdu_id = pmon->mon_ppdu_info.ppdu_id; 5084 rx_bufs_used = 0; 5085 rx_mon_stats = &pmon->rx_mon_stats; 5086 5087 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5088 struct sk_buff *head_msdu, *tail_msdu; 5089 5090 head_msdu = NULL; 5091 tail_msdu = NULL; 5092 5093 mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry, 5094 &head_msdu, 5095 &tail_msdu, 5096 &npackets, &ppdu_id); 5097 5098 rx_bufs_used += mpdu_rx_bufs_used; 5099 5100 if (mpdu_rx_bufs_used) { 5101 dp->mon_dest_ring_stuck_cnt = 0; 5102 } else { 5103 dp->mon_dest_ring_stuck_cnt++; 5104 rx_mon_stats->dest_mon_not_reaped++; 5105 } 5106 5107 if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) { 5108 rx_mon_stats->dest_mon_stuck++; 5109 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5110 "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n", 5111 pmon->mon_ppdu_info.ppdu_id, ppdu_id, 5112 dp->mon_dest_ring_stuck_cnt, 5113 rx_mon_stats->dest_mon_not_reaped, 5114 rx_mon_stats->dest_mon_stuck); 5115 pmon->mon_ppdu_info.ppdu_id = ppdu_id; 5116 continue; 5117 } 5118 5119 if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 5120 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5121 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5122 "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n", 5123 ppdu_id, pmon->mon_ppdu_info.ppdu_id, 5124 rx_mon_stats->dest_mon_not_reaped, 5125 rx_mon_stats->dest_mon_stuck); 5126 break; 5127 } 5128 if (head_msdu && tail_msdu) { 5129 ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 5130 &pmon->mon_ppdu_info, 5131 tail_msdu, napi); 5132 rx_mon_stats->dest_mpdu_done++; 5133 } 5134 5135 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5136 mon_dst_srng); 5137 } 5138 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5139 5140 spin_unlock_bh(&pmon->mon_lock); 5141 5142 if (rx_bufs_used) { 5143 rx_mon_stats->dest_ppdu_done++; 5144 hal_params = ar->ab->hw_params.hal_params; 5145 5146 if (ar->ab->hw_params.rxdma1_enable) 5147 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5148 &dp->rxdma_mon_buf_ring, 5149 rx_bufs_used, 5150 hal_params->rx_buf_rbm); 5151 else 5152 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5153 &dp->rx_refill_buf_ring, 5154 rx_bufs_used, 5155 hal_params->rx_buf_rbm); 5156 } 5157 } 5158 5159 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 5160 struct napi_struct *napi, int budget) 5161 { 5162 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5163 enum hal_rx_mon_status hal_status; 5164 struct sk_buff *skb; 5165 struct sk_buff_head skb_list; 5166 struct ath11k_peer *peer; 5167 struct ath11k_sta *arsta; 5168 int num_buffs_reaped = 0; 5169 u32 rx_buf_sz; 5170 u16 log_type; 5171 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data; 5172 struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats; 5173 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 5174 5175 __skb_queue_head_init(&skb_list); 5176 5177 num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 5178 &skb_list); 5179 if (!num_buffs_reaped) 5180 goto exit; 5181 5182 memset(ppdu_info, 0, sizeof(*ppdu_info)); 5183 ppdu_info->peer_id = HAL_INVALID_PEERID; 5184 5185 while ((skb = __skb_dequeue(&skb_list))) { 5186 if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) { 5187 log_type = ATH11K_PKTLOG_TYPE_LITE_RX; 5188 rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; 5189 } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) { 5190 log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF; 5191 rx_buf_sz = DP_RX_BUFFER_SIZE; 5192 } else { 5193 log_type = ATH11K_PKTLOG_TYPE_INVALID; 5194 rx_buf_sz = 0; 5195 } 5196 5197 if (log_type != ATH11K_PKTLOG_TYPE_INVALID) 5198 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 5199 5200 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); 5201 hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb); 5202 5203 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 5204 pmon->mon_ppdu_status == DP_PPDU_STATUS_START && 5205 hal_status == HAL_TLV_STATUS_PPDU_DONE) { 5206 rx_mon_stats->status_ppdu_done++; 5207 pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 5208 ath11k_dp_rx_mon_dest_process(ar, mac_id, budget, napi); 5209 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5210 } 5211 5212 if (ppdu_info->peer_id == HAL_INVALID_PEERID || 5213 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 5214 dev_kfree_skb_any(skb); 5215 continue; 5216 } 5217 5218 rcu_read_lock(); 5219 spin_lock_bh(&ab->base_lock); 5220 peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id); 5221 5222 if (!peer || !peer->sta) { 5223 ath11k_dbg(ab, ATH11K_DBG_DATA, 5224 "failed to find the peer with peer_id %d\n", 5225 ppdu_info->peer_id); 5226 goto next_skb; 5227 } 5228 5229 arsta = (struct ath11k_sta *)peer->sta->drv_priv; 5230 ath11k_dp_rx_update_peer_stats(arsta, ppdu_info); 5231 5232 if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) 5233 trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 5234 5235 next_skb: 5236 spin_unlock_bh(&ab->base_lock); 5237 rcu_read_unlock(); 5238 5239 dev_kfree_skb_any(skb); 5240 memset(ppdu_info, 0, sizeof(*ppdu_info)); 5241 ppdu_info->peer_id = HAL_INVALID_PEERID; 5242 } 5243 exit: 5244 return num_buffs_reaped; 5245 } 5246 5247 static u32 5248 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar, 5249 void *ring_entry, struct sk_buff **head_msdu, 5250 struct sk_buff **tail_msdu, 5251 struct hal_sw_mon_ring_entries *sw_mon_entries) 5252 { 5253 struct ath11k_pdev_dp *dp = &ar->dp; 5254 struct ath11k_mon_data *pmon = &dp->mon_data; 5255 struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 5256 struct sk_buff *msdu = NULL, *last = NULL; 5257 struct hal_sw_monitor_ring *sw_desc = ring_entry; 5258 struct hal_rx_msdu_list msdu_list; 5259 struct hal_rx_desc *rx_desc; 5260 struct ath11k_skb_rxcb *rxcb; 5261 void *rx_msdu_link_desc; 5262 void *p_buf_addr_info, *p_last_buf_addr_info; 5263 int buf_id, i = 0; 5264 u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset; 5265 u32 rx_bufs_used = 0, msdu_cnt = 0; 5266 u32 total_len = 0, frag_len = 0, sw_cookie; 5267 u16 num_msdus = 0; 5268 u8 rxdma_err, rbm; 5269 bool is_frag, is_first_msdu; 5270 bool drop_mpdu = false; 5271 5272 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries); 5273 5274 sw_cookie = sw_mon_entries->mon_dst_sw_cookie; 5275 sw_mon_entries->end_of_ppdu = false; 5276 sw_mon_entries->drop_ppdu = false; 5277 p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info; 5278 msdu_cnt = sw_mon_entries->msdu_cnt; 5279 5280 sw_mon_entries->end_of_ppdu = 5281 FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0); 5282 if (sw_mon_entries->end_of_ppdu) 5283 return rx_bufs_used; 5284 5285 if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON, 5286 sw_desc->info0) == 5287 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 5288 rxdma_err = 5289 FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE, 5290 sw_desc->info0); 5291 if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 5292 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 5293 rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 5294 pmon->rx_mon_stats.dest_mpdu_drop++; 5295 drop_mpdu = true; 5296 } 5297 } 5298 5299 is_frag = false; 5300 is_first_msdu = true; 5301 5302 do { 5303 rx_msdu_link_desc = 5304 (u8 *)pmon->link_desc_banks[sw_cookie].vaddr + 5305 (sw_mon_entries->mon_dst_paddr - 5306 pmon->link_desc_banks[sw_cookie].paddr); 5307 5308 ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 5309 &num_msdus); 5310 5311 for (i = 0; i < num_msdus; i++) { 5312 buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 5313 msdu_list.sw_cookie[i]); 5314 5315 spin_lock_bh(&rx_ring->idr_lock); 5316 msdu = idr_find(&rx_ring->bufs_idr, buf_id); 5317 if (!msdu) { 5318 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5319 "full mon msdu_pop: invalid buf_id %d\n", 5320 buf_id); 5321 spin_unlock_bh(&rx_ring->idr_lock); 5322 break; 5323 } 5324 idr_remove(&rx_ring->bufs_idr, buf_id); 5325 spin_unlock_bh(&rx_ring->idr_lock); 5326 5327 rxcb = ATH11K_SKB_RXCB(msdu); 5328 if (!rxcb->unmapped) { 5329 dma_unmap_single(ar->ab->dev, rxcb->paddr, 5330 msdu->len + 5331 skb_tailroom(msdu), 5332 DMA_FROM_DEVICE); 5333 rxcb->unmapped = 1; 5334 } 5335 if (drop_mpdu) { 5336 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5337 "full mon: i %d drop msdu %p *ppdu_id %x\n", 5338 i, msdu, sw_mon_entries->ppdu_id); 5339 dev_kfree_skb_any(msdu); 5340 msdu_cnt--; 5341 goto next_msdu; 5342 } 5343 5344 rx_desc = (struct hal_rx_desc *)msdu->data; 5345 5346 rx_pkt_offset = sizeof(struct hal_rx_desc); 5347 l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 5348 5349 if (is_first_msdu) { 5350 if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 5351 drop_mpdu = true; 5352 dev_kfree_skb_any(msdu); 5353 msdu = NULL; 5354 goto next_msdu; 5355 } 5356 is_first_msdu = false; 5357 } 5358 5359 ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 5360 &is_frag, &total_len, 5361 &frag_len, &msdu_cnt); 5362 5363 rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 5364 5365 ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 5366 5367 if (!(*head_msdu)) 5368 *head_msdu = msdu; 5369 else if (last) 5370 last->next = msdu; 5371 5372 last = msdu; 5373 next_msdu: 5374 rx_bufs_used++; 5375 } 5376 5377 ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, 5378 &sw_mon_entries->mon_dst_paddr, 5379 &sw_mon_entries->mon_dst_sw_cookie, 5380 &rbm, 5381 &p_buf_addr_info); 5382 5383 if (ath11k_dp_rx_monitor_link_desc_return(ar, 5384 p_last_buf_addr_info, 5385 dp->mac_id)) 5386 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5387 "full mon: dp_rx_monitor_link_desc_return failed\n"); 5388 5389 p_last_buf_addr_info = p_buf_addr_info; 5390 5391 } while (sw_mon_entries->mon_dst_paddr && msdu_cnt); 5392 5393 if (last) 5394 last->next = NULL; 5395 5396 *tail_msdu = msdu; 5397 5398 return rx_bufs_used; 5399 } 5400 5401 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp, 5402 struct dp_full_mon_mpdu *mon_mpdu, 5403 struct sk_buff *head, 5404 struct sk_buff *tail) 5405 { 5406 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 5407 if (!mon_mpdu) 5408 return -ENOMEM; 5409 5410 list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list); 5411 mon_mpdu->head = head; 5412 mon_mpdu->tail = tail; 5413 5414 return 0; 5415 } 5416 5417 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp, 5418 struct dp_full_mon_mpdu *mon_mpdu) 5419 { 5420 struct dp_full_mon_mpdu *tmp; 5421 struct sk_buff *tmp_msdu, *skb_next; 5422 5423 if (list_empty(&dp->dp_full_mon_mpdu_list)) 5424 return; 5425 5426 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 5427 list_del(&mon_mpdu->list); 5428 5429 tmp_msdu = mon_mpdu->head; 5430 while (tmp_msdu) { 5431 skb_next = tmp_msdu->next; 5432 dev_kfree_skb_any(tmp_msdu); 5433 tmp_msdu = skb_next; 5434 } 5435 5436 kfree(mon_mpdu); 5437 } 5438 } 5439 5440 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar, 5441 int mac_id, 5442 struct ath11k_mon_data *pmon, 5443 struct napi_struct *napi) 5444 { 5445 struct ath11k_pdev_mon_stats *rx_mon_stats; 5446 struct dp_full_mon_mpdu *tmp; 5447 struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 5448 struct sk_buff *head_msdu, *tail_msdu; 5449 struct ath11k_base *ab = ar->ab; 5450 struct ath11k_dp *dp = &ab->dp; 5451 int ret; 5452 5453 rx_mon_stats = &pmon->rx_mon_stats; 5454 5455 list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 5456 list_del(&mon_mpdu->list); 5457 head_msdu = mon_mpdu->head; 5458 tail_msdu = mon_mpdu->tail; 5459 if (head_msdu && tail_msdu) { 5460 ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu, 5461 &pmon->mon_ppdu_info, 5462 tail_msdu, napi); 5463 rx_mon_stats->dest_mpdu_done++; 5464 ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n"); 5465 } 5466 kfree(mon_mpdu); 5467 } 5468 5469 return ret; 5470 } 5471 5472 static int 5473 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id, 5474 struct napi_struct *napi, int budget) 5475 { 5476 struct ath11k *ar = ab->pdevs[mac_id].ar; 5477 struct ath11k_pdev_dp *dp = &ar->dp; 5478 struct ath11k_mon_data *pmon = &dp->mon_data; 5479 struct hal_sw_mon_ring_entries *sw_mon_entries; 5480 int quota = 0, work = 0, count; 5481 5482 sw_mon_entries = &pmon->sw_mon_entries; 5483 5484 while (pmon->hold_mon_dst_ring) { 5485 quota = ath11k_dp_rx_process_mon_status(ab, mac_id, 5486 napi, 1); 5487 if (pmon->buf_state == DP_MON_STATUS_MATCH) { 5488 count = sw_mon_entries->status_buf_count; 5489 if (count > 1) { 5490 quota += ath11k_dp_rx_process_mon_status(ab, mac_id, 5491 napi, count); 5492 } 5493 5494 ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id, 5495 pmon, napi); 5496 pmon->hold_mon_dst_ring = false; 5497 } else if (!pmon->mon_status_paddr || 5498 pmon->buf_state == DP_MON_STATUS_LEAD) { 5499 sw_mon_entries->drop_ppdu = true; 5500 pmon->hold_mon_dst_ring = false; 5501 } 5502 5503 if (!quota) 5504 break; 5505 5506 work += quota; 5507 } 5508 5509 if (sw_mon_entries->drop_ppdu) 5510 ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu); 5511 5512 return work; 5513 } 5514 5515 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id, 5516 struct napi_struct *napi, int budget) 5517 { 5518 struct ath11k *ar = ab->pdevs[mac_id].ar; 5519 struct ath11k_pdev_dp *dp = &ar->dp; 5520 struct ath11k_mon_data *pmon = &dp->mon_data; 5521 struct hal_sw_mon_ring_entries *sw_mon_entries; 5522 struct ath11k_pdev_mon_stats *rx_mon_stats; 5523 struct sk_buff *head_msdu, *tail_msdu; 5524 void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id]; 5525 void *ring_entry; 5526 u32 rx_bufs_used = 0, mpdu_rx_bufs_used; 5527 int quota = 0, ret; 5528 bool break_dst_ring = false; 5529 5530 spin_lock_bh(&pmon->mon_lock); 5531 5532 sw_mon_entries = &pmon->sw_mon_entries; 5533 rx_mon_stats = &pmon->rx_mon_stats; 5534 5535 if (pmon->hold_mon_dst_ring) { 5536 spin_unlock_bh(&pmon->mon_lock); 5537 goto reap_status_ring; 5538 } 5539 5540 ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5541 while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5542 head_msdu = NULL; 5543 tail_msdu = NULL; 5544 5545 mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry, 5546 &head_msdu, 5547 &tail_msdu, 5548 sw_mon_entries); 5549 rx_bufs_used += mpdu_rx_bufs_used; 5550 5551 if (!sw_mon_entries->end_of_ppdu) { 5552 if (head_msdu) { 5553 ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp, 5554 pmon->mon_mpdu, 5555 head_msdu, 5556 tail_msdu); 5557 if (ret) 5558 break_dst_ring = true; 5559 } 5560 5561 goto next_entry; 5562 } else { 5563 if (!sw_mon_entries->ppdu_id && 5564 !sw_mon_entries->mon_status_paddr) { 5565 break_dst_ring = true; 5566 goto next_entry; 5567 } 5568 } 5569 5570 rx_mon_stats->dest_ppdu_done++; 5571 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5572 pmon->buf_state = DP_MON_STATUS_LAG; 5573 pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr; 5574 pmon->hold_mon_dst_ring = true; 5575 next_entry: 5576 ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5577 mon_dst_srng); 5578 if (break_dst_ring) 5579 break; 5580 } 5581 5582 ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5583 spin_unlock_bh(&pmon->mon_lock); 5584 5585 if (rx_bufs_used) { 5586 ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5587 &dp->rxdma_mon_buf_ring, 5588 rx_bufs_used, 5589 HAL_RX_BUF_RBM_SW3_BM); 5590 } 5591 5592 reap_status_ring: 5593 quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id, 5594 napi, budget); 5595 5596 return quota; 5597 } 5598 5599 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 5600 struct napi_struct *napi, int budget) 5601 { 5602 struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5603 int ret = 0; 5604 5605 if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 5606 ab->hw_params.full_monitor_mode) 5607 ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget); 5608 else 5609 ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 5610 5611 return ret; 5612 } 5613 5614 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 5615 { 5616 struct ath11k_pdev_dp *dp = &ar->dp; 5617 struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5618 5619 skb_queue_head_init(&pmon->rx_status_q); 5620 5621 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5622 5623 memset(&pmon->rx_mon_stats, 0, 5624 sizeof(pmon->rx_mon_stats)); 5625 return 0; 5626 } 5627 5628 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 5629 { 5630 struct ath11k_pdev_dp *dp = &ar->dp; 5631 struct ath11k_mon_data *pmon = &dp->mon_data; 5632 struct hal_srng *mon_desc_srng = NULL; 5633 struct dp_srng *dp_srng; 5634 int ret = 0; 5635 u32 n_link_desc = 0; 5636 5637 ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 5638 if (ret) { 5639 ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 5640 return ret; 5641 } 5642 5643 /* if rxdma1_enable is false, no need to setup 5644 * rxdma_mon_desc_ring. 5645 */ 5646 if (!ar->ab->hw_params.rxdma1_enable) 5647 return 0; 5648 5649 dp_srng = &dp->rxdma_mon_desc_ring; 5650 n_link_desc = dp_srng->size / 5651 ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC); 5652 mon_desc_srng = 5653 &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 5654 5655 ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 5656 HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 5657 n_link_desc); 5658 if (ret) { 5659 ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 5660 return ret; 5661 } 5662 pmon->mon_last_linkdesc_paddr = 0; 5663 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 5664 spin_lock_init(&pmon->mon_lock); 5665 5666 return 0; 5667 } 5668 5669 static int ath11k_dp_mon_link_free(struct ath11k *ar) 5670 { 5671 struct ath11k_pdev_dp *dp = &ar->dp; 5672 struct ath11k_mon_data *pmon = &dp->mon_data; 5673 5674 ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 5675 HAL_RXDMA_MONITOR_DESC, 5676 &dp->rxdma_mon_desc_ring); 5677 return 0; 5678 } 5679 5680 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 5681 { 5682 ath11k_dp_mon_link_free(ar); 5683 return 0; 5684 } 5685 5686 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab) 5687 { 5688 /* start reap timer */ 5689 mod_timer(&ab->mon_reap_timer, 5690 jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 5691 5692 return 0; 5693 } 5694 5695 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer) 5696 { 5697 int ret; 5698 5699 if (stop_timer) 5700 del_timer_sync(&ab->mon_reap_timer); 5701 5702 /* reap all the monitor related rings */ 5703 ret = ath11k_dp_purge_mon_ring(ab); 5704 if (ret) { 5705 ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 5706 return ret; 5707 } 5708 5709 return 0; 5710 } 5711