1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/ieee80211.h>
7 #include <linux/kernel.h>
8 #include <linux/skbuff.h>
9 #include <crypto/hash.h>
10 #include "core.h"
11 #include "debug.h"
12 #include "debugfs_htt_stats.h"
13 #include "debugfs_sta.h"
14 #include "hal_desc.h"
15 #include "hw.h"
16 #include "dp_rx.h"
17 #include "hal_rx.h"
18 #include "dp_tx.h"
19 #include "peer.h"
20 
21 #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
22 
23 static inline
24 u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc)
25 {
26 	return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc);
27 }
28 
29 static inline
30 enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab,
31 							struct hal_rx_desc *desc)
32 {
33 	if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc))
34 		return HAL_ENCRYPT_TYPE_OPEN;
35 
36 	return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc);
37 }
38 
39 static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab,
40 						      struct hal_rx_desc *desc)
41 {
42 	return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc);
43 }
44 
45 static inline
46 u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab,
47 					      struct hal_rx_desc *desc)
48 {
49 	return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc);
50 }
51 
52 static inline
53 bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab,
54 					      struct hal_rx_desc *desc)
55 {
56 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc);
57 }
58 
59 static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab,
60 						      struct hal_rx_desc *desc)
61 {
62 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc);
63 }
64 
65 static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab,
66 							struct sk_buff *skb)
67 {
68 	struct ieee80211_hdr *hdr;
69 
70 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
71 	return ieee80211_has_morefrags(hdr->frame_control);
72 }
73 
74 static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab,
75 						    struct sk_buff *skb)
76 {
77 	struct ieee80211_hdr *hdr;
78 
79 	hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz);
80 	return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
81 }
82 
83 static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab,
84 						   struct hal_rx_desc *desc)
85 {
86 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc);
87 }
88 
89 static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab,
90 					       struct hal_rx_desc *desc)
91 {
92 	return ab->hw_params.hw_ops->rx_desc_get_attention(desc);
93 }
94 
95 static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn)
96 {
97 	return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE,
98 			   __le32_to_cpu(attn->info2));
99 }
100 
101 static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn)
102 {
103 	return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL,
104 			   __le32_to_cpu(attn->info1));
105 }
106 
107 static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn)
108 {
109 	return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL,
110 			   __le32_to_cpu(attn->info1));
111 }
112 
113 static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn)
114 {
115 	return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE,
116 			  __le32_to_cpu(attn->info2)) ==
117 		RX_DESC_DECRYPT_STATUS_CODE_OK);
118 }
119 
120 static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn)
121 {
122 	u32 info = __le32_to_cpu(attn->info1);
123 	u32 errmap = 0;
124 
125 	if (info & RX_ATTENTION_INFO1_FCS_ERR)
126 		errmap |= DP_RX_MPDU_ERR_FCS;
127 
128 	if (info & RX_ATTENTION_INFO1_DECRYPT_ERR)
129 		errmap |= DP_RX_MPDU_ERR_DECRYPT;
130 
131 	if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR)
132 		errmap |= DP_RX_MPDU_ERR_TKIP_MIC;
133 
134 	if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR)
135 		errmap |= DP_RX_MPDU_ERR_AMSDU_ERR;
136 
137 	if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR)
138 		errmap |= DP_RX_MPDU_ERR_OVERFLOW;
139 
140 	if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR)
141 		errmap |= DP_RX_MPDU_ERR_MSDU_LEN;
142 
143 	if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR)
144 		errmap |= DP_RX_MPDU_ERR_MPDU_LEN;
145 
146 	return errmap;
147 }
148 
149 static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab,
150 					     struct hal_rx_desc *desc)
151 {
152 	struct rx_attention *rx_attention;
153 	u32 errmap;
154 
155 	rx_attention = ath11k_dp_rx_get_attention(ab, desc);
156 	errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
157 
158 	return errmap & DP_RX_MPDU_ERR_MSDU_LEN;
159 }
160 
161 static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab,
162 						     struct hal_rx_desc *desc)
163 {
164 	return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc);
165 }
166 
167 static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab,
168 					       struct hal_rx_desc *desc)
169 {
170 	return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc);
171 }
172 
173 static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab,
174 						    struct hal_rx_desc *desc)
175 {
176 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc);
177 }
178 
179 static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab,
180 						 struct hal_rx_desc *desc)
181 {
182 	return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc);
183 }
184 
185 static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab,
186 						 struct hal_rx_desc *desc)
187 {
188 	return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc);
189 }
190 
191 static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab,
192 						    struct hal_rx_desc *desc)
193 {
194 	return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc);
195 }
196 
197 static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab,
198 					       struct hal_rx_desc *desc)
199 {
200 	return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc));
201 }
202 
203 static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab,
204 					       struct hal_rx_desc *desc)
205 {
206 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc);
207 }
208 
209 static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab,
210 						    struct hal_rx_desc *desc)
211 {
212 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc);
213 }
214 
215 static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab,
216 					       struct hal_rx_desc *desc)
217 {
218 	return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc);
219 }
220 
221 static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab,
222 						      struct hal_rx_desc *desc)
223 {
224 	return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc);
225 }
226 
227 static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab,
228 					      struct hal_rx_desc *desc)
229 {
230 	return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc);
231 }
232 
233 static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab,
234 					   struct hal_rx_desc *fdesc,
235 					   struct hal_rx_desc *ldesc)
236 {
237 	ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc);
238 }
239 
240 static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn)
241 {
242 	return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR,
243 			 __le32_to_cpu(attn->info1));
244 }
245 
246 static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab,
247 						struct hal_rx_desc *rx_desc)
248 {
249 	u8 *rx_pkt_hdr;
250 
251 	rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc);
252 
253 	return rx_pkt_hdr;
254 }
255 
256 static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab,
257 					       struct hal_rx_desc *rx_desc)
258 {
259 	u32 tlv_tag;
260 
261 	tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc);
262 
263 	return tlv_tag == HAL_RX_MPDU_START;
264 }
265 
266 static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab,
267 					      struct hal_rx_desc *rx_desc)
268 {
269 	return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc);
270 }
271 
272 static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab,
273 						 struct hal_rx_desc *desc,
274 						 u16 len)
275 {
276 	ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len);
277 }
278 
279 static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab,
280 					struct hal_rx_desc *desc)
281 {
282 	struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc);
283 
284 	return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) &&
285 		(!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST,
286 		 __le32_to_cpu(attn->info1)));
287 }
288 
289 static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab,
290 					     struct hal_rx_desc *desc)
291 {
292 	return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc);
293 }
294 
295 static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab,
296 					     struct hal_rx_desc *desc)
297 {
298 	return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc);
299 }
300 
301 static void ath11k_dp_service_mon_ring(struct timer_list *t)
302 {
303 	struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer);
304 	int i;
305 
306 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
307 		ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET);
308 
309 	mod_timer(&ab->mon_reap_timer, jiffies +
310 		  msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
311 }
312 
313 static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab)
314 {
315 	int i, reaped = 0;
316 	unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS);
317 
318 	do {
319 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++)
320 			reaped += ath11k_dp_rx_process_mon_rings(ab, i,
321 								 NULL,
322 								 DP_MON_SERVICE_BUDGET);
323 
324 		/* nothing more to reap */
325 		if (reaped < DP_MON_SERVICE_BUDGET)
326 			return 0;
327 
328 	} while (time_before(jiffies, timeout));
329 
330 	ath11k_warn(ab, "dp mon ring purge timeout");
331 
332 	return -ETIMEDOUT;
333 }
334 
335 /* Returns number of Rx buffers replenished */
336 int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id,
337 			       struct dp_rxdma_ring *rx_ring,
338 			       int req_entries,
339 			       enum hal_rx_buf_return_buf_manager mgr)
340 {
341 	struct hal_srng *srng;
342 	u32 *desc;
343 	struct sk_buff *skb;
344 	int num_free;
345 	int num_remain;
346 	int buf_id;
347 	u32 cookie;
348 	dma_addr_t paddr;
349 
350 	req_entries = min(req_entries, rx_ring->bufs_max);
351 
352 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
353 
354 	spin_lock_bh(&srng->lock);
355 
356 	ath11k_hal_srng_access_begin(ab, srng);
357 
358 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
359 	if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4))
360 		req_entries = num_free;
361 
362 	req_entries = min(num_free, req_entries);
363 	num_remain = req_entries;
364 
365 	while (num_remain > 0) {
366 		skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
367 				    DP_RX_BUFFER_ALIGN_SIZE);
368 		if (!skb)
369 			break;
370 
371 		if (!IS_ALIGNED((unsigned long)skb->data,
372 				DP_RX_BUFFER_ALIGN_SIZE)) {
373 			skb_pull(skb,
374 				 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
375 				 skb->data);
376 		}
377 
378 		paddr = dma_map_single(ab->dev, skb->data,
379 				       skb->len + skb_tailroom(skb),
380 				       DMA_FROM_DEVICE);
381 		if (dma_mapping_error(ab->dev, paddr))
382 			goto fail_free_skb;
383 
384 		spin_lock_bh(&rx_ring->idr_lock);
385 		buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
386 				   rx_ring->bufs_max * 3, GFP_ATOMIC);
387 		spin_unlock_bh(&rx_ring->idr_lock);
388 		if (buf_id < 0)
389 			goto fail_dma_unmap;
390 
391 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
392 		if (!desc)
393 			goto fail_idr_remove;
394 
395 		ATH11K_SKB_RXCB(skb)->paddr = paddr;
396 
397 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
398 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
399 
400 		num_remain--;
401 
402 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
403 	}
404 
405 	ath11k_hal_srng_access_end(ab, srng);
406 
407 	spin_unlock_bh(&srng->lock);
408 
409 	return req_entries - num_remain;
410 
411 fail_idr_remove:
412 	spin_lock_bh(&rx_ring->idr_lock);
413 	idr_remove(&rx_ring->bufs_idr, buf_id);
414 	spin_unlock_bh(&rx_ring->idr_lock);
415 fail_dma_unmap:
416 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
417 			 DMA_FROM_DEVICE);
418 fail_free_skb:
419 	dev_kfree_skb_any(skb);
420 
421 	ath11k_hal_srng_access_end(ab, srng);
422 
423 	spin_unlock_bh(&srng->lock);
424 
425 	return req_entries - num_remain;
426 }
427 
428 static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar,
429 					 struct dp_rxdma_ring *rx_ring)
430 {
431 	struct ath11k_pdev_dp *dp = &ar->dp;
432 	struct sk_buff *skb;
433 	int buf_id;
434 
435 	spin_lock_bh(&rx_ring->idr_lock);
436 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
437 		idr_remove(&rx_ring->bufs_idr, buf_id);
438 		/* TODO: Understand where internal driver does this dma_unmap
439 		 * of rxdma_buffer.
440 		 */
441 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
442 				 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE);
443 		dev_kfree_skb_any(skb);
444 	}
445 
446 	idr_destroy(&rx_ring->bufs_idr);
447 	spin_unlock_bh(&rx_ring->idr_lock);
448 
449 	/* if rxdma1_enable is false, mon_status_refill_ring
450 	 * isn't setup, so don't clean.
451 	 */
452 	if (!ar->ab->hw_params.rxdma1_enable)
453 		return 0;
454 
455 	rx_ring = &dp->rx_mon_status_refill_ring[0];
456 
457 	spin_lock_bh(&rx_ring->idr_lock);
458 	idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) {
459 		idr_remove(&rx_ring->bufs_idr, buf_id);
460 		/* XXX: Understand where internal driver does this dma_unmap
461 		 * of rxdma_buffer.
462 		 */
463 		dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr,
464 				 skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL);
465 		dev_kfree_skb_any(skb);
466 	}
467 
468 	idr_destroy(&rx_ring->bufs_idr);
469 	spin_unlock_bh(&rx_ring->idr_lock);
470 
471 	return 0;
472 }
473 
474 static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar)
475 {
476 	struct ath11k_pdev_dp *dp = &ar->dp;
477 	struct ath11k_base *ab = ar->ab;
478 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
479 	int i;
480 
481 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
482 
483 	rx_ring = &dp->rxdma_mon_buf_ring;
484 	ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
485 
486 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
487 		rx_ring = &dp->rx_mon_status_refill_ring[i];
488 		ath11k_dp_rxdma_buf_ring_free(ar, rx_ring);
489 	}
490 
491 	return 0;
492 }
493 
494 static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar,
495 					  struct dp_rxdma_ring *rx_ring,
496 					  u32 ringtype)
497 {
498 	struct ath11k_pdev_dp *dp = &ar->dp;
499 	int num_entries;
500 
501 	num_entries = rx_ring->refill_buf_ring.size /
502 		ath11k_hal_srng_get_entrysize(ar->ab, ringtype);
503 
504 	rx_ring->bufs_max = num_entries;
505 	ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries,
506 				   ar->ab->hw_params.hal_params->rx_buf_rbm);
507 	return 0;
508 }
509 
510 static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar)
511 {
512 	struct ath11k_pdev_dp *dp = &ar->dp;
513 	struct ath11k_base *ab = ar->ab;
514 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
515 	int i;
516 
517 	ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF);
518 
519 	if (ar->ab->hw_params.rxdma1_enable) {
520 		rx_ring = &dp->rxdma_mon_buf_ring;
521 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF);
522 	}
523 
524 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
525 		rx_ring = &dp->rx_mon_status_refill_ring[i];
526 		ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS);
527 	}
528 
529 	return 0;
530 }
531 
532 static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar)
533 {
534 	struct ath11k_pdev_dp *dp = &ar->dp;
535 	struct ath11k_base *ab = ar->ab;
536 	int i;
537 
538 	ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring);
539 
540 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
541 		if (ab->hw_params.rx_mac_buf_ring)
542 			ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]);
543 
544 		ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]);
545 		ath11k_dp_srng_cleanup(ab,
546 				       &dp->rx_mon_status_refill_ring[i].refill_buf_ring);
547 	}
548 
549 	ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring);
550 }
551 
552 void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab)
553 {
554 	struct ath11k_dp *dp = &ab->dp;
555 	int i;
556 
557 	for (i = 0; i < DP_REO_DST_RING_MAX; i++)
558 		ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]);
559 }
560 
561 int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab)
562 {
563 	struct ath11k_dp *dp = &ab->dp;
564 	int ret;
565 	int i;
566 
567 	for (i = 0; i < DP_REO_DST_RING_MAX; i++) {
568 		ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i],
569 					   HAL_REO_DST, i, 0,
570 					   DP_REO_DST_RING_SIZE);
571 		if (ret) {
572 			ath11k_warn(ab, "failed to setup reo_dst_ring\n");
573 			goto err_reo_cleanup;
574 		}
575 	}
576 
577 	return 0;
578 
579 err_reo_cleanup:
580 	ath11k_dp_pdev_reo_cleanup(ab);
581 
582 	return ret;
583 }
584 
585 static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar)
586 {
587 	struct ath11k_pdev_dp *dp = &ar->dp;
588 	struct ath11k_base *ab = ar->ab;
589 	struct dp_srng *srng = NULL;
590 	int i;
591 	int ret;
592 
593 	ret = ath11k_dp_srng_setup(ar->ab,
594 				   &dp->rx_refill_buf_ring.refill_buf_ring,
595 				   HAL_RXDMA_BUF, 0,
596 				   dp->mac_id, DP_RXDMA_BUF_RING_SIZE);
597 	if (ret) {
598 		ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n");
599 		return ret;
600 	}
601 
602 	if (ar->ab->hw_params.rx_mac_buf_ring) {
603 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
604 			ret = ath11k_dp_srng_setup(ar->ab,
605 						   &dp->rx_mac_buf_ring[i],
606 						   HAL_RXDMA_BUF, 1,
607 						   dp->mac_id + i, 1024);
608 			if (ret) {
609 				ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n",
610 					    i);
611 				return ret;
612 			}
613 		}
614 	}
615 
616 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
617 		ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i],
618 					   HAL_RXDMA_DST, 0, dp->mac_id + i,
619 					   DP_RXDMA_ERR_DST_RING_SIZE);
620 		if (ret) {
621 			ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i);
622 			return ret;
623 		}
624 	}
625 
626 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
627 		srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring;
628 		ret = ath11k_dp_srng_setup(ar->ab,
629 					   srng,
630 					   HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i,
631 					   DP_RXDMA_MON_STATUS_RING_SIZE);
632 		if (ret) {
633 			ath11k_warn(ar->ab,
634 				    "failed to setup rx_mon_status_refill_ring %d\n", i);
635 			return ret;
636 		}
637 	}
638 
639 	/* if rxdma1_enable is false, then it doesn't need
640 	 * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring
641 	 * and rxdma_mon_desc_ring.
642 	 * init reap timer for QCA6390.
643 	 */
644 	if (!ar->ab->hw_params.rxdma1_enable) {
645 		//init mon status buffer reap timer
646 		timer_setup(&ar->ab->mon_reap_timer,
647 			    ath11k_dp_service_mon_ring, 0);
648 		return 0;
649 	}
650 
651 	ret = ath11k_dp_srng_setup(ar->ab,
652 				   &dp->rxdma_mon_buf_ring.refill_buf_ring,
653 				   HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id,
654 				   DP_RXDMA_MONITOR_BUF_RING_SIZE);
655 	if (ret) {
656 		ath11k_warn(ar->ab,
657 			    "failed to setup HAL_RXDMA_MONITOR_BUF\n");
658 		return ret;
659 	}
660 
661 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring,
662 				   HAL_RXDMA_MONITOR_DST, 0, dp->mac_id,
663 				   DP_RXDMA_MONITOR_DST_RING_SIZE);
664 	if (ret) {
665 		ath11k_warn(ar->ab,
666 			    "failed to setup HAL_RXDMA_MONITOR_DST\n");
667 		return ret;
668 	}
669 
670 	ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring,
671 				   HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id,
672 				   DP_RXDMA_MONITOR_DESC_RING_SIZE);
673 	if (ret) {
674 		ath11k_warn(ar->ab,
675 			    "failed to setup HAL_RXDMA_MONITOR_DESC\n");
676 		return ret;
677 	}
678 
679 	return 0;
680 }
681 
682 void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab)
683 {
684 	struct ath11k_dp *dp = &ab->dp;
685 	struct dp_reo_cmd *cmd, *tmp;
686 	struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache;
687 
688 	spin_lock_bh(&dp->reo_cmd_lock);
689 	list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
690 		list_del(&cmd->list);
691 		dma_unmap_single(ab->dev, cmd->data.paddr,
692 				 cmd->data.size, DMA_BIDIRECTIONAL);
693 		kfree(cmd->data.vaddr);
694 		kfree(cmd);
695 	}
696 
697 	list_for_each_entry_safe(cmd_cache, tmp_cache,
698 				 &dp->reo_cmd_cache_flush_list, list) {
699 		list_del(&cmd_cache->list);
700 		dp->reo_cmd_cache_flush_count--;
701 		dma_unmap_single(ab->dev, cmd_cache->data.paddr,
702 				 cmd_cache->data.size, DMA_BIDIRECTIONAL);
703 		kfree(cmd_cache->data.vaddr);
704 		kfree(cmd_cache);
705 	}
706 	spin_unlock_bh(&dp->reo_cmd_lock);
707 }
708 
709 static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx,
710 				   enum hal_reo_cmd_status status)
711 {
712 	struct dp_rx_tid *rx_tid = ctx;
713 
714 	if (status != HAL_REO_CMD_SUCCESS)
715 		ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n",
716 			    rx_tid->tid, status);
717 
718 	dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size,
719 			 DMA_BIDIRECTIONAL);
720 	kfree(rx_tid->vaddr);
721 }
722 
723 static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab,
724 				      struct dp_rx_tid *rx_tid)
725 {
726 	struct ath11k_hal_reo_cmd cmd = {0};
727 	unsigned long tot_desc_sz, desc_sz;
728 	int ret;
729 
730 	tot_desc_sz = rx_tid->size;
731 	desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID);
732 
733 	while (tot_desc_sz > desc_sz) {
734 		tot_desc_sz -= desc_sz;
735 		cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz);
736 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
737 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
738 						HAL_REO_CMD_FLUSH_CACHE, &cmd,
739 						NULL);
740 		if (ret)
741 			ath11k_warn(ab,
742 				    "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n",
743 				    rx_tid->tid, ret);
744 	}
745 
746 	memset(&cmd, 0, sizeof(cmd));
747 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
748 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
749 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
750 	ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
751 					HAL_REO_CMD_FLUSH_CACHE,
752 					&cmd, ath11k_dp_reo_cmd_free);
753 	if (ret) {
754 		ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n",
755 			   rx_tid->tid, ret);
756 		dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
757 				 DMA_BIDIRECTIONAL);
758 		kfree(rx_tid->vaddr);
759 	}
760 }
761 
762 static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx,
763 				      enum hal_reo_cmd_status status)
764 {
765 	struct ath11k_base *ab = dp->ab;
766 	struct dp_rx_tid *rx_tid = ctx;
767 	struct dp_reo_cache_flush_elem *elem, *tmp;
768 
769 	if (status == HAL_REO_CMD_DRAIN) {
770 		goto free_desc;
771 	} else if (status != HAL_REO_CMD_SUCCESS) {
772 		/* Shouldn't happen! Cleanup in case of other failure? */
773 		ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n",
774 			    rx_tid->tid, status);
775 		return;
776 	}
777 
778 	elem = kzalloc(sizeof(*elem), GFP_ATOMIC);
779 	if (!elem)
780 		goto free_desc;
781 
782 	elem->ts = jiffies;
783 	memcpy(&elem->data, rx_tid, sizeof(*rx_tid));
784 
785 	spin_lock_bh(&dp->reo_cmd_lock);
786 	list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list);
787 	dp->reo_cmd_cache_flush_count++;
788 
789 	/* Flush and invalidate aged REO desc from HW cache */
790 	list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list,
791 				 list) {
792 		if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD ||
793 		    time_after(jiffies, elem->ts +
794 			       msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) {
795 			list_del(&elem->list);
796 			dp->reo_cmd_cache_flush_count--;
797 			spin_unlock_bh(&dp->reo_cmd_lock);
798 
799 			ath11k_dp_reo_cache_flush(ab, &elem->data);
800 			kfree(elem);
801 			spin_lock_bh(&dp->reo_cmd_lock);
802 		}
803 	}
804 	spin_unlock_bh(&dp->reo_cmd_lock);
805 
806 	return;
807 free_desc:
808 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
809 			 DMA_BIDIRECTIONAL);
810 	kfree(rx_tid->vaddr);
811 }
812 
813 void ath11k_peer_rx_tid_delete(struct ath11k *ar,
814 			       struct ath11k_peer *peer, u8 tid)
815 {
816 	struct ath11k_hal_reo_cmd cmd = {0};
817 	struct dp_rx_tid *rx_tid = &peer->rx_tid[tid];
818 	int ret;
819 
820 	if (!rx_tid->active)
821 		return;
822 
823 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
824 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
825 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
826 	cmd.upd0 |= HAL_REO_CMD_UPD0_VLD;
827 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
828 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
829 					ath11k_dp_rx_tid_del_func);
830 	if (ret) {
831 		ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n",
832 			   tid, ret);
833 		dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size,
834 				 DMA_BIDIRECTIONAL);
835 		kfree(rx_tid->vaddr);
836 	}
837 
838 	rx_tid->active = false;
839 }
840 
841 static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab,
842 					 u32 *link_desc,
843 					 enum hal_wbm_rel_bm_act action)
844 {
845 	struct ath11k_dp *dp = &ab->dp;
846 	struct hal_srng *srng;
847 	u32 *desc;
848 	int ret = 0;
849 
850 	srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id];
851 
852 	spin_lock_bh(&srng->lock);
853 
854 	ath11k_hal_srng_access_begin(ab, srng);
855 
856 	desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
857 	if (!desc) {
858 		ret = -ENOBUFS;
859 		goto exit;
860 	}
861 
862 	ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc,
863 					 action);
864 
865 exit:
866 	ath11k_hal_srng_access_end(ab, srng);
867 
868 	spin_unlock_bh(&srng->lock);
869 
870 	return ret;
871 }
872 
873 static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc)
874 {
875 	struct ath11k_base *ab = rx_tid->ab;
876 
877 	lockdep_assert_held(&ab->base_lock);
878 
879 	if (rx_tid->dst_ring_desc) {
880 		if (rel_link_desc)
881 			ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc,
882 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
883 		kfree(rx_tid->dst_ring_desc);
884 		rx_tid->dst_ring_desc = NULL;
885 	}
886 
887 	rx_tid->cur_sn = 0;
888 	rx_tid->last_frag_no = 0;
889 	rx_tid->rx_frag_bitmap = 0;
890 	__skb_queue_purge(&rx_tid->rx_frags);
891 }
892 
893 void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer)
894 {
895 	struct dp_rx_tid *rx_tid;
896 	int i;
897 
898 	lockdep_assert_held(&ar->ab->base_lock);
899 
900 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
901 		rx_tid = &peer->rx_tid[i];
902 
903 		spin_unlock_bh(&ar->ab->base_lock);
904 		del_timer_sync(&rx_tid->frag_timer);
905 		spin_lock_bh(&ar->ab->base_lock);
906 
907 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
908 	}
909 }
910 
911 void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer)
912 {
913 	struct dp_rx_tid *rx_tid;
914 	int i;
915 
916 	lockdep_assert_held(&ar->ab->base_lock);
917 
918 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
919 		rx_tid = &peer->rx_tid[i];
920 
921 		ath11k_peer_rx_tid_delete(ar, peer, i);
922 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
923 
924 		spin_unlock_bh(&ar->ab->base_lock);
925 		del_timer_sync(&rx_tid->frag_timer);
926 		spin_lock_bh(&ar->ab->base_lock);
927 	}
928 }
929 
930 static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar,
931 					 struct ath11k_peer *peer,
932 					 struct dp_rx_tid *rx_tid,
933 					 u32 ba_win_sz, u16 ssn,
934 					 bool update_ssn)
935 {
936 	struct ath11k_hal_reo_cmd cmd = {0};
937 	int ret;
938 
939 	cmd.addr_lo = lower_32_bits(rx_tid->paddr);
940 	cmd.addr_hi = upper_32_bits(rx_tid->paddr);
941 	cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS;
942 	cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE;
943 	cmd.ba_window_size = ba_win_sz;
944 
945 	if (update_ssn) {
946 		cmd.upd0 |= HAL_REO_CMD_UPD0_SSN;
947 		cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn);
948 	}
949 
950 	ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid,
951 					HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd,
952 					NULL);
953 	if (ret) {
954 		ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n",
955 			    rx_tid->tid, ret);
956 		return ret;
957 	}
958 
959 	rx_tid->ba_win_sz = ba_win_sz;
960 
961 	return 0;
962 }
963 
964 static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab,
965 				      const u8 *peer_mac, int vdev_id, u8 tid)
966 {
967 	struct ath11k_peer *peer;
968 	struct dp_rx_tid *rx_tid;
969 
970 	spin_lock_bh(&ab->base_lock);
971 
972 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
973 	if (!peer) {
974 		ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n");
975 		goto unlock_exit;
976 	}
977 
978 	rx_tid = &peer->rx_tid[tid];
979 	if (!rx_tid->active)
980 		goto unlock_exit;
981 
982 	dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size,
983 			 DMA_BIDIRECTIONAL);
984 	kfree(rx_tid->vaddr);
985 
986 	rx_tid->active = false;
987 
988 unlock_exit:
989 	spin_unlock_bh(&ab->base_lock);
990 }
991 
992 int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id,
993 			     u8 tid, u32 ba_win_sz, u16 ssn,
994 			     enum hal_pn_type pn_type)
995 {
996 	struct ath11k_base *ab = ar->ab;
997 	struct ath11k_peer *peer;
998 	struct dp_rx_tid *rx_tid;
999 	u32 hw_desc_sz;
1000 	u32 *addr_aligned;
1001 	void *vaddr;
1002 	dma_addr_t paddr;
1003 	int ret;
1004 
1005 	spin_lock_bh(&ab->base_lock);
1006 
1007 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
1008 	if (!peer) {
1009 		ath11k_warn(ab, "failed to find the peer to set up rx tid\n");
1010 		spin_unlock_bh(&ab->base_lock);
1011 		return -ENOENT;
1012 	}
1013 
1014 	rx_tid = &peer->rx_tid[tid];
1015 	/* Update the tid queue if it is already setup */
1016 	if (rx_tid->active) {
1017 		paddr = rx_tid->paddr;
1018 		ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid,
1019 						    ba_win_sz, ssn, true);
1020 		spin_unlock_bh(&ab->base_lock);
1021 		if (ret) {
1022 			ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid);
1023 			return ret;
1024 		}
1025 
1026 		ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1027 							     peer_mac, paddr,
1028 							     tid, 1, ba_win_sz);
1029 		if (ret)
1030 			ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n",
1031 				    tid, ret);
1032 		return ret;
1033 	}
1034 
1035 	rx_tid->tid = tid;
1036 
1037 	rx_tid->ba_win_sz = ba_win_sz;
1038 
1039 	/* TODO: Optimize the memory allocation for qos tid based on
1040 	 * the actual BA window size in REO tid update path.
1041 	 */
1042 	if (tid == HAL_DESC_REO_NON_QOS_TID)
1043 		hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid);
1044 	else
1045 		hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid);
1046 
1047 	vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC);
1048 	if (!vaddr) {
1049 		spin_unlock_bh(&ab->base_lock);
1050 		return -ENOMEM;
1051 	}
1052 
1053 	addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN);
1054 
1055 	ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz,
1056 				   ssn, pn_type);
1057 
1058 	paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz,
1059 			       DMA_BIDIRECTIONAL);
1060 
1061 	ret = dma_mapping_error(ab->dev, paddr);
1062 	if (ret) {
1063 		spin_unlock_bh(&ab->base_lock);
1064 		goto err_mem_free;
1065 	}
1066 
1067 	rx_tid->vaddr = vaddr;
1068 	rx_tid->paddr = paddr;
1069 	rx_tid->size = hw_desc_sz;
1070 	rx_tid->active = true;
1071 
1072 	spin_unlock_bh(&ab->base_lock);
1073 
1074 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac,
1075 						     paddr, tid, 1, ba_win_sz);
1076 	if (ret) {
1077 		ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n",
1078 			    tid, ret);
1079 		ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid);
1080 	}
1081 
1082 	return ret;
1083 
1084 err_mem_free:
1085 	kfree(vaddr);
1086 
1087 	return ret;
1088 }
1089 
1090 int ath11k_dp_rx_ampdu_start(struct ath11k *ar,
1091 			     struct ieee80211_ampdu_params *params)
1092 {
1093 	struct ath11k_base *ab = ar->ab;
1094 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1095 	int vdev_id = arsta->arvif->vdev_id;
1096 	int ret;
1097 
1098 	ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id,
1099 				       params->tid, params->buf_size,
1100 				       params->ssn, arsta->pn_type);
1101 	if (ret)
1102 		ath11k_warn(ab, "failed to setup rx tid %d\n", ret);
1103 
1104 	return ret;
1105 }
1106 
1107 int ath11k_dp_rx_ampdu_stop(struct ath11k *ar,
1108 			    struct ieee80211_ampdu_params *params)
1109 {
1110 	struct ath11k_base *ab = ar->ab;
1111 	struct ath11k_peer *peer;
1112 	struct ath11k_sta *arsta = (void *)params->sta->drv_priv;
1113 	int vdev_id = arsta->arvif->vdev_id;
1114 	dma_addr_t paddr;
1115 	bool active;
1116 	int ret;
1117 
1118 	spin_lock_bh(&ab->base_lock);
1119 
1120 	peer = ath11k_peer_find(ab, vdev_id, params->sta->addr);
1121 	if (!peer) {
1122 		ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n");
1123 		spin_unlock_bh(&ab->base_lock);
1124 		return -ENOENT;
1125 	}
1126 
1127 	paddr = peer->rx_tid[params->tid].paddr;
1128 	active = peer->rx_tid[params->tid].active;
1129 
1130 	if (!active) {
1131 		spin_unlock_bh(&ab->base_lock);
1132 		return 0;
1133 	}
1134 
1135 	ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false);
1136 	spin_unlock_bh(&ab->base_lock);
1137 	if (ret) {
1138 		ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n",
1139 			    params->tid, ret);
1140 		return ret;
1141 	}
1142 
1143 	ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id,
1144 						     params->sta->addr, paddr,
1145 						     params->tid, 1, 1);
1146 	if (ret)
1147 		ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n",
1148 			    ret);
1149 
1150 	return ret;
1151 }
1152 
1153 int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif,
1154 				       const u8 *peer_addr,
1155 				       enum set_key_cmd key_cmd,
1156 				       struct ieee80211_key_conf *key)
1157 {
1158 	struct ath11k *ar = arvif->ar;
1159 	struct ath11k_base *ab = ar->ab;
1160 	struct ath11k_hal_reo_cmd cmd = {0};
1161 	struct ath11k_peer *peer;
1162 	struct dp_rx_tid *rx_tid;
1163 	u8 tid;
1164 	int ret = 0;
1165 
1166 	/* NOTE: Enable PN/TSC replay check offload only for unicast frames.
1167 	 * We use mac80211 PN/TSC replay check functionality for bcast/mcast
1168 	 * for now.
1169 	 */
1170 	if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1171 		return 0;
1172 
1173 	cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS;
1174 	cmd.upd0 |= HAL_REO_CMD_UPD0_PN |
1175 		    HAL_REO_CMD_UPD0_PN_SIZE |
1176 		    HAL_REO_CMD_UPD0_PN_VALID |
1177 		    HAL_REO_CMD_UPD0_PN_CHECK |
1178 		    HAL_REO_CMD_UPD0_SVLD;
1179 
1180 	switch (key->cipher) {
1181 	case WLAN_CIPHER_SUITE_TKIP:
1182 	case WLAN_CIPHER_SUITE_CCMP:
1183 	case WLAN_CIPHER_SUITE_CCMP_256:
1184 	case WLAN_CIPHER_SUITE_GCMP:
1185 	case WLAN_CIPHER_SUITE_GCMP_256:
1186 		if (key_cmd == SET_KEY) {
1187 			cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK;
1188 			cmd.pn_size = 48;
1189 		}
1190 		break;
1191 	default:
1192 		break;
1193 	}
1194 
1195 	spin_lock_bh(&ab->base_lock);
1196 
1197 	peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr);
1198 	if (!peer) {
1199 		ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n");
1200 		spin_unlock_bh(&ab->base_lock);
1201 		return -ENOENT;
1202 	}
1203 
1204 	for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) {
1205 		rx_tid = &peer->rx_tid[tid];
1206 		if (!rx_tid->active)
1207 			continue;
1208 		cmd.addr_lo = lower_32_bits(rx_tid->paddr);
1209 		cmd.addr_hi = upper_32_bits(rx_tid->paddr);
1210 		ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid,
1211 						HAL_REO_CMD_UPDATE_RX_QUEUE,
1212 						&cmd, NULL);
1213 		if (ret) {
1214 			ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n",
1215 				    tid, ret);
1216 			break;
1217 		}
1218 	}
1219 
1220 	spin_unlock_bh(&ab->base_lock);
1221 
1222 	return ret;
1223 }
1224 
1225 static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats,
1226 					     u16 peer_id)
1227 {
1228 	int i;
1229 
1230 	for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) {
1231 		if (ppdu_stats->user_stats[i].is_valid_peer_id) {
1232 			if (peer_id == ppdu_stats->user_stats[i].peer_id)
1233 				return i;
1234 		} else {
1235 			return i;
1236 		}
1237 	}
1238 
1239 	return -EINVAL;
1240 }
1241 
1242 static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab,
1243 					   u16 tag, u16 len, const void *ptr,
1244 					   void *data)
1245 {
1246 	struct htt_ppdu_stats_info *ppdu_info;
1247 	struct htt_ppdu_user_stats *user_stats;
1248 	int cur_user;
1249 	u16 peer_id;
1250 
1251 	ppdu_info = (struct htt_ppdu_stats_info *)data;
1252 
1253 	switch (tag) {
1254 	case HTT_PPDU_STATS_TAG_COMMON:
1255 		if (len < sizeof(struct htt_ppdu_stats_common)) {
1256 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1257 				    len, tag);
1258 			return -EINVAL;
1259 		}
1260 		memcpy((void *)&ppdu_info->ppdu_stats.common, ptr,
1261 		       sizeof(struct htt_ppdu_stats_common));
1262 		break;
1263 	case HTT_PPDU_STATS_TAG_USR_RATE:
1264 		if (len < sizeof(struct htt_ppdu_stats_user_rate)) {
1265 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1266 				    len, tag);
1267 			return -EINVAL;
1268 		}
1269 
1270 		peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id;
1271 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1272 						      peer_id);
1273 		if (cur_user < 0)
1274 			return -EINVAL;
1275 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1276 		user_stats->peer_id = peer_id;
1277 		user_stats->is_valid_peer_id = true;
1278 		memcpy((void *)&user_stats->rate, ptr,
1279 		       sizeof(struct htt_ppdu_stats_user_rate));
1280 		user_stats->tlv_flags |= BIT(tag);
1281 		break;
1282 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON:
1283 		if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) {
1284 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1285 				    len, tag);
1286 			return -EINVAL;
1287 		}
1288 
1289 		peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id;
1290 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1291 						      peer_id);
1292 		if (cur_user < 0)
1293 			return -EINVAL;
1294 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1295 		user_stats->peer_id = peer_id;
1296 		user_stats->is_valid_peer_id = true;
1297 		memcpy((void *)&user_stats->cmpltn_cmn, ptr,
1298 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn));
1299 		user_stats->tlv_flags |= BIT(tag);
1300 		break;
1301 	case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS:
1302 		if (len <
1303 		    sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) {
1304 			ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n",
1305 				    len, tag);
1306 			return -EINVAL;
1307 		}
1308 
1309 		peer_id =
1310 		((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id;
1311 		cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats,
1312 						      peer_id);
1313 		if (cur_user < 0)
1314 			return -EINVAL;
1315 		user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user];
1316 		user_stats->peer_id = peer_id;
1317 		user_stats->is_valid_peer_id = true;
1318 		memcpy((void *)&user_stats->ack_ba, ptr,
1319 		       sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status));
1320 		user_stats->tlv_flags |= BIT(tag);
1321 		break;
1322 	}
1323 	return 0;
1324 }
1325 
1326 int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len,
1327 			   int (*iter)(struct ath11k_base *ar, u16 tag, u16 len,
1328 				       const void *ptr, void *data),
1329 			   void *data)
1330 {
1331 	const struct htt_tlv *tlv;
1332 	const void *begin = ptr;
1333 	u16 tlv_tag, tlv_len;
1334 	int ret = -EINVAL;
1335 
1336 	while (len > 0) {
1337 		if (len < sizeof(*tlv)) {
1338 			ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n",
1339 				   ptr - begin, len, sizeof(*tlv));
1340 			return -EINVAL;
1341 		}
1342 		tlv = (struct htt_tlv *)ptr;
1343 		tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header);
1344 		tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header);
1345 		ptr += sizeof(*tlv);
1346 		len -= sizeof(*tlv);
1347 
1348 		if (tlv_len > len) {
1349 			ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n",
1350 				   tlv_tag, ptr - begin, len, tlv_len);
1351 			return -EINVAL;
1352 		}
1353 		ret = iter(ab, tlv_tag, tlv_len, ptr, data);
1354 		if (ret == -ENOMEM)
1355 			return ret;
1356 
1357 		ptr += tlv_len;
1358 		len -= tlv_len;
1359 	}
1360 	return 0;
1361 }
1362 
1363 static void
1364 ath11k_update_per_peer_tx_stats(struct ath11k *ar,
1365 				struct htt_ppdu_stats *ppdu_stats, u8 user)
1366 {
1367 	struct ath11k_base *ab = ar->ab;
1368 	struct ath11k_peer *peer;
1369 	struct ieee80211_sta *sta;
1370 	struct ath11k_sta *arsta;
1371 	struct htt_ppdu_stats_user_rate *user_rate;
1372 	struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats;
1373 	struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user];
1374 	struct htt_ppdu_stats_common *common = &ppdu_stats->common;
1375 	int ret;
1376 	u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0;
1377 	u32 succ_bytes = 0;
1378 	u16 rate = 0, succ_pkts = 0;
1379 	u32 tx_duration = 0;
1380 	u8 tid = HTT_PPDU_STATS_NON_QOS_TID;
1381 	bool is_ampdu = false;
1382 
1383 	if (!usr_stats)
1384 		return;
1385 
1386 	if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE)))
1387 		return;
1388 
1389 	if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON))
1390 		is_ampdu =
1391 			HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags);
1392 
1393 	if (usr_stats->tlv_flags &
1394 	    BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) {
1395 		succ_bytes = usr_stats->ack_ba.success_bytes;
1396 		succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M,
1397 				      usr_stats->ack_ba.info);
1398 		tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM,
1399 				usr_stats->ack_ba.info);
1400 	}
1401 
1402 	if (common->fes_duration_us)
1403 		tx_duration = common->fes_duration_us;
1404 
1405 	user_rate = &usr_stats->rate;
1406 	flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags);
1407 	bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2;
1408 	nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1;
1409 	mcs = HTT_USR_RATE_MCS(user_rate->rate_flags);
1410 	sgi = HTT_USR_RATE_GI(user_rate->rate_flags);
1411 	dcm = HTT_USR_RATE_DCM(user_rate->rate_flags);
1412 
1413 	/* Note: If host configured fixed rates and in some other special
1414 	 * cases, the broadcast/management frames are sent in different rates.
1415 	 * Firmware rate's control to be skipped for this?
1416 	 */
1417 
1418 	if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) {
1419 		ath11k_warn(ab, "Invalid HE mcs %d peer stats",  mcs);
1420 		return;
1421 	}
1422 
1423 	if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) {
1424 		ath11k_warn(ab, "Invalid VHT mcs %d peer stats",  mcs);
1425 		return;
1426 	}
1427 
1428 	if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) {
1429 		ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats",
1430 			    mcs, nss);
1431 		return;
1432 	}
1433 
1434 	if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) {
1435 		ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
1436 							    flags,
1437 							    &rate_idx,
1438 							    &rate);
1439 		if (ret < 0)
1440 			return;
1441 	}
1442 
1443 	rcu_read_lock();
1444 	spin_lock_bh(&ab->base_lock);
1445 	peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id);
1446 
1447 	if (!peer || !peer->sta) {
1448 		spin_unlock_bh(&ab->base_lock);
1449 		rcu_read_unlock();
1450 		return;
1451 	}
1452 
1453 	sta = peer->sta;
1454 	arsta = (struct ath11k_sta *)sta->drv_priv;
1455 
1456 	memset(&arsta->txrate, 0, sizeof(arsta->txrate));
1457 
1458 	switch (flags) {
1459 	case WMI_RATE_PREAMBLE_OFDM:
1460 		arsta->txrate.legacy = rate;
1461 		break;
1462 	case WMI_RATE_PREAMBLE_CCK:
1463 		arsta->txrate.legacy = rate;
1464 		break;
1465 	case WMI_RATE_PREAMBLE_HT:
1466 		arsta->txrate.mcs = mcs + 8 * (nss - 1);
1467 		arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
1468 		if (sgi)
1469 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1470 		break;
1471 	case WMI_RATE_PREAMBLE_VHT:
1472 		arsta->txrate.mcs = mcs;
1473 		arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
1474 		if (sgi)
1475 			arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
1476 		break;
1477 	case WMI_RATE_PREAMBLE_HE:
1478 		arsta->txrate.mcs = mcs;
1479 		arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
1480 		arsta->txrate.he_dcm = dcm;
1481 		arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
1482 		arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc
1483 						((user_rate->ru_end -
1484 						 user_rate->ru_start) + 1);
1485 		break;
1486 	}
1487 
1488 	arsta->txrate.nss = nss;
1489 
1490 	arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
1491 	arsta->tx_duration += tx_duration;
1492 	memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info));
1493 
1494 	/* PPDU stats reported for mgmt packet doesn't have valid tx bytes.
1495 	 * So skip peer stats update for mgmt packets.
1496 	 */
1497 	if (tid < HTT_PPDU_STATS_NON_QOS_TID) {
1498 		memset(peer_stats, 0, sizeof(*peer_stats));
1499 		peer_stats->succ_pkts = succ_pkts;
1500 		peer_stats->succ_bytes = succ_bytes;
1501 		peer_stats->is_ampdu = is_ampdu;
1502 		peer_stats->duration = tx_duration;
1503 		peer_stats->ba_fails =
1504 			HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) +
1505 			HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags);
1506 
1507 		if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
1508 			ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
1509 	}
1510 
1511 	spin_unlock_bh(&ab->base_lock);
1512 	rcu_read_unlock();
1513 }
1514 
1515 static void ath11k_htt_update_ppdu_stats(struct ath11k *ar,
1516 					 struct htt_ppdu_stats *ppdu_stats)
1517 {
1518 	u8 user;
1519 
1520 	for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++)
1521 		ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user);
1522 }
1523 
1524 static
1525 struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar,
1526 							u32 ppdu_id)
1527 {
1528 	struct htt_ppdu_stats_info *ppdu_info;
1529 
1530 	spin_lock_bh(&ar->data_lock);
1531 	if (!list_empty(&ar->ppdu_stats_info)) {
1532 		list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) {
1533 			if (ppdu_info->ppdu_id == ppdu_id) {
1534 				spin_unlock_bh(&ar->data_lock);
1535 				return ppdu_info;
1536 			}
1537 		}
1538 
1539 		if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) {
1540 			ppdu_info = list_first_entry(&ar->ppdu_stats_info,
1541 						     typeof(*ppdu_info), list);
1542 			list_del(&ppdu_info->list);
1543 			ar->ppdu_stat_list_depth--;
1544 			ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats);
1545 			kfree(ppdu_info);
1546 		}
1547 	}
1548 	spin_unlock_bh(&ar->data_lock);
1549 
1550 	ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC);
1551 	if (!ppdu_info)
1552 		return NULL;
1553 
1554 	spin_lock_bh(&ar->data_lock);
1555 	list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info);
1556 	ar->ppdu_stat_list_depth++;
1557 	spin_unlock_bh(&ar->data_lock);
1558 
1559 	return ppdu_info;
1560 }
1561 
1562 static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab,
1563 				      struct sk_buff *skb)
1564 {
1565 	struct ath11k_htt_ppdu_stats_msg *msg;
1566 	struct htt_ppdu_stats_info *ppdu_info;
1567 	struct ath11k *ar;
1568 	int ret;
1569 	u8 pdev_id;
1570 	u32 ppdu_id, len;
1571 
1572 	msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data;
1573 	len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info);
1574 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info);
1575 	ppdu_id = msg->ppdu_id;
1576 
1577 	rcu_read_lock();
1578 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1579 	if (!ar) {
1580 		ret = -EINVAL;
1581 		goto exit;
1582 	}
1583 
1584 	if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar))
1585 		trace_ath11k_htt_ppdu_stats(ar, skb->data, len);
1586 
1587 	ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id);
1588 	if (!ppdu_info) {
1589 		ret = -EINVAL;
1590 		goto exit;
1591 	}
1592 
1593 	ppdu_info->ppdu_id = ppdu_id;
1594 	ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len,
1595 				     ath11k_htt_tlv_ppdu_stats_parse,
1596 				     (void *)ppdu_info);
1597 	if (ret) {
1598 		ath11k_warn(ab, "Failed to parse tlv %d\n", ret);
1599 		goto exit;
1600 	}
1601 
1602 exit:
1603 	rcu_read_unlock();
1604 
1605 	return ret;
1606 }
1607 
1608 static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb)
1609 {
1610 	struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data;
1611 	struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data;
1612 	struct ath11k *ar;
1613 	u8 pdev_id;
1614 
1615 	pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr);
1616 	ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id);
1617 	if (!ar) {
1618 		ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id);
1619 		return;
1620 	}
1621 
1622 	trace_ath11k_htt_pktlog(ar, data->payload, hdr->size,
1623 				ar->ab->pktlog_defs_checksum);
1624 }
1625 
1626 static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab,
1627 						  struct sk_buff *skb)
1628 {
1629 	u32 *data = (u32 *)skb->data;
1630 	u8 pdev_id, ring_type, ring_id, pdev_idx;
1631 	u16 hp, tp;
1632 	u32 backpressure_time;
1633 	struct ath11k_bp_stats *bp_stats;
1634 
1635 	pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data);
1636 	ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data);
1637 	ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data);
1638 	++data;
1639 
1640 	hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data);
1641 	tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data);
1642 	++data;
1643 
1644 	backpressure_time = *data;
1645 
1646 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n",
1647 		   pdev_id, ring_type, ring_id, hp, tp, backpressure_time);
1648 
1649 	if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) {
1650 		if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX)
1651 			return;
1652 
1653 		bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id];
1654 	} else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) {
1655 		pdev_idx = DP_HW2SW_MACID(pdev_id);
1656 
1657 		if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS)
1658 			return;
1659 
1660 		bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx];
1661 	} else {
1662 		ath11k_warn(ab, "unknown ring type received in htt bp event %d\n",
1663 			    ring_type);
1664 		return;
1665 	}
1666 
1667 	spin_lock_bh(&ab->base_lock);
1668 	bp_stats->hp = hp;
1669 	bp_stats->tp = tp;
1670 	bp_stats->count++;
1671 	bp_stats->jiffies = jiffies;
1672 	spin_unlock_bh(&ab->base_lock);
1673 }
1674 
1675 void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab,
1676 				       struct sk_buff *skb)
1677 {
1678 	struct ath11k_dp *dp = &ab->dp;
1679 	struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data;
1680 	enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp);
1681 	u16 peer_id;
1682 	u8 vdev_id;
1683 	u8 mac_addr[ETH_ALEN];
1684 	u16 peer_mac_h16;
1685 	u16 ast_hash;
1686 	u16 hw_peer_id;
1687 
1688 	ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type);
1689 
1690 	switch (type) {
1691 	case HTT_T2H_MSG_TYPE_VERSION_CONF:
1692 		dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR,
1693 						  resp->version_msg.version);
1694 		dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR,
1695 						  resp->version_msg.version);
1696 		complete(&dp->htt_tgt_version_received);
1697 		break;
1698 	case HTT_T2H_MSG_TYPE_PEER_MAP:
1699 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1700 				    resp->peer_map_ev.info);
1701 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1702 				    resp->peer_map_ev.info);
1703 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1704 					 resp->peer_map_ev.info1);
1705 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1706 				       peer_mac_h16, mac_addr);
1707 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0);
1708 		break;
1709 	case HTT_T2H_MSG_TYPE_PEER_MAP2:
1710 		vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID,
1711 				    resp->peer_map_ev.info);
1712 		peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID,
1713 				    resp->peer_map_ev.info);
1714 		peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16,
1715 					 resp->peer_map_ev.info1);
1716 		ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32,
1717 				       peer_mac_h16, mac_addr);
1718 		ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL,
1719 				     resp->peer_map_ev.info2);
1720 		hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID,
1721 				       resp->peer_map_ev.info1);
1722 		ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash,
1723 				      hw_peer_id);
1724 		break;
1725 	case HTT_T2H_MSG_TYPE_PEER_UNMAP:
1726 	case HTT_T2H_MSG_TYPE_PEER_UNMAP2:
1727 		peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID,
1728 				    resp->peer_unmap_ev.info);
1729 		ath11k_peer_unmap_event(ab, peer_id);
1730 		break;
1731 	case HTT_T2H_MSG_TYPE_PPDU_STATS_IND:
1732 		ath11k_htt_pull_ppdu_stats(ab, skb);
1733 		break;
1734 	case HTT_T2H_MSG_TYPE_EXT_STATS_CONF:
1735 		ath11k_debugfs_htt_ext_stats_handler(ab, skb);
1736 		break;
1737 	case HTT_T2H_MSG_TYPE_PKTLOG:
1738 		ath11k_htt_pktlog(ab, skb);
1739 		break;
1740 	case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND:
1741 		ath11k_htt_backpressure_event_handler(ab, skb);
1742 		break;
1743 	default:
1744 		ath11k_warn(ab, "htt event %d not handled\n", type);
1745 		break;
1746 	}
1747 
1748 	dev_kfree_skb_any(skb);
1749 }
1750 
1751 static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar,
1752 				      struct sk_buff_head *msdu_list,
1753 				      struct sk_buff *first, struct sk_buff *last,
1754 				      u8 l3pad_bytes, int msdu_len)
1755 {
1756 	struct ath11k_base *ab = ar->ab;
1757 	struct sk_buff *skb;
1758 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1759 	int buf_first_hdr_len, buf_first_len;
1760 	struct hal_rx_desc *ldesc;
1761 	int space_extra, rem_len, buf_len;
1762 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
1763 
1764 	/* As the msdu is spread across multiple rx buffers,
1765 	 * find the offset to the start of msdu for computing
1766 	 * the length of the msdu in the first buffer.
1767 	 */
1768 	buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes;
1769 	buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len;
1770 
1771 	if (WARN_ON_ONCE(msdu_len <= buf_first_len)) {
1772 		skb_put(first, buf_first_hdr_len + msdu_len);
1773 		skb_pull(first, buf_first_hdr_len);
1774 		return 0;
1775 	}
1776 
1777 	ldesc = (struct hal_rx_desc *)last->data;
1778 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc);
1779 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc);
1780 
1781 	/* MSDU spans over multiple buffers because the length of the MSDU
1782 	 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data
1783 	 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE.
1784 	 */
1785 	skb_put(first, DP_RX_BUFFER_SIZE);
1786 	skb_pull(first, buf_first_hdr_len);
1787 
1788 	/* When an MSDU spread over multiple buffers attention, MSDU_END and
1789 	 * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs.
1790 	 */
1791 	ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc);
1792 
1793 	space_extra = msdu_len - (buf_first_len + skb_tailroom(first));
1794 	if (space_extra > 0 &&
1795 	    (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) {
1796 		/* Free up all buffers of the MSDU */
1797 		while ((skb = __skb_dequeue(msdu_list)) != NULL) {
1798 			rxcb = ATH11K_SKB_RXCB(skb);
1799 			if (!rxcb->is_continuation) {
1800 				dev_kfree_skb_any(skb);
1801 				break;
1802 			}
1803 			dev_kfree_skb_any(skb);
1804 		}
1805 		return -ENOMEM;
1806 	}
1807 
1808 	rem_len = msdu_len - buf_first_len;
1809 	while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) {
1810 		rxcb = ATH11K_SKB_RXCB(skb);
1811 		if (rxcb->is_continuation)
1812 			buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz;
1813 		else
1814 			buf_len = rem_len;
1815 
1816 		if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) {
1817 			WARN_ON_ONCE(1);
1818 			dev_kfree_skb_any(skb);
1819 			return -EINVAL;
1820 		}
1821 
1822 		skb_put(skb, buf_len + hal_rx_desc_sz);
1823 		skb_pull(skb, hal_rx_desc_sz);
1824 		skb_copy_from_linear_data(skb, skb_put(first, buf_len),
1825 					  buf_len);
1826 		dev_kfree_skb_any(skb);
1827 
1828 		rem_len -= buf_len;
1829 		if (!rxcb->is_continuation)
1830 			break;
1831 	}
1832 
1833 	return 0;
1834 }
1835 
1836 static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list,
1837 						      struct sk_buff *first)
1838 {
1839 	struct sk_buff *skb;
1840 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first);
1841 
1842 	if (!rxcb->is_continuation)
1843 		return first;
1844 
1845 	skb_queue_walk(msdu_list, skb) {
1846 		rxcb = ATH11K_SKB_RXCB(skb);
1847 		if (!rxcb->is_continuation)
1848 			return skb;
1849 	}
1850 
1851 	return NULL;
1852 }
1853 
1854 static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu)
1855 {
1856 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1857 	struct rx_attention *rx_attention;
1858 	bool ip_csum_fail, l4_csum_fail;
1859 
1860 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc);
1861 	ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention);
1862 	l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention);
1863 
1864 	msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ?
1865 			  CHECKSUM_NONE : CHECKSUM_UNNECESSARY;
1866 }
1867 
1868 static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar,
1869 				       enum hal_encrypt_type enctype)
1870 {
1871 	switch (enctype) {
1872 	case HAL_ENCRYPT_TYPE_OPEN:
1873 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1874 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1875 		return 0;
1876 	case HAL_ENCRYPT_TYPE_CCMP_128:
1877 		return IEEE80211_CCMP_MIC_LEN;
1878 	case HAL_ENCRYPT_TYPE_CCMP_256:
1879 		return IEEE80211_CCMP_256_MIC_LEN;
1880 	case HAL_ENCRYPT_TYPE_GCMP_128:
1881 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1882 		return IEEE80211_GCMP_MIC_LEN;
1883 	case HAL_ENCRYPT_TYPE_WEP_40:
1884 	case HAL_ENCRYPT_TYPE_WEP_104:
1885 	case HAL_ENCRYPT_TYPE_WEP_128:
1886 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1887 	case HAL_ENCRYPT_TYPE_WAPI:
1888 		break;
1889 	}
1890 
1891 	ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype);
1892 	return 0;
1893 }
1894 
1895 static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar,
1896 					 enum hal_encrypt_type enctype)
1897 {
1898 	switch (enctype) {
1899 	case HAL_ENCRYPT_TYPE_OPEN:
1900 		return 0;
1901 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1902 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1903 		return IEEE80211_TKIP_IV_LEN;
1904 	case HAL_ENCRYPT_TYPE_CCMP_128:
1905 		return IEEE80211_CCMP_HDR_LEN;
1906 	case HAL_ENCRYPT_TYPE_CCMP_256:
1907 		return IEEE80211_CCMP_256_HDR_LEN;
1908 	case HAL_ENCRYPT_TYPE_GCMP_128:
1909 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1910 		return IEEE80211_GCMP_HDR_LEN;
1911 	case HAL_ENCRYPT_TYPE_WEP_40:
1912 	case HAL_ENCRYPT_TYPE_WEP_104:
1913 	case HAL_ENCRYPT_TYPE_WEP_128:
1914 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1915 	case HAL_ENCRYPT_TYPE_WAPI:
1916 		break;
1917 	}
1918 
1919 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1920 	return 0;
1921 }
1922 
1923 static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar,
1924 				       enum hal_encrypt_type enctype)
1925 {
1926 	switch (enctype) {
1927 	case HAL_ENCRYPT_TYPE_OPEN:
1928 	case HAL_ENCRYPT_TYPE_CCMP_128:
1929 	case HAL_ENCRYPT_TYPE_CCMP_256:
1930 	case HAL_ENCRYPT_TYPE_GCMP_128:
1931 	case HAL_ENCRYPT_TYPE_AES_GCMP_256:
1932 		return 0;
1933 	case HAL_ENCRYPT_TYPE_TKIP_NO_MIC:
1934 	case HAL_ENCRYPT_TYPE_TKIP_MIC:
1935 		return IEEE80211_TKIP_ICV_LEN;
1936 	case HAL_ENCRYPT_TYPE_WEP_40:
1937 	case HAL_ENCRYPT_TYPE_WEP_104:
1938 	case HAL_ENCRYPT_TYPE_WEP_128:
1939 	case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4:
1940 	case HAL_ENCRYPT_TYPE_WAPI:
1941 		break;
1942 	}
1943 
1944 	ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype);
1945 	return 0;
1946 }
1947 
1948 static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar,
1949 					 struct sk_buff *msdu,
1950 					 u8 *first_hdr,
1951 					 enum hal_encrypt_type enctype,
1952 					 struct ieee80211_rx_status *status)
1953 {
1954 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
1955 	u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN];
1956 	struct ieee80211_hdr *hdr;
1957 	size_t hdr_len;
1958 	u8 da[ETH_ALEN];
1959 	u8 sa[ETH_ALEN];
1960 	u16 qos_ctl = 0;
1961 	u8 *qos;
1962 
1963 	/* copy SA & DA and pull decapped header */
1964 	hdr = (struct ieee80211_hdr *)msdu->data;
1965 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
1966 	ether_addr_copy(da, ieee80211_get_DA(hdr));
1967 	ether_addr_copy(sa, ieee80211_get_SA(hdr));
1968 	skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control));
1969 
1970 	if (rxcb->is_first_msdu) {
1971 		/* original 802.11 header is valid for the first msdu
1972 		 * hence we can reuse the same header
1973 		 */
1974 		hdr = (struct ieee80211_hdr *)first_hdr;
1975 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
1976 
1977 		/* Each A-MSDU subframe will be reported as a separate MSDU,
1978 		 * so strip the A-MSDU bit from QoS Ctl.
1979 		 */
1980 		if (ieee80211_is_data_qos(hdr->frame_control)) {
1981 			qos = ieee80211_get_qos_ctl(hdr);
1982 			qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
1983 		}
1984 	} else {
1985 		/*  Rebuild qos header if this is a middle/last msdu */
1986 		hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
1987 
1988 		/* Reset the order bit as the HT_Control header is stripped */
1989 		hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER));
1990 
1991 		qos_ctl = rxcb->tid;
1992 
1993 		if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc))
1994 			qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT;
1995 
1996 		/* TODO Add other QoS ctl fields when required */
1997 
1998 		/* copy decap header before overwriting for reuse below */
1999 		memcpy(decap_hdr, (uint8_t *)hdr, hdr_len);
2000 	}
2001 
2002 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2003 		memcpy(skb_push(msdu,
2004 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2005 		       (void *)hdr + hdr_len,
2006 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2007 	}
2008 
2009 	if (!rxcb->is_first_msdu) {
2010 		memcpy(skb_push(msdu,
2011 				IEEE80211_QOS_CTL_LEN), &qos_ctl,
2012 				IEEE80211_QOS_CTL_LEN);
2013 		memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len);
2014 		return;
2015 	}
2016 
2017 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2018 
2019 	/* original 802.11 header has a different DA and in
2020 	 * case of 4addr it may also have different SA
2021 	 */
2022 	hdr = (struct ieee80211_hdr *)msdu->data;
2023 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2024 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2025 }
2026 
2027 static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu,
2028 				       enum hal_encrypt_type enctype,
2029 				       struct ieee80211_rx_status *status,
2030 				       bool decrypted)
2031 {
2032 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2033 	struct ieee80211_hdr *hdr;
2034 	size_t hdr_len;
2035 	size_t crypto_len;
2036 
2037 	if (!rxcb->is_first_msdu ||
2038 	    !(rxcb->is_first_msdu && rxcb->is_last_msdu)) {
2039 		WARN_ON_ONCE(1);
2040 		return;
2041 	}
2042 
2043 	skb_trim(msdu, msdu->len - FCS_LEN);
2044 
2045 	if (!decrypted)
2046 		return;
2047 
2048 	hdr = (void *)msdu->data;
2049 
2050 	/* Tail */
2051 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2052 		skb_trim(msdu, msdu->len -
2053 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2054 
2055 		skb_trim(msdu, msdu->len -
2056 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2057 	} else {
2058 		/* MIC */
2059 		if (status->flag & RX_FLAG_MIC_STRIPPED)
2060 			skb_trim(msdu, msdu->len -
2061 				 ath11k_dp_rx_crypto_mic_len(ar, enctype));
2062 
2063 		/* ICV */
2064 		if (status->flag & RX_FLAG_ICV_STRIPPED)
2065 			skb_trim(msdu, msdu->len -
2066 				 ath11k_dp_rx_crypto_icv_len(ar, enctype));
2067 	}
2068 
2069 	/* MMIC */
2070 	if ((status->flag & RX_FLAG_MMIC_STRIPPED) &&
2071 	    !ieee80211_has_morefrags(hdr->frame_control) &&
2072 	    enctype == HAL_ENCRYPT_TYPE_TKIP_MIC)
2073 		skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN);
2074 
2075 	/* Head */
2076 	if (status->flag & RX_FLAG_IV_STRIPPED) {
2077 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2078 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2079 
2080 		memmove((void *)msdu->data + crypto_len,
2081 			(void *)msdu->data, hdr_len);
2082 		skb_pull(msdu, crypto_len);
2083 	}
2084 }
2085 
2086 static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar,
2087 					 struct sk_buff *msdu,
2088 					 enum hal_encrypt_type enctype)
2089 {
2090 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2091 	struct ieee80211_hdr *hdr;
2092 	size_t hdr_len, crypto_len;
2093 	void *rfc1042;
2094 	bool is_amsdu;
2095 
2096 	is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu);
2097 	hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc);
2098 	rfc1042 = hdr;
2099 
2100 	if (rxcb->is_first_msdu) {
2101 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
2102 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
2103 
2104 		rfc1042 += hdr_len + crypto_len;
2105 	}
2106 
2107 	if (is_amsdu)
2108 		rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr);
2109 
2110 	return rfc1042;
2111 }
2112 
2113 static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar,
2114 				       struct sk_buff *msdu,
2115 				       u8 *first_hdr,
2116 				       enum hal_encrypt_type enctype,
2117 				       struct ieee80211_rx_status *status)
2118 {
2119 	struct ieee80211_hdr *hdr;
2120 	struct ethhdr *eth;
2121 	size_t hdr_len;
2122 	u8 da[ETH_ALEN];
2123 	u8 sa[ETH_ALEN];
2124 	void *rfc1042;
2125 
2126 	rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype);
2127 	if (WARN_ON_ONCE(!rfc1042))
2128 		return;
2129 
2130 	/* pull decapped header and copy SA & DA */
2131 	eth = (struct ethhdr *)msdu->data;
2132 	ether_addr_copy(da, eth->h_dest);
2133 	ether_addr_copy(sa, eth->h_source);
2134 	skb_pull(msdu, sizeof(struct ethhdr));
2135 
2136 	/* push rfc1042/llc/snap */
2137 	memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042,
2138 	       sizeof(struct ath11k_dp_rfc1042_hdr));
2139 
2140 	/* push original 802.11 header */
2141 	hdr = (struct ieee80211_hdr *)first_hdr;
2142 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
2143 
2144 	if (!(status->flag & RX_FLAG_IV_STRIPPED)) {
2145 		memcpy(skb_push(msdu,
2146 				ath11k_dp_rx_crypto_param_len(ar, enctype)),
2147 		       (void *)hdr + hdr_len,
2148 		       ath11k_dp_rx_crypto_param_len(ar, enctype));
2149 	}
2150 
2151 	memcpy(skb_push(msdu, hdr_len), hdr, hdr_len);
2152 
2153 	/* original 802.11 header has a different DA and in
2154 	 * case of 4addr it may also have different SA
2155 	 */
2156 	hdr = (struct ieee80211_hdr *)msdu->data;
2157 	ether_addr_copy(ieee80211_get_DA(hdr), da);
2158 	ether_addr_copy(ieee80211_get_SA(hdr), sa);
2159 }
2160 
2161 static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu,
2162 				   struct hal_rx_desc *rx_desc,
2163 				   enum hal_encrypt_type enctype,
2164 				   struct ieee80211_rx_status *status,
2165 				   bool decrypted)
2166 {
2167 	u8 *first_hdr;
2168 	u8 decap;
2169 	struct ethhdr *ehdr;
2170 
2171 	first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
2172 	decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc);
2173 
2174 	switch (decap) {
2175 	case DP_RX_DECAP_TYPE_NATIVE_WIFI:
2176 		ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr,
2177 					     enctype, status);
2178 		break;
2179 	case DP_RX_DECAP_TYPE_RAW:
2180 		ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status,
2181 					   decrypted);
2182 		break;
2183 	case DP_RX_DECAP_TYPE_ETHERNET2_DIX:
2184 		ehdr = (struct ethhdr *)msdu->data;
2185 
2186 		/* mac80211 allows fast path only for authorized STA */
2187 		if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) {
2188 			ATH11K_SKB_RXCB(msdu)->is_eapol = true;
2189 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2190 						   enctype, status);
2191 			break;
2192 		}
2193 
2194 		/* PN for mcast packets will be validated in mac80211;
2195 		 * remove eth header and add 802.11 header.
2196 		 */
2197 		if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted)
2198 			ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr,
2199 						   enctype, status);
2200 		break;
2201 	case DP_RX_DECAP_TYPE_8023:
2202 		/* TODO: Handle undecap for these formats */
2203 		break;
2204 	}
2205 }
2206 
2207 static struct ath11k_peer *
2208 ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu)
2209 {
2210 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2211 	struct hal_rx_desc *rx_desc = rxcb->rx_desc;
2212 	struct ath11k_peer *peer = NULL;
2213 
2214 	lockdep_assert_held(&ab->base_lock);
2215 
2216 	if (rxcb->peer_id)
2217 		peer = ath11k_peer_find_by_id(ab, rxcb->peer_id);
2218 
2219 	if (peer)
2220 		return peer;
2221 
2222 	if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)))
2223 		return NULL;
2224 
2225 	peer = ath11k_peer_find_by_addr(ab,
2226 					ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc));
2227 	return peer;
2228 }
2229 
2230 static void ath11k_dp_rx_h_mpdu(struct ath11k *ar,
2231 				struct sk_buff *msdu,
2232 				struct hal_rx_desc *rx_desc,
2233 				struct ieee80211_rx_status *rx_status)
2234 {
2235 	bool  fill_crypto_hdr;
2236 	enum hal_encrypt_type enctype;
2237 	bool is_decrypted = false;
2238 	struct ath11k_skb_rxcb *rxcb;
2239 	struct ieee80211_hdr *hdr;
2240 	struct ath11k_peer *peer;
2241 	struct rx_attention *rx_attention;
2242 	u32 err_bitmap;
2243 
2244 	/* PN for multicast packets will be checked in mac80211 */
2245 	rxcb = ATH11K_SKB_RXCB(msdu);
2246 	fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
2247 	rxcb->is_mcbc = fill_crypto_hdr;
2248 
2249 	if (rxcb->is_mcbc) {
2250 		rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
2251 		rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
2252 	}
2253 
2254 	spin_lock_bh(&ar->ab->base_lock);
2255 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2256 	if (peer) {
2257 		if (rxcb->is_mcbc)
2258 			enctype = peer->sec_type_grp;
2259 		else
2260 			enctype = peer->sec_type;
2261 	} else {
2262 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
2263 	}
2264 	spin_unlock_bh(&ar->ab->base_lock);
2265 
2266 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
2267 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
2268 	if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap)
2269 		is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
2270 
2271 	/* Clear per-MPDU flags while leaving per-PPDU flags intact */
2272 	rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC |
2273 			     RX_FLAG_MMIC_ERROR |
2274 			     RX_FLAG_DECRYPTED |
2275 			     RX_FLAG_IV_STRIPPED |
2276 			     RX_FLAG_MMIC_STRIPPED);
2277 
2278 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
2279 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
2280 	if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC)
2281 		rx_status->flag |= RX_FLAG_MMIC_ERROR;
2282 
2283 	if (is_decrypted) {
2284 		rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED;
2285 
2286 		if (fill_crypto_hdr)
2287 			rx_status->flag |= RX_FLAG_MIC_STRIPPED |
2288 					RX_FLAG_ICV_STRIPPED;
2289 		else
2290 			rx_status->flag |= RX_FLAG_IV_STRIPPED |
2291 					   RX_FLAG_PN_VALIDATED;
2292 	}
2293 
2294 	ath11k_dp_rx_h_csum_offload(ar, msdu);
2295 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
2296 			       enctype, rx_status, is_decrypted);
2297 
2298 	if (!is_decrypted || fill_crypto_hdr)
2299 		return;
2300 
2301 	if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) !=
2302 	    DP_RX_DECAP_TYPE_ETHERNET2_DIX) {
2303 		hdr = (void *)msdu->data;
2304 		hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED);
2305 	}
2306 }
2307 
2308 static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2309 				struct ieee80211_rx_status *rx_status)
2310 {
2311 	struct ieee80211_supported_band *sband;
2312 	enum rx_msdu_start_pkt_type pkt_type;
2313 	u8 bw;
2314 	u8 rate_mcs, nss;
2315 	u8 sgi;
2316 	bool is_cck;
2317 
2318 	pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc);
2319 	bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc);
2320 	rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc);
2321 	nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc);
2322 	sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc);
2323 
2324 	switch (pkt_type) {
2325 	case RX_MSDU_START_PKT_TYPE_11A:
2326 	case RX_MSDU_START_PKT_TYPE_11B:
2327 		is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B);
2328 		sband = &ar->mac.sbands[rx_status->band];
2329 		rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs,
2330 								is_cck);
2331 		break;
2332 	case RX_MSDU_START_PKT_TYPE_11N:
2333 		rx_status->encoding = RX_ENC_HT;
2334 		if (rate_mcs > ATH11K_HT_MCS_MAX) {
2335 			ath11k_warn(ar->ab,
2336 				    "Received with invalid mcs in HT mode %d\n",
2337 				     rate_mcs);
2338 			break;
2339 		}
2340 		rx_status->rate_idx = rate_mcs + (8 * (nss - 1));
2341 		if (sgi)
2342 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2343 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2344 		break;
2345 	case RX_MSDU_START_PKT_TYPE_11AC:
2346 		rx_status->encoding = RX_ENC_VHT;
2347 		rx_status->rate_idx = rate_mcs;
2348 		if (rate_mcs > ATH11K_VHT_MCS_MAX) {
2349 			ath11k_warn(ar->ab,
2350 				    "Received with invalid mcs in VHT mode %d\n",
2351 				     rate_mcs);
2352 			break;
2353 		}
2354 		rx_status->nss = nss;
2355 		if (sgi)
2356 			rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
2357 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2358 		break;
2359 	case RX_MSDU_START_PKT_TYPE_11AX:
2360 		rx_status->rate_idx = rate_mcs;
2361 		if (rate_mcs > ATH11K_HE_MCS_MAX) {
2362 			ath11k_warn(ar->ab,
2363 				    "Received with invalid mcs in HE mode %d\n",
2364 				    rate_mcs);
2365 			break;
2366 		}
2367 		rx_status->encoding = RX_ENC_HE;
2368 		rx_status->nss = nss;
2369 		rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
2370 		rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw);
2371 		break;
2372 	}
2373 }
2374 
2375 static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc,
2376 				struct ieee80211_rx_status *rx_status)
2377 {
2378 	u8 channel_num;
2379 	u32 center_freq, meta_data;
2380 	struct ieee80211_channel *channel;
2381 
2382 	rx_status->freq = 0;
2383 	rx_status->rate_idx = 0;
2384 	rx_status->nss = 0;
2385 	rx_status->encoding = RX_ENC_LEGACY;
2386 	rx_status->bw = RATE_INFO_BW_20;
2387 
2388 	rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
2389 
2390 	meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc);
2391 	channel_num = meta_data;
2392 	center_freq = meta_data >> 16;
2393 
2394 	if (center_freq >= ATH11K_MIN_6G_FREQ &&
2395 	    center_freq <= ATH11K_MAX_6G_FREQ) {
2396 		rx_status->band = NL80211_BAND_6GHZ;
2397 		rx_status->freq = center_freq;
2398 	} else if (channel_num >= 1 && channel_num <= 14) {
2399 		rx_status->band = NL80211_BAND_2GHZ;
2400 	} else if (channel_num >= 36 && channel_num <= 173) {
2401 		rx_status->band = NL80211_BAND_5GHZ;
2402 	} else {
2403 		spin_lock_bh(&ar->data_lock);
2404 		channel = ar->rx_channel;
2405 		if (channel) {
2406 			rx_status->band = channel->band;
2407 			channel_num =
2408 				ieee80211_frequency_to_channel(channel->center_freq);
2409 		}
2410 		spin_unlock_bh(&ar->data_lock);
2411 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
2412 				rx_desc, sizeof(struct hal_rx_desc));
2413 	}
2414 
2415 	if (rx_status->band != NL80211_BAND_6GHZ)
2416 		rx_status->freq = ieee80211_channel_to_frequency(channel_num,
2417 								 rx_status->band);
2418 
2419 	ath11k_dp_rx_h_rate(ar, rx_desc, rx_status);
2420 }
2421 
2422 static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi,
2423 				      struct sk_buff *msdu,
2424 				      struct ieee80211_rx_status *status)
2425 {
2426 	static const struct ieee80211_radiotap_he known = {
2427 		.data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
2428 				     IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
2429 		.data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
2430 	};
2431 	struct ieee80211_rx_status *rx_status;
2432 	struct ieee80211_radiotap_he *he = NULL;
2433 	struct ieee80211_sta *pubsta = NULL;
2434 	struct ath11k_peer *peer;
2435 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
2436 	u8 decap = DP_RX_DECAP_TYPE_RAW;
2437 	bool is_mcbc = rxcb->is_mcbc;
2438 	bool is_eapol = rxcb->is_eapol;
2439 
2440 	if (status->encoding == RX_ENC_HE &&
2441 	    !(status->flag & RX_FLAG_RADIOTAP_HE) &&
2442 	    !(status->flag & RX_FLAG_SKIP_MONITOR)) {
2443 		he = skb_push(msdu, sizeof(known));
2444 		memcpy(he, &known, sizeof(known));
2445 		status->flag |= RX_FLAG_RADIOTAP_HE;
2446 	}
2447 
2448 	if (!(status->flag & RX_FLAG_ONLY_MONITOR))
2449 		decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc);
2450 
2451 	spin_lock_bh(&ar->ab->base_lock);
2452 	peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu);
2453 	if (peer && peer->sta)
2454 		pubsta = peer->sta;
2455 	spin_unlock_bh(&ar->ab->base_lock);
2456 
2457 	ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
2458 		   "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
2459 		   msdu,
2460 		   msdu->len,
2461 		   peer ? peer->addr : NULL,
2462 		   rxcb->tid,
2463 		   is_mcbc ? "mcast" : "ucast",
2464 		   rxcb->seq_no,
2465 		   (status->encoding == RX_ENC_LEGACY) ? "legacy" : "",
2466 		   (status->encoding == RX_ENC_HT) ? "ht" : "",
2467 		   (status->encoding == RX_ENC_VHT) ? "vht" : "",
2468 		   (status->encoding == RX_ENC_HE) ? "he" : "",
2469 		   (status->bw == RATE_INFO_BW_40) ? "40" : "",
2470 		   (status->bw == RATE_INFO_BW_80) ? "80" : "",
2471 		   (status->bw == RATE_INFO_BW_160) ? "160" : "",
2472 		   status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "",
2473 		   status->rate_idx,
2474 		   status->nss,
2475 		   status->freq,
2476 		   status->band, status->flag,
2477 		   !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
2478 		   !!(status->flag & RX_FLAG_MMIC_ERROR),
2479 		   !!(status->flag & RX_FLAG_AMSDU_MORE));
2480 
2481 	ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ",
2482 			msdu->data, msdu->len);
2483 
2484 	rx_status = IEEE80211_SKB_RXCB(msdu);
2485 	*rx_status = *status;
2486 
2487 	/* TODO: trace rx packet */
2488 
2489 	/* PN for multicast packets are not validate in HW,
2490 	 * so skip 802.3 rx path
2491 	 * Also, fast_rx expectes the STA to be authorized, hence
2492 	 * eapol packets are sent in slow path.
2493 	 */
2494 	if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol &&
2495 	    !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED))
2496 		rx_status->flag |= RX_FLAG_8023;
2497 
2498 	ieee80211_rx_napi(ar->hw, pubsta, msdu, napi);
2499 }
2500 
2501 static int ath11k_dp_rx_process_msdu(struct ath11k *ar,
2502 				     struct sk_buff *msdu,
2503 				     struct sk_buff_head *msdu_list,
2504 				     struct ieee80211_rx_status *rx_status)
2505 {
2506 	struct ath11k_base *ab = ar->ab;
2507 	struct hal_rx_desc *rx_desc, *lrx_desc;
2508 	struct rx_attention *rx_attention;
2509 	struct ath11k_skb_rxcb *rxcb;
2510 	struct sk_buff *last_buf;
2511 	u8 l3_pad_bytes;
2512 	u8 *hdr_status;
2513 	u16 msdu_len;
2514 	int ret;
2515 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
2516 
2517 	last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu);
2518 	if (!last_buf) {
2519 		ath11k_warn(ab,
2520 			    "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n");
2521 		ret = -EIO;
2522 		goto free_out;
2523 	}
2524 
2525 	rx_desc = (struct hal_rx_desc *)msdu->data;
2526 	if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) {
2527 		ath11k_warn(ar->ab, "msdu len not valid\n");
2528 		ret = -EIO;
2529 		goto free_out;
2530 	}
2531 
2532 	lrx_desc = (struct hal_rx_desc *)last_buf->data;
2533 	rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc);
2534 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
2535 		ath11k_warn(ab, "msdu_done bit in attention is not set\n");
2536 		ret = -EIO;
2537 		goto free_out;
2538 	}
2539 
2540 	rxcb = ATH11K_SKB_RXCB(msdu);
2541 	rxcb->rx_desc = rx_desc;
2542 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc);
2543 	l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc);
2544 
2545 	if (rxcb->is_frag) {
2546 		skb_pull(msdu, hal_rx_desc_sz);
2547 	} else if (!rxcb->is_continuation) {
2548 		if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
2549 			hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc);
2550 			ret = -EINVAL;
2551 			ath11k_warn(ab, "invalid msdu len %u\n", msdu_len);
2552 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
2553 					sizeof(struct ieee80211_hdr));
2554 			ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
2555 					sizeof(struct hal_rx_desc));
2556 			goto free_out;
2557 		}
2558 		skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len);
2559 		skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes);
2560 	} else {
2561 		ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list,
2562 						 msdu, last_buf,
2563 						 l3_pad_bytes, msdu_len);
2564 		if (ret) {
2565 			ath11k_warn(ab,
2566 				    "failed to coalesce msdu rx buffer%d\n", ret);
2567 			goto free_out;
2568 		}
2569 	}
2570 
2571 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status);
2572 	ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status);
2573 
2574 	rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED;
2575 
2576 	return 0;
2577 
2578 free_out:
2579 	return ret;
2580 }
2581 
2582 static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab,
2583 						  struct napi_struct *napi,
2584 						  struct sk_buff_head *msdu_list,
2585 						  int mac_id)
2586 {
2587 	struct sk_buff *msdu;
2588 	struct ath11k *ar;
2589 	struct ieee80211_rx_status rx_status = {0};
2590 	int ret;
2591 
2592 	if (skb_queue_empty(msdu_list))
2593 		return;
2594 
2595 	if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) {
2596 		__skb_queue_purge(msdu_list);
2597 		return;
2598 	}
2599 
2600 	ar = ab->pdevs[mac_id].ar;
2601 	if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) {
2602 		__skb_queue_purge(msdu_list);
2603 		return;
2604 	}
2605 
2606 	while ((msdu = __skb_dequeue(msdu_list))) {
2607 		ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status);
2608 		if (unlikely(ret)) {
2609 			ath11k_dbg(ab, ATH11K_DBG_DATA,
2610 				   "Unable to process msdu %d", ret);
2611 			dev_kfree_skb_any(msdu);
2612 			continue;
2613 		}
2614 
2615 		ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status);
2616 	}
2617 }
2618 
2619 int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id,
2620 			 struct napi_struct *napi, int budget)
2621 {
2622 	struct ath11k_dp *dp = &ab->dp;
2623 	struct dp_rxdma_ring *rx_ring;
2624 	int num_buffs_reaped[MAX_RADIOS] = {0};
2625 	struct sk_buff_head msdu_list[MAX_RADIOS];
2626 	struct ath11k_skb_rxcb *rxcb;
2627 	int total_msdu_reaped = 0;
2628 	struct hal_srng *srng;
2629 	struct sk_buff *msdu;
2630 	bool done = false;
2631 	int buf_id, mac_id;
2632 	struct ath11k *ar;
2633 	struct hal_reo_dest_ring *desc;
2634 	enum hal_reo_dest_ring_push_reason push_reason;
2635 	u32 cookie;
2636 	int i;
2637 
2638 	for (i = 0; i < MAX_RADIOS; i++)
2639 		__skb_queue_head_init(&msdu_list[i]);
2640 
2641 	srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id];
2642 
2643 	spin_lock_bh(&srng->lock);
2644 
2645 	ath11k_hal_srng_access_begin(ab, srng);
2646 
2647 try_again:
2648 	while (likely(desc =
2649 	      (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab,
2650 									     srng))) {
2651 		cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
2652 				   desc->buf_addr_info.info1);
2653 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
2654 				   cookie);
2655 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie);
2656 
2657 		ar = ab->pdevs[mac_id].ar;
2658 		rx_ring = &ar->dp.rx_refill_buf_ring;
2659 		spin_lock_bh(&rx_ring->idr_lock);
2660 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
2661 		if (unlikely(!msdu)) {
2662 			ath11k_warn(ab, "frame rx with invalid buf_id %d\n",
2663 				    buf_id);
2664 			spin_unlock_bh(&rx_ring->idr_lock);
2665 			continue;
2666 		}
2667 
2668 		idr_remove(&rx_ring->bufs_idr, buf_id);
2669 		spin_unlock_bh(&rx_ring->idr_lock);
2670 
2671 		rxcb = ATH11K_SKB_RXCB(msdu);
2672 		dma_unmap_single(ab->dev, rxcb->paddr,
2673 				 msdu->len + skb_tailroom(msdu),
2674 				 DMA_FROM_DEVICE);
2675 
2676 		num_buffs_reaped[mac_id]++;
2677 
2678 		push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
2679 					desc->info0);
2680 		if (unlikely(push_reason !=
2681 			     HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) {
2682 			dev_kfree_skb_any(msdu);
2683 			ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++;
2684 			continue;
2685 		}
2686 
2687 		rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 &
2688 					 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU);
2689 		rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 &
2690 					RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU);
2691 		rxcb->is_continuation = !!(desc->rx_msdu_info.info0 &
2692 					   RX_MSDU_DESC_INFO0_MSDU_CONTINUATION);
2693 		rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID,
2694 					  desc->rx_mpdu_info.meta_data);
2695 		rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM,
2696 					 desc->rx_mpdu_info.info0);
2697 		rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM,
2698 				      desc->info0);
2699 
2700 		rxcb->mac_id = mac_id;
2701 		__skb_queue_tail(&msdu_list[mac_id], msdu);
2702 
2703 		if (rxcb->is_continuation) {
2704 			done = false;
2705 		} else {
2706 			total_msdu_reaped++;
2707 			done = true;
2708 		}
2709 
2710 		if (total_msdu_reaped >= budget)
2711 			break;
2712 	}
2713 
2714 	/* Hw might have updated the head pointer after we cached it.
2715 	 * In this case, even though there are entries in the ring we'll
2716 	 * get rx_desc NULL. Give the read another try with updated cached
2717 	 * head pointer so that we can reap complete MPDU in the current
2718 	 * rx processing.
2719 	 */
2720 	if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) {
2721 		ath11k_hal_srng_access_end(ab, srng);
2722 		goto try_again;
2723 	}
2724 
2725 	ath11k_hal_srng_access_end(ab, srng);
2726 
2727 	spin_unlock_bh(&srng->lock);
2728 
2729 	if (unlikely(!total_msdu_reaped))
2730 		goto exit;
2731 
2732 	for (i = 0; i < ab->num_radios; i++) {
2733 		if (!num_buffs_reaped[i])
2734 			continue;
2735 
2736 		ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i);
2737 
2738 		ar = ab->pdevs[i].ar;
2739 		rx_ring = &ar->dp.rx_refill_buf_ring;
2740 
2741 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
2742 					   ab->hw_params.hal_params->rx_buf_rbm);
2743 	}
2744 exit:
2745 	return total_msdu_reaped;
2746 }
2747 
2748 static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta,
2749 					   struct hal_rx_mon_ppdu_info *ppdu_info)
2750 {
2751 	struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats;
2752 	u32 num_msdu;
2753 	int i;
2754 
2755 	if (!rx_stats)
2756 		return;
2757 
2758 	num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count +
2759 		   ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count;
2760 
2761 	rx_stats->num_msdu += num_msdu;
2762 	rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count +
2763 				    ppdu_info->tcp_ack_msdu_count;
2764 	rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count;
2765 	rx_stats->other_msdu_count += ppdu_info->other_msdu_count;
2766 
2767 	if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A ||
2768 	    ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) {
2769 		ppdu_info->nss = 1;
2770 		ppdu_info->mcs = HAL_RX_MAX_MCS;
2771 		ppdu_info->tid = IEEE80211_NUM_TIDS;
2772 	}
2773 
2774 	if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS)
2775 		rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu;
2776 
2777 	if (ppdu_info->mcs <= HAL_RX_MAX_MCS)
2778 		rx_stats->mcs_count[ppdu_info->mcs] += num_msdu;
2779 
2780 	if (ppdu_info->gi < HAL_RX_GI_MAX)
2781 		rx_stats->gi_count[ppdu_info->gi] += num_msdu;
2782 
2783 	if (ppdu_info->bw < HAL_RX_BW_MAX)
2784 		rx_stats->bw_count[ppdu_info->bw] += num_msdu;
2785 
2786 	if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX)
2787 		rx_stats->coding_count[ppdu_info->ldpc] += num_msdu;
2788 
2789 	if (ppdu_info->tid <= IEEE80211_NUM_TIDS)
2790 		rx_stats->tid_count[ppdu_info->tid] += num_msdu;
2791 
2792 	if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX)
2793 		rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu;
2794 
2795 	if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX)
2796 		rx_stats->reception_type[ppdu_info->reception_type] += num_msdu;
2797 
2798 	if (ppdu_info->is_stbc)
2799 		rx_stats->stbc_count += num_msdu;
2800 
2801 	if (ppdu_info->beamformed)
2802 		rx_stats->beamformed_count += num_msdu;
2803 
2804 	if (ppdu_info->num_mpdu_fcs_ok > 1)
2805 		rx_stats->ampdu_msdu_count += num_msdu;
2806 	else
2807 		rx_stats->non_ampdu_msdu_count += num_msdu;
2808 
2809 	rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok;
2810 	rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err;
2811 	rx_stats->dcm_count += ppdu_info->dcm;
2812 	rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu;
2813 
2814 	arsta->rssi_comb = ppdu_info->rssi_comb;
2815 
2816 	BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) >
2817 			     ARRAY_SIZE(ppdu_info->rssi_chain_pri20));
2818 
2819 	for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++)
2820 		arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i];
2821 
2822 	rx_stats->rx_duration += ppdu_info->rx_duration;
2823 	arsta->rx_duration = rx_stats->rx_duration;
2824 }
2825 
2826 static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab,
2827 							 struct dp_rxdma_ring *rx_ring,
2828 							 int *buf_id)
2829 {
2830 	struct sk_buff *skb;
2831 	dma_addr_t paddr;
2832 
2833 	skb = dev_alloc_skb(DP_RX_BUFFER_SIZE +
2834 			    DP_RX_BUFFER_ALIGN_SIZE);
2835 
2836 	if (!skb)
2837 		goto fail_alloc_skb;
2838 
2839 	if (!IS_ALIGNED((unsigned long)skb->data,
2840 			DP_RX_BUFFER_ALIGN_SIZE)) {
2841 		skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) -
2842 			 skb->data);
2843 	}
2844 
2845 	paddr = dma_map_single(ab->dev, skb->data,
2846 			       skb->len + skb_tailroom(skb),
2847 			       DMA_FROM_DEVICE);
2848 	if (unlikely(dma_mapping_error(ab->dev, paddr)))
2849 		goto fail_free_skb;
2850 
2851 	spin_lock_bh(&rx_ring->idr_lock);
2852 	*buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0,
2853 			    rx_ring->bufs_max, GFP_ATOMIC);
2854 	spin_unlock_bh(&rx_ring->idr_lock);
2855 	if (*buf_id < 0)
2856 		goto fail_dma_unmap;
2857 
2858 	ATH11K_SKB_RXCB(skb)->paddr = paddr;
2859 	return skb;
2860 
2861 fail_dma_unmap:
2862 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2863 			 DMA_FROM_DEVICE);
2864 fail_free_skb:
2865 	dev_kfree_skb_any(skb);
2866 fail_alloc_skb:
2867 	return NULL;
2868 }
2869 
2870 int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id,
2871 					   struct dp_rxdma_ring *rx_ring,
2872 					   int req_entries,
2873 					   enum hal_rx_buf_return_buf_manager mgr)
2874 {
2875 	struct hal_srng *srng;
2876 	u32 *desc;
2877 	struct sk_buff *skb;
2878 	int num_free;
2879 	int num_remain;
2880 	int buf_id;
2881 	u32 cookie;
2882 	dma_addr_t paddr;
2883 
2884 	req_entries = min(req_entries, rx_ring->bufs_max);
2885 
2886 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2887 
2888 	spin_lock_bh(&srng->lock);
2889 
2890 	ath11k_hal_srng_access_begin(ab, srng);
2891 
2892 	num_free = ath11k_hal_srng_src_num_free(ab, srng, true);
2893 
2894 	req_entries = min(num_free, req_entries);
2895 	num_remain = req_entries;
2896 
2897 	while (num_remain > 0) {
2898 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
2899 							&buf_id);
2900 		if (!skb)
2901 			break;
2902 		paddr = ATH11K_SKB_RXCB(skb)->paddr;
2903 
2904 		desc = ath11k_hal_srng_src_get_next_entry(ab, srng);
2905 		if (!desc)
2906 			goto fail_desc_get;
2907 
2908 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
2909 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
2910 
2911 		num_remain--;
2912 
2913 		ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr);
2914 	}
2915 
2916 	ath11k_hal_srng_access_end(ab, srng);
2917 
2918 	spin_unlock_bh(&srng->lock);
2919 
2920 	return req_entries - num_remain;
2921 
2922 fail_desc_get:
2923 	spin_lock_bh(&rx_ring->idr_lock);
2924 	idr_remove(&rx_ring->bufs_idr, buf_id);
2925 	spin_unlock_bh(&rx_ring->idr_lock);
2926 	dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb),
2927 			 DMA_FROM_DEVICE);
2928 	dev_kfree_skb_any(skb);
2929 	ath11k_hal_srng_access_end(ab, srng);
2930 	spin_unlock_bh(&srng->lock);
2931 
2932 	return req_entries - num_remain;
2933 }
2934 
2935 #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535
2936 
2937 static void
2938 ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon,
2939 					 struct hal_tlv_hdr *tlv)
2940 {
2941 	struct hal_rx_ppdu_start *ppdu_start;
2942 	u16 ppdu_id_diff, ppdu_id, tlv_len;
2943 	u8 *ptr;
2944 
2945 	/* PPDU id is part of second tlv, move ptr to second tlv */
2946 	tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
2947 	ptr = (u8 *)tlv;
2948 	ptr += sizeof(*tlv) + tlv_len;
2949 	tlv = (struct hal_tlv_hdr *)ptr;
2950 
2951 	if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START)
2952 		return;
2953 
2954 	ptr += sizeof(*tlv);
2955 	ppdu_start = (struct hal_rx_ppdu_start *)ptr;
2956 	ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
2957 			    __le32_to_cpu(ppdu_start->info0));
2958 
2959 	if (pmon->sw_mon_entries.ppdu_id < ppdu_id) {
2960 		pmon->buf_state = DP_MON_STATUS_LEAD;
2961 		ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id;
2962 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2963 			pmon->buf_state = DP_MON_STATUS_LAG;
2964 	} else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) {
2965 		pmon->buf_state = DP_MON_STATUS_LAG;
2966 		ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id;
2967 		if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP)
2968 			pmon->buf_state = DP_MON_STATUS_LEAD;
2969 	}
2970 }
2971 
2972 static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id,
2973 					     int *budget, struct sk_buff_head *skb_list)
2974 {
2975 	struct ath11k *ar;
2976 	const struct ath11k_hw_hal_params *hal_params;
2977 	struct ath11k_pdev_dp *dp;
2978 	struct dp_rxdma_ring *rx_ring;
2979 	struct ath11k_mon_data *pmon;
2980 	struct hal_srng *srng;
2981 	void *rx_mon_status_desc;
2982 	struct sk_buff *skb;
2983 	struct ath11k_skb_rxcb *rxcb;
2984 	struct hal_tlv_hdr *tlv;
2985 	u32 cookie;
2986 	int buf_id, srng_id;
2987 	dma_addr_t paddr;
2988 	u8 rbm;
2989 	int num_buffs_reaped = 0;
2990 
2991 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
2992 	dp = &ar->dp;
2993 	pmon = &dp->mon_data;
2994 	srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id);
2995 	rx_ring = &dp->rx_mon_status_refill_ring[srng_id];
2996 
2997 	srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id];
2998 
2999 	spin_lock_bh(&srng->lock);
3000 
3001 	ath11k_hal_srng_access_begin(ab, srng);
3002 	while (*budget) {
3003 		*budget -= 1;
3004 		rx_mon_status_desc =
3005 			ath11k_hal_srng_src_peek(ab, srng);
3006 		if (!rx_mon_status_desc) {
3007 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3008 			break;
3009 		}
3010 
3011 		ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr,
3012 						&cookie, &rbm);
3013 		if (paddr) {
3014 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie);
3015 
3016 			spin_lock_bh(&rx_ring->idr_lock);
3017 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
3018 			if (!skb) {
3019 				ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n",
3020 					    buf_id);
3021 				spin_unlock_bh(&rx_ring->idr_lock);
3022 				pmon->buf_state = DP_MON_STATUS_REPLINISH;
3023 				goto move_next;
3024 			}
3025 
3026 			idr_remove(&rx_ring->bufs_idr, buf_id);
3027 			spin_unlock_bh(&rx_ring->idr_lock);
3028 
3029 			rxcb = ATH11K_SKB_RXCB(skb);
3030 
3031 			dma_unmap_single(ab->dev, rxcb->paddr,
3032 					 skb->len + skb_tailroom(skb),
3033 					 DMA_FROM_DEVICE);
3034 
3035 			tlv = (struct hal_tlv_hdr *)skb->data;
3036 			if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) !=
3037 					HAL_RX_STATUS_BUFFER_DONE) {
3038 				ath11k_warn(ab, "mon status DONE not set %lx\n",
3039 					    FIELD_GET(HAL_TLV_HDR_TAG,
3040 						      tlv->tl));
3041 				dev_kfree_skb_any(skb);
3042 				pmon->buf_state = DP_MON_STATUS_NO_DMA;
3043 				goto move_next;
3044 			}
3045 
3046 			if (ab->hw_params.full_monitor_mode) {
3047 				ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv);
3048 				if (paddr == pmon->mon_status_paddr)
3049 					pmon->buf_state = DP_MON_STATUS_MATCH;
3050 			}
3051 			__skb_queue_tail(skb_list, skb);
3052 		} else {
3053 			pmon->buf_state = DP_MON_STATUS_REPLINISH;
3054 		}
3055 move_next:
3056 		skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring,
3057 							&buf_id);
3058 
3059 		if (!skb) {
3060 			hal_params = ab->hw_params.hal_params;
3061 			ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0,
3062 							hal_params->rx_buf_rbm);
3063 			num_buffs_reaped++;
3064 			break;
3065 		}
3066 		rxcb = ATH11K_SKB_RXCB(skb);
3067 
3068 		cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) |
3069 			 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3070 
3071 		ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr,
3072 						cookie,
3073 						ab->hw_params.hal_params->rx_buf_rbm);
3074 		ath11k_hal_srng_src_get_next_entry(ab, srng);
3075 		num_buffs_reaped++;
3076 	}
3077 	ath11k_hal_srng_access_end(ab, srng);
3078 	spin_unlock_bh(&srng->lock);
3079 
3080 	return num_buffs_reaped;
3081 }
3082 
3083 int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id,
3084 				    struct napi_struct *napi, int budget)
3085 {
3086 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
3087 	enum hal_rx_mon_status hal_status;
3088 	struct sk_buff *skb;
3089 	struct sk_buff_head skb_list;
3090 	struct hal_rx_mon_ppdu_info ppdu_info;
3091 	struct ath11k_peer *peer;
3092 	struct ath11k_sta *arsta;
3093 	int num_buffs_reaped = 0;
3094 	u32 rx_buf_sz;
3095 	u16 log_type = 0;
3096 
3097 	__skb_queue_head_init(&skb_list);
3098 
3099 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget,
3100 							     &skb_list);
3101 	if (!num_buffs_reaped)
3102 		goto exit;
3103 
3104 	memset(&ppdu_info, 0, sizeof(ppdu_info));
3105 	ppdu_info.peer_id = HAL_INVALID_PEERID;
3106 
3107 	while ((skb = __skb_dequeue(&skb_list))) {
3108 		if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) {
3109 			log_type = ATH11K_PKTLOG_TYPE_LITE_RX;
3110 			rx_buf_sz = DP_RX_BUFFER_SIZE_LITE;
3111 		} else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) {
3112 			log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF;
3113 			rx_buf_sz = DP_RX_BUFFER_SIZE;
3114 		}
3115 
3116 		if (log_type)
3117 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
3118 
3119 		hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb);
3120 
3121 		if (ppdu_info.peer_id == HAL_INVALID_PEERID ||
3122 		    hal_status != HAL_RX_MON_STATUS_PPDU_DONE) {
3123 			dev_kfree_skb_any(skb);
3124 			continue;
3125 		}
3126 
3127 		rcu_read_lock();
3128 		spin_lock_bh(&ab->base_lock);
3129 		peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id);
3130 
3131 		if (!peer || !peer->sta) {
3132 			ath11k_dbg(ab, ATH11K_DBG_DATA,
3133 				   "failed to find the peer with peer_id %d\n",
3134 				   ppdu_info.peer_id);
3135 			goto next_skb;
3136 		}
3137 
3138 		arsta = (struct ath11k_sta *)peer->sta->drv_priv;
3139 		ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info);
3140 
3141 		if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr))
3142 			trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz);
3143 
3144 next_skb:
3145 		spin_unlock_bh(&ab->base_lock);
3146 		rcu_read_unlock();
3147 
3148 		dev_kfree_skb_any(skb);
3149 		memset(&ppdu_info, 0, sizeof(ppdu_info));
3150 		ppdu_info.peer_id = HAL_INVALID_PEERID;
3151 	}
3152 exit:
3153 	return num_buffs_reaped;
3154 }
3155 
3156 static void ath11k_dp_rx_frag_timer(struct timer_list *timer)
3157 {
3158 	struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer);
3159 
3160 	spin_lock_bh(&rx_tid->ab->base_lock);
3161 	if (rx_tid->last_frag_no &&
3162 	    rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) {
3163 		spin_unlock_bh(&rx_tid->ab->base_lock);
3164 		return;
3165 	}
3166 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3167 	spin_unlock_bh(&rx_tid->ab->base_lock);
3168 }
3169 
3170 int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id)
3171 {
3172 	struct ath11k_base *ab = ar->ab;
3173 	struct crypto_shash *tfm;
3174 	struct ath11k_peer *peer;
3175 	struct dp_rx_tid *rx_tid;
3176 	int i;
3177 
3178 	tfm = crypto_alloc_shash("michael_mic", 0, 0);
3179 	if (IS_ERR(tfm))
3180 		return PTR_ERR(tfm);
3181 
3182 	spin_lock_bh(&ab->base_lock);
3183 
3184 	peer = ath11k_peer_find(ab, vdev_id, peer_mac);
3185 	if (!peer) {
3186 		ath11k_warn(ab, "failed to find the peer to set up fragment info\n");
3187 		spin_unlock_bh(&ab->base_lock);
3188 		return -ENOENT;
3189 	}
3190 
3191 	for (i = 0; i <= IEEE80211_NUM_TIDS; i++) {
3192 		rx_tid = &peer->rx_tid[i];
3193 		rx_tid->ab = ab;
3194 		timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0);
3195 		skb_queue_head_init(&rx_tid->rx_frags);
3196 	}
3197 
3198 	peer->tfm_mmic = tfm;
3199 	spin_unlock_bh(&ab->base_lock);
3200 
3201 	return 0;
3202 }
3203 
3204 static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key,
3205 				      struct ieee80211_hdr *hdr, u8 *data,
3206 				      size_t data_len, u8 *mic)
3207 {
3208 	SHASH_DESC_ON_STACK(desc, tfm);
3209 	u8 mic_hdr[16] = {0};
3210 	u8 tid = 0;
3211 	int ret;
3212 
3213 	if (!tfm)
3214 		return -EINVAL;
3215 
3216 	desc->tfm = tfm;
3217 
3218 	ret = crypto_shash_setkey(tfm, key, 8);
3219 	if (ret)
3220 		goto out;
3221 
3222 	ret = crypto_shash_init(desc);
3223 	if (ret)
3224 		goto out;
3225 
3226 	/* TKIP MIC header */
3227 	memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN);
3228 	memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN);
3229 	if (ieee80211_is_data_qos(hdr->frame_control))
3230 		tid = ieee80211_get_tid(hdr);
3231 	mic_hdr[12] = tid;
3232 
3233 	ret = crypto_shash_update(desc, mic_hdr, 16);
3234 	if (ret)
3235 		goto out;
3236 	ret = crypto_shash_update(desc, data, data_len);
3237 	if (ret)
3238 		goto out;
3239 	ret = crypto_shash_final(desc, mic);
3240 out:
3241 	shash_desc_zero(desc);
3242 	return ret;
3243 }
3244 
3245 static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer,
3246 					  struct sk_buff *msdu)
3247 {
3248 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data;
3249 	struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu);
3250 	struct ieee80211_key_conf *key_conf;
3251 	struct ieee80211_hdr *hdr;
3252 	u8 mic[IEEE80211_CCMP_MIC_LEN];
3253 	int head_len, tail_len, ret;
3254 	size_t data_len;
3255 	u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3256 	u8 *key, *data;
3257 	u8 key_idx;
3258 
3259 	if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) !=
3260 	    HAL_ENCRYPT_TYPE_TKIP_MIC)
3261 		return 0;
3262 
3263 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3264 	hdr_len = ieee80211_hdrlen(hdr->frame_control);
3265 	head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN;
3266 	tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN;
3267 
3268 	if (!is_multicast_ether_addr(hdr->addr1))
3269 		key_idx = peer->ucast_keyidx;
3270 	else
3271 		key_idx = peer->mcast_keyidx;
3272 
3273 	key_conf = peer->keys[key_idx];
3274 
3275 	data = msdu->data + head_len;
3276 	data_len = msdu->len - head_len - tail_len;
3277 	key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY];
3278 
3279 	ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic);
3280 	if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN))
3281 		goto mic_fail;
3282 
3283 	return 0;
3284 
3285 mic_fail:
3286 	(ATH11K_SKB_RXCB(msdu))->is_first_msdu = true;
3287 	(ATH11K_SKB_RXCB(msdu))->is_last_msdu = true;
3288 
3289 	rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED |
3290 		    RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED;
3291 	skb_pull(msdu, hal_rx_desc_sz);
3292 
3293 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
3294 	ath11k_dp_rx_h_undecap(ar, msdu, rx_desc,
3295 			       HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true);
3296 	ieee80211_rx(ar->hw, msdu);
3297 	return -EINVAL;
3298 }
3299 
3300 static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu,
3301 					enum hal_encrypt_type enctype, u32 flags)
3302 {
3303 	struct ieee80211_hdr *hdr;
3304 	size_t hdr_len;
3305 	size_t crypto_len;
3306 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3307 
3308 	if (!flags)
3309 		return;
3310 
3311 	hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz);
3312 
3313 	if (flags & RX_FLAG_MIC_STRIPPED)
3314 		skb_trim(msdu, msdu->len -
3315 			 ath11k_dp_rx_crypto_mic_len(ar, enctype));
3316 
3317 	if (flags & RX_FLAG_ICV_STRIPPED)
3318 		skb_trim(msdu, msdu->len -
3319 			 ath11k_dp_rx_crypto_icv_len(ar, enctype));
3320 
3321 	if (flags & RX_FLAG_IV_STRIPPED) {
3322 		hdr_len = ieee80211_hdrlen(hdr->frame_control);
3323 		crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype);
3324 
3325 		memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len,
3326 			(void *)msdu->data + hal_rx_desc_sz, hdr_len);
3327 		skb_pull(msdu, crypto_len);
3328 	}
3329 }
3330 
3331 static int ath11k_dp_rx_h_defrag(struct ath11k *ar,
3332 				 struct ath11k_peer *peer,
3333 				 struct dp_rx_tid *rx_tid,
3334 				 struct sk_buff **defrag_skb)
3335 {
3336 	struct hal_rx_desc *rx_desc;
3337 	struct sk_buff *skb, *first_frag, *last_frag;
3338 	struct ieee80211_hdr *hdr;
3339 	struct rx_attention *rx_attention;
3340 	enum hal_encrypt_type enctype;
3341 	bool is_decrypted = false;
3342 	int msdu_len = 0;
3343 	int extra_space;
3344 	u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3345 
3346 	first_frag = skb_peek(&rx_tid->rx_frags);
3347 	last_frag = skb_peek_tail(&rx_tid->rx_frags);
3348 
3349 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3350 		flags = 0;
3351 		rx_desc = (struct hal_rx_desc *)skb->data;
3352 		hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3353 
3354 		enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc);
3355 		if (enctype != HAL_ENCRYPT_TYPE_OPEN) {
3356 			rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc);
3357 			is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention);
3358 		}
3359 
3360 		if (is_decrypted) {
3361 			if (skb != first_frag)
3362 				flags |=  RX_FLAG_IV_STRIPPED;
3363 			if (skb != last_frag)
3364 				flags |= RX_FLAG_ICV_STRIPPED |
3365 					 RX_FLAG_MIC_STRIPPED;
3366 		}
3367 
3368 		/* RX fragments are always raw packets */
3369 		if (skb != last_frag)
3370 			skb_trim(skb, skb->len - FCS_LEN);
3371 		ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags);
3372 
3373 		if (skb != first_frag)
3374 			skb_pull(skb, hal_rx_desc_sz +
3375 				      ieee80211_hdrlen(hdr->frame_control));
3376 		msdu_len += skb->len;
3377 	}
3378 
3379 	extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag));
3380 	if (extra_space > 0 &&
3381 	    (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0))
3382 		return -ENOMEM;
3383 
3384 	__skb_unlink(first_frag, &rx_tid->rx_frags);
3385 	while ((skb = __skb_dequeue(&rx_tid->rx_frags))) {
3386 		skb_put_data(first_frag, skb->data, skb->len);
3387 		dev_kfree_skb_any(skb);
3388 	}
3389 
3390 	hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz);
3391 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS);
3392 	ATH11K_SKB_RXCB(first_frag)->is_frag = 1;
3393 
3394 	if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag))
3395 		first_frag = NULL;
3396 
3397 	*defrag_skb = first_frag;
3398 	return 0;
3399 }
3400 
3401 static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid,
3402 					      struct sk_buff *defrag_skb)
3403 {
3404 	struct ath11k_base *ab = ar->ab;
3405 	struct ath11k_pdev_dp *dp = &ar->dp;
3406 	struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring;
3407 	struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data;
3408 	struct hal_reo_entrance_ring *reo_ent_ring;
3409 	struct hal_reo_dest_ring *reo_dest_ring;
3410 	struct dp_link_desc_bank *link_desc_banks;
3411 	struct hal_rx_msdu_link *msdu_link;
3412 	struct hal_rx_msdu_details *msdu0;
3413 	struct hal_srng *srng;
3414 	dma_addr_t paddr;
3415 	u32 desc_bank, msdu_info, mpdu_info;
3416 	u32 dst_idx, cookie, hal_rx_desc_sz;
3417 	int ret, buf_id;
3418 
3419 	hal_rx_desc_sz = ab->hw_params.hal_desc_sz;
3420 	link_desc_banks = ab->dp.link_desc_banks;
3421 	reo_dest_ring = rx_tid->dst_ring_desc;
3422 
3423 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3424 	msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr +
3425 			(paddr - link_desc_banks[desc_bank].paddr));
3426 	msdu0 = &msdu_link->msdu_link[0];
3427 	dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0);
3428 	memset(msdu0, 0, sizeof(*msdu0));
3429 
3430 	msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) |
3431 		    FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) |
3432 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) |
3433 		    FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH,
3434 			       defrag_skb->len - hal_rx_desc_sz) |
3435 		    FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) |
3436 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) |
3437 		    FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1);
3438 	msdu0->rx_msdu_info.info0 = msdu_info;
3439 
3440 	/* change msdu len in hal rx desc */
3441 	ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz);
3442 
3443 	paddr = dma_map_single(ab->dev, defrag_skb->data,
3444 			       defrag_skb->len + skb_tailroom(defrag_skb),
3445 			       DMA_TO_DEVICE);
3446 	if (dma_mapping_error(ab->dev, paddr))
3447 		return -ENOMEM;
3448 
3449 	spin_lock_bh(&rx_refill_ring->idr_lock);
3450 	buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0,
3451 			   rx_refill_ring->bufs_max * 3, GFP_ATOMIC);
3452 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3453 	if (buf_id < 0) {
3454 		ret = -ENOMEM;
3455 		goto err_unmap_dma;
3456 	}
3457 
3458 	ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr;
3459 	cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) |
3460 		 FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id);
3461 
3462 	ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie,
3463 					ab->hw_params.hal_params->rx_buf_rbm);
3464 
3465 	/* Fill mpdu details into reo entrace ring */
3466 	srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id];
3467 
3468 	spin_lock_bh(&srng->lock);
3469 	ath11k_hal_srng_access_begin(ab, srng);
3470 
3471 	reo_ent_ring = (struct hal_reo_entrance_ring *)
3472 			ath11k_hal_srng_src_get_next_entry(ab, srng);
3473 	if (!reo_ent_ring) {
3474 		ath11k_hal_srng_access_end(ab, srng);
3475 		spin_unlock_bh(&srng->lock);
3476 		ret = -ENOSPC;
3477 		goto err_free_idr;
3478 	}
3479 	memset(reo_ent_ring, 0, sizeof(*reo_ent_ring));
3480 
3481 	ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank);
3482 	ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank,
3483 					HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST);
3484 
3485 	mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) |
3486 		    FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) |
3487 		    FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) |
3488 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) |
3489 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) |
3490 		    FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) |
3491 		    FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1);
3492 
3493 	reo_ent_ring->rx_mpdu_info.info0 = mpdu_info;
3494 	reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data;
3495 	reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo;
3496 	reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI,
3497 					 FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI,
3498 						   reo_dest_ring->info0)) |
3499 			      FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx);
3500 	ath11k_hal_srng_access_end(ab, srng);
3501 	spin_unlock_bh(&srng->lock);
3502 
3503 	return 0;
3504 
3505 err_free_idr:
3506 	spin_lock_bh(&rx_refill_ring->idr_lock);
3507 	idr_remove(&rx_refill_ring->bufs_idr, buf_id);
3508 	spin_unlock_bh(&rx_refill_ring->idr_lock);
3509 err_unmap_dma:
3510 	dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb),
3511 			 DMA_TO_DEVICE);
3512 	return ret;
3513 }
3514 
3515 static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar,
3516 				    struct sk_buff *a, struct sk_buff *b)
3517 {
3518 	int frag1, frag2;
3519 
3520 	frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a);
3521 	frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b);
3522 
3523 	return frag1 - frag2;
3524 }
3525 
3526 static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar,
3527 				      struct sk_buff_head *frag_list,
3528 				      struct sk_buff *cur_frag)
3529 {
3530 	struct sk_buff *skb;
3531 	int cmp;
3532 
3533 	skb_queue_walk(frag_list, skb) {
3534 		cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag);
3535 		if (cmp < 0)
3536 			continue;
3537 		__skb_queue_before(frag_list, skb, cur_frag);
3538 		return;
3539 	}
3540 	__skb_queue_tail(frag_list, cur_frag);
3541 }
3542 
3543 static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb)
3544 {
3545 	struct ieee80211_hdr *hdr;
3546 	u64 pn = 0;
3547 	u8 *ehdr;
3548 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3549 
3550 	hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz);
3551 	ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control);
3552 
3553 	pn = ehdr[0];
3554 	pn |= (u64)ehdr[1] << 8;
3555 	pn |= (u64)ehdr[4] << 16;
3556 	pn |= (u64)ehdr[5] << 24;
3557 	pn |= (u64)ehdr[6] << 32;
3558 	pn |= (u64)ehdr[7] << 40;
3559 
3560 	return pn;
3561 }
3562 
3563 static bool
3564 ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid)
3565 {
3566 	enum hal_encrypt_type encrypt_type;
3567 	struct sk_buff *first_frag, *skb;
3568 	struct hal_rx_desc *desc;
3569 	u64 last_pn;
3570 	u64 cur_pn;
3571 
3572 	first_frag = skb_peek(&rx_tid->rx_frags);
3573 	desc = (struct hal_rx_desc *)first_frag->data;
3574 
3575 	encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc);
3576 	if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 &&
3577 	    encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 &&
3578 	    encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 &&
3579 	    encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256)
3580 		return true;
3581 
3582 	last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag);
3583 	skb_queue_walk(&rx_tid->rx_frags, skb) {
3584 		if (skb == first_frag)
3585 			continue;
3586 
3587 		cur_pn = ath11k_dp_rx_h_get_pn(ar, skb);
3588 		if (cur_pn != last_pn + 1)
3589 			return false;
3590 		last_pn = cur_pn;
3591 	}
3592 	return true;
3593 }
3594 
3595 static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar,
3596 				    struct sk_buff *msdu,
3597 				    u32 *ring_desc)
3598 {
3599 	struct ath11k_base *ab = ar->ab;
3600 	struct hal_rx_desc *rx_desc;
3601 	struct ath11k_peer *peer;
3602 	struct dp_rx_tid *rx_tid;
3603 	struct sk_buff *defrag_skb = NULL;
3604 	u32 peer_id;
3605 	u16 seqno, frag_no;
3606 	u8 tid;
3607 	int ret = 0;
3608 	bool more_frags;
3609 	bool is_mcbc;
3610 
3611 	rx_desc = (struct hal_rx_desc *)msdu->data;
3612 	peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc);
3613 	tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc);
3614 	seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc);
3615 	frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu);
3616 	more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu);
3617 	is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc);
3618 
3619 	/* Multicast/Broadcast fragments are not expected */
3620 	if (is_mcbc)
3621 		return -EINVAL;
3622 
3623 	if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) ||
3624 	    !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) ||
3625 	    tid > IEEE80211_NUM_TIDS)
3626 		return -EINVAL;
3627 
3628 	/* received unfragmented packet in reo
3629 	 * exception ring, this shouldn't happen
3630 	 * as these packets typically come from
3631 	 * reo2sw srngs.
3632 	 */
3633 	if (WARN_ON_ONCE(!frag_no && !more_frags))
3634 		return -EINVAL;
3635 
3636 	spin_lock_bh(&ab->base_lock);
3637 	peer = ath11k_peer_find_by_id(ab, peer_id);
3638 	if (!peer) {
3639 		ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n",
3640 			    peer_id);
3641 		ret = -ENOENT;
3642 		goto out_unlock;
3643 	}
3644 	rx_tid = &peer->rx_tid[tid];
3645 
3646 	if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) ||
3647 	    skb_queue_empty(&rx_tid->rx_frags)) {
3648 		/* Flush stored fragments and start a new sequence */
3649 		ath11k_dp_rx_frags_cleanup(rx_tid, true);
3650 		rx_tid->cur_sn = seqno;
3651 	}
3652 
3653 	if (rx_tid->rx_frag_bitmap & BIT(frag_no)) {
3654 		/* Fragment already present */
3655 		ret = -EINVAL;
3656 		goto out_unlock;
3657 	}
3658 
3659 	if (frag_no > __fls(rx_tid->rx_frag_bitmap))
3660 		__skb_queue_tail(&rx_tid->rx_frags, msdu);
3661 	else
3662 		ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu);
3663 
3664 	rx_tid->rx_frag_bitmap |= BIT(frag_no);
3665 	if (!more_frags)
3666 		rx_tid->last_frag_no = frag_no;
3667 
3668 	if (frag_no == 0) {
3669 		rx_tid->dst_ring_desc = kmemdup(ring_desc,
3670 						sizeof(*rx_tid->dst_ring_desc),
3671 						GFP_ATOMIC);
3672 		if (!rx_tid->dst_ring_desc) {
3673 			ret = -ENOMEM;
3674 			goto out_unlock;
3675 		}
3676 	} else {
3677 		ath11k_dp_rx_link_desc_return(ab, ring_desc,
3678 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3679 	}
3680 
3681 	if (!rx_tid->last_frag_no ||
3682 	    rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) {
3683 		mod_timer(&rx_tid->frag_timer, jiffies +
3684 					       ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS);
3685 		goto out_unlock;
3686 	}
3687 
3688 	spin_unlock_bh(&ab->base_lock);
3689 	del_timer_sync(&rx_tid->frag_timer);
3690 	spin_lock_bh(&ab->base_lock);
3691 
3692 	peer = ath11k_peer_find_by_id(ab, peer_id);
3693 	if (!peer)
3694 		goto err_frags_cleanup;
3695 
3696 	if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid))
3697 		goto err_frags_cleanup;
3698 
3699 	if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb))
3700 		goto err_frags_cleanup;
3701 
3702 	if (!defrag_skb)
3703 		goto err_frags_cleanup;
3704 
3705 	if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb))
3706 		goto err_frags_cleanup;
3707 
3708 	ath11k_dp_rx_frags_cleanup(rx_tid, false);
3709 	goto out_unlock;
3710 
3711 err_frags_cleanup:
3712 	dev_kfree_skb_any(defrag_skb);
3713 	ath11k_dp_rx_frags_cleanup(rx_tid, true);
3714 out_unlock:
3715 	spin_unlock_bh(&ab->base_lock);
3716 	return ret;
3717 }
3718 
3719 static int
3720 ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop)
3721 {
3722 	struct ath11k_pdev_dp *dp = &ar->dp;
3723 	struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring;
3724 	struct sk_buff *msdu;
3725 	struct ath11k_skb_rxcb *rxcb;
3726 	struct hal_rx_desc *rx_desc;
3727 	u8 *hdr_status;
3728 	u16 msdu_len;
3729 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3730 
3731 	spin_lock_bh(&rx_ring->idr_lock);
3732 	msdu = idr_find(&rx_ring->bufs_idr, buf_id);
3733 	if (!msdu) {
3734 		ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n",
3735 			    buf_id);
3736 		spin_unlock_bh(&rx_ring->idr_lock);
3737 		return -EINVAL;
3738 	}
3739 
3740 	idr_remove(&rx_ring->bufs_idr, buf_id);
3741 	spin_unlock_bh(&rx_ring->idr_lock);
3742 
3743 	rxcb = ATH11K_SKB_RXCB(msdu);
3744 	dma_unmap_single(ar->ab->dev, rxcb->paddr,
3745 			 msdu->len + skb_tailroom(msdu),
3746 			 DMA_FROM_DEVICE);
3747 
3748 	if (drop) {
3749 		dev_kfree_skb_any(msdu);
3750 		return 0;
3751 	}
3752 
3753 	rcu_read_lock();
3754 	if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) {
3755 		dev_kfree_skb_any(msdu);
3756 		goto exit;
3757 	}
3758 
3759 	if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
3760 		dev_kfree_skb_any(msdu);
3761 		goto exit;
3762 	}
3763 
3764 	rx_desc = (struct hal_rx_desc *)msdu->data;
3765 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc);
3766 	if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) {
3767 		hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc);
3768 		ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len);
3769 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status,
3770 				sizeof(struct ieee80211_hdr));
3771 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc,
3772 				sizeof(struct hal_rx_desc));
3773 		dev_kfree_skb_any(msdu);
3774 		goto exit;
3775 	}
3776 
3777 	skb_put(msdu, hal_rx_desc_sz + msdu_len);
3778 
3779 	if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) {
3780 		dev_kfree_skb_any(msdu);
3781 		ath11k_dp_rx_link_desc_return(ar->ab, ring_desc,
3782 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3783 	}
3784 exit:
3785 	rcu_read_unlock();
3786 	return 0;
3787 }
3788 
3789 int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi,
3790 			     int budget)
3791 {
3792 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
3793 	struct dp_link_desc_bank *link_desc_banks;
3794 	enum hal_rx_buf_return_buf_manager rbm;
3795 	int tot_n_bufs_reaped, quota, ret, i;
3796 	int n_bufs_reaped[MAX_RADIOS] = {0};
3797 	struct dp_rxdma_ring *rx_ring;
3798 	struct dp_srng *reo_except;
3799 	u32 desc_bank, num_msdus;
3800 	struct hal_srng *srng;
3801 	struct ath11k_dp *dp;
3802 	void *link_desc_va;
3803 	int buf_id, mac_id;
3804 	struct ath11k *ar;
3805 	dma_addr_t paddr;
3806 	u32 *desc;
3807 	bool is_frag;
3808 	u8 drop = 0;
3809 
3810 	tot_n_bufs_reaped = 0;
3811 	quota = budget;
3812 
3813 	dp = &ab->dp;
3814 	reo_except = &dp->reo_except_ring;
3815 	link_desc_banks = dp->link_desc_banks;
3816 
3817 	srng = &ab->hal.srng_list[reo_except->ring_id];
3818 
3819 	spin_lock_bh(&srng->lock);
3820 
3821 	ath11k_hal_srng_access_begin(ab, srng);
3822 
3823 	while (budget &&
3824 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
3825 		struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc;
3826 
3827 		ab->soc_stats.err_ring_pkts++;
3828 		ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr,
3829 						    &desc_bank);
3830 		if (ret) {
3831 			ath11k_warn(ab, "failed to parse error reo desc %d\n",
3832 				    ret);
3833 			continue;
3834 		}
3835 		link_desc_va = link_desc_banks[desc_bank].vaddr +
3836 			       (paddr - link_desc_banks[desc_bank].paddr);
3837 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies,
3838 						 &rbm);
3839 		if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST &&
3840 		    rbm != HAL_RX_BUF_RBM_SW3_BM) {
3841 			ab->soc_stats.invalid_rbm++;
3842 			ath11k_warn(ab, "invalid return buffer manager %d\n", rbm);
3843 			ath11k_dp_rx_link_desc_return(ab, desc,
3844 						      HAL_WBM_REL_BM_ACT_REL_MSDU);
3845 			continue;
3846 		}
3847 
3848 		is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG);
3849 
3850 		/* Process only rx fragments with one msdu per link desc below, and drop
3851 		 * msdu's indicated due to error reasons.
3852 		 */
3853 		if (!is_frag || num_msdus > 1) {
3854 			drop = 1;
3855 			/* Return the link desc back to wbm idle list */
3856 			ath11k_dp_rx_link_desc_return(ab, desc,
3857 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
3858 		}
3859 
3860 		for (i = 0; i < num_msdus; i++) {
3861 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
3862 					   msdu_cookies[i]);
3863 
3864 			mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID,
3865 					   msdu_cookies[i]);
3866 
3867 			ar = ab->pdevs[mac_id].ar;
3868 
3869 			if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) {
3870 				n_bufs_reaped[mac_id]++;
3871 				tot_n_bufs_reaped++;
3872 			}
3873 		}
3874 
3875 		if (tot_n_bufs_reaped >= quota) {
3876 			tot_n_bufs_reaped = quota;
3877 			goto exit;
3878 		}
3879 
3880 		budget = quota - tot_n_bufs_reaped;
3881 	}
3882 
3883 exit:
3884 	ath11k_hal_srng_access_end(ab, srng);
3885 
3886 	spin_unlock_bh(&srng->lock);
3887 
3888 	for (i = 0; i <  ab->num_radios; i++) {
3889 		if (!n_bufs_reaped[i])
3890 			continue;
3891 
3892 		ar = ab->pdevs[i].ar;
3893 		rx_ring = &ar->dp.rx_refill_buf_ring;
3894 
3895 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i],
3896 					   ab->hw_params.hal_params->rx_buf_rbm);
3897 	}
3898 
3899 	return tot_n_bufs_reaped;
3900 }
3901 
3902 static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar,
3903 					     int msdu_len,
3904 					     struct sk_buff_head *msdu_list)
3905 {
3906 	struct sk_buff *skb, *tmp;
3907 	struct ath11k_skb_rxcb *rxcb;
3908 	int n_buffs;
3909 
3910 	n_buffs = DIV_ROUND_UP(msdu_len,
3911 			       (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz));
3912 
3913 	skb_queue_walk_safe(msdu_list, skb, tmp) {
3914 		rxcb = ATH11K_SKB_RXCB(skb);
3915 		if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO &&
3916 		    rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) {
3917 			if (!n_buffs)
3918 				break;
3919 			__skb_unlink(skb, msdu_list);
3920 			dev_kfree_skb_any(skb);
3921 			n_buffs--;
3922 		}
3923 	}
3924 }
3925 
3926 static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu,
3927 				      struct ieee80211_rx_status *status,
3928 				      struct sk_buff_head *msdu_list)
3929 {
3930 	u16 msdu_len;
3931 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
3932 	struct rx_attention *rx_attention;
3933 	u8 l3pad_bytes;
3934 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3935 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
3936 
3937 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
3938 
3939 	if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) {
3940 		/* First buffer will be freed by the caller, so deduct it's length */
3941 		msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz);
3942 		ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list);
3943 		return -EINVAL;
3944 	}
3945 
3946 	rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc);
3947 	if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) {
3948 		ath11k_warn(ar->ab,
3949 			    "msdu_done bit not set in null_q_des processing\n");
3950 		__skb_queue_purge(msdu_list);
3951 		return -EIO;
3952 	}
3953 
3954 	/* Handle NULL queue descriptor violations arising out a missing
3955 	 * REO queue for a given peer or a given TID. This typically
3956 	 * may happen if a packet is received on a QOS enabled TID before the
3957 	 * ADDBA negotiation for that TID, when the TID queue is setup. Or
3958 	 * it may also happen for MC/BC frames if they are not routed to the
3959 	 * non-QOS TID queue, in the absence of any other default TID queue.
3960 	 * This error can show up both in a REO destination or WBM release ring.
3961 	 */
3962 
3963 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
3964 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
3965 
3966 	if (rxcb->is_frag) {
3967 		skb_pull(msdu, hal_rx_desc_sz);
3968 	} else {
3969 		l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
3970 
3971 		if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE)
3972 			return -EINVAL;
3973 
3974 		skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
3975 		skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
3976 	}
3977 	ath11k_dp_rx_h_ppdu(ar, desc, status);
3978 
3979 	ath11k_dp_rx_h_mpdu(ar, msdu, desc, status);
3980 
3981 	rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc);
3982 
3983 	/* Please note that caller will having the access to msdu and completing
3984 	 * rx with mac80211. Need not worry about cleaning up amsdu_list.
3985 	 */
3986 
3987 	return 0;
3988 }
3989 
3990 static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu,
3991 				   struct ieee80211_rx_status *status,
3992 				   struct sk_buff_head *msdu_list)
3993 {
3994 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
3995 	bool drop = false;
3996 
3997 	ar->ab->soc_stats.reo_error[rxcb->err_code]++;
3998 
3999 	switch (rxcb->err_code) {
4000 	case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO:
4001 		if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list))
4002 			drop = true;
4003 		break;
4004 	case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED:
4005 		/* TODO: Do not drop PN failed packets in the driver;
4006 		 * instead, it is good to drop such packets in mac80211
4007 		 * after incrementing the replay counters.
4008 		 */
4009 		fallthrough;
4010 	default:
4011 		/* TODO: Review other errors and process them to mac80211
4012 		 * as appropriate.
4013 		 */
4014 		drop = true;
4015 		break;
4016 	}
4017 
4018 	return drop;
4019 }
4020 
4021 static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu,
4022 					struct ieee80211_rx_status *status)
4023 {
4024 	u16 msdu_len;
4025 	struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data;
4026 	u8 l3pad_bytes;
4027 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4028 	u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz;
4029 
4030 	rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc);
4031 	rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc);
4032 
4033 	l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc);
4034 	msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc);
4035 	skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len);
4036 	skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes);
4037 
4038 	ath11k_dp_rx_h_ppdu(ar, desc, status);
4039 
4040 	status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR |
4041 			 RX_FLAG_DECRYPTED);
4042 
4043 	ath11k_dp_rx_h_undecap(ar, msdu, desc,
4044 			       HAL_ENCRYPT_TYPE_TKIP_MIC, status, false);
4045 }
4046 
4047 static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar,  struct sk_buff *msdu,
4048 				     struct ieee80211_rx_status *status)
4049 {
4050 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4051 	bool drop = false;
4052 
4053 	ar->ab->soc_stats.rxdma_error[rxcb->err_code]++;
4054 
4055 	switch (rxcb->err_code) {
4056 	case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR:
4057 		ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status);
4058 		break;
4059 	default:
4060 		/* TODO: Review other rxdma error code to check if anything is
4061 		 * worth reporting to mac80211
4062 		 */
4063 		drop = true;
4064 		break;
4065 	}
4066 
4067 	return drop;
4068 }
4069 
4070 static void ath11k_dp_rx_wbm_err(struct ath11k *ar,
4071 				 struct napi_struct *napi,
4072 				 struct sk_buff *msdu,
4073 				 struct sk_buff_head *msdu_list)
4074 {
4075 	struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu);
4076 	struct ieee80211_rx_status rxs = {0};
4077 	bool drop = true;
4078 
4079 	switch (rxcb->err_rel_src) {
4080 	case HAL_WBM_REL_SRC_MODULE_REO:
4081 		drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list);
4082 		break;
4083 	case HAL_WBM_REL_SRC_MODULE_RXDMA:
4084 		drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs);
4085 		break;
4086 	default:
4087 		/* msdu will get freed */
4088 		break;
4089 	}
4090 
4091 	if (drop) {
4092 		dev_kfree_skb_any(msdu);
4093 		return;
4094 	}
4095 
4096 	ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs);
4097 }
4098 
4099 int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab,
4100 				 struct napi_struct *napi, int budget)
4101 {
4102 	struct ath11k *ar;
4103 	struct ath11k_dp *dp = &ab->dp;
4104 	struct dp_rxdma_ring *rx_ring;
4105 	struct hal_rx_wbm_rel_info err_info;
4106 	struct hal_srng *srng;
4107 	struct sk_buff *msdu;
4108 	struct sk_buff_head msdu_list[MAX_RADIOS];
4109 	struct ath11k_skb_rxcb *rxcb;
4110 	u32 *rx_desc;
4111 	int buf_id, mac_id;
4112 	int num_buffs_reaped[MAX_RADIOS] = {0};
4113 	int total_num_buffs_reaped = 0;
4114 	int ret, i;
4115 
4116 	for (i = 0; i < ab->num_radios; i++)
4117 		__skb_queue_head_init(&msdu_list[i]);
4118 
4119 	srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id];
4120 
4121 	spin_lock_bh(&srng->lock);
4122 
4123 	ath11k_hal_srng_access_begin(ab, srng);
4124 
4125 	while (budget) {
4126 		rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng);
4127 		if (!rx_desc)
4128 			break;
4129 
4130 		ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info);
4131 		if (ret) {
4132 			ath11k_warn(ab,
4133 				    "failed to parse rx error in wbm_rel ring desc %d\n",
4134 				    ret);
4135 			continue;
4136 		}
4137 
4138 		buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie);
4139 		mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie);
4140 
4141 		ar = ab->pdevs[mac_id].ar;
4142 		rx_ring = &ar->dp.rx_refill_buf_ring;
4143 
4144 		spin_lock_bh(&rx_ring->idr_lock);
4145 		msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4146 		if (!msdu) {
4147 			ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n",
4148 				    buf_id, mac_id);
4149 			spin_unlock_bh(&rx_ring->idr_lock);
4150 			continue;
4151 		}
4152 
4153 		idr_remove(&rx_ring->bufs_idr, buf_id);
4154 		spin_unlock_bh(&rx_ring->idr_lock);
4155 
4156 		rxcb = ATH11K_SKB_RXCB(msdu);
4157 		dma_unmap_single(ab->dev, rxcb->paddr,
4158 				 msdu->len + skb_tailroom(msdu),
4159 				 DMA_FROM_DEVICE);
4160 
4161 		num_buffs_reaped[mac_id]++;
4162 		total_num_buffs_reaped++;
4163 		budget--;
4164 
4165 		if (err_info.push_reason !=
4166 		    HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4167 			dev_kfree_skb_any(msdu);
4168 			continue;
4169 		}
4170 
4171 		rxcb->err_rel_src = err_info.err_rel_src;
4172 		rxcb->err_code = err_info.err_code;
4173 		rxcb->rx_desc = (struct hal_rx_desc *)msdu->data;
4174 		__skb_queue_tail(&msdu_list[mac_id], msdu);
4175 	}
4176 
4177 	ath11k_hal_srng_access_end(ab, srng);
4178 
4179 	spin_unlock_bh(&srng->lock);
4180 
4181 	if (!total_num_buffs_reaped)
4182 		goto done;
4183 
4184 	for (i = 0; i <  ab->num_radios; i++) {
4185 		if (!num_buffs_reaped[i])
4186 			continue;
4187 
4188 		ar = ab->pdevs[i].ar;
4189 		rx_ring = &ar->dp.rx_refill_buf_ring;
4190 
4191 		ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i],
4192 					   ab->hw_params.hal_params->rx_buf_rbm);
4193 	}
4194 
4195 	rcu_read_lock();
4196 	for (i = 0; i <  ab->num_radios; i++) {
4197 		if (!rcu_dereference(ab->pdevs_active[i])) {
4198 			__skb_queue_purge(&msdu_list[i]);
4199 			continue;
4200 		}
4201 
4202 		ar = ab->pdevs[i].ar;
4203 
4204 		if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) {
4205 			__skb_queue_purge(&msdu_list[i]);
4206 			continue;
4207 		}
4208 
4209 		while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL)
4210 			ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]);
4211 	}
4212 	rcu_read_unlock();
4213 done:
4214 	return total_num_buffs_reaped;
4215 }
4216 
4217 int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget)
4218 {
4219 	struct ath11k *ar;
4220 	struct dp_srng *err_ring;
4221 	struct dp_rxdma_ring *rx_ring;
4222 	struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks;
4223 	struct hal_srng *srng;
4224 	u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC];
4225 	enum hal_rx_buf_return_buf_manager rbm;
4226 	enum hal_reo_entr_rxdma_ecode rxdma_err_code;
4227 	struct ath11k_skb_rxcb *rxcb;
4228 	struct sk_buff *skb;
4229 	struct hal_reo_entrance_ring *entr_ring;
4230 	void *desc;
4231 	int num_buf_freed = 0;
4232 	int quota = budget;
4233 	dma_addr_t paddr;
4234 	u32 desc_bank;
4235 	void *link_desc_va;
4236 	int num_msdus;
4237 	int i;
4238 	int buf_id;
4239 
4240 	ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
4241 	err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params,
4242 									  mac_id)];
4243 	rx_ring = &ar->dp.rx_refill_buf_ring;
4244 
4245 	srng = &ab->hal.srng_list[err_ring->ring_id];
4246 
4247 	spin_lock_bh(&srng->lock);
4248 
4249 	ath11k_hal_srng_access_begin(ab, srng);
4250 
4251 	while (quota-- &&
4252 	       (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4253 		ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank);
4254 
4255 		entr_ring = (struct hal_reo_entrance_ring *)desc;
4256 		rxdma_err_code =
4257 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4258 				  entr_ring->info1);
4259 		ab->soc_stats.rxdma_error[rxdma_err_code]++;
4260 
4261 		link_desc_va = link_desc_banks[desc_bank].vaddr +
4262 			       (paddr - link_desc_banks[desc_bank].paddr);
4263 		ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus,
4264 						 msdu_cookies, &rbm);
4265 
4266 		for (i = 0; i < num_msdus; i++) {
4267 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4268 					   msdu_cookies[i]);
4269 
4270 			spin_lock_bh(&rx_ring->idr_lock);
4271 			skb = idr_find(&rx_ring->bufs_idr, buf_id);
4272 			if (!skb) {
4273 				ath11k_warn(ab, "rxdma error with invalid buf_id %d\n",
4274 					    buf_id);
4275 				spin_unlock_bh(&rx_ring->idr_lock);
4276 				continue;
4277 			}
4278 
4279 			idr_remove(&rx_ring->bufs_idr, buf_id);
4280 			spin_unlock_bh(&rx_ring->idr_lock);
4281 
4282 			rxcb = ATH11K_SKB_RXCB(skb);
4283 			dma_unmap_single(ab->dev, rxcb->paddr,
4284 					 skb->len + skb_tailroom(skb),
4285 					 DMA_FROM_DEVICE);
4286 			dev_kfree_skb_any(skb);
4287 
4288 			num_buf_freed++;
4289 		}
4290 
4291 		ath11k_dp_rx_link_desc_return(ab, desc,
4292 					      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4293 	}
4294 
4295 	ath11k_hal_srng_access_end(ab, srng);
4296 
4297 	spin_unlock_bh(&srng->lock);
4298 
4299 	if (num_buf_freed)
4300 		ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed,
4301 					   ab->hw_params.hal_params->rx_buf_rbm);
4302 
4303 	return budget - quota;
4304 }
4305 
4306 void ath11k_dp_process_reo_status(struct ath11k_base *ab)
4307 {
4308 	struct ath11k_dp *dp = &ab->dp;
4309 	struct hal_srng *srng;
4310 	struct dp_reo_cmd *cmd, *tmp;
4311 	bool found = false;
4312 	u32 *reo_desc;
4313 	u16 tag;
4314 	struct hal_reo_status reo_status;
4315 
4316 	srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id];
4317 
4318 	memset(&reo_status, 0, sizeof(reo_status));
4319 
4320 	spin_lock_bh(&srng->lock);
4321 
4322 	ath11k_hal_srng_access_begin(ab, srng);
4323 
4324 	while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) {
4325 		tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc);
4326 
4327 		switch (tag) {
4328 		case HAL_REO_GET_QUEUE_STATS_STATUS:
4329 			ath11k_hal_reo_status_queue_stats(ab, reo_desc,
4330 							  &reo_status);
4331 			break;
4332 		case HAL_REO_FLUSH_QUEUE_STATUS:
4333 			ath11k_hal_reo_flush_queue_status(ab, reo_desc,
4334 							  &reo_status);
4335 			break;
4336 		case HAL_REO_FLUSH_CACHE_STATUS:
4337 			ath11k_hal_reo_flush_cache_status(ab, reo_desc,
4338 							  &reo_status);
4339 			break;
4340 		case HAL_REO_UNBLOCK_CACHE_STATUS:
4341 			ath11k_hal_reo_unblk_cache_status(ab, reo_desc,
4342 							  &reo_status);
4343 			break;
4344 		case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS:
4345 			ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc,
4346 								 &reo_status);
4347 			break;
4348 		case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS:
4349 			ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc,
4350 								  &reo_status);
4351 			break;
4352 		case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS:
4353 			ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc,
4354 								  &reo_status);
4355 			break;
4356 		default:
4357 			ath11k_warn(ab, "Unknown reo status type %d\n", tag);
4358 			continue;
4359 		}
4360 
4361 		spin_lock_bh(&dp->reo_cmd_lock);
4362 		list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) {
4363 			if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) {
4364 				found = true;
4365 				list_del(&cmd->list);
4366 				break;
4367 			}
4368 		}
4369 		spin_unlock_bh(&dp->reo_cmd_lock);
4370 
4371 		if (found) {
4372 			cmd->handler(dp, (void *)&cmd->data,
4373 				     reo_status.uniform_hdr.cmd_status);
4374 			kfree(cmd);
4375 		}
4376 
4377 		found = false;
4378 	}
4379 
4380 	ath11k_hal_srng_access_end(ab, srng);
4381 
4382 	spin_unlock_bh(&srng->lock);
4383 }
4384 
4385 void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id)
4386 {
4387 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4388 
4389 	ath11k_dp_rx_pdev_srng_free(ar);
4390 	ath11k_dp_rxdma_pdev_buf_free(ar);
4391 }
4392 
4393 int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id)
4394 {
4395 	struct ath11k *ar = ab->pdevs[mac_id].ar;
4396 	struct ath11k_pdev_dp *dp = &ar->dp;
4397 	u32 ring_id;
4398 	int i;
4399 	int ret;
4400 
4401 	ret = ath11k_dp_rx_pdev_srng_alloc(ar);
4402 	if (ret) {
4403 		ath11k_warn(ab, "failed to setup rx srngs\n");
4404 		return ret;
4405 	}
4406 
4407 	ret = ath11k_dp_rxdma_pdev_buf_setup(ar);
4408 	if (ret) {
4409 		ath11k_warn(ab, "failed to setup rxdma ring\n");
4410 		return ret;
4411 	}
4412 
4413 	ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id;
4414 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF);
4415 	if (ret) {
4416 		ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n",
4417 			    ret);
4418 		return ret;
4419 	}
4420 
4421 	if (ab->hw_params.rx_mac_buf_ring) {
4422 		for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4423 			ring_id = dp->rx_mac_buf_ring[i].ring_id;
4424 			ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4425 							  mac_id + i, HAL_RXDMA_BUF);
4426 			if (ret) {
4427 				ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n",
4428 					    i, ret);
4429 				return ret;
4430 			}
4431 		}
4432 	}
4433 
4434 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4435 		ring_id = dp->rxdma_err_dst_ring[i].ring_id;
4436 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4437 						  mac_id + i, HAL_RXDMA_DST);
4438 		if (ret) {
4439 			ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n",
4440 				    i, ret);
4441 			return ret;
4442 		}
4443 	}
4444 
4445 	if (!ab->hw_params.rxdma1_enable)
4446 		goto config_refill_ring;
4447 
4448 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
4449 	ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id,
4450 					  mac_id, HAL_RXDMA_MONITOR_BUF);
4451 	if (ret) {
4452 		ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n",
4453 			    ret);
4454 		return ret;
4455 	}
4456 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4457 					  dp->rxdma_mon_dst_ring.ring_id,
4458 					  mac_id, HAL_RXDMA_MONITOR_DST);
4459 	if (ret) {
4460 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4461 			    ret);
4462 		return ret;
4463 	}
4464 	ret = ath11k_dp_tx_htt_srng_setup(ab,
4465 					  dp->rxdma_mon_desc_ring.ring_id,
4466 					  mac_id, HAL_RXDMA_MONITOR_DESC);
4467 	if (ret) {
4468 		ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n",
4469 			    ret);
4470 		return ret;
4471 	}
4472 
4473 config_refill_ring:
4474 	for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
4475 		ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
4476 		ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i,
4477 						  HAL_RXDMA_MONITOR_STATUS);
4478 		if (ret) {
4479 			ath11k_warn(ab,
4480 				    "failed to configure mon_status_refill_ring%d %d\n",
4481 				    i, ret);
4482 			return ret;
4483 		}
4484 	}
4485 
4486 	return 0;
4487 }
4488 
4489 static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len)
4490 {
4491 	if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) {
4492 		*frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc);
4493 		*total_len -= *frag_len;
4494 	} else {
4495 		*frag_len = *total_len;
4496 		*total_len = 0;
4497 	}
4498 }
4499 
4500 static
4501 int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar,
4502 					  void *p_last_buf_addr_info,
4503 					  u8 mac_id)
4504 {
4505 	struct ath11k_pdev_dp *dp = &ar->dp;
4506 	struct dp_srng *dp_srng;
4507 	void *hal_srng;
4508 	void *src_srng_desc;
4509 	int ret = 0;
4510 
4511 	if (ar->ab->hw_params.rxdma1_enable) {
4512 		dp_srng = &dp->rxdma_mon_desc_ring;
4513 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4514 	} else {
4515 		dp_srng = &ar->ab->dp.wbm_desc_rel_ring;
4516 		hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id];
4517 	}
4518 
4519 	ath11k_hal_srng_access_begin(ar->ab, hal_srng);
4520 
4521 	src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng);
4522 
4523 	if (src_srng_desc) {
4524 		struct ath11k_buffer_addr *src_desc =
4525 				(struct ath11k_buffer_addr *)src_srng_desc;
4526 
4527 		*src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info);
4528 	} else {
4529 		ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4530 			   "Monitor Link Desc Ring %d Full", mac_id);
4531 		ret = -ENOMEM;
4532 	}
4533 
4534 	ath11k_hal_srng_access_end(ar->ab, hal_srng);
4535 	return ret;
4536 }
4537 
4538 static
4539 void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
4540 					 dma_addr_t *paddr, u32 *sw_cookie,
4541 					 u8 *rbm,
4542 					 void **pp_buf_addr_info)
4543 {
4544 	struct hal_rx_msdu_link *msdu_link =
4545 			(struct hal_rx_msdu_link *)rx_msdu_link_desc;
4546 	struct ath11k_buffer_addr *buf_addr_info;
4547 
4548 	buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info;
4549 
4550 	ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm);
4551 
4552 	*pp_buf_addr_info = (void *)buf_addr_info;
4553 }
4554 
4555 static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len)
4556 {
4557 	if (skb->len > len) {
4558 		skb_trim(skb, len);
4559 	} else {
4560 		if (skb_tailroom(skb) < len - skb->len) {
4561 			if ((pskb_expand_head(skb, 0,
4562 					      len - skb->len - skb_tailroom(skb),
4563 					      GFP_ATOMIC))) {
4564 				dev_kfree_skb_any(skb);
4565 				return -ENOMEM;
4566 			}
4567 		}
4568 		skb_put(skb, (len - skb->len));
4569 	}
4570 	return 0;
4571 }
4572 
4573 static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar,
4574 					void *msdu_link_desc,
4575 					struct hal_rx_msdu_list *msdu_list,
4576 					u16 *num_msdus)
4577 {
4578 	struct hal_rx_msdu_details *msdu_details = NULL;
4579 	struct rx_msdu_desc *msdu_desc_info = NULL;
4580 	struct hal_rx_msdu_link *msdu_link = NULL;
4581 	int i;
4582 	u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1);
4583 	u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1);
4584 	u8  tmp  = 0;
4585 
4586 	msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc;
4587 	msdu_details = &msdu_link->msdu_link[0];
4588 
4589 	for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
4590 		if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
4591 			      msdu_details[i].buf_addr_info.info0) == 0) {
4592 			msdu_desc_info = &msdu_details[i - 1].rx_msdu_info;
4593 			msdu_desc_info->info0 |= last;
4594 			;
4595 			break;
4596 		}
4597 		msdu_desc_info = &msdu_details[i].rx_msdu_info;
4598 
4599 		if (!i)
4600 			msdu_desc_info->info0 |= first;
4601 		else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
4602 			msdu_desc_info->info0 |= last;
4603 		msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0;
4604 		msdu_list->msdu_info[i].msdu_len =
4605 			 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0);
4606 		msdu_list->sw_cookie[i] =
4607 			FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
4608 				  msdu_details[i].buf_addr_info.info1);
4609 		tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
4610 				msdu_details[i].buf_addr_info.info1);
4611 		msdu_list->rbm[i] = tmp;
4612 	}
4613 	*num_msdus = i;
4614 }
4615 
4616 static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id,
4617 					u32 *rx_bufs_used)
4618 {
4619 	u32 ret = 0;
4620 
4621 	if ((*ppdu_id < msdu_ppdu_id) &&
4622 	    ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) {
4623 		*ppdu_id = msdu_ppdu_id;
4624 		ret = msdu_ppdu_id;
4625 	} else if ((*ppdu_id > msdu_ppdu_id) &&
4626 		((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) {
4627 		/* mon_dst is behind than mon_status
4628 		 * skip dst_ring and free it
4629 		 */
4630 		*rx_bufs_used += 1;
4631 		*ppdu_id = msdu_ppdu_id;
4632 		ret = msdu_ppdu_id;
4633 	}
4634 	return ret;
4635 }
4636 
4637 static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info,
4638 				      bool *is_frag, u32 *total_len,
4639 				      u32 *frag_len, u32 *msdu_cnt)
4640 {
4641 	if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) {
4642 		if (!*is_frag) {
4643 			*total_len = info->msdu_len;
4644 			*is_frag = true;
4645 		}
4646 		ath11k_dp_mon_set_frag_len(total_len,
4647 					   frag_len);
4648 	} else {
4649 		if (*is_frag) {
4650 			ath11k_dp_mon_set_frag_len(total_len,
4651 						   frag_len);
4652 		} else {
4653 			*frag_len = info->msdu_len;
4654 		}
4655 		*is_frag = false;
4656 		*msdu_cnt -= 1;
4657 	}
4658 }
4659 
4660 static u32
4661 ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id,
4662 			  void *ring_entry, struct sk_buff **head_msdu,
4663 			  struct sk_buff **tail_msdu, u32 *npackets,
4664 			  u32 *ppdu_id)
4665 {
4666 	struct ath11k_pdev_dp *dp = &ar->dp;
4667 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
4668 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
4669 	struct sk_buff *msdu = NULL, *last = NULL;
4670 	struct hal_rx_msdu_list msdu_list;
4671 	void *p_buf_addr_info, *p_last_buf_addr_info;
4672 	struct hal_rx_desc *rx_desc;
4673 	void *rx_msdu_link_desc;
4674 	dma_addr_t paddr;
4675 	u16 num_msdus = 0;
4676 	u32 rx_buf_size, rx_pkt_offset, sw_cookie;
4677 	u32 rx_bufs_used = 0, i = 0;
4678 	u32 msdu_ppdu_id = 0, msdu_cnt = 0;
4679 	u32 total_len = 0, frag_len = 0;
4680 	bool is_frag, is_first_msdu;
4681 	bool drop_mpdu = false;
4682 	struct ath11k_skb_rxcb *rxcb;
4683 	struct hal_reo_entrance_ring *ent_desc =
4684 			(struct hal_reo_entrance_ring *)ring_entry;
4685 	int buf_id;
4686 	u32 rx_link_buf_info[2];
4687 	u8 rbm;
4688 
4689 	if (!ar->ab->hw_params.rxdma1_enable)
4690 		rx_ring = &dp->rx_refill_buf_ring;
4691 
4692 	ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr,
4693 					    &sw_cookie,
4694 					    &p_last_buf_addr_info, &rbm,
4695 					    &msdu_cnt);
4696 
4697 	if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON,
4698 		      ent_desc->info1) ==
4699 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
4700 		u8 rxdma_err =
4701 			FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE,
4702 				  ent_desc->info1);
4703 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
4704 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
4705 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
4706 			drop_mpdu = true;
4707 			pmon->rx_mon_stats.dest_mpdu_drop++;
4708 		}
4709 	}
4710 
4711 	is_frag = false;
4712 	is_first_msdu = true;
4713 
4714 	do {
4715 		if (pmon->mon_last_linkdesc_paddr == paddr) {
4716 			pmon->rx_mon_stats.dup_mon_linkdesc_cnt++;
4717 			return rx_bufs_used;
4718 		}
4719 
4720 		if (ar->ab->hw_params.rxdma1_enable)
4721 			rx_msdu_link_desc =
4722 				(void *)pmon->link_desc_banks[sw_cookie].vaddr +
4723 				(paddr - pmon->link_desc_banks[sw_cookie].paddr);
4724 		else
4725 			rx_msdu_link_desc =
4726 				(void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr +
4727 				(paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr);
4728 
4729 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
4730 					    &num_msdus);
4731 
4732 		for (i = 0; i < num_msdus; i++) {
4733 			u32 l2_hdr_offset;
4734 
4735 			if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) {
4736 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4737 					   "i %d last_cookie %d is same\n",
4738 					   i, pmon->mon_last_buf_cookie);
4739 				drop_mpdu = true;
4740 				pmon->rx_mon_stats.dup_mon_buf_cnt++;
4741 				continue;
4742 			}
4743 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
4744 					   msdu_list.sw_cookie[i]);
4745 
4746 			spin_lock_bh(&rx_ring->idr_lock);
4747 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
4748 			spin_unlock_bh(&rx_ring->idr_lock);
4749 			if (!msdu) {
4750 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4751 					   "msdu_pop: invalid buf_id %d\n", buf_id);
4752 				break;
4753 			}
4754 			rxcb = ATH11K_SKB_RXCB(msdu);
4755 			if (!rxcb->unmapped) {
4756 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
4757 						 msdu->len +
4758 						 skb_tailroom(msdu),
4759 						 DMA_FROM_DEVICE);
4760 				rxcb->unmapped = 1;
4761 			}
4762 			if (drop_mpdu) {
4763 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4764 					   "i %d drop msdu %p *ppdu_id %x\n",
4765 					   i, msdu, *ppdu_id);
4766 				dev_kfree_skb_any(msdu);
4767 				msdu = NULL;
4768 				goto next_msdu;
4769 			}
4770 
4771 			rx_desc = (struct hal_rx_desc *)msdu->data;
4772 
4773 			rx_pkt_offset = sizeof(struct hal_rx_desc);
4774 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
4775 
4776 			if (is_first_msdu) {
4777 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
4778 					drop_mpdu = true;
4779 					dev_kfree_skb_any(msdu);
4780 					msdu = NULL;
4781 					pmon->mon_last_linkdesc_paddr = paddr;
4782 					goto next_msdu;
4783 				}
4784 
4785 				msdu_ppdu_id =
4786 					ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc);
4787 
4788 				if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id,
4789 								 ppdu_id,
4790 								 &rx_bufs_used)) {
4791 					if (rx_bufs_used) {
4792 						drop_mpdu = true;
4793 						dev_kfree_skb_any(msdu);
4794 						msdu = NULL;
4795 						goto next_msdu;
4796 					}
4797 					return rx_bufs_used;
4798 				}
4799 				pmon->mon_last_linkdesc_paddr = paddr;
4800 				is_first_msdu = false;
4801 			}
4802 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
4803 						  &is_frag, &total_len,
4804 						  &frag_len, &msdu_cnt);
4805 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
4806 
4807 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
4808 
4809 			if (!(*head_msdu))
4810 				*head_msdu = msdu;
4811 			else if (last)
4812 				last->next = msdu;
4813 
4814 			last = msdu;
4815 next_msdu:
4816 			pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i];
4817 			rx_bufs_used++;
4818 			spin_lock_bh(&rx_ring->idr_lock);
4819 			idr_remove(&rx_ring->bufs_idr, buf_id);
4820 			spin_unlock_bh(&rx_ring->idr_lock);
4821 		}
4822 
4823 		ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm);
4824 
4825 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr,
4826 						    &sw_cookie, &rbm,
4827 						    &p_buf_addr_info);
4828 
4829 		if (ar->ab->hw_params.rxdma1_enable) {
4830 			if (ath11k_dp_rx_monitor_link_desc_return(ar,
4831 								  p_last_buf_addr_info,
4832 								  dp->mac_id))
4833 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
4834 					   "dp_rx_monitor_link_desc_return failed");
4835 		} else {
4836 			ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info,
4837 						      HAL_WBM_REL_BM_ACT_PUT_IN_IDLE);
4838 		}
4839 
4840 		p_last_buf_addr_info = p_buf_addr_info;
4841 
4842 	} while (paddr && msdu_cnt);
4843 
4844 	if (last)
4845 		last->next = NULL;
4846 
4847 	*tail_msdu = msdu;
4848 
4849 	if (msdu_cnt == 0)
4850 		*npackets = 1;
4851 
4852 	return rx_bufs_used;
4853 }
4854 
4855 static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu)
4856 {
4857 	u32 rx_pkt_offset, l2_hdr_offset;
4858 
4859 	rx_pkt_offset = ar->ab->hw_params.hal_desc_sz;
4860 	l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab,
4861 						      (struct hal_rx_desc *)msdu->data);
4862 	skb_pull(msdu, rx_pkt_offset + l2_hdr_offset);
4863 }
4864 
4865 static struct sk_buff *
4866 ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar,
4867 			    u32 mac_id, struct sk_buff *head_msdu,
4868 			    struct sk_buff *last_msdu,
4869 			    struct ieee80211_rx_status *rxs, bool *fcs_err)
4870 {
4871 	struct ath11k_base *ab = ar->ab;
4872 	struct sk_buff *msdu, *prev_buf;
4873 	u32 wifi_hdr_len;
4874 	struct hal_rx_desc *rx_desc;
4875 	char *hdr_desc;
4876 	u8 *dest, decap_format;
4877 	struct ieee80211_hdr_3addr *wh;
4878 	struct rx_attention *rx_attention;
4879 	u32 err_bitmap;
4880 
4881 	if (!head_msdu)
4882 		goto err_merge_fail;
4883 
4884 	rx_desc = (struct hal_rx_desc *)head_msdu->data;
4885 	rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc);
4886 	err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention);
4887 
4888 	if (err_bitmap & DP_RX_MPDU_ERR_FCS)
4889 		*fcs_err = true;
4890 
4891 	if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention))
4892 		return NULL;
4893 
4894 	decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc);
4895 
4896 	ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs);
4897 
4898 	if (decap_format == DP_RX_DECAP_TYPE_RAW) {
4899 		ath11k_dp_rx_msdus_set_payload(ar, head_msdu);
4900 
4901 		prev_buf = head_msdu;
4902 		msdu = head_msdu->next;
4903 
4904 		while (msdu) {
4905 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4906 
4907 			prev_buf = msdu;
4908 			msdu = msdu->next;
4909 		}
4910 
4911 		prev_buf->next = NULL;
4912 
4913 		skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN);
4914 	} else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) {
4915 		__le16 qos_field;
4916 		u8 qos_pkt = 0;
4917 
4918 		rx_desc = (struct hal_rx_desc *)head_msdu->data;
4919 		hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4920 
4921 		/* Base size */
4922 		wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr);
4923 		wh = (struct ieee80211_hdr_3addr *)hdr_desc;
4924 
4925 		if (ieee80211_is_data_qos(wh->frame_control)) {
4926 			struct ieee80211_qos_hdr *qwh =
4927 					(struct ieee80211_qos_hdr *)hdr_desc;
4928 
4929 			qos_field = qwh->qos_ctrl;
4930 			qos_pkt = 1;
4931 		}
4932 		msdu = head_msdu;
4933 
4934 		while (msdu) {
4935 			rx_desc = (struct hal_rx_desc *)msdu->data;
4936 			hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc);
4937 
4938 			if (qos_pkt) {
4939 				dest = skb_push(msdu, sizeof(__le16));
4940 				if (!dest)
4941 					goto err_merge_fail;
4942 				memcpy(dest, hdr_desc, wifi_hdr_len);
4943 				memcpy(dest + wifi_hdr_len,
4944 				       (u8 *)&qos_field, sizeof(__le16));
4945 			}
4946 			ath11k_dp_rx_msdus_set_payload(ar, msdu);
4947 			prev_buf = msdu;
4948 			msdu = msdu->next;
4949 		}
4950 		dest = skb_put(prev_buf, HAL_RX_FCS_LEN);
4951 		if (!dest)
4952 			goto err_merge_fail;
4953 
4954 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4955 			   "mpdu_buf %pK mpdu_buf->len %u",
4956 			   prev_buf, prev_buf->len);
4957 	} else {
4958 		ath11k_dbg(ab, ATH11K_DBG_DATA,
4959 			   "decap format %d is not supported!\n",
4960 			   decap_format);
4961 		goto err_merge_fail;
4962 	}
4963 
4964 	return head_msdu;
4965 
4966 err_merge_fail:
4967 	return NULL;
4968 }
4969 
4970 static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id,
4971 				    struct sk_buff *head_msdu,
4972 				    struct sk_buff *tail_msdu,
4973 				    struct napi_struct *napi)
4974 {
4975 	struct ath11k_pdev_dp *dp = &ar->dp;
4976 	struct sk_buff *mon_skb, *skb_next, *header;
4977 	struct ieee80211_rx_status *rxs = &dp->rx_status;
4978 	bool fcs_err = false;
4979 
4980 	mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu,
4981 					      tail_msdu, rxs, &fcs_err);
4982 
4983 	if (!mon_skb)
4984 		goto mon_deliver_fail;
4985 
4986 	header = mon_skb;
4987 
4988 	rxs->flag = 0;
4989 
4990 	if (fcs_err)
4991 		rxs->flag = RX_FLAG_FAILED_FCS_CRC;
4992 
4993 	do {
4994 		skb_next = mon_skb->next;
4995 		if (!skb_next)
4996 			rxs->flag &= ~RX_FLAG_AMSDU_MORE;
4997 		else
4998 			rxs->flag |= RX_FLAG_AMSDU_MORE;
4999 
5000 		if (mon_skb == header) {
5001 			header = NULL;
5002 			rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN;
5003 		} else {
5004 			rxs->flag |= RX_FLAG_ALLOW_SAME_PN;
5005 		}
5006 		rxs->flag |= RX_FLAG_ONLY_MONITOR;
5007 
5008 		ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs);
5009 		mon_skb = skb_next;
5010 	} while (mon_skb);
5011 	rxs->flag = 0;
5012 
5013 	return 0;
5014 
5015 mon_deliver_fail:
5016 	mon_skb = head_msdu;
5017 	while (mon_skb) {
5018 		skb_next = mon_skb->next;
5019 		dev_kfree_skb_any(mon_skb);
5020 		mon_skb = skb_next;
5021 	}
5022 	return -EINVAL;
5023 }
5024 
5025 static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id,
5026 					  u32 quota, struct napi_struct *napi)
5027 {
5028 	struct ath11k_pdev_dp *dp = &ar->dp;
5029 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5030 	const struct ath11k_hw_hal_params *hal_params;
5031 	void *ring_entry;
5032 	void *mon_dst_srng;
5033 	u32 ppdu_id;
5034 	u32 rx_bufs_used;
5035 	u32 ring_id;
5036 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5037 	u32	 npackets = 0;
5038 
5039 	if (ar->ab->hw_params.rxdma1_enable)
5040 		ring_id = dp->rxdma_mon_dst_ring.ring_id;
5041 	else
5042 		ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id;
5043 
5044 	mon_dst_srng = &ar->ab->hal.srng_list[ring_id];
5045 
5046 	if (!mon_dst_srng) {
5047 		ath11k_warn(ar->ab,
5048 			    "HAL Monitor Destination Ring Init Failed -- %pK",
5049 			    mon_dst_srng);
5050 		return;
5051 	}
5052 
5053 	spin_lock_bh(&pmon->mon_lock);
5054 
5055 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5056 
5057 	ppdu_id = pmon->mon_ppdu_info.ppdu_id;
5058 	rx_bufs_used = 0;
5059 	rx_mon_stats = &pmon->rx_mon_stats;
5060 
5061 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5062 		struct sk_buff *head_msdu, *tail_msdu;
5063 
5064 		head_msdu = NULL;
5065 		tail_msdu = NULL;
5066 
5067 		rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry,
5068 							  &head_msdu,
5069 							  &tail_msdu,
5070 							  &npackets, &ppdu_id);
5071 
5072 		if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) {
5073 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5074 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5075 				   "dest_rx: new ppdu_id %x != status ppdu_id %x",
5076 				   ppdu_id, pmon->mon_ppdu_info.ppdu_id);
5077 			break;
5078 		}
5079 		if (head_msdu && tail_msdu) {
5080 			ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu,
5081 						 tail_msdu, napi);
5082 			rx_mon_stats->dest_mpdu_done++;
5083 		}
5084 
5085 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5086 								mon_dst_srng);
5087 	}
5088 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5089 
5090 	spin_unlock_bh(&pmon->mon_lock);
5091 
5092 	if (rx_bufs_used) {
5093 		rx_mon_stats->dest_ppdu_done++;
5094 		hal_params = ar->ab->hw_params.hal_params;
5095 
5096 		if (ar->ab->hw_params.rxdma1_enable)
5097 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5098 						   &dp->rxdma_mon_buf_ring,
5099 						   rx_bufs_used,
5100 						   hal_params->rx_buf_rbm);
5101 		else
5102 			ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5103 						   &dp->rx_refill_buf_ring,
5104 						   rx_bufs_used,
5105 						   hal_params->rx_buf_rbm);
5106 	}
5107 }
5108 
5109 static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar,
5110 						int mac_id, u32 quota,
5111 						struct napi_struct *napi)
5112 {
5113 	struct ath11k_pdev_dp *dp = &ar->dp;
5114 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5115 	struct hal_rx_mon_ppdu_info *ppdu_info;
5116 	struct sk_buff *status_skb;
5117 	u32 tlv_status = HAL_TLV_STATUS_BUF_DONE;
5118 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5119 
5120 	ppdu_info = &pmon->mon_ppdu_info;
5121 	rx_mon_stats = &pmon->rx_mon_stats;
5122 
5123 	if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START)
5124 		return;
5125 
5126 	while (!skb_queue_empty(&pmon->rx_status_q)) {
5127 		status_skb = skb_dequeue(&pmon->rx_status_q);
5128 
5129 		tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info,
5130 							    status_skb);
5131 		if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) {
5132 			rx_mon_stats->status_ppdu_done++;
5133 			pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE;
5134 			ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi);
5135 			pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5136 		}
5137 		dev_kfree_skb_any(status_skb);
5138 	}
5139 }
5140 
5141 static u32
5142 ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar,
5143 			       void *ring_entry, struct sk_buff **head_msdu,
5144 			       struct sk_buff **tail_msdu,
5145 			       struct hal_sw_mon_ring_entries *sw_mon_entries)
5146 {
5147 	struct ath11k_pdev_dp *dp = &ar->dp;
5148 	struct ath11k_mon_data *pmon = &dp->mon_data;
5149 	struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring;
5150 	struct sk_buff *msdu = NULL, *last = NULL;
5151 	struct hal_sw_monitor_ring *sw_desc = ring_entry;
5152 	struct hal_rx_msdu_list msdu_list;
5153 	struct hal_rx_desc *rx_desc;
5154 	struct ath11k_skb_rxcb *rxcb;
5155 	void *rx_msdu_link_desc;
5156 	void *p_buf_addr_info, *p_last_buf_addr_info;
5157 	int buf_id, i = 0;
5158 	u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset;
5159 	u32 rx_bufs_used = 0, msdu_cnt = 0;
5160 	u32 total_len = 0, frag_len = 0, sw_cookie;
5161 	u16 num_msdus = 0;
5162 	u8 rxdma_err, rbm;
5163 	bool is_frag, is_first_msdu;
5164 	bool drop_mpdu = false;
5165 
5166 	ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries);
5167 
5168 	sw_cookie = sw_mon_entries->mon_dst_sw_cookie;
5169 	sw_mon_entries->end_of_ppdu = false;
5170 	sw_mon_entries->drop_ppdu = false;
5171 	p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info;
5172 	msdu_cnt = sw_mon_entries->msdu_cnt;
5173 
5174 	sw_mon_entries->end_of_ppdu =
5175 		FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0);
5176 	if (sw_mon_entries->end_of_ppdu)
5177 		return rx_bufs_used;
5178 
5179 	if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON,
5180 		      sw_desc->info0) ==
5181 		      HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) {
5182 		rxdma_err =
5183 			FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE,
5184 				  sw_desc->info0);
5185 		if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR ||
5186 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR ||
5187 		    rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) {
5188 			pmon->rx_mon_stats.dest_mpdu_drop++;
5189 			drop_mpdu = true;
5190 		}
5191 	}
5192 
5193 	is_frag = false;
5194 	is_first_msdu = true;
5195 
5196 	do {
5197 		rx_msdu_link_desc =
5198 			(u8 *)pmon->link_desc_banks[sw_cookie].vaddr +
5199 			(sw_mon_entries->mon_dst_paddr -
5200 			 pmon->link_desc_banks[sw_cookie].paddr);
5201 
5202 		ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list,
5203 					    &num_msdus);
5204 
5205 		for (i = 0; i < num_msdus; i++) {
5206 			buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID,
5207 					   msdu_list.sw_cookie[i]);
5208 
5209 			spin_lock_bh(&rx_ring->idr_lock);
5210 			msdu = idr_find(&rx_ring->bufs_idr, buf_id);
5211 			if (!msdu) {
5212 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5213 					   "full mon msdu_pop: invalid buf_id %d\n",
5214 					    buf_id);
5215 				spin_unlock_bh(&rx_ring->idr_lock);
5216 				break;
5217 			}
5218 			idr_remove(&rx_ring->bufs_idr, buf_id);
5219 			spin_unlock_bh(&rx_ring->idr_lock);
5220 
5221 			rxcb = ATH11K_SKB_RXCB(msdu);
5222 			if (!rxcb->unmapped) {
5223 				dma_unmap_single(ar->ab->dev, rxcb->paddr,
5224 						 msdu->len +
5225 						 skb_tailroom(msdu),
5226 						 DMA_FROM_DEVICE);
5227 				rxcb->unmapped = 1;
5228 			}
5229 			if (drop_mpdu) {
5230 				ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5231 					   "full mon: i %d drop msdu %p *ppdu_id %x\n",
5232 					   i, msdu, sw_mon_entries->ppdu_id);
5233 				dev_kfree_skb_any(msdu);
5234 				msdu_cnt--;
5235 				goto next_msdu;
5236 			}
5237 
5238 			rx_desc = (struct hal_rx_desc *)msdu->data;
5239 
5240 			rx_pkt_offset = sizeof(struct hal_rx_desc);
5241 			l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc);
5242 
5243 			if (is_first_msdu) {
5244 				if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) {
5245 					drop_mpdu = true;
5246 					dev_kfree_skb_any(msdu);
5247 					msdu = NULL;
5248 					goto next_msdu;
5249 				}
5250 				is_first_msdu = false;
5251 			}
5252 
5253 			ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i],
5254 						  &is_frag, &total_len,
5255 						  &frag_len, &msdu_cnt);
5256 
5257 			rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len;
5258 
5259 			ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size);
5260 
5261 			if (!(*head_msdu))
5262 				*head_msdu = msdu;
5263 			else if (last)
5264 				last->next = msdu;
5265 
5266 			last = msdu;
5267 next_msdu:
5268 			rx_bufs_used++;
5269 		}
5270 
5271 		ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc,
5272 						    &sw_mon_entries->mon_dst_paddr,
5273 						    &sw_mon_entries->mon_dst_sw_cookie,
5274 						    &rbm,
5275 						    &p_buf_addr_info);
5276 
5277 		if (ath11k_dp_rx_monitor_link_desc_return(ar,
5278 							  p_last_buf_addr_info,
5279 							  dp->mac_id))
5280 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA,
5281 				   "full mon: dp_rx_monitor_link_desc_return failed\n");
5282 
5283 		p_last_buf_addr_info = p_buf_addr_info;
5284 
5285 	} while (sw_mon_entries->mon_dst_paddr && msdu_cnt);
5286 
5287 	if (last)
5288 		last->next = NULL;
5289 
5290 	*tail_msdu = msdu;
5291 
5292 	return rx_bufs_used;
5293 }
5294 
5295 static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp,
5296 					      struct dp_full_mon_mpdu *mon_mpdu,
5297 					      struct sk_buff *head,
5298 					      struct sk_buff *tail)
5299 {
5300 	mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC);
5301 	if (!mon_mpdu)
5302 		return -ENOMEM;
5303 
5304 	list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list);
5305 	mon_mpdu->head = head;
5306 	mon_mpdu->tail = tail;
5307 
5308 	return 0;
5309 }
5310 
5311 static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp,
5312 					    struct dp_full_mon_mpdu *mon_mpdu)
5313 {
5314 	struct dp_full_mon_mpdu *tmp;
5315 	struct sk_buff *tmp_msdu, *skb_next;
5316 
5317 	if (list_empty(&dp->dp_full_mon_mpdu_list))
5318 		return;
5319 
5320 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5321 		list_del(&mon_mpdu->list);
5322 
5323 		tmp_msdu = mon_mpdu->head;
5324 		while (tmp_msdu) {
5325 			skb_next = tmp_msdu->next;
5326 			dev_kfree_skb_any(tmp_msdu);
5327 			tmp_msdu = skb_next;
5328 		}
5329 
5330 		kfree(mon_mpdu);
5331 	}
5332 }
5333 
5334 static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar,
5335 					      int mac_id,
5336 					      struct ath11k_mon_data *pmon,
5337 					      struct napi_struct *napi)
5338 {
5339 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5340 	struct dp_full_mon_mpdu *tmp;
5341 	struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu;
5342 	struct sk_buff *head_msdu, *tail_msdu;
5343 	struct ath11k_base *ab = ar->ab;
5344 	struct ath11k_dp *dp = &ab->dp;
5345 	int ret;
5346 
5347 	rx_mon_stats = &pmon->rx_mon_stats;
5348 
5349 	list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) {
5350 		list_del(&mon_mpdu->list);
5351 		head_msdu = mon_mpdu->head;
5352 		tail_msdu = mon_mpdu->tail;
5353 		if (head_msdu && tail_msdu) {
5354 			ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu,
5355 						       tail_msdu, napi);
5356 			rx_mon_stats->dest_mpdu_done++;
5357 			ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n");
5358 		}
5359 		kfree(mon_mpdu);
5360 	}
5361 
5362 	return ret;
5363 }
5364 
5365 static int
5366 ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id,
5367 					  struct napi_struct *napi, int budget)
5368 {
5369 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5370 	struct ath11k_pdev_dp *dp = &ar->dp;
5371 	struct ath11k_mon_data *pmon = &dp->mon_data;
5372 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5373 	int quota = 0, work = 0, count;
5374 
5375 	sw_mon_entries = &pmon->sw_mon_entries;
5376 
5377 	while (pmon->hold_mon_dst_ring) {
5378 		quota = ath11k_dp_rx_process_mon_status(ab, mac_id,
5379 							napi, 1);
5380 		if (pmon->buf_state == DP_MON_STATUS_MATCH) {
5381 			count = sw_mon_entries->status_buf_count;
5382 			if (count > 1) {
5383 				quota += ath11k_dp_rx_process_mon_status(ab, mac_id,
5384 									 napi, count);
5385 			}
5386 
5387 			ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id,
5388 							   pmon, napi);
5389 			pmon->hold_mon_dst_ring = false;
5390 		} else if (!pmon->mon_status_paddr ||
5391 			   pmon->buf_state == DP_MON_STATUS_LEAD) {
5392 			sw_mon_entries->drop_ppdu = true;
5393 			pmon->hold_mon_dst_ring = false;
5394 		}
5395 
5396 		if (!quota)
5397 			break;
5398 
5399 		work += quota;
5400 	}
5401 
5402 	if (sw_mon_entries->drop_ppdu)
5403 		ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu);
5404 
5405 	return work;
5406 }
5407 
5408 static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id,
5409 					 struct napi_struct *napi, int budget)
5410 {
5411 	struct ath11k *ar = ab->pdevs[mac_id].ar;
5412 	struct ath11k_pdev_dp *dp = &ar->dp;
5413 	struct ath11k_mon_data *pmon = &dp->mon_data;
5414 	struct hal_sw_mon_ring_entries *sw_mon_entries;
5415 	struct ath11k_pdev_mon_stats *rx_mon_stats;
5416 	struct sk_buff *head_msdu, *tail_msdu;
5417 	void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id];
5418 	void *ring_entry;
5419 	u32 rx_bufs_used = 0, mpdu_rx_bufs_used;
5420 	int quota = 0, ret;
5421 	bool break_dst_ring = false;
5422 
5423 	spin_lock_bh(&pmon->mon_lock);
5424 
5425 	sw_mon_entries = &pmon->sw_mon_entries;
5426 	rx_mon_stats = &pmon->rx_mon_stats;
5427 
5428 	if (pmon->hold_mon_dst_ring) {
5429 		spin_unlock_bh(&pmon->mon_lock);
5430 		goto reap_status_ring;
5431 	}
5432 
5433 	ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng);
5434 	while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) {
5435 		head_msdu = NULL;
5436 		tail_msdu = NULL;
5437 
5438 		mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry,
5439 								   &head_msdu,
5440 								   &tail_msdu,
5441 								   sw_mon_entries);
5442 		rx_bufs_used += mpdu_rx_bufs_used;
5443 
5444 		if (!sw_mon_entries->end_of_ppdu) {
5445 			if (head_msdu) {
5446 				ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp,
5447 									 pmon->mon_mpdu,
5448 									 head_msdu,
5449 									 tail_msdu);
5450 				if (ret)
5451 					break_dst_ring = true;
5452 			}
5453 
5454 			goto next_entry;
5455 		} else {
5456 			if (!sw_mon_entries->ppdu_id &&
5457 			    !sw_mon_entries->mon_status_paddr) {
5458 				break_dst_ring = true;
5459 				goto next_entry;
5460 			}
5461 		}
5462 
5463 		rx_mon_stats->dest_ppdu_done++;
5464 		pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5465 		pmon->buf_state = DP_MON_STATUS_LAG;
5466 		pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr;
5467 		pmon->hold_mon_dst_ring = true;
5468 next_entry:
5469 		ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab,
5470 								mon_dst_srng);
5471 		if (break_dst_ring)
5472 			break;
5473 	}
5474 
5475 	ath11k_hal_srng_access_end(ar->ab, mon_dst_srng);
5476 	spin_unlock_bh(&pmon->mon_lock);
5477 
5478 	if (rx_bufs_used) {
5479 		ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id,
5480 					   &dp->rxdma_mon_buf_ring,
5481 					   rx_bufs_used,
5482 					   HAL_RX_BUF_RBM_SW3_BM);
5483 	}
5484 
5485 reap_status_ring:
5486 	quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id,
5487 							  napi, budget);
5488 
5489 	return quota;
5490 }
5491 
5492 static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id,
5493 				    struct napi_struct *napi, int budget)
5494 {
5495 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5496 	struct ath11k_pdev_dp *dp = &ar->dp;
5497 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5498 	int num_buffs_reaped = 0;
5499 
5500 	num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget,
5501 							     &pmon->rx_status_q);
5502 	if (num_buffs_reaped)
5503 		ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi);
5504 
5505 	return num_buffs_reaped;
5506 }
5507 
5508 int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id,
5509 				   struct napi_struct *napi, int budget)
5510 {
5511 	struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id);
5512 	int ret = 0;
5513 
5514 	if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) &&
5515 	    ab->hw_params.full_monitor_mode)
5516 		ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget);
5517 	else if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags))
5518 		ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget);
5519 	else
5520 		ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget);
5521 
5522 	return ret;
5523 }
5524 
5525 static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar)
5526 {
5527 	struct ath11k_pdev_dp *dp = &ar->dp;
5528 	struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data;
5529 
5530 	skb_queue_head_init(&pmon->rx_status_q);
5531 
5532 	pmon->mon_ppdu_status = DP_PPDU_STATUS_START;
5533 
5534 	memset(&pmon->rx_mon_stats, 0,
5535 	       sizeof(pmon->rx_mon_stats));
5536 	return 0;
5537 }
5538 
5539 int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar)
5540 {
5541 	struct ath11k_pdev_dp *dp = &ar->dp;
5542 	struct ath11k_mon_data *pmon = &dp->mon_data;
5543 	struct hal_srng *mon_desc_srng = NULL;
5544 	struct dp_srng *dp_srng;
5545 	int ret = 0;
5546 	u32 n_link_desc = 0;
5547 
5548 	ret = ath11k_dp_rx_pdev_mon_status_attach(ar);
5549 	if (ret) {
5550 		ath11k_warn(ar->ab, "pdev_mon_status_attach() failed");
5551 		return ret;
5552 	}
5553 
5554 	/* if rxdma1_enable is false, no need to setup
5555 	 * rxdma_mon_desc_ring.
5556 	 */
5557 	if (!ar->ab->hw_params.rxdma1_enable)
5558 		return 0;
5559 
5560 	dp_srng = &dp->rxdma_mon_desc_ring;
5561 	n_link_desc = dp_srng->size /
5562 		ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC);
5563 	mon_desc_srng =
5564 		&ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id];
5565 
5566 	ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks,
5567 					HAL_RXDMA_MONITOR_DESC, mon_desc_srng,
5568 					n_link_desc);
5569 	if (ret) {
5570 		ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed");
5571 		return ret;
5572 	}
5573 	pmon->mon_last_linkdesc_paddr = 0;
5574 	pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1;
5575 	spin_lock_init(&pmon->mon_lock);
5576 
5577 	return 0;
5578 }
5579 
5580 static int ath11k_dp_mon_link_free(struct ath11k *ar)
5581 {
5582 	struct ath11k_pdev_dp *dp = &ar->dp;
5583 	struct ath11k_mon_data *pmon = &dp->mon_data;
5584 
5585 	ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks,
5586 				    HAL_RXDMA_MONITOR_DESC,
5587 				    &dp->rxdma_mon_desc_ring);
5588 	return 0;
5589 }
5590 
5591 int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar)
5592 {
5593 	ath11k_dp_mon_link_free(ar);
5594 	return 0;
5595 }
5596 
5597 int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab)
5598 {
5599 	/* start reap timer */
5600 	mod_timer(&ab->mon_reap_timer,
5601 		  jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
5602 
5603 	return 0;
5604 }
5605 
5606 int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer)
5607 {
5608 	int ret;
5609 
5610 	if (stop_timer)
5611 		del_timer_sync(&ab->mon_reap_timer);
5612 
5613 	/* reap all the monitor related rings */
5614 	ret = ath11k_dp_purge_mon_ring(ab);
5615 	if (ret) {
5616 		ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret);
5617 		return ret;
5618 	}
5619 
5620 	return 0;
5621 }
5622