1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #include <linux/ieee80211.h> 7acc79d98SSriram R #include <linux/kernel.h> 8acc79d98SSriram R #include <linux/skbuff.h> 9243874c6SManikanta Pubbisetty #include <crypto/hash.h> 10d5c65159SKalle Valo #include "core.h" 11d5c65159SKalle Valo #include "debug.h" 12568f0603SKalle Valo #include "debugfs_htt_stats.h" 13568f0603SKalle Valo #include "debugfs_sta.h" 14d5c65159SKalle Valo #include "hal_desc.h" 15d5c65159SKalle Valo #include "hw.h" 16d5c65159SKalle Valo #include "dp_rx.h" 17d5c65159SKalle Valo #include "hal_rx.h" 18d5c65159SKalle Valo #include "dp_tx.h" 19d5c65159SKalle Valo #include "peer.h" 20d5c65159SKalle Valo 21243874c6SManikanta Pubbisetty #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22243874c6SManikanta Pubbisetty 235e76fe03SP Praneesh static inline 245e76fe03SP Praneesh u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc) 25d5c65159SKalle Valo { 26e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); 27d5c65159SKalle Valo } 28d5c65159SKalle Valo 295e76fe03SP Praneesh static inline 305e76fe03SP Praneesh enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab, 31e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 32d5c65159SKalle Valo { 33e678fbd4SKarthikeyan Periyasamy if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) 34d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN; 35d5c65159SKalle Valo 36e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); 37d5c65159SKalle Valo } 38d5c65159SKalle Valo 395e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab, 40e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 41d5c65159SKalle Valo { 42e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); 43243874c6SManikanta Pubbisetty } 44243874c6SManikanta Pubbisetty 455e76fe03SP Praneesh static inline 465e76fe03SP Praneesh u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab, 47e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 48acc79d98SSriram R { 49e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); 50acc79d98SSriram R } 51acc79d98SSriram R 525e76fe03SP Praneesh static inline 535e76fe03SP Praneesh bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab, 54e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 55243874c6SManikanta Pubbisetty { 56e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 57243874c6SManikanta Pubbisetty } 58243874c6SManikanta Pubbisetty 595e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab, 60e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 61243874c6SManikanta Pubbisetty { 62e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc); 63243874c6SManikanta Pubbisetty } 64243874c6SManikanta Pubbisetty 655e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab, 66e678fbd4SKarthikeyan Periyasamy struct sk_buff *skb) 67243874c6SManikanta Pubbisetty { 68243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 69243874c6SManikanta Pubbisetty 70e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 71243874c6SManikanta Pubbisetty return ieee80211_has_morefrags(hdr->frame_control); 72243874c6SManikanta Pubbisetty } 73243874c6SManikanta Pubbisetty 745e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab, 75e678fbd4SKarthikeyan Periyasamy struct sk_buff *skb) 76243874c6SManikanta Pubbisetty { 77243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 78243874c6SManikanta Pubbisetty 79e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 80243874c6SManikanta Pubbisetty return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 81243874c6SManikanta Pubbisetty } 82243874c6SManikanta Pubbisetty 835e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab, 84e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 85243874c6SManikanta Pubbisetty { 86e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc); 87d5c65159SKalle Valo } 88d5c65159SKalle Valo 895e76fe03SP Praneesh static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab, 90e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 91e678fbd4SKarthikeyan Periyasamy { 92e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_attention(desc); 93e678fbd4SKarthikeyan Periyasamy } 94e678fbd4SKarthikeyan Periyasamy 955e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn) 96d5c65159SKalle Valo { 97d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 98e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info2)); 99d5c65159SKalle Valo } 100d5c65159SKalle Valo 1015e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn) 102d5c65159SKalle Valo { 103d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 104e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 105d5c65159SKalle Valo } 106d5c65159SKalle Valo 1075e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn) 108d5c65159SKalle Valo { 109d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 110e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 111d5c65159SKalle Valo } 112d5c65159SKalle Valo 1135e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn) 114d5c65159SKalle Valo { 115d5c65159SKalle Valo return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 116e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info2)) == 117d5c65159SKalle Valo RX_DESC_DECRYPT_STATUS_CODE_OK); 118d5c65159SKalle Valo } 119d5c65159SKalle Valo 120e678fbd4SKarthikeyan Periyasamy static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn) 121d5c65159SKalle Valo { 122e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(attn->info1); 123d5c65159SKalle Valo u32 errmap = 0; 124d5c65159SKalle Valo 125d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_FCS_ERR) 126d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_FCS; 127d5c65159SKalle Valo 128d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 129d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_DECRYPT; 130d5c65159SKalle Valo 131d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 132d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 133d5c65159SKalle Valo 134d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 135d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 136d5c65159SKalle Valo 137d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 138d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_OVERFLOW; 139d5c65159SKalle Valo 140d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 141d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 142d5c65159SKalle Valo 143d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 144d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 145d5c65159SKalle Valo 146d5c65159SKalle Valo return errmap; 147d5c65159SKalle Valo } 148d5c65159SKalle Valo 149cd18ed4cSBaochen Qiang static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab, 150cd18ed4cSBaochen Qiang struct hal_rx_desc *desc) 151cd18ed4cSBaochen Qiang { 152cd18ed4cSBaochen Qiang struct rx_attention *rx_attention; 153cd18ed4cSBaochen Qiang u32 errmap; 154cd18ed4cSBaochen Qiang 155cd18ed4cSBaochen Qiang rx_attention = ath11k_dp_rx_get_attention(ab, desc); 156cd18ed4cSBaochen Qiang errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 157cd18ed4cSBaochen Qiang 158cd18ed4cSBaochen Qiang return errmap & DP_RX_MPDU_ERR_MSDU_LEN; 159cd18ed4cSBaochen Qiang } 160cd18ed4cSBaochen Qiang 1615e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab, 162e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 163d5c65159SKalle Valo { 164e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc); 165d5c65159SKalle Valo } 166d5c65159SKalle Valo 1675e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab, 168e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 169d5c65159SKalle Valo { 170e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc); 171d5c65159SKalle Valo } 172d5c65159SKalle Valo 1735e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab, 174e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 175d5c65159SKalle Valo { 176e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc); 177d5c65159SKalle Valo } 178d5c65159SKalle Valo 1795e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab, 180e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 181d5c65159SKalle Valo { 182e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc); 183d5c65159SKalle Valo } 184d5c65159SKalle Valo 1855e76fe03SP Praneesh static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab, 186e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 187d5c65159SKalle Valo { 188e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc); 189d5c65159SKalle Valo } 190d5c65159SKalle Valo 1915e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab, 192e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 193d5c65159SKalle Valo { 194e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc); 195d5c65159SKalle Valo } 196d5c65159SKalle Valo 1975e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab, 198e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 199d5c65159SKalle Valo { 200e678fbd4SKarthikeyan Periyasamy return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc)); 201d5c65159SKalle Valo } 202d5c65159SKalle Valo 2035e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab, 204e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 205243874c6SManikanta Pubbisetty { 206e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc); 207243874c6SManikanta Pubbisetty } 208243874c6SManikanta Pubbisetty 2095e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab, 210e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 211243874c6SManikanta Pubbisetty { 212e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc); 213243874c6SManikanta Pubbisetty } 214243874c6SManikanta Pubbisetty 2155e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab, 216e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 217d5c65159SKalle Valo { 218e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc); 219d5c65159SKalle Valo } 220d5c65159SKalle Valo 2215e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab, 222e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 223d5c65159SKalle Valo { 224e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc); 225d5c65159SKalle Valo } 226d5c65159SKalle Valo 227e678fbd4SKarthikeyan Periyasamy static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab, 228e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 229d5c65159SKalle Valo { 230e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc); 231d5c65159SKalle Valo } 232d5c65159SKalle Valo 233e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab, 234e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *fdesc, 235d5c65159SKalle Valo struct hal_rx_desc *ldesc) 236d5c65159SKalle Valo { 237e678fbd4SKarthikeyan Periyasamy ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc); 238d5c65159SKalle Valo } 239d5c65159SKalle Valo 2405e76fe03SP Praneesh static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn) 241d5c65159SKalle Valo { 242d5c65159SKalle Valo return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 243e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 244d5c65159SKalle Valo } 245d5c65159SKalle Valo 2465e76fe03SP Praneesh static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab, 247e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 248d5c65159SKalle Valo { 249d5c65159SKalle Valo u8 *rx_pkt_hdr; 250d5c65159SKalle Valo 251e678fbd4SKarthikeyan Periyasamy rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc); 252d5c65159SKalle Valo 253d5c65159SKalle Valo return rx_pkt_hdr; 254d5c65159SKalle Valo } 255d5c65159SKalle Valo 2565e76fe03SP Praneesh static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab, 257e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 258d5c65159SKalle Valo { 259d5c65159SKalle Valo u32 tlv_tag; 260d5c65159SKalle Valo 261e678fbd4SKarthikeyan Periyasamy tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc); 262d5c65159SKalle Valo 2638af40902SJason Yan return tlv_tag == HAL_RX_MPDU_START; 264d5c65159SKalle Valo } 265d5c65159SKalle Valo 2665e76fe03SP Praneesh static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab, 267e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 268d5c65159SKalle Valo { 269e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 270e678fbd4SKarthikeyan Periyasamy } 271e678fbd4SKarthikeyan Periyasamy 2725e76fe03SP Praneesh static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab, 273e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc, 274e678fbd4SKarthikeyan Periyasamy u16 len) 275e678fbd4SKarthikeyan Periyasamy { 276e678fbd4SKarthikeyan Periyasamy ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len); 277d5c65159SKalle Valo } 278d5c65159SKalle Valo 279210f563bSSriram R static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab, 280210f563bSSriram R struct hal_rx_desc *desc) 281210f563bSSriram R { 282210f563bSSriram R struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc); 283210f563bSSriram R 284210f563bSSriram R return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) && 285210f563bSSriram R (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST, 286210f563bSSriram R __le32_to_cpu(attn->info1))); 287210f563bSSriram R } 288210f563bSSriram R 2892167fa60SSriram R static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab, 2902167fa60SSriram R struct hal_rx_desc *desc) 2912167fa60SSriram R { 2922167fa60SSriram R return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc); 2932167fa60SSriram R } 2942167fa60SSriram R 2952167fa60SSriram R static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab, 2962167fa60SSriram R struct hal_rx_desc *desc) 2972167fa60SSriram R { 2982167fa60SSriram R return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc); 2992167fa60SSriram R } 3002167fa60SSriram R 301701e48a4SCarl Huang static void ath11k_dp_service_mon_ring(struct timer_list *t) 302701e48a4SCarl Huang { 303701e48a4SCarl Huang struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer); 304701e48a4SCarl Huang int i; 305701e48a4SCarl Huang 306701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 307701e48a4SCarl Huang ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET); 308701e48a4SCarl Huang 309701e48a4SCarl Huang mod_timer(&ab->mon_reap_timer, jiffies + 310701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 311701e48a4SCarl Huang } 312701e48a4SCarl Huang 313840c36faSCarl Huang static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab) 314840c36faSCarl Huang { 315840c36faSCarl Huang int i, reaped = 0; 316840c36faSCarl Huang unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 317840c36faSCarl Huang 318840c36faSCarl Huang do { 319840c36faSCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 320840c36faSCarl Huang reaped += ath11k_dp_rx_process_mon_rings(ab, i, 321840c36faSCarl Huang NULL, 322840c36faSCarl Huang DP_MON_SERVICE_BUDGET); 323840c36faSCarl Huang 324840c36faSCarl Huang /* nothing more to reap */ 325840c36faSCarl Huang if (reaped < DP_MON_SERVICE_BUDGET) 326840c36faSCarl Huang return 0; 327840c36faSCarl Huang 328840c36faSCarl Huang } while (time_before(jiffies, timeout)); 329840c36faSCarl Huang 330840c36faSCarl Huang ath11k_warn(ab, "dp mon ring purge timeout"); 331840c36faSCarl Huang 332840c36faSCarl Huang return -ETIMEDOUT; 333840c36faSCarl Huang } 334840c36faSCarl Huang 335d5c65159SKalle Valo /* Returns number of Rx buffers replenished */ 336d5c65159SKalle Valo int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 337d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 338d5c65159SKalle Valo int req_entries, 33987e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 340d5c65159SKalle Valo { 341d5c65159SKalle Valo struct hal_srng *srng; 342d5c65159SKalle Valo u32 *desc; 343d5c65159SKalle Valo struct sk_buff *skb; 344d5c65159SKalle Valo int num_free; 345d5c65159SKalle Valo int num_remain; 346d5c65159SKalle Valo int buf_id; 347d5c65159SKalle Valo u32 cookie; 348d5c65159SKalle Valo dma_addr_t paddr; 349d5c65159SKalle Valo 350d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 351d5c65159SKalle Valo 352d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 353d5c65159SKalle Valo 354d5c65159SKalle Valo spin_lock_bh(&srng->lock); 355d5c65159SKalle Valo 356d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 357d5c65159SKalle Valo 358d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 359d5c65159SKalle Valo if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 360d5c65159SKalle Valo req_entries = num_free; 361d5c65159SKalle Valo 362d5c65159SKalle Valo req_entries = min(num_free, req_entries); 363d5c65159SKalle Valo num_remain = req_entries; 364d5c65159SKalle Valo 365d5c65159SKalle Valo while (num_remain > 0) { 366d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 367d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 368d5c65159SKalle Valo if (!skb) 369d5c65159SKalle Valo break; 370d5c65159SKalle Valo 371d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 372d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 373d5c65159SKalle Valo skb_pull(skb, 374d5c65159SKalle Valo PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 375d5c65159SKalle Valo skb->data); 376d5c65159SKalle Valo } 377d5c65159SKalle Valo 378d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 379d5c65159SKalle Valo skb->len + skb_tailroom(skb), 380d5c65159SKalle Valo DMA_FROM_DEVICE); 381d5c65159SKalle Valo if (dma_mapping_error(ab->dev, paddr)) 382d5c65159SKalle Valo goto fail_free_skb; 383d5c65159SKalle Valo 384d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 385d5c65159SKalle Valo buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 38687e8497aSGovind Singh rx_ring->bufs_max * 3, GFP_ATOMIC); 387d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 388d5c65159SKalle Valo if (buf_id < 0) 389d5c65159SKalle Valo goto fail_dma_unmap; 390d5c65159SKalle Valo 391d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 392d5c65159SKalle Valo if (!desc) 393d5c65159SKalle Valo goto fail_idr_remove; 394d5c65159SKalle Valo 395d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 396d5c65159SKalle Valo 397d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 398d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 399d5c65159SKalle Valo 400d5c65159SKalle Valo num_remain--; 401d5c65159SKalle Valo 402d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 403d5c65159SKalle Valo } 404d5c65159SKalle Valo 405d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 406d5c65159SKalle Valo 407d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 408d5c65159SKalle Valo 409d5c65159SKalle Valo return req_entries - num_remain; 410d5c65159SKalle Valo 411d5c65159SKalle Valo fail_idr_remove: 412d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 413d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 414d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 415d5c65159SKalle Valo fail_dma_unmap: 416d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 417d5c65159SKalle Valo DMA_FROM_DEVICE); 418d5c65159SKalle Valo fail_free_skb: 419d5c65159SKalle Valo dev_kfree_skb_any(skb); 420d5c65159SKalle Valo 421d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 422d5c65159SKalle Valo 423d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 424d5c65159SKalle Valo 425d5c65159SKalle Valo return req_entries - num_remain; 426d5c65159SKalle Valo } 427d5c65159SKalle Valo 428d5c65159SKalle Valo static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 429d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring) 430d5c65159SKalle Valo { 431d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 432d5c65159SKalle Valo struct sk_buff *skb; 433d5c65159SKalle Valo int buf_id; 434d5c65159SKalle Valo 435d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 436d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 437d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 43816f283f0SKalle Valo /* TODO: Understand where internal driver does this dma_unmap 439d5c65159SKalle Valo * of rxdma_buffer. 440d5c65159SKalle Valo */ 441d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 442d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 443d5c65159SKalle Valo dev_kfree_skb_any(skb); 444d5c65159SKalle Valo } 445d5c65159SKalle Valo 446d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 447d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 448d5c65159SKalle Valo 4497f6fc1ebSCarl Huang /* if rxdma1_enable is false, mon_status_refill_ring 4507f6fc1ebSCarl Huang * isn't setup, so don't clean. 4517f6fc1ebSCarl Huang */ 4527f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 4537f6fc1ebSCarl Huang return 0; 4547f6fc1ebSCarl Huang 4554152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[0]; 456d5c65159SKalle Valo 457d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 458d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 459d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 46016f283f0SKalle Valo /* XXX: Understand where internal driver does this dma_unmap 461d5c65159SKalle Valo * of rxdma_buffer. 462d5c65159SKalle Valo */ 463d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 464d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); 465d5c65159SKalle Valo dev_kfree_skb_any(skb); 466d5c65159SKalle Valo } 467d5c65159SKalle Valo 468d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 469d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4707f6fc1ebSCarl Huang 471d5c65159SKalle Valo return 0; 472d5c65159SKalle Valo } 473d5c65159SKalle Valo 474d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 475d5c65159SKalle Valo { 476d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4774152e420SCarl Huang struct ath11k_base *ab = ar->ab; 478d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 4794152e420SCarl Huang int i; 480d5c65159SKalle Valo 481d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 482d5c65159SKalle Valo 483d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 484d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 485d5c65159SKalle Valo 4864152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4874152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 488d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 4894152e420SCarl Huang } 4904152e420SCarl Huang 491d5c65159SKalle Valo return 0; 492d5c65159SKalle Valo } 493d5c65159SKalle Valo 494d5c65159SKalle Valo static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 495d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 496d5c65159SKalle Valo u32 ringtype) 497d5c65159SKalle Valo { 498d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 499d5c65159SKalle Valo int num_entries; 500d5c65159SKalle Valo 501d5c65159SKalle Valo num_entries = rx_ring->refill_buf_ring.size / 502f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, ringtype); 503d5c65159SKalle Valo 504d5c65159SKalle Valo rx_ring->bufs_max = num_entries; 505d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 506734223d7SBaochen Qiang ar->ab->hw_params.hal_params->rx_buf_rbm); 507d5c65159SKalle Valo return 0; 508d5c65159SKalle Valo } 509d5c65159SKalle Valo 510d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 511d5c65159SKalle Valo { 512d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5134152e420SCarl Huang struct ath11k_base *ab = ar->ab; 514d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 5154152e420SCarl Huang int i; 516d5c65159SKalle Valo 517d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 518d5c65159SKalle Valo 5197f6fc1ebSCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 520d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 521d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 5227f6fc1ebSCarl Huang } 523d5c65159SKalle Valo 5244152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5254152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 526d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 5274152e420SCarl Huang } 528d5c65159SKalle Valo 529d5c65159SKalle Valo return 0; 530d5c65159SKalle Valo } 531d5c65159SKalle Valo 532d5c65159SKalle Valo static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 533d5c65159SKalle Valo { 534d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5354152e420SCarl Huang struct ath11k_base *ab = ar->ab; 5364152e420SCarl Huang int i; 537d5c65159SKalle Valo 5384152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 5394152e420SCarl Huang 5404152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5414152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) 5424152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 5434152e420SCarl Huang 5444152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 5454152e420SCarl Huang ath11k_dp_srng_cleanup(ab, 5464152e420SCarl Huang &dp->rx_mon_status_refill_ring[i].refill_buf_ring); 5474152e420SCarl Huang } 5484152e420SCarl Huang 5494152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 550d5c65159SKalle Valo } 551d5c65159SKalle Valo 5529c57d7e3SVasanthakumar Thiagarajan void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 5539c57d7e3SVasanthakumar Thiagarajan { 554acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 5559c57d7e3SVasanthakumar Thiagarajan int i; 5569c57d7e3SVasanthakumar Thiagarajan 557acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) 558acc79d98SSriram R ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 5599c57d7e3SVasanthakumar Thiagarajan } 5609c57d7e3SVasanthakumar Thiagarajan 5619c57d7e3SVasanthakumar Thiagarajan int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 5629c57d7e3SVasanthakumar Thiagarajan { 563acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 5649c57d7e3SVasanthakumar Thiagarajan int ret; 5659c57d7e3SVasanthakumar Thiagarajan int i; 5669c57d7e3SVasanthakumar Thiagarajan 567acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 568acc79d98SSriram R ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 569acc79d98SSriram R HAL_REO_DST, i, 0, 5709c57d7e3SVasanthakumar Thiagarajan DP_REO_DST_RING_SIZE); 5719c57d7e3SVasanthakumar Thiagarajan if (ret) { 572acc79d98SSriram R ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 5739c57d7e3SVasanthakumar Thiagarajan goto err_reo_cleanup; 5749c57d7e3SVasanthakumar Thiagarajan } 5759c57d7e3SVasanthakumar Thiagarajan } 5769c57d7e3SVasanthakumar Thiagarajan 5779c57d7e3SVasanthakumar Thiagarajan return 0; 5789c57d7e3SVasanthakumar Thiagarajan 5799c57d7e3SVasanthakumar Thiagarajan err_reo_cleanup: 5809c57d7e3SVasanthakumar Thiagarajan ath11k_dp_pdev_reo_cleanup(ab); 5819c57d7e3SVasanthakumar Thiagarajan 5829c57d7e3SVasanthakumar Thiagarajan return ret; 5839c57d7e3SVasanthakumar Thiagarajan } 5849c57d7e3SVasanthakumar Thiagarajan 585d5c65159SKalle Valo static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 586d5c65159SKalle Valo { 587d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5884152e420SCarl Huang struct ath11k_base *ab = ar->ab; 589d5c65159SKalle Valo struct dp_srng *srng = NULL; 5904152e420SCarl Huang int i; 591d5c65159SKalle Valo int ret; 592d5c65159SKalle Valo 593d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 594d5c65159SKalle Valo &dp->rx_refill_buf_ring.refill_buf_ring, 595d5c65159SKalle Valo HAL_RXDMA_BUF, 0, 596d5c65159SKalle Valo dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 597d5c65159SKalle Valo if (ret) { 598d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 599d5c65159SKalle Valo return ret; 600d5c65159SKalle Valo } 601d5c65159SKalle Valo 6024152e420SCarl Huang if (ar->ab->hw_params.rx_mac_buf_ring) { 6034152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6044152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, 6054152e420SCarl Huang &dp->rx_mac_buf_ring[i], 6064152e420SCarl Huang HAL_RXDMA_BUF, 1, 6074152e420SCarl Huang dp->mac_id + i, 1024); 608d5c65159SKalle Valo if (ret) { 6094152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n", 6104152e420SCarl Huang i); 611d5c65159SKalle Valo return ret; 612d5c65159SKalle Valo } 6134152e420SCarl Huang } 6144152e420SCarl Huang } 615d5c65159SKalle Valo 6164152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6174152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i], 6184152e420SCarl Huang HAL_RXDMA_DST, 0, dp->mac_id + i, 6194152e420SCarl Huang DP_RXDMA_ERR_DST_RING_SIZE); 6204152e420SCarl Huang if (ret) { 6214152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i); 6224152e420SCarl Huang return ret; 6234152e420SCarl Huang } 6244152e420SCarl Huang } 6254152e420SCarl Huang 6264152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6274152e420SCarl Huang srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 628d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 629d5c65159SKalle Valo srng, 6304152e420SCarl Huang HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i, 631d5c65159SKalle Valo DP_RXDMA_MON_STATUS_RING_SIZE); 632d5c65159SKalle Valo if (ret) { 633d5c65159SKalle Valo ath11k_warn(ar->ab, 6344152e420SCarl Huang "failed to setup rx_mon_status_refill_ring %d\n", i); 635d5c65159SKalle Valo return ret; 636d5c65159SKalle Valo } 6374152e420SCarl Huang } 6387f6fc1ebSCarl Huang 6397f6fc1ebSCarl Huang /* if rxdma1_enable is false, then it doesn't need 6407f6fc1ebSCarl Huang * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring 6417f6fc1ebSCarl Huang * and rxdma_mon_desc_ring. 642701e48a4SCarl Huang * init reap timer for QCA6390. 6437f6fc1ebSCarl Huang */ 644701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) { 645701e48a4SCarl Huang //init mon status buffer reap timer 646701e48a4SCarl Huang timer_setup(&ar->ab->mon_reap_timer, 647701e48a4SCarl Huang ath11k_dp_service_mon_ring, 0); 6487f6fc1ebSCarl Huang return 0; 649701e48a4SCarl Huang } 6507f6fc1ebSCarl Huang 651d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 652d5c65159SKalle Valo &dp->rxdma_mon_buf_ring.refill_buf_ring, 653d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 654d5c65159SKalle Valo DP_RXDMA_MONITOR_BUF_RING_SIZE); 655d5c65159SKalle Valo if (ret) { 656d5c65159SKalle Valo ath11k_warn(ar->ab, 657d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 658d5c65159SKalle Valo return ret; 659d5c65159SKalle Valo } 660d5c65159SKalle Valo 661d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 662d5c65159SKalle Valo HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 663d5c65159SKalle Valo DP_RXDMA_MONITOR_DST_RING_SIZE); 664d5c65159SKalle Valo if (ret) { 665d5c65159SKalle Valo ath11k_warn(ar->ab, 666d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DST\n"); 667d5c65159SKalle Valo return ret; 668d5c65159SKalle Valo } 669d5c65159SKalle Valo 670d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 671d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 672d5c65159SKalle Valo DP_RXDMA_MONITOR_DESC_RING_SIZE); 673d5c65159SKalle Valo if (ret) { 674d5c65159SKalle Valo ath11k_warn(ar->ab, 675d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 676d5c65159SKalle Valo return ret; 677d5c65159SKalle Valo } 678d5c65159SKalle Valo 679d5c65159SKalle Valo return 0; 680d5c65159SKalle Valo } 681d5c65159SKalle Valo 682d5c65159SKalle Valo void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 683d5c65159SKalle Valo { 684d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 685d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 686d5c65159SKalle Valo struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 687d5c65159SKalle Valo 688d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 689d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 690d5c65159SKalle Valo list_del(&cmd->list); 691d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd->data.paddr, 692d5c65159SKalle Valo cmd->data.size, DMA_BIDIRECTIONAL); 693d5c65159SKalle Valo kfree(cmd->data.vaddr); 694d5c65159SKalle Valo kfree(cmd); 695d5c65159SKalle Valo } 696d5c65159SKalle Valo 697d5c65159SKalle Valo list_for_each_entry_safe(cmd_cache, tmp_cache, 698d5c65159SKalle Valo &dp->reo_cmd_cache_flush_list, list) { 699d5c65159SKalle Valo list_del(&cmd_cache->list); 7005cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 701d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd_cache->data.paddr, 702d5c65159SKalle Valo cmd_cache->data.size, DMA_BIDIRECTIONAL); 703d5c65159SKalle Valo kfree(cmd_cache->data.vaddr); 704d5c65159SKalle Valo kfree(cmd_cache); 705d5c65159SKalle Valo } 706d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 707d5c65159SKalle Valo } 708d5c65159SKalle Valo 709d5c65159SKalle Valo static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 710d5c65159SKalle Valo enum hal_reo_cmd_status status) 711d5c65159SKalle Valo { 712d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 713d5c65159SKalle Valo 714d5c65159SKalle Valo if (status != HAL_REO_CMD_SUCCESS) 715d5c65159SKalle Valo ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 716d5c65159SKalle Valo rx_tid->tid, status); 717d5c65159SKalle Valo 718d5c65159SKalle Valo dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 719d5c65159SKalle Valo DMA_BIDIRECTIONAL); 720d5c65159SKalle Valo kfree(rx_tid->vaddr); 721d5c65159SKalle Valo } 722d5c65159SKalle Valo 723d5c65159SKalle Valo static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 724d5c65159SKalle Valo struct dp_rx_tid *rx_tid) 725d5c65159SKalle Valo { 726d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 727d5c65159SKalle Valo unsigned long tot_desc_sz, desc_sz; 728d5c65159SKalle Valo int ret; 729d5c65159SKalle Valo 730d5c65159SKalle Valo tot_desc_sz = rx_tid->size; 731d5c65159SKalle Valo desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 732d5c65159SKalle Valo 733d5c65159SKalle Valo while (tot_desc_sz > desc_sz) { 734d5c65159SKalle Valo tot_desc_sz -= desc_sz; 735d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 736d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 737d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 738d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, &cmd, 739d5c65159SKalle Valo NULL); 740d5c65159SKalle Valo if (ret) 741d5c65159SKalle Valo ath11k_warn(ab, 742d5c65159SKalle Valo "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 743d5c65159SKalle Valo rx_tid->tid, ret); 744d5c65159SKalle Valo } 745d5c65159SKalle Valo 746d5c65159SKalle Valo memset(&cmd, 0, sizeof(cmd)); 747d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 748d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 749d5c65159SKalle Valo cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 750d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 751d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, 752d5c65159SKalle Valo &cmd, ath11k_dp_reo_cmd_free); 753d5c65159SKalle Valo if (ret) { 754d5c65159SKalle Valo ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 755d5c65159SKalle Valo rx_tid->tid, ret); 756d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 757d5c65159SKalle Valo DMA_BIDIRECTIONAL); 758d5c65159SKalle Valo kfree(rx_tid->vaddr); 759d5c65159SKalle Valo } 760d5c65159SKalle Valo } 761d5c65159SKalle Valo 762d5c65159SKalle Valo static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 763d5c65159SKalle Valo enum hal_reo_cmd_status status) 764d5c65159SKalle Valo { 765d5c65159SKalle Valo struct ath11k_base *ab = dp->ab; 766d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 767d5c65159SKalle Valo struct dp_reo_cache_flush_elem *elem, *tmp; 768d5c65159SKalle Valo 769d5c65159SKalle Valo if (status == HAL_REO_CMD_DRAIN) { 770d5c65159SKalle Valo goto free_desc; 771d5c65159SKalle Valo } else if (status != HAL_REO_CMD_SUCCESS) { 772d5c65159SKalle Valo /* Shouldn't happen! Cleanup in case of other failure? */ 773d5c65159SKalle Valo ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 774d5c65159SKalle Valo rx_tid->tid, status); 775d5c65159SKalle Valo return; 776d5c65159SKalle Valo } 777d5c65159SKalle Valo 778d5c65159SKalle Valo elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 779d5c65159SKalle Valo if (!elem) 780d5c65159SKalle Valo goto free_desc; 781d5c65159SKalle Valo 782d5c65159SKalle Valo elem->ts = jiffies; 783d5c65159SKalle Valo memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 784d5c65159SKalle Valo 785d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 786d5c65159SKalle Valo list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 7875cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count++; 788d5c65159SKalle Valo 789d5c65159SKalle Valo /* Flush and invalidate aged REO desc from HW cache */ 790d5c65159SKalle Valo list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 791d5c65159SKalle Valo list) { 7925cb899ddSKarthikeyan Periyasamy if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 7935cb899ddSKarthikeyan Periyasamy time_after(jiffies, elem->ts + 794d5c65159SKalle Valo msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 795d5c65159SKalle Valo list_del(&elem->list); 7965cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 797d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 798d5c65159SKalle Valo 799d5c65159SKalle Valo ath11k_dp_reo_cache_flush(ab, &elem->data); 800d5c65159SKalle Valo kfree(elem); 801d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 802d5c65159SKalle Valo } 803d5c65159SKalle Valo } 804d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 805d5c65159SKalle Valo 806d5c65159SKalle Valo return; 807d5c65159SKalle Valo free_desc: 808d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 809d5c65159SKalle Valo DMA_BIDIRECTIONAL); 810d5c65159SKalle Valo kfree(rx_tid->vaddr); 811d5c65159SKalle Valo } 812d5c65159SKalle Valo 813a36adf54SGovindaraj Saminathan void ath11k_peer_rx_tid_delete(struct ath11k *ar, 814d5c65159SKalle Valo struct ath11k_peer *peer, u8 tid) 815d5c65159SKalle Valo { 816d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 817d5c65159SKalle Valo struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 818d5c65159SKalle Valo int ret; 819d5c65159SKalle Valo 820d5c65159SKalle Valo if (!rx_tid->active) 821d5c65159SKalle Valo return; 822d5c65159SKalle Valo 823d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 824d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 825d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 826d5c65159SKalle Valo cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 827d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 828d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 829d5c65159SKalle Valo ath11k_dp_rx_tid_del_func); 830d5c65159SKalle Valo if (ret) { 831d5c65159SKalle Valo ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 832d5c65159SKalle Valo tid, ret); 833d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 834d5c65159SKalle Valo DMA_BIDIRECTIONAL); 835d5c65159SKalle Valo kfree(rx_tid->vaddr); 836d5c65159SKalle Valo } 837d5c65159SKalle Valo 838d5c65159SKalle Valo rx_tid->active = false; 839d5c65159SKalle Valo } 840d5c65159SKalle Valo 841243874c6SManikanta Pubbisetty static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 842243874c6SManikanta Pubbisetty u32 *link_desc, 843243874c6SManikanta Pubbisetty enum hal_wbm_rel_bm_act action) 844243874c6SManikanta Pubbisetty { 845243874c6SManikanta Pubbisetty struct ath11k_dp *dp = &ab->dp; 846243874c6SManikanta Pubbisetty struct hal_srng *srng; 847243874c6SManikanta Pubbisetty u32 *desc; 848243874c6SManikanta Pubbisetty int ret = 0; 849243874c6SManikanta Pubbisetty 850243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 851243874c6SManikanta Pubbisetty 852243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 853243874c6SManikanta Pubbisetty 854243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 855243874c6SManikanta Pubbisetty 856243874c6SManikanta Pubbisetty desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 857243874c6SManikanta Pubbisetty if (!desc) { 858243874c6SManikanta Pubbisetty ret = -ENOBUFS; 859243874c6SManikanta Pubbisetty goto exit; 860243874c6SManikanta Pubbisetty } 861243874c6SManikanta Pubbisetty 862243874c6SManikanta Pubbisetty ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 863243874c6SManikanta Pubbisetty action); 864243874c6SManikanta Pubbisetty 865243874c6SManikanta Pubbisetty exit: 866243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 867243874c6SManikanta Pubbisetty 868243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 869243874c6SManikanta Pubbisetty 870243874c6SManikanta Pubbisetty return ret; 871243874c6SManikanta Pubbisetty } 872243874c6SManikanta Pubbisetty 873243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 874243874c6SManikanta Pubbisetty { 875243874c6SManikanta Pubbisetty struct ath11k_base *ab = rx_tid->ab; 876243874c6SManikanta Pubbisetty 877243874c6SManikanta Pubbisetty lockdep_assert_held(&ab->base_lock); 878243874c6SManikanta Pubbisetty 879243874c6SManikanta Pubbisetty if (rx_tid->dst_ring_desc) { 880243874c6SManikanta Pubbisetty if (rel_link_desc) 881243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 882243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 883243874c6SManikanta Pubbisetty kfree(rx_tid->dst_ring_desc); 884243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = NULL; 885243874c6SManikanta Pubbisetty } 886243874c6SManikanta Pubbisetty 887243874c6SManikanta Pubbisetty rx_tid->cur_sn = 0; 888243874c6SManikanta Pubbisetty rx_tid->last_frag_no = 0; 889243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap = 0; 890243874c6SManikanta Pubbisetty __skb_queue_purge(&rx_tid->rx_frags); 891243874c6SManikanta Pubbisetty } 892243874c6SManikanta Pubbisetty 893c3944a56SSriram R void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer) 894c3944a56SSriram R { 895c3944a56SSriram R struct dp_rx_tid *rx_tid; 896c3944a56SSriram R int i; 897c3944a56SSriram R 898c3944a56SSriram R lockdep_assert_held(&ar->ab->base_lock); 899c3944a56SSriram R 900c3944a56SSriram R for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 901c3944a56SSriram R rx_tid = &peer->rx_tid[i]; 902c3944a56SSriram R 903c3944a56SSriram R spin_unlock_bh(&ar->ab->base_lock); 904c3944a56SSriram R del_timer_sync(&rx_tid->frag_timer); 905c3944a56SSriram R spin_lock_bh(&ar->ab->base_lock); 906c3944a56SSriram R 907c3944a56SSriram R ath11k_dp_rx_frags_cleanup(rx_tid, true); 908c3944a56SSriram R } 909c3944a56SSriram R } 910c3944a56SSriram R 911d5c65159SKalle Valo void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 912d5c65159SKalle Valo { 913243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 914d5c65159SKalle Valo int i; 915d5c65159SKalle Valo 916243874c6SManikanta Pubbisetty lockdep_assert_held(&ar->ab->base_lock); 917243874c6SManikanta Pubbisetty 918243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 919243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 920243874c6SManikanta Pubbisetty 921d5c65159SKalle Valo ath11k_peer_rx_tid_delete(ar, peer, i); 922243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 923243874c6SManikanta Pubbisetty 924243874c6SManikanta Pubbisetty spin_unlock_bh(&ar->ab->base_lock); 925243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 926243874c6SManikanta Pubbisetty spin_lock_bh(&ar->ab->base_lock); 927243874c6SManikanta Pubbisetty } 928d5c65159SKalle Valo } 929d5c65159SKalle Valo 930d5c65159SKalle Valo static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 931d5c65159SKalle Valo struct ath11k_peer *peer, 932d5c65159SKalle Valo struct dp_rx_tid *rx_tid, 933fe201947SVenkateswara Naralasetty u32 ba_win_sz, u16 ssn, 934fe201947SVenkateswara Naralasetty bool update_ssn) 935d5c65159SKalle Valo { 936d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 937d5c65159SKalle Valo int ret; 938d5c65159SKalle Valo 939d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 940d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 941d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 942fe201947SVenkateswara Naralasetty cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 943d5c65159SKalle Valo cmd.ba_window_size = ba_win_sz; 944fe201947SVenkateswara Naralasetty 945fe201947SVenkateswara Naralasetty if (update_ssn) { 946fe201947SVenkateswara Naralasetty cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 947d5c65159SKalle Valo cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 948fe201947SVenkateswara Naralasetty } 949d5c65159SKalle Valo 950d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 951d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 952d5c65159SKalle Valo NULL); 953d5c65159SKalle Valo if (ret) { 954d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 955d5c65159SKalle Valo rx_tid->tid, ret); 956d5c65159SKalle Valo return ret; 957d5c65159SKalle Valo } 958d5c65159SKalle Valo 959d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 960d5c65159SKalle Valo 961d5c65159SKalle Valo return 0; 962d5c65159SKalle Valo } 963d5c65159SKalle Valo 964d5c65159SKalle Valo static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 965d5c65159SKalle Valo const u8 *peer_mac, int vdev_id, u8 tid) 966d5c65159SKalle Valo { 967d5c65159SKalle Valo struct ath11k_peer *peer; 968d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 969d5c65159SKalle Valo 970d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 971d5c65159SKalle Valo 972d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 973d5c65159SKalle Valo if (!peer) { 974d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 975d5c65159SKalle Valo goto unlock_exit; 976d5c65159SKalle Valo } 977d5c65159SKalle Valo 978d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 979d5c65159SKalle Valo if (!rx_tid->active) 980d5c65159SKalle Valo goto unlock_exit; 981d5c65159SKalle Valo 982d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 983d5c65159SKalle Valo DMA_BIDIRECTIONAL); 984d5c65159SKalle Valo kfree(rx_tid->vaddr); 985d5c65159SKalle Valo 986d5c65159SKalle Valo rx_tid->active = false; 987d5c65159SKalle Valo 988d5c65159SKalle Valo unlock_exit: 989d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 990d5c65159SKalle Valo } 991d5c65159SKalle Valo 992d5c65159SKalle Valo int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 9931441b2f2SManikanta Pubbisetty u8 tid, u32 ba_win_sz, u16 ssn, 9941441b2f2SManikanta Pubbisetty enum hal_pn_type pn_type) 995d5c65159SKalle Valo { 996d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 997d5c65159SKalle Valo struct ath11k_peer *peer; 998d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 999d5c65159SKalle Valo u32 hw_desc_sz; 1000d5c65159SKalle Valo u32 *addr_aligned; 1001d5c65159SKalle Valo void *vaddr; 1002d5c65159SKalle Valo dma_addr_t paddr; 1003d5c65159SKalle Valo int ret; 1004d5c65159SKalle Valo 1005d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1006d5c65159SKalle Valo 1007d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 1008d5c65159SKalle Valo if (!peer) { 1009d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); 1010d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1011d5c65159SKalle Valo return -ENOENT; 1012d5c65159SKalle Valo } 1013d5c65159SKalle Valo 1014d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 1015d5c65159SKalle Valo /* Update the tid queue if it is already setup */ 1016d5c65159SKalle Valo if (rx_tid->active) { 1017d5c65159SKalle Valo paddr = rx_tid->paddr; 1018d5c65159SKalle Valo ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1019fe201947SVenkateswara Naralasetty ba_win_sz, ssn, true); 1020d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1021d5c65159SKalle Valo if (ret) { 1022d5c65159SKalle Valo ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1023d5c65159SKalle Valo return ret; 1024d5c65159SKalle Valo } 1025d5c65159SKalle Valo 1026d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1027d5c65159SKalle Valo peer_mac, paddr, 1028d5c65159SKalle Valo tid, 1, ba_win_sz); 1029d5c65159SKalle Valo if (ret) 1030d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", 1031d5c65159SKalle Valo tid, ret); 1032d5c65159SKalle Valo return ret; 1033d5c65159SKalle Valo } 1034d5c65159SKalle Valo 1035d5c65159SKalle Valo rx_tid->tid = tid; 1036d5c65159SKalle Valo 1037d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 1038d5c65159SKalle Valo 103916f283f0SKalle Valo /* TODO: Optimize the memory allocation for qos tid based on 1040d5c65159SKalle Valo * the actual BA window size in REO tid update path. 1041d5c65159SKalle Valo */ 1042d5c65159SKalle Valo if (tid == HAL_DESC_REO_NON_QOS_TID) 1043d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 1044d5c65159SKalle Valo else 1045d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1046d5c65159SKalle Valo 104769c93f96SWei Yongjun vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1048d5c65159SKalle Valo if (!vaddr) { 1049d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1050d5c65159SKalle Valo return -ENOMEM; 1051d5c65159SKalle Valo } 1052d5c65159SKalle Valo 1053d5c65159SKalle Valo addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1054d5c65159SKalle Valo 10551441b2f2SManikanta Pubbisetty ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 10561441b2f2SManikanta Pubbisetty ssn, pn_type); 1057d5c65159SKalle Valo 1058d5c65159SKalle Valo paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1059d5c65159SKalle Valo DMA_BIDIRECTIONAL); 1060d5c65159SKalle Valo 1061d5c65159SKalle Valo ret = dma_mapping_error(ab->dev, paddr); 1062d5c65159SKalle Valo if (ret) { 1063d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1064d5c65159SKalle Valo goto err_mem_free; 1065d5c65159SKalle Valo } 1066d5c65159SKalle Valo 1067d5c65159SKalle Valo rx_tid->vaddr = vaddr; 1068d5c65159SKalle Valo rx_tid->paddr = paddr; 1069d5c65159SKalle Valo rx_tid->size = hw_desc_sz; 1070d5c65159SKalle Valo rx_tid->active = true; 1071d5c65159SKalle Valo 1072d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1073d5c65159SKalle Valo 1074d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1075d5c65159SKalle Valo paddr, tid, 1, ba_win_sz); 1076d5c65159SKalle Valo if (ret) { 1077d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", 1078d5c65159SKalle Valo tid, ret); 1079d5c65159SKalle Valo ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 1080d5c65159SKalle Valo } 1081d5c65159SKalle Valo 1082d5c65159SKalle Valo return ret; 1083d5c65159SKalle Valo 1084d5c65159SKalle Valo err_mem_free: 1085d5c65159SKalle Valo kfree(vaddr); 1086d5c65159SKalle Valo 1087d5c65159SKalle Valo return ret; 1088d5c65159SKalle Valo } 1089d5c65159SKalle Valo 1090d5c65159SKalle Valo int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 1091d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1092d5c65159SKalle Valo { 1093d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1094d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1095d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1096d5c65159SKalle Valo int ret; 1097d5c65159SKalle Valo 1098d5c65159SKalle Valo ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 1099d5c65159SKalle Valo params->tid, params->buf_size, 11001441b2f2SManikanta Pubbisetty params->ssn, arsta->pn_type); 1101d5c65159SKalle Valo if (ret) 1102d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 1103d5c65159SKalle Valo 1104d5c65159SKalle Valo return ret; 1105d5c65159SKalle Valo } 1106d5c65159SKalle Valo 1107d5c65159SKalle Valo int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 1108d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1109d5c65159SKalle Valo { 1110d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1111d5c65159SKalle Valo struct ath11k_peer *peer; 1112d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1113d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1114d5c65159SKalle Valo dma_addr_t paddr; 1115d5c65159SKalle Valo bool active; 1116d5c65159SKalle Valo int ret; 1117d5c65159SKalle Valo 1118d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1119d5c65159SKalle Valo 1120d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 1121d5c65159SKalle Valo if (!peer) { 1122d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1123d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1124d5c65159SKalle Valo return -ENOENT; 1125d5c65159SKalle Valo } 1126d5c65159SKalle Valo 1127d5c65159SKalle Valo paddr = peer->rx_tid[params->tid].paddr; 1128d5c65159SKalle Valo active = peer->rx_tid[params->tid].active; 1129d5c65159SKalle Valo 1130fe201947SVenkateswara Naralasetty if (!active) { 1131d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1132d5c65159SKalle Valo return 0; 1133fe201947SVenkateswara Naralasetty } 1134fe201947SVenkateswara Naralasetty 1135fe201947SVenkateswara Naralasetty ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1136fe201947SVenkateswara Naralasetty spin_unlock_bh(&ab->base_lock); 1137fe201947SVenkateswara Naralasetty if (ret) { 1138fe201947SVenkateswara Naralasetty ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1139fe201947SVenkateswara Naralasetty params->tid, ret); 1140fe201947SVenkateswara Naralasetty return ret; 1141fe201947SVenkateswara Naralasetty } 1142d5c65159SKalle Valo 1143d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1144d5c65159SKalle Valo params->sta->addr, paddr, 1145d5c65159SKalle Valo params->tid, 1, 1); 1146d5c65159SKalle Valo if (ret) 1147d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1148d5c65159SKalle Valo ret); 1149d5c65159SKalle Valo 1150d5c65159SKalle Valo return ret; 1151d5c65159SKalle Valo } 1152d5c65159SKalle Valo 11531441b2f2SManikanta Pubbisetty int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 11541441b2f2SManikanta Pubbisetty const u8 *peer_addr, 11551441b2f2SManikanta Pubbisetty enum set_key_cmd key_cmd, 11561441b2f2SManikanta Pubbisetty struct ieee80211_key_conf *key) 11571441b2f2SManikanta Pubbisetty { 11581441b2f2SManikanta Pubbisetty struct ath11k *ar = arvif->ar; 11591441b2f2SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 11601441b2f2SManikanta Pubbisetty struct ath11k_hal_reo_cmd cmd = {0}; 11611441b2f2SManikanta Pubbisetty struct ath11k_peer *peer; 11621441b2f2SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 11631441b2f2SManikanta Pubbisetty u8 tid; 11641441b2f2SManikanta Pubbisetty int ret = 0; 11651441b2f2SManikanta Pubbisetty 11661441b2f2SManikanta Pubbisetty /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 11671441b2f2SManikanta Pubbisetty * We use mac80211 PN/TSC replay check functionality for bcast/mcast 11681441b2f2SManikanta Pubbisetty * for now. 11691441b2f2SManikanta Pubbisetty */ 11701441b2f2SManikanta Pubbisetty if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 11711441b2f2SManikanta Pubbisetty return 0; 11721441b2f2SManikanta Pubbisetty 11731441b2f2SManikanta Pubbisetty cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 11741441b2f2SManikanta Pubbisetty cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 11751441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_SIZE | 11761441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_VALID | 11771441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_CHECK | 11781441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_SVLD; 11791441b2f2SManikanta Pubbisetty 11801441b2f2SManikanta Pubbisetty switch (key->cipher) { 11811441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_TKIP: 11821441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP: 11831441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP_256: 11841441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP: 11851441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP_256: 11861441b2f2SManikanta Pubbisetty if (key_cmd == SET_KEY) { 11871441b2f2SManikanta Pubbisetty cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 11881441b2f2SManikanta Pubbisetty cmd.pn_size = 48; 11891441b2f2SManikanta Pubbisetty } 11901441b2f2SManikanta Pubbisetty break; 11911441b2f2SManikanta Pubbisetty default: 11921441b2f2SManikanta Pubbisetty break; 11931441b2f2SManikanta Pubbisetty } 11941441b2f2SManikanta Pubbisetty 11951441b2f2SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 11961441b2f2SManikanta Pubbisetty 11971441b2f2SManikanta Pubbisetty peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 11981441b2f2SManikanta Pubbisetty if (!peer) { 11991441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 12001441b2f2SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 12011441b2f2SManikanta Pubbisetty return -ENOENT; 12021441b2f2SManikanta Pubbisetty } 12031441b2f2SManikanta Pubbisetty 12041441b2f2SManikanta Pubbisetty for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 12051441b2f2SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 12061441b2f2SManikanta Pubbisetty if (!rx_tid->active) 12071441b2f2SManikanta Pubbisetty continue; 12081441b2f2SManikanta Pubbisetty cmd.addr_lo = lower_32_bits(rx_tid->paddr); 12091441b2f2SManikanta Pubbisetty cmd.addr_hi = upper_32_bits(rx_tid->paddr); 12101441b2f2SManikanta Pubbisetty ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 12111441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPDATE_RX_QUEUE, 12121441b2f2SManikanta Pubbisetty &cmd, NULL); 12131441b2f2SManikanta Pubbisetty if (ret) { 12141441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 12151441b2f2SManikanta Pubbisetty tid, ret); 12161441b2f2SManikanta Pubbisetty break; 12171441b2f2SManikanta Pubbisetty } 12181441b2f2SManikanta Pubbisetty } 12191441b2f2SManikanta Pubbisetty 1220abdcd4cbSDan Carpenter spin_unlock_bh(&ab->base_lock); 12211441b2f2SManikanta Pubbisetty 12221441b2f2SManikanta Pubbisetty return ret; 12231441b2f2SManikanta Pubbisetty } 12241441b2f2SManikanta Pubbisetty 12251441b2f2SManikanta Pubbisetty static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1226d5c65159SKalle Valo u16 peer_id) 1227d5c65159SKalle Valo { 1228d5c65159SKalle Valo int i; 1229d5c65159SKalle Valo 1230d5c65159SKalle Valo for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1231d5c65159SKalle Valo if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1232d5c65159SKalle Valo if (peer_id == ppdu_stats->user_stats[i].peer_id) 1233d5c65159SKalle Valo return i; 1234d5c65159SKalle Valo } else { 1235d5c65159SKalle Valo return i; 1236d5c65159SKalle Valo } 1237d5c65159SKalle Valo } 1238d5c65159SKalle Valo 1239d5c65159SKalle Valo return -EINVAL; 1240d5c65159SKalle Valo } 1241d5c65159SKalle Valo 1242d5c65159SKalle Valo static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1243d5c65159SKalle Valo u16 tag, u16 len, const void *ptr, 1244d5c65159SKalle Valo void *data) 1245d5c65159SKalle Valo { 1246d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1247d5c65159SKalle Valo struct htt_ppdu_user_stats *user_stats; 1248d5c65159SKalle Valo int cur_user; 1249d5c65159SKalle Valo u16 peer_id; 1250d5c65159SKalle Valo 1251d5c65159SKalle Valo ppdu_info = (struct htt_ppdu_stats_info *)data; 1252d5c65159SKalle Valo 1253d5c65159SKalle Valo switch (tag) { 1254d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_COMMON: 1255d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_common)) { 1256d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1257d5c65159SKalle Valo len, tag); 1258d5c65159SKalle Valo return -EINVAL; 1259d5c65159SKalle Valo } 1260d5c65159SKalle Valo memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1261d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_common)); 1262d5c65159SKalle Valo break; 1263d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_RATE: 1264d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1265d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1266d5c65159SKalle Valo len, tag); 1267d5c65159SKalle Valo return -EINVAL; 1268d5c65159SKalle Valo } 1269d5c65159SKalle Valo 1270d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1271d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1272d5c65159SKalle Valo peer_id); 1273d5c65159SKalle Valo if (cur_user < 0) 1274d5c65159SKalle Valo return -EINVAL; 1275d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1276d5c65159SKalle Valo user_stats->peer_id = peer_id; 1277d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1278d5c65159SKalle Valo memcpy((void *)&user_stats->rate, ptr, 1279d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_user_rate)); 1280d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1281d5c65159SKalle Valo break; 1282d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1283d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1284d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1285d5c65159SKalle Valo len, tag); 1286d5c65159SKalle Valo return -EINVAL; 1287d5c65159SKalle Valo } 1288d5c65159SKalle Valo 1289d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1290d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1291d5c65159SKalle Valo peer_id); 1292d5c65159SKalle Valo if (cur_user < 0) 1293d5c65159SKalle Valo return -EINVAL; 1294d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1295d5c65159SKalle Valo user_stats->peer_id = peer_id; 1296d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1297d5c65159SKalle Valo memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1298d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1299d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1300d5c65159SKalle Valo break; 1301d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1302d5c65159SKalle Valo if (len < 1303d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1304d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1305d5c65159SKalle Valo len, tag); 1306d5c65159SKalle Valo return -EINVAL; 1307d5c65159SKalle Valo } 1308d5c65159SKalle Valo 1309d5c65159SKalle Valo peer_id = 1310d5c65159SKalle Valo ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1311d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1312d5c65159SKalle Valo peer_id); 1313d5c65159SKalle Valo if (cur_user < 0) 1314d5c65159SKalle Valo return -EINVAL; 1315d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1316d5c65159SKalle Valo user_stats->peer_id = peer_id; 1317d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1318d5c65159SKalle Valo memcpy((void *)&user_stats->ack_ba, ptr, 1319d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1320d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1321d5c65159SKalle Valo break; 1322d5c65159SKalle Valo } 1323d5c65159SKalle Valo return 0; 1324d5c65159SKalle Valo } 1325d5c65159SKalle Valo 1326d5c65159SKalle Valo int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1327d5c65159SKalle Valo int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1328d5c65159SKalle Valo const void *ptr, void *data), 1329d5c65159SKalle Valo void *data) 1330d5c65159SKalle Valo { 1331d5c65159SKalle Valo const struct htt_tlv *tlv; 1332d5c65159SKalle Valo const void *begin = ptr; 1333d5c65159SKalle Valo u16 tlv_tag, tlv_len; 1334d5c65159SKalle Valo int ret = -EINVAL; 1335d5c65159SKalle Valo 1336d5c65159SKalle Valo while (len > 0) { 1337d5c65159SKalle Valo if (len < sizeof(*tlv)) { 1338d5c65159SKalle Valo ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1339d5c65159SKalle Valo ptr - begin, len, sizeof(*tlv)); 1340d5c65159SKalle Valo return -EINVAL; 1341d5c65159SKalle Valo } 1342d5c65159SKalle Valo tlv = (struct htt_tlv *)ptr; 1343d5c65159SKalle Valo tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1344d5c65159SKalle Valo tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1345d5c65159SKalle Valo ptr += sizeof(*tlv); 1346d5c65159SKalle Valo len -= sizeof(*tlv); 1347d5c65159SKalle Valo 1348d5c65159SKalle Valo if (tlv_len > len) { 1349bb2d2dfdSTom Rix ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1350d5c65159SKalle Valo tlv_tag, ptr - begin, len, tlv_len); 1351d5c65159SKalle Valo return -EINVAL; 1352d5c65159SKalle Valo } 1353d5c65159SKalle Valo ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1354d5c65159SKalle Valo if (ret == -ENOMEM) 1355d5c65159SKalle Valo return ret; 1356d5c65159SKalle Valo 1357d5c65159SKalle Valo ptr += tlv_len; 1358d5c65159SKalle Valo len -= tlv_len; 1359d5c65159SKalle Valo } 1360d5c65159SKalle Valo return 0; 1361d5c65159SKalle Valo } 1362d5c65159SKalle Valo 13636a0c3702SJohn Crispin static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi) 13646a0c3702SJohn Crispin { 13656a0c3702SJohn Crispin u32 ret = 0; 13666a0c3702SJohn Crispin 13676a0c3702SJohn Crispin switch (sgi) { 13686a0c3702SJohn Crispin case RX_MSDU_START_SGI_0_8_US: 13696a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_0_8; 13706a0c3702SJohn Crispin break; 13716a0c3702SJohn Crispin case RX_MSDU_START_SGI_1_6_US: 13726a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_1_6; 13736a0c3702SJohn Crispin break; 13746a0c3702SJohn Crispin case RX_MSDU_START_SGI_3_2_US: 13756a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_3_2; 13766a0c3702SJohn Crispin break; 13776a0c3702SJohn Crispin } 13786a0c3702SJohn Crispin 13796a0c3702SJohn Crispin return ret; 13806a0c3702SJohn Crispin } 13816a0c3702SJohn Crispin 1382d5c65159SKalle Valo static void 1383d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1384d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats, u8 user) 1385d5c65159SKalle Valo { 1386d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1387d5c65159SKalle Valo struct ath11k_peer *peer; 1388d5c65159SKalle Valo struct ieee80211_sta *sta; 1389d5c65159SKalle Valo struct ath11k_sta *arsta; 1390d5c65159SKalle Valo struct htt_ppdu_stats_user_rate *user_rate; 1391d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1392d5c65159SKalle Valo struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1393d5c65159SKalle Valo struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1394d5c65159SKalle Valo int ret; 13956a0c3702SJohn Crispin u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1396d5c65159SKalle Valo u32 succ_bytes = 0; 1397d5c65159SKalle Valo u16 rate = 0, succ_pkts = 0; 1398d5c65159SKalle Valo u32 tx_duration = 0; 1399b9269a07SVenkateswara Naralasetty u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1400d5c65159SKalle Valo bool is_ampdu = false; 1401d5c65159SKalle Valo 1402d5c65159SKalle Valo if (!usr_stats) 1403d5c65159SKalle Valo return; 1404d5c65159SKalle Valo 1405d5c65159SKalle Valo if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1406d5c65159SKalle Valo return; 1407d5c65159SKalle Valo 1408d5c65159SKalle Valo if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1409d5c65159SKalle Valo is_ampdu = 1410d5c65159SKalle Valo HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1411d5c65159SKalle Valo 1412d5c65159SKalle Valo if (usr_stats->tlv_flags & 1413d5c65159SKalle Valo BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1414d5c65159SKalle Valo succ_bytes = usr_stats->ack_ba.success_bytes; 1415d5c65159SKalle Valo succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1416d5c65159SKalle Valo usr_stats->ack_ba.info); 1417b9269a07SVenkateswara Naralasetty tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1418b9269a07SVenkateswara Naralasetty usr_stats->ack_ba.info); 1419d5c65159SKalle Valo } 1420d5c65159SKalle Valo 1421d5c65159SKalle Valo if (common->fes_duration_us) 1422d5c65159SKalle Valo tx_duration = common->fes_duration_us; 1423d5c65159SKalle Valo 1424d5c65159SKalle Valo user_rate = &usr_stats->rate; 1425d5c65159SKalle Valo flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1426d5c65159SKalle Valo bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1427d5c65159SKalle Valo nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1428d5c65159SKalle Valo mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1429d5c65159SKalle Valo sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 14306a0c3702SJohn Crispin dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1431d5c65159SKalle Valo 1432d5c65159SKalle Valo /* Note: If host configured fixed rates and in some other special 1433d5c65159SKalle Valo * cases, the broadcast/management frames are sent in different rates. 1434d5c65159SKalle Valo * Firmware rate's control to be skipped for this? 1435d5c65159SKalle Valo */ 1436d5c65159SKalle Valo 14376a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 1438bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 14396a0c3702SJohn Crispin return; 14406a0c3702SJohn Crispin } 14416a0c3702SJohn Crispin 14426a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1443bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1444d5c65159SKalle Valo return; 1445d5c65159SKalle Valo } 1446d5c65159SKalle Valo 14476a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1448bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1449d5c65159SKalle Valo mcs, nss); 1450d5c65159SKalle Valo return; 1451d5c65159SKalle Valo } 1452d5c65159SKalle Valo 1453d5c65159SKalle Valo if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1454d5c65159SKalle Valo ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1455d5c65159SKalle Valo flags, 1456d5c65159SKalle Valo &rate_idx, 1457d5c65159SKalle Valo &rate); 1458d5c65159SKalle Valo if (ret < 0) 1459d5c65159SKalle Valo return; 1460d5c65159SKalle Valo } 1461d5c65159SKalle Valo 1462d5c65159SKalle Valo rcu_read_lock(); 1463d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1464d5c65159SKalle Valo peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1465d5c65159SKalle Valo 1466d5c65159SKalle Valo if (!peer || !peer->sta) { 1467d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1468d5c65159SKalle Valo rcu_read_unlock(); 1469d5c65159SKalle Valo return; 1470d5c65159SKalle Valo } 1471d5c65159SKalle Valo 1472d5c65159SKalle Valo sta = peer->sta; 1473d5c65159SKalle Valo arsta = (struct ath11k_sta *)sta->drv_priv; 1474d5c65159SKalle Valo 1475d5c65159SKalle Valo memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1476d5c65159SKalle Valo 1477d5c65159SKalle Valo switch (flags) { 1478d5c65159SKalle Valo case WMI_RATE_PREAMBLE_OFDM: 1479d5c65159SKalle Valo arsta->txrate.legacy = rate; 1480d5c65159SKalle Valo break; 1481d5c65159SKalle Valo case WMI_RATE_PREAMBLE_CCK: 1482d5c65159SKalle Valo arsta->txrate.legacy = rate; 1483d5c65159SKalle Valo break; 1484d5c65159SKalle Valo case WMI_RATE_PREAMBLE_HT: 1485d5c65159SKalle Valo arsta->txrate.mcs = mcs + 8 * (nss - 1); 1486d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1487be43ce64SJohn Crispin if (sgi) 1488d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1489d5c65159SKalle Valo break; 1490d5c65159SKalle Valo case WMI_RATE_PREAMBLE_VHT: 1491d5c65159SKalle Valo arsta->txrate.mcs = mcs; 1492d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1493be43ce64SJohn Crispin if (sgi) 1494d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1495d5c65159SKalle Valo break; 14966a0c3702SJohn Crispin case WMI_RATE_PREAMBLE_HE: 14976a0c3702SJohn Crispin arsta->txrate.mcs = mcs; 14986a0c3702SJohn Crispin arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 14996a0c3702SJohn Crispin arsta->txrate.he_dcm = dcm; 15006a0c3702SJohn Crispin arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 15016a0c3702SJohn Crispin arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc( 15026a0c3702SJohn Crispin (user_rate->ru_end - 15036a0c3702SJohn Crispin user_rate->ru_start) + 1); 15046a0c3702SJohn Crispin break; 1505d5c65159SKalle Valo } 1506d5c65159SKalle Valo 1507d5c65159SKalle Valo arsta->txrate.nss = nss; 150839e81c6aSTamizh chelvam arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1509a9e945eaSVenkateswara Naralasetty arsta->tx_duration += tx_duration; 1510d5c65159SKalle Valo memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1511d5c65159SKalle Valo 1512b9269a07SVenkateswara Naralasetty /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1513b9269a07SVenkateswara Naralasetty * So skip peer stats update for mgmt packets. 1514b9269a07SVenkateswara Naralasetty */ 1515b9269a07SVenkateswara Naralasetty if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1516d5c65159SKalle Valo memset(peer_stats, 0, sizeof(*peer_stats)); 1517d5c65159SKalle Valo peer_stats->succ_pkts = succ_pkts; 1518d5c65159SKalle Valo peer_stats->succ_bytes = succ_bytes; 1519d5c65159SKalle Valo peer_stats->is_ampdu = is_ampdu; 1520d5c65159SKalle Valo peer_stats->duration = tx_duration; 1521d5c65159SKalle Valo peer_stats->ba_fails = 1522d5c65159SKalle Valo HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1523d5c65159SKalle Valo HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1524d5c65159SKalle Valo 1525cb4e57dbSKalle Valo if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 1526568f0603SKalle Valo ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 1527b9269a07SVenkateswara Naralasetty } 1528d5c65159SKalle Valo 1529d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1530d5c65159SKalle Valo rcu_read_unlock(); 1531d5c65159SKalle Valo } 1532d5c65159SKalle Valo 1533d5c65159SKalle Valo static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1534d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats) 1535d5c65159SKalle Valo { 1536d5c65159SKalle Valo u8 user; 1537d5c65159SKalle Valo 1538d5c65159SKalle Valo for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1539d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1540d5c65159SKalle Valo } 1541d5c65159SKalle Valo 1542d5c65159SKalle Valo static 1543d5c65159SKalle Valo struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1544d5c65159SKalle Valo u32 ppdu_id) 1545d5c65159SKalle Valo { 1546269663f1SDan Carpenter struct htt_ppdu_stats_info *ppdu_info; 1547d5c65159SKalle Valo 1548d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1549d5c65159SKalle Valo if (!list_empty(&ar->ppdu_stats_info)) { 1550d5c65159SKalle Valo list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1551269663f1SDan Carpenter if (ppdu_info->ppdu_id == ppdu_id) { 1552d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1553d5c65159SKalle Valo return ppdu_info; 1554d5c65159SKalle Valo } 1555d5c65159SKalle Valo } 1556d5c65159SKalle Valo 1557d5c65159SKalle Valo if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1558d5c65159SKalle Valo ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1559d5c65159SKalle Valo typeof(*ppdu_info), list); 1560d5c65159SKalle Valo list_del(&ppdu_info->list); 1561d5c65159SKalle Valo ar->ppdu_stat_list_depth--; 1562d5c65159SKalle Valo ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1563d5c65159SKalle Valo kfree(ppdu_info); 1564d5c65159SKalle Valo } 1565d5c65159SKalle Valo } 1566d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1567d5c65159SKalle Valo 15686a8be1baSWen Gong ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1569d5c65159SKalle Valo if (!ppdu_info) 1570d5c65159SKalle Valo return NULL; 1571d5c65159SKalle Valo 1572d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1573d5c65159SKalle Valo list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1574d5c65159SKalle Valo ar->ppdu_stat_list_depth++; 1575d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1576d5c65159SKalle Valo 1577d5c65159SKalle Valo return ppdu_info; 1578d5c65159SKalle Valo } 1579d5c65159SKalle Valo 1580d5c65159SKalle Valo static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1581d5c65159SKalle Valo struct sk_buff *skb) 1582d5c65159SKalle Valo { 1583d5c65159SKalle Valo struct ath11k_htt_ppdu_stats_msg *msg; 1584d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1585d5c65159SKalle Valo struct ath11k *ar; 1586d5c65159SKalle Valo int ret; 1587d5c65159SKalle Valo u8 pdev_id; 1588d5c65159SKalle Valo u32 ppdu_id, len; 1589d5c65159SKalle Valo 1590d5c65159SKalle Valo msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1591d5c65159SKalle Valo len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1592d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1593d5c65159SKalle Valo ppdu_id = msg->ppdu_id; 1594d5c65159SKalle Valo 1595d5c65159SKalle Valo rcu_read_lock(); 1596d5c65159SKalle Valo ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1597d5c65159SKalle Valo if (!ar) { 1598d5c65159SKalle Valo ret = -EINVAL; 1599d5c65159SKalle Valo goto exit; 1600d5c65159SKalle Valo } 1601d5c65159SKalle Valo 1602cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) 1603d5c65159SKalle Valo trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1604d5c65159SKalle Valo 1605d5c65159SKalle Valo ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1606d5c65159SKalle Valo if (!ppdu_info) { 1607d5c65159SKalle Valo ret = -EINVAL; 1608d5c65159SKalle Valo goto exit; 1609d5c65159SKalle Valo } 1610d5c65159SKalle Valo 1611d5c65159SKalle Valo ppdu_info->ppdu_id = ppdu_id; 1612d5c65159SKalle Valo ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1613d5c65159SKalle Valo ath11k_htt_tlv_ppdu_stats_parse, 1614d5c65159SKalle Valo (void *)ppdu_info); 1615d5c65159SKalle Valo if (ret) { 1616d5c65159SKalle Valo ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1617d5c65159SKalle Valo goto exit; 1618d5c65159SKalle Valo } 1619d5c65159SKalle Valo 1620d5c65159SKalle Valo exit: 1621d5c65159SKalle Valo rcu_read_unlock(); 1622d5c65159SKalle Valo 1623d5c65159SKalle Valo return ret; 1624d5c65159SKalle Valo } 1625d5c65159SKalle Valo 1626d5c65159SKalle Valo static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1627d5c65159SKalle Valo { 1628d5c65159SKalle Valo struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1629443d2ee7SAnilkumar Kolli struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1630d5c65159SKalle Valo struct ath11k *ar; 1631d5c65159SKalle Valo u8 pdev_id; 1632d5c65159SKalle Valo 1633d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1634d0f390eaSAnilkumar Kolli ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1635d0f390eaSAnilkumar Kolli if (!ar) { 1636d0f390eaSAnilkumar Kolli ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1637d0f390eaSAnilkumar Kolli return; 1638d0f390eaSAnilkumar Kolli } 1639d5c65159SKalle Valo 164021c1b063SMaharaja Kennadyrajan trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 164121c1b063SMaharaja Kennadyrajan ar->ab->pktlog_defs_checksum); 1642d5c65159SKalle Valo } 1643d5c65159SKalle Valo 1644678e8414SSriram R static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1645678e8414SSriram R struct sk_buff *skb) 1646678e8414SSriram R { 1647678e8414SSriram R u32 *data = (u32 *)skb->data; 164871fbc847SSriram R u8 pdev_id, ring_type, ring_id, pdev_idx; 1649678e8414SSriram R u16 hp, tp; 1650678e8414SSriram R u32 backpressure_time; 165171fbc847SSriram R struct ath11k_bp_stats *bp_stats; 1652678e8414SSriram R 1653678e8414SSriram R pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1654678e8414SSriram R ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1655678e8414SSriram R ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1656678e8414SSriram R ++data; 1657678e8414SSriram R 1658678e8414SSriram R hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1659678e8414SSriram R tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1660678e8414SSriram R ++data; 1661678e8414SSriram R 1662678e8414SSriram R backpressure_time = *data; 1663678e8414SSriram R 1664678e8414SSriram R ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1665678e8414SSriram R pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 166671fbc847SSriram R 166771fbc847SSriram R if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { 166871fbc847SSriram R if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) 166971fbc847SSriram R return; 167071fbc847SSriram R 167171fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; 167271fbc847SSriram R } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { 167371fbc847SSriram R pdev_idx = DP_HW2SW_MACID(pdev_id); 167471fbc847SSriram R 167571fbc847SSriram R if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) 167671fbc847SSriram R return; 167771fbc847SSriram R 167871fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; 167971fbc847SSriram R } else { 168071fbc847SSriram R ath11k_warn(ab, "unknown ring type received in htt bp event %d\n", 168171fbc847SSriram R ring_type); 168271fbc847SSriram R return; 168371fbc847SSriram R } 168471fbc847SSriram R 168571fbc847SSriram R spin_lock_bh(&ab->base_lock); 168671fbc847SSriram R bp_stats->hp = hp; 168771fbc847SSriram R bp_stats->tp = tp; 168871fbc847SSriram R bp_stats->count++; 168971fbc847SSriram R bp_stats->jiffies = jiffies; 169071fbc847SSriram R spin_unlock_bh(&ab->base_lock); 1691678e8414SSriram R } 1692678e8414SSriram R 1693d5c65159SKalle Valo void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1694d5c65159SKalle Valo struct sk_buff *skb) 1695d5c65159SKalle Valo { 1696d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 1697d5c65159SKalle Valo struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1698d5c65159SKalle Valo enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1699d5c65159SKalle Valo u16 peer_id; 1700d5c65159SKalle Valo u8 vdev_id; 1701d5c65159SKalle Valo u8 mac_addr[ETH_ALEN]; 1702d5c65159SKalle Valo u16 peer_mac_h16; 1703d5c65159SKalle Valo u16 ast_hash; 17044b965be5SKarthikeyan Periyasamy u16 hw_peer_id; 1705d5c65159SKalle Valo 1706d5c65159SKalle Valo ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1707d5c65159SKalle Valo 1708d5c65159SKalle Valo switch (type) { 1709d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: 1710d5c65159SKalle Valo dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1711d5c65159SKalle Valo resp->version_msg.version); 1712d5c65159SKalle Valo dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1713d5c65159SKalle Valo resp->version_msg.version); 1714d5c65159SKalle Valo complete(&dp->htt_tgt_version_received); 1715d5c65159SKalle Valo break; 1716d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: 1717a6275302SCarl Huang vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1718a6275302SCarl Huang resp->peer_map_ev.info); 1719a6275302SCarl Huang peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1720a6275302SCarl Huang resp->peer_map_ev.info); 1721a6275302SCarl Huang peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1722a6275302SCarl Huang resp->peer_map_ev.info1); 1723a6275302SCarl Huang ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1724a6275302SCarl Huang peer_mac_h16, mac_addr); 17254b965be5SKarthikeyan Periyasamy ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1726a6275302SCarl Huang break; 172713ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_MAP2: 1728d5c65159SKalle Valo vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1729d5c65159SKalle Valo resp->peer_map_ev.info); 1730d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1731d5c65159SKalle Valo resp->peer_map_ev.info); 1732d5c65159SKalle Valo peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1733d5c65159SKalle Valo resp->peer_map_ev.info1); 1734d5c65159SKalle Valo ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1735d5c65159SKalle Valo peer_mac_h16, mac_addr); 1736d5c65159SKalle Valo ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 17370f37fbf4SAnilkumar Kolli resp->peer_map_ev.info2); 17384b965be5SKarthikeyan Periyasamy hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID, 17394b965be5SKarthikeyan Periyasamy resp->peer_map_ev.info1); 17404b965be5SKarthikeyan Periyasamy ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 17414b965be5SKarthikeyan Periyasamy hw_peer_id); 1742d5c65159SKalle Valo break; 1743d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: 174413ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1745d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1746d5c65159SKalle Valo resp->peer_unmap_ev.info); 1747d5c65159SKalle Valo ath11k_peer_unmap_event(ab, peer_id); 1748d5c65159SKalle Valo break; 1749d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1750d5c65159SKalle Valo ath11k_htt_pull_ppdu_stats(ab, skb); 1751d5c65159SKalle Valo break; 1752d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1753568f0603SKalle Valo ath11k_debugfs_htt_ext_stats_handler(ab, skb); 1754d5c65159SKalle Valo break; 1755d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PKTLOG: 1756d5c65159SKalle Valo ath11k_htt_pktlog(ab, skb); 1757d5c65159SKalle Valo break; 1758678e8414SSriram R case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1759678e8414SSriram R ath11k_htt_backpressure_event_handler(ab, skb); 1760678e8414SSriram R break; 1761d5c65159SKalle Valo default: 1762d5c65159SKalle Valo ath11k_warn(ab, "htt event %d not handled\n", type); 1763d5c65159SKalle Valo break; 1764d5c65159SKalle Valo } 1765d5c65159SKalle Valo 1766d5c65159SKalle Valo dev_kfree_skb_any(skb); 1767d5c65159SKalle Valo } 1768d5c65159SKalle Valo 1769d5c65159SKalle Valo static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1770d5c65159SKalle Valo struct sk_buff_head *msdu_list, 1771d5c65159SKalle Valo struct sk_buff *first, struct sk_buff *last, 1772d5c65159SKalle Valo u8 l3pad_bytes, int msdu_len) 1773d5c65159SKalle Valo { 1774e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 1775d5c65159SKalle Valo struct sk_buff *skb; 1776d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1777d2f510faSSriram R int buf_first_hdr_len, buf_first_len; 1778d5c65159SKalle Valo struct hal_rx_desc *ldesc; 1779e678fbd4SKarthikeyan Periyasamy int space_extra, rem_len, buf_len; 1780e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 1781d5c65159SKalle Valo 1782d2f510faSSriram R /* As the msdu is spread across multiple rx buffers, 1783d2f510faSSriram R * find the offset to the start of msdu for computing 1784d2f510faSSriram R * the length of the msdu in the first buffer. 1785d2f510faSSriram R */ 1786e678fbd4SKarthikeyan Periyasamy buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1787d2f510faSSriram R buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1788d2f510faSSriram R 1789d2f510faSSriram R if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1790d2f510faSSriram R skb_put(first, buf_first_hdr_len + msdu_len); 1791d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1792d5c65159SKalle Valo return 0; 1793d5c65159SKalle Valo } 1794d5c65159SKalle Valo 1795d5c65159SKalle Valo ldesc = (struct hal_rx_desc *)last->data; 1796e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc); 1797e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc); 1798d5c65159SKalle Valo 1799d5c65159SKalle Valo /* MSDU spans over multiple buffers because the length of the MSDU 1800d5c65159SKalle Valo * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1801d5c65159SKalle Valo * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1802d5c65159SKalle Valo */ 1803d5c65159SKalle Valo skb_put(first, DP_RX_BUFFER_SIZE); 1804d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1805d5c65159SKalle Valo 180630679ec4SKarthikeyan Periyasamy /* When an MSDU spread over multiple buffers attention, MSDU_END and 180730679ec4SKarthikeyan Periyasamy * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 180830679ec4SKarthikeyan Periyasamy */ 1809e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 181030679ec4SKarthikeyan Periyasamy 1811d2f510faSSriram R space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1812d5c65159SKalle Valo if (space_extra > 0 && 1813d5c65159SKalle Valo (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1814d5c65159SKalle Valo /* Free up all buffers of the MSDU */ 1815d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1816d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1817d5c65159SKalle Valo if (!rxcb->is_continuation) { 1818d5c65159SKalle Valo dev_kfree_skb_any(skb); 1819d5c65159SKalle Valo break; 1820d5c65159SKalle Valo } 1821d5c65159SKalle Valo dev_kfree_skb_any(skb); 1822d5c65159SKalle Valo } 1823d5c65159SKalle Valo return -ENOMEM; 1824d5c65159SKalle Valo } 1825d5c65159SKalle Valo 1826d2f510faSSriram R rem_len = msdu_len - buf_first_len; 1827d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1828d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1829d5c65159SKalle Valo if (rxcb->is_continuation) 1830e678fbd4SKarthikeyan Periyasamy buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1831d5c65159SKalle Valo else 1832d5c65159SKalle Valo buf_len = rem_len; 1833d5c65159SKalle Valo 1834e678fbd4SKarthikeyan Periyasamy if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1835d5c65159SKalle Valo WARN_ON_ONCE(1); 1836d5c65159SKalle Valo dev_kfree_skb_any(skb); 1837d5c65159SKalle Valo return -EINVAL; 1838d5c65159SKalle Valo } 1839d5c65159SKalle Valo 1840e678fbd4SKarthikeyan Periyasamy skb_put(skb, buf_len + hal_rx_desc_sz); 1841e678fbd4SKarthikeyan Periyasamy skb_pull(skb, hal_rx_desc_sz); 1842d5c65159SKalle Valo skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1843d5c65159SKalle Valo buf_len); 1844d5c65159SKalle Valo dev_kfree_skb_any(skb); 1845d5c65159SKalle Valo 1846d5c65159SKalle Valo rem_len -= buf_len; 1847d5c65159SKalle Valo if (!rxcb->is_continuation) 1848d5c65159SKalle Valo break; 1849d5c65159SKalle Valo } 1850d5c65159SKalle Valo 1851d5c65159SKalle Valo return 0; 1852d5c65159SKalle Valo } 1853d5c65159SKalle Valo 1854d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1855d5c65159SKalle Valo struct sk_buff *first) 1856d5c65159SKalle Valo { 1857d5c65159SKalle Valo struct sk_buff *skb; 1858d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1859d5c65159SKalle Valo 1860d5c65159SKalle Valo if (!rxcb->is_continuation) 1861d5c65159SKalle Valo return first; 1862d5c65159SKalle Valo 1863d5c65159SKalle Valo skb_queue_walk(msdu_list, skb) { 1864d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1865d5c65159SKalle Valo if (!rxcb->is_continuation) 1866d5c65159SKalle Valo return skb; 1867d5c65159SKalle Valo } 1868d5c65159SKalle Valo 1869d5c65159SKalle Valo return NULL; 1870d5c65159SKalle Valo } 1871d5c65159SKalle Valo 1872e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu) 1873d5c65159SKalle Valo { 1874d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1875e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 1876d5c65159SKalle Valo bool ip_csum_fail, l4_csum_fail; 1877d5c65159SKalle Valo 1878e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc); 1879e678fbd4SKarthikeyan Periyasamy ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention); 1880e678fbd4SKarthikeyan Periyasamy l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention); 1881d5c65159SKalle Valo 1882d5c65159SKalle Valo msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1883d5c65159SKalle Valo CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1884d5c65159SKalle Valo } 1885d5c65159SKalle Valo 1886d5c65159SKalle Valo static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1887d5c65159SKalle Valo enum hal_encrypt_type enctype) 1888d5c65159SKalle Valo { 1889d5c65159SKalle Valo switch (enctype) { 1890d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1891d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1892d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1893d5c65159SKalle Valo return 0; 1894d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1895d5c65159SKalle Valo return IEEE80211_CCMP_MIC_LEN; 1896d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1897d5c65159SKalle Valo return IEEE80211_CCMP_256_MIC_LEN; 1898d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1899d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1900d5c65159SKalle Valo return IEEE80211_GCMP_MIC_LEN; 1901d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1902d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1903d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1904d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1905d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1906d5c65159SKalle Valo break; 1907d5c65159SKalle Valo } 1908d5c65159SKalle Valo 1909d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1910d5c65159SKalle Valo return 0; 1911d5c65159SKalle Valo } 1912d5c65159SKalle Valo 1913d5c65159SKalle Valo static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1914d5c65159SKalle Valo enum hal_encrypt_type enctype) 1915d5c65159SKalle Valo { 1916d5c65159SKalle Valo switch (enctype) { 1917d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1918d5c65159SKalle Valo return 0; 1919d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1920d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1921d5c65159SKalle Valo return IEEE80211_TKIP_IV_LEN; 1922d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1923d5c65159SKalle Valo return IEEE80211_CCMP_HDR_LEN; 1924d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1925d5c65159SKalle Valo return IEEE80211_CCMP_256_HDR_LEN; 1926d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1927d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1928d5c65159SKalle Valo return IEEE80211_GCMP_HDR_LEN; 1929d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1930d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1931d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1932d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1933d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1934d5c65159SKalle Valo break; 1935d5c65159SKalle Valo } 1936d5c65159SKalle Valo 1937d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1938d5c65159SKalle Valo return 0; 1939d5c65159SKalle Valo } 1940d5c65159SKalle Valo 1941d5c65159SKalle Valo static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1942d5c65159SKalle Valo enum hal_encrypt_type enctype) 1943d5c65159SKalle Valo { 1944d5c65159SKalle Valo switch (enctype) { 1945d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1946d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1947d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1948d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1949d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1950d5c65159SKalle Valo return 0; 1951d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1952d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1953d5c65159SKalle Valo return IEEE80211_TKIP_ICV_LEN; 1954d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1955d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1956d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1957d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1958d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1959d5c65159SKalle Valo break; 1960d5c65159SKalle Valo } 1961d5c65159SKalle Valo 1962d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1963d5c65159SKalle Valo return 0; 1964d5c65159SKalle Valo } 1965d5c65159SKalle Valo 1966d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1967d5c65159SKalle Valo struct sk_buff *msdu, 1968d5c65159SKalle Valo u8 *first_hdr, 1969d5c65159SKalle Valo enum hal_encrypt_type enctype, 1970d5c65159SKalle Valo struct ieee80211_rx_status *status) 1971d5c65159SKalle Valo { 1972acc79d98SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1973acc79d98SSriram R u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1974d5c65159SKalle Valo struct ieee80211_hdr *hdr; 1975d5c65159SKalle Valo size_t hdr_len; 1976d5c65159SKalle Valo u8 da[ETH_ALEN]; 1977d5c65159SKalle Valo u8 sa[ETH_ALEN]; 1978acc79d98SSriram R u16 qos_ctl = 0; 1979acc79d98SSriram R u8 *qos; 1980d5c65159SKalle Valo 1981acc79d98SSriram R /* copy SA & DA and pull decapped header */ 1982d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 1983acc79d98SSriram R hdr_len = ieee80211_hdrlen(hdr->frame_control); 1984d5c65159SKalle Valo ether_addr_copy(da, ieee80211_get_DA(hdr)); 1985d5c65159SKalle Valo ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1986d5c65159SKalle Valo skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1987d5c65159SKalle Valo 1988acc79d98SSriram R if (rxcb->is_first_msdu) { 1989acc79d98SSriram R /* original 802.11 header is valid for the first msdu 1990acc79d98SSriram R * hence we can reuse the same header 1991acc79d98SSriram R */ 1992d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 1993d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 1994d5c65159SKalle Valo 1995acc79d98SSriram R /* Each A-MSDU subframe will be reported as a separate MSDU, 1996acc79d98SSriram R * so strip the A-MSDU bit from QoS Ctl. 1997acc79d98SSriram R */ 1998acc79d98SSriram R if (ieee80211_is_data_qos(hdr->frame_control)) { 1999acc79d98SSriram R qos = ieee80211_get_qos_ctl(hdr); 2000acc79d98SSriram R qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 2001acc79d98SSriram R } 2002acc79d98SSriram R } else { 2003acc79d98SSriram R /* Rebuild qos header if this is a middle/last msdu */ 2004acc79d98SSriram R hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 2005acc79d98SSriram R 2006acc79d98SSriram R /* Reset the order bit as the HT_Control header is stripped */ 2007acc79d98SSriram R hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 2008acc79d98SSriram R 2009acc79d98SSriram R qos_ctl = rxcb->tid; 2010acc79d98SSriram R 2011e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc)) 2012acc79d98SSriram R qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2013acc79d98SSriram R 2014acc79d98SSriram R /* TODO Add other QoS ctl fields when required */ 2015acc79d98SSriram R 2016acc79d98SSriram R /* copy decap header before overwriting for reuse below */ 2017acc79d98SSriram R memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 2018acc79d98SSriram R } 2019acc79d98SSriram R 2020d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2021d5c65159SKalle Valo memcpy(skb_push(msdu, 2022d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 2023d5c65159SKalle Valo (void *)hdr + hdr_len, 2024d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 2025d5c65159SKalle Valo } 2026d5c65159SKalle Valo 2027acc79d98SSriram R if (!rxcb->is_first_msdu) { 2028acc79d98SSriram R memcpy(skb_push(msdu, 2029acc79d98SSriram R IEEE80211_QOS_CTL_LEN), &qos_ctl, 2030acc79d98SSriram R IEEE80211_QOS_CTL_LEN); 2031acc79d98SSriram R memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2032acc79d98SSriram R return; 2033acc79d98SSriram R } 2034acc79d98SSriram R 2035d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2036d5c65159SKalle Valo 2037d5c65159SKalle Valo /* original 802.11 header has a different DA and in 2038d5c65159SKalle Valo * case of 4addr it may also have different SA 2039d5c65159SKalle Valo */ 2040d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 2041d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 2042d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 2043d5c65159SKalle Valo } 2044d5c65159SKalle Valo 2045d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 2046d5c65159SKalle Valo enum hal_encrypt_type enctype, 2047d5c65159SKalle Valo struct ieee80211_rx_status *status, 2048d5c65159SKalle Valo bool decrypted) 2049d5c65159SKalle Valo { 2050d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2051d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2052d5c65159SKalle Valo size_t hdr_len; 2053d5c65159SKalle Valo size_t crypto_len; 2054d5c65159SKalle Valo 2055d5c65159SKalle Valo if (!rxcb->is_first_msdu || 2056d5c65159SKalle Valo !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2057d5c65159SKalle Valo WARN_ON_ONCE(1); 2058d5c65159SKalle Valo return; 2059d5c65159SKalle Valo } 2060d5c65159SKalle Valo 2061d5c65159SKalle Valo skb_trim(msdu, msdu->len - FCS_LEN); 2062d5c65159SKalle Valo 2063d5c65159SKalle Valo if (!decrypted) 2064d5c65159SKalle Valo return; 2065d5c65159SKalle Valo 2066d5c65159SKalle Valo hdr = (void *)msdu->data; 2067d5c65159SKalle Valo 2068d5c65159SKalle Valo /* Tail */ 2069d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 2070d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2071d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2072d5c65159SKalle Valo 2073d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2074d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2075d5c65159SKalle Valo } else { 2076d5c65159SKalle Valo /* MIC */ 2077d5c65159SKalle Valo if (status->flag & RX_FLAG_MIC_STRIPPED) 2078d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2079d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2080d5c65159SKalle Valo 2081d5c65159SKalle Valo /* ICV */ 2082d5c65159SKalle Valo if (status->flag & RX_FLAG_ICV_STRIPPED) 2083d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2084d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2085d5c65159SKalle Valo } 2086d5c65159SKalle Valo 2087d5c65159SKalle Valo /* MMIC */ 2088d5c65159SKalle Valo if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2089d5c65159SKalle Valo !ieee80211_has_morefrags(hdr->frame_control) && 2090d5c65159SKalle Valo enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2091d5c65159SKalle Valo skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2092d5c65159SKalle Valo 2093d5c65159SKalle Valo /* Head */ 2094d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 2095d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2096d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2097d5c65159SKalle Valo 2098d5c65159SKalle Valo memmove((void *)msdu->data + crypto_len, 2099d5c65159SKalle Valo (void *)msdu->data, hdr_len); 2100d5c65159SKalle Valo skb_pull(msdu, crypto_len); 2101d5c65159SKalle Valo } 2102d5c65159SKalle Valo } 2103d5c65159SKalle Valo 2104d5c65159SKalle Valo static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 2105d5c65159SKalle Valo struct sk_buff *msdu, 2106d5c65159SKalle Valo enum hal_encrypt_type enctype) 2107d5c65159SKalle Valo { 2108d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2109d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2110d5c65159SKalle Valo size_t hdr_len, crypto_len; 2111d5c65159SKalle Valo void *rfc1042; 2112d5c65159SKalle Valo bool is_amsdu; 2113d5c65159SKalle Valo 2114d5c65159SKalle Valo is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 2115e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc); 2116d5c65159SKalle Valo rfc1042 = hdr; 2117d5c65159SKalle Valo 2118d5c65159SKalle Valo if (rxcb->is_first_msdu) { 2119d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2120d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2121d5c65159SKalle Valo 2122d5c65159SKalle Valo rfc1042 += hdr_len + crypto_len; 2123d5c65159SKalle Valo } 2124d5c65159SKalle Valo 2125d5c65159SKalle Valo if (is_amsdu) 2126d5c65159SKalle Valo rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 2127d5c65159SKalle Valo 2128d5c65159SKalle Valo return rfc1042; 2129d5c65159SKalle Valo } 2130d5c65159SKalle Valo 2131d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 2132d5c65159SKalle Valo struct sk_buff *msdu, 2133d5c65159SKalle Valo u8 *first_hdr, 2134d5c65159SKalle Valo enum hal_encrypt_type enctype, 2135d5c65159SKalle Valo struct ieee80211_rx_status *status) 2136d5c65159SKalle Valo { 2137d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2138d5c65159SKalle Valo struct ethhdr *eth; 2139d5c65159SKalle Valo size_t hdr_len; 2140d5c65159SKalle Valo u8 da[ETH_ALEN]; 2141d5c65159SKalle Valo u8 sa[ETH_ALEN]; 2142d5c65159SKalle Valo void *rfc1042; 2143d5c65159SKalle Valo 2144d5c65159SKalle Valo rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 2145d5c65159SKalle Valo if (WARN_ON_ONCE(!rfc1042)) 2146d5c65159SKalle Valo return; 2147d5c65159SKalle Valo 2148d5c65159SKalle Valo /* pull decapped header and copy SA & DA */ 2149d5c65159SKalle Valo eth = (struct ethhdr *)msdu->data; 2150d5c65159SKalle Valo ether_addr_copy(da, eth->h_dest); 2151d5c65159SKalle Valo ether_addr_copy(sa, eth->h_source); 2152d5c65159SKalle Valo skb_pull(msdu, sizeof(struct ethhdr)); 2153d5c65159SKalle Valo 2154d5c65159SKalle Valo /* push rfc1042/llc/snap */ 2155d5c65159SKalle Valo memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 2156d5c65159SKalle Valo sizeof(struct ath11k_dp_rfc1042_hdr)); 2157d5c65159SKalle Valo 2158d5c65159SKalle Valo /* push original 802.11 header */ 2159d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 2160d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2161d5c65159SKalle Valo 2162d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2163d5c65159SKalle Valo memcpy(skb_push(msdu, 2164d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 2165d5c65159SKalle Valo (void *)hdr + hdr_len, 2166d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 2167d5c65159SKalle Valo } 2168d5c65159SKalle Valo 2169d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2170d5c65159SKalle Valo 2171d5c65159SKalle Valo /* original 802.11 header has a different DA and in 2172d5c65159SKalle Valo * case of 4addr it may also have different SA 2173d5c65159SKalle Valo */ 2174d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 2175d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 2176d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 2177d5c65159SKalle Valo } 2178d5c65159SKalle Valo 2179d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 2180d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2181d5c65159SKalle Valo enum hal_encrypt_type enctype, 2182d5c65159SKalle Valo struct ieee80211_rx_status *status, 2183d5c65159SKalle Valo bool decrypted) 2184d5c65159SKalle Valo { 2185d5c65159SKalle Valo u8 *first_hdr; 2186d5c65159SKalle Valo u8 decap; 21872167fa60SSriram R struct ethhdr *ehdr; 2188d5c65159SKalle Valo 2189e678fbd4SKarthikeyan Periyasamy first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 2190e678fbd4SKarthikeyan Periyasamy decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc); 2191d5c65159SKalle Valo 2192d5c65159SKalle Valo switch (decap) { 2193d5c65159SKalle Valo case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2194d5c65159SKalle Valo ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2195d5c65159SKalle Valo enctype, status); 2196d5c65159SKalle Valo break; 2197d5c65159SKalle Valo case DP_RX_DECAP_TYPE_RAW: 2198d5c65159SKalle Valo ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2199d5c65159SKalle Valo decrypted); 2200d5c65159SKalle Valo break; 2201d5c65159SKalle Valo case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 22022167fa60SSriram R ehdr = (struct ethhdr *)msdu->data; 22032167fa60SSriram R 22042167fa60SSriram R /* mac80211 allows fast path only for authorized STA */ 22052167fa60SSriram R if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 22062167fa60SSriram R ATH11K_SKB_RXCB(msdu)->is_eapol = true; 22072167fa60SSriram R ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 22082167fa60SSriram R enctype, status); 22092167fa60SSriram R break; 22102167fa60SSriram R } 22112167fa60SSriram R 22122167fa60SSriram R /* PN for mcast packets will be validated in mac80211; 22132167fa60SSriram R * remove eth header and add 802.11 header. 22142167fa60SSriram R */ 22152167fa60SSriram R if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2216d5c65159SKalle Valo ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2217d5c65159SKalle Valo enctype, status); 2218d5c65159SKalle Valo break; 2219d5c65159SKalle Valo case DP_RX_DECAP_TYPE_8023: 2220d5c65159SKalle Valo /* TODO: Handle undecap for these formats */ 2221d5c65159SKalle Valo break; 2222d5c65159SKalle Valo } 2223d5c65159SKalle Valo } 2224d5c65159SKalle Valo 22252167fa60SSriram R static struct ath11k_peer * 22262167fa60SSriram R ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu) 22272167fa60SSriram R { 22282167fa60SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 22292167fa60SSriram R struct hal_rx_desc *rx_desc = rxcb->rx_desc; 22302167fa60SSriram R struct ath11k_peer *peer = NULL; 22312167fa60SSriram R 22322167fa60SSriram R lockdep_assert_held(&ab->base_lock); 22332167fa60SSriram R 22342167fa60SSriram R if (rxcb->peer_id) 22352167fa60SSriram R peer = ath11k_peer_find_by_id(ab, rxcb->peer_id); 22362167fa60SSriram R 22372167fa60SSriram R if (peer) 22382167fa60SSriram R return peer; 22392167fa60SSriram R 22402167fa60SSriram R if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 22412167fa60SSriram R return NULL; 22422167fa60SSriram R 22432167fa60SSriram R peer = ath11k_peer_find_by_addr(ab, 22442167fa60SSriram R ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc)); 22452167fa60SSriram R return peer; 22462167fa60SSriram R } 22472167fa60SSriram R 2248d5c65159SKalle Valo static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2249acc79d98SSriram R struct sk_buff *msdu, 2250d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2251d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2252d5c65159SKalle Valo { 22532167fa60SSriram R bool fill_crypto_hdr; 2254d5c65159SKalle Valo enum hal_encrypt_type enctype; 2255acc79d98SSriram R bool is_decrypted = false; 22562167fa60SSriram R struct ath11k_skb_rxcb *rxcb; 2257acc79d98SSriram R struct ieee80211_hdr *hdr; 2258acc79d98SSriram R struct ath11k_peer *peer; 2259e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 2260d5c65159SKalle Valo u32 err_bitmap; 2261d5c65159SKalle Valo 22621441b2f2SManikanta Pubbisetty /* PN for multicast packets will be checked in mac80211 */ 22632167fa60SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 22642167fa60SSriram R fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 22652167fa60SSriram R rxcb->is_mcbc = fill_crypto_hdr; 2266acc79d98SSriram R 22672167fa60SSriram R if (rxcb->is_mcbc) { 22682167fa60SSriram R rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 22692167fa60SSriram R rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 22702167fa60SSriram R } 22711441b2f2SManikanta Pubbisetty 2272acc79d98SSriram R spin_lock_bh(&ar->ab->base_lock); 22732167fa60SSriram R peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2274acc79d98SSriram R if (peer) { 22752167fa60SSriram R if (rxcb->is_mcbc) 2276acc79d98SSriram R enctype = peer->sec_type_grp; 2277acc79d98SSriram R else 2278acc79d98SSriram R enctype = peer->sec_type; 2279acc79d98SSriram R } else { 22802167fa60SSriram R enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 2281acc79d98SSriram R } 2282acc79d98SSriram R spin_unlock_bh(&ar->ab->base_lock); 2283d5c65159SKalle Valo 2284e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 2285e678fbd4SKarthikeyan Periyasamy err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 2286aa2092a9SVenkateswara Naralasetty if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2287e678fbd4SKarthikeyan Periyasamy is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 2288d5c65159SKalle Valo 2289acc79d98SSriram R /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2290d5c65159SKalle Valo rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2291d5c65159SKalle Valo RX_FLAG_MMIC_ERROR | 2292d5c65159SKalle Valo RX_FLAG_DECRYPTED | 2293d5c65159SKalle Valo RX_FLAG_IV_STRIPPED | 2294d5c65159SKalle Valo RX_FLAG_MMIC_STRIPPED); 2295d5c65159SKalle Valo 2296d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2297d5c65159SKalle Valo rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2298d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2299d5c65159SKalle Valo rx_status->flag |= RX_FLAG_MMIC_ERROR; 2300d5c65159SKalle Valo 23011441b2f2SManikanta Pubbisetty if (is_decrypted) { 23021441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 23031441b2f2SManikanta Pubbisetty 23041441b2f2SManikanta Pubbisetty if (fill_crypto_hdr) 23051441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_MIC_STRIPPED | 23061441b2f2SManikanta Pubbisetty RX_FLAG_ICV_STRIPPED; 23071441b2f2SManikanta Pubbisetty else 23081441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_IV_STRIPPED | 23091441b2f2SManikanta Pubbisetty RX_FLAG_PN_VALIDATED; 23101441b2f2SManikanta Pubbisetty } 2311d5c65159SKalle Valo 2312e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_h_csum_offload(ar, msdu); 2313d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2314d5c65159SKalle Valo enctype, rx_status, is_decrypted); 23151441b2f2SManikanta Pubbisetty 23161441b2f2SManikanta Pubbisetty if (!is_decrypted || fill_crypto_hdr) 2317acc79d98SSriram R return; 23181441b2f2SManikanta Pubbisetty 23192167fa60SSriram R if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) != 23202167fa60SSriram R DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 23211441b2f2SManikanta Pubbisetty hdr = (void *)msdu->data; 23221441b2f2SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2323d5c65159SKalle Valo } 23242167fa60SSriram R } 2325d5c65159SKalle Valo 2326d5c65159SKalle Valo static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2327d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2328d5c65159SKalle Valo { 2329d5c65159SKalle Valo struct ieee80211_supported_band *sband; 2330d5c65159SKalle Valo enum rx_msdu_start_pkt_type pkt_type; 2331d5c65159SKalle Valo u8 bw; 2332d5c65159SKalle Valo u8 rate_mcs, nss; 2333d5c65159SKalle Valo u8 sgi; 2334d5c65159SKalle Valo bool is_cck; 2335d5c65159SKalle Valo 2336e678fbd4SKarthikeyan Periyasamy pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc); 2337e678fbd4SKarthikeyan Periyasamy bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc); 2338e678fbd4SKarthikeyan Periyasamy rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc); 2339e678fbd4SKarthikeyan Periyasamy nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc); 2340e678fbd4SKarthikeyan Periyasamy sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc); 2341d5c65159SKalle Valo 2342d5c65159SKalle Valo switch (pkt_type) { 2343d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11A: 2344d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11B: 2345d5c65159SKalle Valo is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2346d5c65159SKalle Valo sband = &ar->mac.sbands[rx_status->band]; 2347d5c65159SKalle Valo rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2348d5c65159SKalle Valo is_cck); 2349d5c65159SKalle Valo break; 2350d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11N: 2351d5c65159SKalle Valo rx_status->encoding = RX_ENC_HT; 2352d5c65159SKalle Valo if (rate_mcs > ATH11K_HT_MCS_MAX) { 2353d5c65159SKalle Valo ath11k_warn(ar->ab, 2354d5c65159SKalle Valo "Received with invalid mcs in HT mode %d\n", 2355d5c65159SKalle Valo rate_mcs); 2356d5c65159SKalle Valo break; 2357d5c65159SKalle Valo } 2358d5c65159SKalle Valo rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2359d5c65159SKalle Valo if (sgi) 2360d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 236139e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2362d5c65159SKalle Valo break; 2363d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AC: 2364d5c65159SKalle Valo rx_status->encoding = RX_ENC_VHT; 2365d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2366d5c65159SKalle Valo if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2367d5c65159SKalle Valo ath11k_warn(ar->ab, 2368d5c65159SKalle Valo "Received with invalid mcs in VHT mode %d\n", 2369d5c65159SKalle Valo rate_mcs); 2370d5c65159SKalle Valo break; 2371d5c65159SKalle Valo } 2372d5c65159SKalle Valo rx_status->nss = nss; 2373d5c65159SKalle Valo if (sgi) 2374d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 237539e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2376d5c65159SKalle Valo break; 2377d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AX: 2378d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2379d5c65159SKalle Valo if (rate_mcs > ATH11K_HE_MCS_MAX) { 2380d5c65159SKalle Valo ath11k_warn(ar->ab, 2381d5c65159SKalle Valo "Received with invalid mcs in HE mode %d\n", 2382d5c65159SKalle Valo rate_mcs); 2383d5c65159SKalle Valo break; 2384d5c65159SKalle Valo } 2385d5c65159SKalle Valo rx_status->encoding = RX_ENC_HE; 2386d5c65159SKalle Valo rx_status->nss = nss; 23876a0c3702SJohn Crispin rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 238839e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2389d5c65159SKalle Valo break; 2390d5c65159SKalle Valo } 2391d5c65159SKalle Valo } 2392d5c65159SKalle Valo 2393d5c65159SKalle Valo static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2394d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2395d5c65159SKalle Valo { 2396d5c65159SKalle Valo u8 channel_num; 2397e678fbd4SKarthikeyan Periyasamy u32 center_freq, meta_data; 239835970106SCarl Huang struct ieee80211_channel *channel; 2399d5c65159SKalle Valo 2400d5c65159SKalle Valo rx_status->freq = 0; 2401d5c65159SKalle Valo rx_status->rate_idx = 0; 2402d5c65159SKalle Valo rx_status->nss = 0; 2403d5c65159SKalle Valo rx_status->encoding = RX_ENC_LEGACY; 2404d5c65159SKalle Valo rx_status->bw = RATE_INFO_BW_20; 2405d5c65159SKalle Valo 2406d5c65159SKalle Valo rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2407d5c65159SKalle Valo 2408e678fbd4SKarthikeyan Periyasamy meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc); 2409e678fbd4SKarthikeyan Periyasamy channel_num = meta_data; 2410e678fbd4SKarthikeyan Periyasamy center_freq = meta_data >> 16; 2411d5c65159SKalle Valo 24129d6ae1f5SPradeep Kumar Chitrapu if (center_freq >= ATH11K_MIN_6G_FREQ && 24139d6ae1f5SPradeep Kumar Chitrapu center_freq <= ATH11K_MAX_6G_FREQ) { 24145dcf42f8SPradeep Kumar Chitrapu rx_status->band = NL80211_BAND_6GHZ; 24159d6ae1f5SPradeep Kumar Chitrapu rx_status->freq = center_freq; 24165dcf42f8SPradeep Kumar Chitrapu } else if (channel_num >= 1 && channel_num <= 14) { 2417d5c65159SKalle Valo rx_status->band = NL80211_BAND_2GHZ; 2418d5c65159SKalle Valo } else if (channel_num >= 36 && channel_num <= 173) { 2419d5c65159SKalle Valo rx_status->band = NL80211_BAND_5GHZ; 2420d5c65159SKalle Valo } else { 2421de06b2f7SVenkateswara Naralasetty spin_lock_bh(&ar->data_lock); 242235970106SCarl Huang channel = ar->rx_channel; 242335970106SCarl Huang if (channel) { 242435970106SCarl Huang rx_status->band = channel->band; 2425de06b2f7SVenkateswara Naralasetty channel_num = 242635970106SCarl Huang ieee80211_frequency_to_channel(channel->center_freq); 242735970106SCarl Huang } 2428de06b2f7SVenkateswara Naralasetty spin_unlock_bh(&ar->data_lock); 2429de06b2f7SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2430de06b2f7SVenkateswara Naralasetty rx_desc, sizeof(struct hal_rx_desc)); 2431d5c65159SKalle Valo } 2432d5c65159SKalle Valo 24339d6ae1f5SPradeep Kumar Chitrapu if (rx_status->band != NL80211_BAND_6GHZ) 2434d5c65159SKalle Valo rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2435d5c65159SKalle Valo rx_status->band); 2436d5c65159SKalle Valo 2437d5c65159SKalle Valo ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2438d5c65159SKalle Valo } 2439d5c65159SKalle Valo 2440d5c65159SKalle Valo static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 24412167fa60SSriram R struct sk_buff *msdu, 24422167fa60SSriram R struct ieee80211_rx_status *status) 2443d5c65159SKalle Valo { 2444e4eb7b5cSJohn Crispin static const struct ieee80211_radiotap_he known = { 244593634c61SJohn Crispin .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 244693634c61SJohn Crispin IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2447e4eb7b5cSJohn Crispin .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2448e4eb7b5cSJohn Crispin }; 24492167fa60SSriram R struct ieee80211_rx_status *rx_status; 2450e4eb7b5cSJohn Crispin struct ieee80211_radiotap_he *he = NULL; 24512167fa60SSriram R struct ieee80211_sta *pubsta = NULL; 24522167fa60SSriram R struct ath11k_peer *peer; 24532167fa60SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 24542167fa60SSriram R u8 decap = DP_RX_DECAP_TYPE_RAW; 24552167fa60SSriram R bool is_mcbc = rxcb->is_mcbc; 24562167fa60SSriram R bool is_eapol = rxcb->is_eapol; 2457d5c65159SKalle Valo 24582167fa60SSriram R if (status->encoding == RX_ENC_HE && 24592167fa60SSriram R !(status->flag & RX_FLAG_RADIOTAP_HE) && 24602167fa60SSriram R !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2461e4eb7b5cSJohn Crispin he = skb_push(msdu, sizeof(known)); 2462e4eb7b5cSJohn Crispin memcpy(he, &known, sizeof(known)); 2463e4eb7b5cSJohn Crispin status->flag |= RX_FLAG_RADIOTAP_HE; 2464e4eb7b5cSJohn Crispin } 2465d5c65159SKalle Valo 24662167fa60SSriram R if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 24672167fa60SSriram R decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc); 24682167fa60SSriram R 24692167fa60SSriram R spin_lock_bh(&ar->ab->base_lock); 24702167fa60SSriram R peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 24712167fa60SSriram R if (peer && peer->sta) 24722167fa60SSriram R pubsta = peer->sta; 24732167fa60SSriram R spin_unlock_bh(&ar->ab->base_lock); 24742167fa60SSriram R 2475d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 24762167fa60SSriram R "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2477d5c65159SKalle Valo msdu, 2478d5c65159SKalle Valo msdu->len, 24792167fa60SSriram R peer ? peer->addr : NULL, 24802167fa60SSriram R rxcb->tid, 24812167fa60SSriram R is_mcbc ? "mcast" : "ucast", 24822167fa60SSriram R rxcb->seq_no, 2483d5c65159SKalle Valo (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2484d5c65159SKalle Valo (status->encoding == RX_ENC_HT) ? "ht" : "", 2485d5c65159SKalle Valo (status->encoding == RX_ENC_VHT) ? "vht" : "", 2486d5c65159SKalle Valo (status->encoding == RX_ENC_HE) ? "he" : "", 2487d5c65159SKalle Valo (status->bw == RATE_INFO_BW_40) ? "40" : "", 2488d5c65159SKalle Valo (status->bw == RATE_INFO_BW_80) ? "80" : "", 2489d5c65159SKalle Valo (status->bw == RATE_INFO_BW_160) ? "160" : "", 2490d5c65159SKalle Valo status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2491d5c65159SKalle Valo status->rate_idx, 2492d5c65159SKalle Valo status->nss, 2493d5c65159SKalle Valo status->freq, 2494d5c65159SKalle Valo status->band, status->flag, 2495d5c65159SKalle Valo !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2496d5c65159SKalle Valo !!(status->flag & RX_FLAG_MMIC_ERROR), 2497d5c65159SKalle Valo !!(status->flag & RX_FLAG_AMSDU_MORE)); 2498d5c65159SKalle Valo 2499aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ", 2500aa2092a9SVenkateswara Naralasetty msdu->data, msdu->len); 2501aa2092a9SVenkateswara Naralasetty 25022167fa60SSriram R rx_status = IEEE80211_SKB_RXCB(msdu); 25032167fa60SSriram R *rx_status = *status; 25042167fa60SSriram R 2505d5c65159SKalle Valo /* TODO: trace rx packet */ 2506d5c65159SKalle Valo 25072167fa60SSriram R /* PN for multicast packets are not validate in HW, 25082167fa60SSriram R * so skip 802.3 rx path 25092167fa60SSriram R * Also, fast_rx expectes the STA to be authorized, hence 25102167fa60SSriram R * eapol packets are sent in slow path. 25112167fa60SSriram R */ 25122167fa60SSriram R if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 25132167fa60SSriram R !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 25142167fa60SSriram R rx_status->flag |= RX_FLAG_8023; 25152167fa60SSriram R 25162167fa60SSriram R ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 2517d5c65159SKalle Valo } 2518d5c65159SKalle Valo 2519acc79d98SSriram R static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2520acc79d98SSriram R struct sk_buff *msdu, 25212167fa60SSriram R struct sk_buff_head *msdu_list, 25222167fa60SSriram R struct ieee80211_rx_status *rx_status) 2523d5c65159SKalle Valo { 2524e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 2525acc79d98SSriram R struct hal_rx_desc *rx_desc, *lrx_desc; 2526e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 2527acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2528acc79d98SSriram R struct sk_buff *last_buf; 2529acc79d98SSriram R u8 l3_pad_bytes; 2530d7d43782STamizh Chelvam u8 *hdr_status; 2531acc79d98SSriram R u16 msdu_len; 2532acc79d98SSriram R int ret; 2533e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 2534d5c65159SKalle Valo 2535acc79d98SSriram R last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2536acc79d98SSriram R if (!last_buf) { 2537e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, 2538acc79d98SSriram R "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2539acc79d98SSriram R ret = -EIO; 2540acc79d98SSriram R goto free_out; 2541d5c65159SKalle Valo } 2542acc79d98SSriram R 2543acc79d98SSriram R rx_desc = (struct hal_rx_desc *)msdu->data; 2544cd18ed4cSBaochen Qiang if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) { 2545cd18ed4cSBaochen Qiang ath11k_warn(ar->ab, "msdu len not valid\n"); 2546cd18ed4cSBaochen Qiang ret = -EIO; 2547cd18ed4cSBaochen Qiang goto free_out; 2548cd18ed4cSBaochen Qiang } 2549cd18ed4cSBaochen Qiang 2550acc79d98SSriram R lrx_desc = (struct hal_rx_desc *)last_buf->data; 2551e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc); 2552e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 2553e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, "msdu_done bit in attention is not set\n"); 2554acc79d98SSriram R ret = -EIO; 2555acc79d98SSriram R goto free_out; 2556acc79d98SSriram R } 2557acc79d98SSriram R 2558acc79d98SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 2559acc79d98SSriram R rxcb->rx_desc = rx_desc; 2560e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc); 2561e678fbd4SKarthikeyan Periyasamy l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc); 2562acc79d98SSriram R 2563acc79d98SSriram R if (rxcb->is_frag) { 2564e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 2565acc79d98SSriram R } else if (!rxcb->is_continuation) { 2566e678fbd4SKarthikeyan Periyasamy if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2567e678fbd4SKarthikeyan Periyasamy hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc); 2568acc79d98SSriram R ret = -EINVAL; 2569e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, "invalid msdu len %u\n", msdu_len); 2570e678fbd4SKarthikeyan Periyasamy ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2571d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 2572e678fbd4SKarthikeyan Periyasamy ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2573d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 2574acc79d98SSriram R goto free_out; 2575acc79d98SSriram R } 2576e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2577e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2578acc79d98SSriram R } else { 2579acc79d98SSriram R ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2580acc79d98SSriram R msdu, last_buf, 2581acc79d98SSriram R l3_pad_bytes, msdu_len); 2582acc79d98SSriram R if (ret) { 2583e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, 2584acc79d98SSriram R "failed to coalesce msdu rx buffer%d\n", ret); 2585acc79d98SSriram R goto free_out; 2586acc79d98SSriram R } 2587acc79d98SSriram R } 2588acc79d98SSriram R 25892167fa60SSriram R ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 25902167fa60SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2591acc79d98SSriram R 25922167fa60SSriram R rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2593acc79d98SSriram R 2594acc79d98SSriram R return 0; 2595acc79d98SSriram R 2596acc79d98SSriram R free_out: 2597acc79d98SSriram R return ret; 2598d5c65159SKalle Valo } 2599d5c65159SKalle Valo 2600acc79d98SSriram R static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2601d5c65159SKalle Valo struct napi_struct *napi, 2602acc79d98SSriram R struct sk_buff_head *msdu_list, 2603db2ecf9fSP Praneesh int mac_id) 2604d5c65159SKalle Valo { 2605d5c65159SKalle Valo struct sk_buff *msdu; 2606acc79d98SSriram R struct ath11k *ar; 26072167fa60SSriram R struct ieee80211_rx_status rx_status = {0}; 2608acc79d98SSriram R int ret; 2609d5c65159SKalle Valo 2610acc79d98SSriram R if (skb_queue_empty(msdu_list)) 2611d5c65159SKalle Valo return; 2612d5c65159SKalle Valo 261340058803SP Praneesh if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) { 2614c4d12cb3SP Praneesh __skb_queue_purge(msdu_list); 2615c4d12cb3SP Praneesh return; 2616acc79d98SSriram R } 2617acc79d98SSriram R 261840058803SP Praneesh ar = ab->pdevs[mac_id].ar; 261940058803SP Praneesh if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) { 2620c4d12cb3SP Praneesh __skb_queue_purge(msdu_list); 2621c4d12cb3SP Praneesh return; 2622acc79d98SSriram R } 2623acc79d98SSriram R 2624c4d12cb3SP Praneesh while ((msdu = __skb_dequeue(msdu_list))) { 26252167fa60SSriram R ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 262640058803SP Praneesh if (unlikely(ret)) { 2627acc79d98SSriram R ath11k_dbg(ab, ATH11K_DBG_DATA, 2628acc79d98SSriram R "Unable to process msdu %d", ret); 2629d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2630d5c65159SKalle Valo continue; 2631d5c65159SKalle Valo } 2632d5c65159SKalle Valo 26332167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2634d5c65159SKalle Valo } 2635d5c65159SKalle Valo } 2636d5c65159SKalle Valo 2637acc79d98SSriram R int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2638acc79d98SSriram R struct napi_struct *napi, int budget) 2639d5c65159SKalle Valo { 2640acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 2641acc79d98SSriram R struct dp_rxdma_ring *rx_ring; 2642acc79d98SSriram R int num_buffs_reaped[MAX_RADIOS] = {0}; 2643c4d12cb3SP Praneesh struct sk_buff_head msdu_list[MAX_RADIOS]; 2644acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2645acc79d98SSriram R int total_msdu_reaped = 0; 2646d5c65159SKalle Valo struct hal_srng *srng; 2647d5c65159SKalle Valo struct sk_buff *msdu; 2648d5c65159SKalle Valo bool done = false; 2649acc79d98SSriram R int buf_id, mac_id; 2650acc79d98SSriram R struct ath11k *ar; 2651c4d12cb3SP Praneesh struct hal_reo_dest_ring *desc; 2652c4d12cb3SP Praneesh enum hal_reo_dest_ring_push_reason push_reason; 2653c4d12cb3SP Praneesh u32 cookie; 2654acc79d98SSriram R int i; 2655d5c65159SKalle Valo 2656c4d12cb3SP Praneesh for (i = 0; i < MAX_RADIOS; i++) 2657c4d12cb3SP Praneesh __skb_queue_head_init(&msdu_list[i]); 2658d5c65159SKalle Valo 2659acc79d98SSriram R srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2660d5c65159SKalle Valo 2661d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2662d5c65159SKalle Valo 2663d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2664d5c65159SKalle Valo 2665d5c65159SKalle Valo try_again: 2666c4d12cb3SP Praneesh while (likely(desc = 2667c4d12cb3SP Praneesh (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab, 2668c4d12cb3SP Praneesh srng))) { 2669293cb583SJohn Crispin cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 2670c4d12cb3SP Praneesh desc->buf_addr_info.info1); 2671d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2672293cb583SJohn Crispin cookie); 2673acc79d98SSriram R mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2674acc79d98SSriram R 2675acc79d98SSriram R ar = ab->pdevs[mac_id].ar; 2676acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2677d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2678d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 267940058803SP Praneesh if (unlikely(!msdu)) { 2680d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2681d5c65159SKalle Valo buf_id); 2682d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2683d5c65159SKalle Valo continue; 2684d5c65159SKalle Valo } 2685d5c65159SKalle Valo 2686d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2687d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2688d5c65159SKalle Valo 2689d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 2690d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 2691d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 2692d5c65159SKalle Valo DMA_FROM_DEVICE); 2693d5c65159SKalle Valo 2694acc79d98SSriram R num_buffs_reaped[mac_id]++; 2695d5c65159SKalle Valo 2696293cb583SJohn Crispin push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 2697c4d12cb3SP Praneesh desc->info0); 269840058803SP Praneesh if (unlikely(push_reason != 269940058803SP Praneesh HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) { 2700d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2701acc79d98SSriram R ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2702d5c65159SKalle Valo continue; 2703d5c65159SKalle Valo } 2704d5c65159SKalle Valo 2705c4d12cb3SP Praneesh rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 & 2706293cb583SJohn Crispin RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2707c4d12cb3SP Praneesh rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 & 2708293cb583SJohn Crispin RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2709c4d12cb3SP Praneesh rxcb->is_continuation = !!(desc->rx_msdu_info.info0 & 2710293cb583SJohn Crispin RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 27112167fa60SSriram R rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID, 2712c4d12cb3SP Praneesh desc->rx_mpdu_info.meta_data); 27132167fa60SSriram R rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM, 2714c4d12cb3SP Praneesh desc->rx_mpdu_info.info0); 2715acc79d98SSriram R rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 2716c4d12cb3SP Praneesh desc->info0); 2717acc79d98SSriram R 27182167fa60SSriram R rxcb->mac_id = mac_id; 2719c4d12cb3SP Praneesh __skb_queue_tail(&msdu_list[mac_id], msdu); 2720d5c65159SKalle Valo 2721a1775e73SP Praneesh if (rxcb->is_continuation) { 2722a1775e73SP Praneesh done = false; 2723a1775e73SP Praneesh } else { 2724a1775e73SP Praneesh total_msdu_reaped++; 2725d5c65159SKalle Valo done = true; 2726d5c65159SKalle Valo } 2727a1775e73SP Praneesh 2728a1775e73SP Praneesh if (total_msdu_reaped >= budget) 2729a1775e73SP Praneesh break; 2730d5c65159SKalle Valo } 2731d5c65159SKalle Valo 2732d5c65159SKalle Valo /* Hw might have updated the head pointer after we cached it. 2733d5c65159SKalle Valo * In this case, even though there are entries in the ring we'll 2734d5c65159SKalle Valo * get rx_desc NULL. Give the read another try with updated cached 2735d5c65159SKalle Valo * head pointer so that we can reap complete MPDU in the current 2736d5c65159SKalle Valo * rx processing. 2737d5c65159SKalle Valo */ 273840058803SP Praneesh if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) { 2739d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2740d5c65159SKalle Valo goto try_again; 2741d5c65159SKalle Valo } 2742d5c65159SKalle Valo 2743d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2744d5c65159SKalle Valo 2745d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2746d5c65159SKalle Valo 274740058803SP Praneesh if (unlikely(!total_msdu_reaped)) 2748d5c65159SKalle Valo goto exit; 2749d5c65159SKalle Valo 2750acc79d98SSriram R for (i = 0; i < ab->num_radios; i++) { 2751acc79d98SSriram R if (!num_buffs_reaped[i]) 2752d5c65159SKalle Valo continue; 2753acc79d98SSriram R 2754db2ecf9fSP Praneesh ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i); 2755c4d12cb3SP Praneesh 2756acc79d98SSriram R ar = ab->pdevs[i].ar; 2757acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2758acc79d98SSriram R 2759acc79d98SSriram R ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 2760734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 2761d5c65159SKalle Valo } 2762d5c65159SKalle Valo exit: 2763db2ecf9fSP Praneesh return total_msdu_reaped; 2764d5c65159SKalle Valo } 2765d5c65159SKalle Valo 2766d5c65159SKalle Valo static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2767d5c65159SKalle Valo struct hal_rx_mon_ppdu_info *ppdu_info) 2768d5c65159SKalle Valo { 2769d5c65159SKalle Valo struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2770d5c65159SKalle Valo u32 num_msdu; 2771d5c65159SKalle Valo 2772d5c65159SKalle Valo if (!rx_stats) 2773d5c65159SKalle Valo return; 2774d5c65159SKalle Valo 2775d5c65159SKalle Valo num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2776d5c65159SKalle Valo ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2777d5c65159SKalle Valo 2778d5c65159SKalle Valo rx_stats->num_msdu += num_msdu; 2779d5c65159SKalle Valo rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2780d5c65159SKalle Valo ppdu_info->tcp_ack_msdu_count; 2781d5c65159SKalle Valo rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2782d5c65159SKalle Valo rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2783d5c65159SKalle Valo 2784d5c65159SKalle Valo if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2785d5c65159SKalle Valo ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2786d5c65159SKalle Valo ppdu_info->nss = 1; 2787d5c65159SKalle Valo ppdu_info->mcs = HAL_RX_MAX_MCS; 2788d5c65159SKalle Valo ppdu_info->tid = IEEE80211_NUM_TIDS; 2789d5c65159SKalle Valo } 2790d5c65159SKalle Valo 2791d5c65159SKalle Valo if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2792d5c65159SKalle Valo rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2793d5c65159SKalle Valo 2794d5c65159SKalle Valo if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2795d5c65159SKalle Valo rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2796d5c65159SKalle Valo 2797d5c65159SKalle Valo if (ppdu_info->gi < HAL_RX_GI_MAX) 2798d5c65159SKalle Valo rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2799d5c65159SKalle Valo 2800d5c65159SKalle Valo if (ppdu_info->bw < HAL_RX_BW_MAX) 2801d5c65159SKalle Valo rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2802d5c65159SKalle Valo 2803d5c65159SKalle Valo if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2804d5c65159SKalle Valo rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2805d5c65159SKalle Valo 2806d5c65159SKalle Valo if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2807d5c65159SKalle Valo rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2808d5c65159SKalle Valo 2809d5c65159SKalle Valo if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2810d5c65159SKalle Valo rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2811d5c65159SKalle Valo 2812d5c65159SKalle Valo if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2813d5c65159SKalle Valo rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2814d5c65159SKalle Valo 2815d5c65159SKalle Valo if (ppdu_info->is_stbc) 2816d5c65159SKalle Valo rx_stats->stbc_count += num_msdu; 2817d5c65159SKalle Valo 2818d5c65159SKalle Valo if (ppdu_info->beamformed) 2819d5c65159SKalle Valo rx_stats->beamformed_count += num_msdu; 2820d5c65159SKalle Valo 2821d5c65159SKalle Valo if (ppdu_info->num_mpdu_fcs_ok > 1) 2822d5c65159SKalle Valo rx_stats->ampdu_msdu_count += num_msdu; 2823d5c65159SKalle Valo else 2824d5c65159SKalle Valo rx_stats->non_ampdu_msdu_count += num_msdu; 2825d5c65159SKalle Valo 2826d5c65159SKalle Valo rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2827d5c65159SKalle Valo rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 28286a0c3702SJohn Crispin rx_stats->dcm_count += ppdu_info->dcm; 28296a0c3702SJohn Crispin rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2830d5c65159SKalle Valo 2831d5c65159SKalle Valo arsta->rssi_comb = ppdu_info->rssi_comb; 2832d5c65159SKalle Valo rx_stats->rx_duration += ppdu_info->rx_duration; 2833d5c65159SKalle Valo arsta->rx_duration = rx_stats->rx_duration; 2834d5c65159SKalle Valo } 2835d5c65159SKalle Valo 2836d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2837d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 283887e8497aSGovind Singh int *buf_id) 2839d5c65159SKalle Valo { 2840d5c65159SKalle Valo struct sk_buff *skb; 2841d5c65159SKalle Valo dma_addr_t paddr; 2842d5c65159SKalle Valo 2843d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2844d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 2845d5c65159SKalle Valo 2846d5c65159SKalle Valo if (!skb) 2847d5c65159SKalle Valo goto fail_alloc_skb; 2848d5c65159SKalle Valo 2849d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 2850d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 2851d5c65159SKalle Valo skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2852d5c65159SKalle Valo skb->data); 2853d5c65159SKalle Valo } 2854d5c65159SKalle Valo 2855d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 2856d5c65159SKalle Valo skb->len + skb_tailroom(skb), 2857cd6181ffSKalle Valo DMA_FROM_DEVICE); 2858d5c65159SKalle Valo if (unlikely(dma_mapping_error(ab->dev, paddr))) 2859d5c65159SKalle Valo goto fail_free_skb; 2860d5c65159SKalle Valo 2861d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2862d5c65159SKalle Valo *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 286387e8497aSGovind Singh rx_ring->bufs_max, GFP_ATOMIC); 2864d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2865d5c65159SKalle Valo if (*buf_id < 0) 2866d5c65159SKalle Valo goto fail_dma_unmap; 2867d5c65159SKalle Valo 2868d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 2869d5c65159SKalle Valo return skb; 2870d5c65159SKalle Valo 2871d5c65159SKalle Valo fail_dma_unmap: 2872d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2873cd6181ffSKalle Valo DMA_FROM_DEVICE); 2874d5c65159SKalle Valo fail_free_skb: 2875d5c65159SKalle Valo dev_kfree_skb_any(skb); 2876d5c65159SKalle Valo fail_alloc_skb: 2877d5c65159SKalle Valo return NULL; 2878d5c65159SKalle Valo } 2879d5c65159SKalle Valo 2880d5c65159SKalle Valo int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2881d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 2882d5c65159SKalle Valo int req_entries, 288387e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 2884d5c65159SKalle Valo { 2885d5c65159SKalle Valo struct hal_srng *srng; 2886d5c65159SKalle Valo u32 *desc; 2887d5c65159SKalle Valo struct sk_buff *skb; 2888d5c65159SKalle Valo int num_free; 2889d5c65159SKalle Valo int num_remain; 2890d5c65159SKalle Valo int buf_id; 2891d5c65159SKalle Valo u32 cookie; 2892d5c65159SKalle Valo dma_addr_t paddr; 2893d5c65159SKalle Valo 2894d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 2895d5c65159SKalle Valo 2896d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2897d5c65159SKalle Valo 2898d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2899d5c65159SKalle Valo 2900d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2901d5c65159SKalle Valo 2902d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2903d5c65159SKalle Valo 2904d5c65159SKalle Valo req_entries = min(num_free, req_entries); 2905d5c65159SKalle Valo num_remain = req_entries; 2906d5c65159SKalle Valo 2907d5c65159SKalle Valo while (num_remain > 0) { 2908d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 290987e8497aSGovind Singh &buf_id); 2910d5c65159SKalle Valo if (!skb) 2911d5c65159SKalle Valo break; 2912d5c65159SKalle Valo paddr = ATH11K_SKB_RXCB(skb)->paddr; 2913d5c65159SKalle Valo 2914d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2915d5c65159SKalle Valo if (!desc) 2916d5c65159SKalle Valo goto fail_desc_get; 2917d5c65159SKalle Valo 2918d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2919d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2920d5c65159SKalle Valo 2921d5c65159SKalle Valo num_remain--; 2922d5c65159SKalle Valo 2923d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2924d5c65159SKalle Valo } 2925d5c65159SKalle Valo 2926d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2927d5c65159SKalle Valo 2928d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2929d5c65159SKalle Valo 2930d5c65159SKalle Valo return req_entries - num_remain; 2931d5c65159SKalle Valo 2932d5c65159SKalle Valo fail_desc_get: 2933d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2934d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2935d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2936d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2937cd6181ffSKalle Valo DMA_FROM_DEVICE); 2938d5c65159SKalle Valo dev_kfree_skb_any(skb); 2939d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2940d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2941d5c65159SKalle Valo 2942d5c65159SKalle Valo return req_entries - num_remain; 2943d5c65159SKalle Valo } 2944d5c65159SKalle Valo 2945d5c65159SKalle Valo static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2946d5c65159SKalle Valo int *budget, struct sk_buff_head *skb_list) 2947d5c65159SKalle Valo { 29484152e420SCarl Huang struct ath11k *ar; 2949734223d7SBaochen Qiang const struct ath11k_hw_hal_params *hal_params; 29504152e420SCarl Huang struct ath11k_pdev_dp *dp; 29514152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 2952d5c65159SKalle Valo struct hal_srng *srng; 2953d5c65159SKalle Valo void *rx_mon_status_desc; 2954d5c65159SKalle Valo struct sk_buff *skb; 2955d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 2956d5c65159SKalle Valo struct hal_tlv_hdr *tlv; 2957d5c65159SKalle Valo u32 cookie; 29584152e420SCarl Huang int buf_id, srng_id; 2959d5c65159SKalle Valo dma_addr_t paddr; 2960d5c65159SKalle Valo u8 rbm; 2961d5c65159SKalle Valo int num_buffs_reaped = 0; 2962d5c65159SKalle Valo 29634152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 29644152e420SCarl Huang dp = &ar->dp; 29654152e420SCarl Huang srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id); 29664152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 29674152e420SCarl Huang 2968d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2969d5c65159SKalle Valo 2970d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2971d5c65159SKalle Valo 2972d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2973d5c65159SKalle Valo while (*budget) { 2974d5c65159SKalle Valo *budget -= 1; 2975d5c65159SKalle Valo rx_mon_status_desc = 2976d5c65159SKalle Valo ath11k_hal_srng_src_peek(ab, srng); 2977d5c65159SKalle Valo if (!rx_mon_status_desc) 2978d5c65159SKalle Valo break; 2979d5c65159SKalle Valo 2980d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 2981d5c65159SKalle Valo &cookie, &rbm); 2982d5c65159SKalle Valo if (paddr) { 2983d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 2984d5c65159SKalle Valo 2985d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2986d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 2987d5c65159SKalle Valo if (!skb) { 2988d5c65159SKalle Valo ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 2989d5c65159SKalle Valo buf_id); 2990d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 299132a2be49SMiles Hu goto move_next; 2992d5c65159SKalle Valo } 2993d5c65159SKalle Valo 2994d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2995d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2996d5c65159SKalle Valo 2997d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 2998d5c65159SKalle Valo 2999d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 3000d5c65159SKalle Valo skb->len + skb_tailroom(skb), 3001cd6181ffSKalle Valo DMA_FROM_DEVICE); 3002d5c65159SKalle Valo 3003d5c65159SKalle Valo tlv = (struct hal_tlv_hdr *)skb->data; 3004d5c65159SKalle Valo if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 3005d5c65159SKalle Valo HAL_RX_STATUS_BUFFER_DONE) { 300632a2be49SMiles Hu ath11k_warn(ab, "mon status DONE not set %lx\n", 300732a2be49SMiles Hu FIELD_GET(HAL_TLV_HDR_TAG, 300832a2be49SMiles Hu tlv->tl)); 300932a2be49SMiles Hu dev_kfree_skb_any(skb); 301032a2be49SMiles Hu goto move_next; 3011d5c65159SKalle Valo } 3012d5c65159SKalle Valo 3013d5c65159SKalle Valo __skb_queue_tail(skb_list, skb); 3014d5c65159SKalle Valo } 301532a2be49SMiles Hu move_next: 3016d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 301787e8497aSGovind Singh &buf_id); 3018d5c65159SKalle Valo 3019d5c65159SKalle Valo if (!skb) { 3020734223d7SBaochen Qiang hal_params = ab->hw_params.hal_params; 3021d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 3022734223d7SBaochen Qiang hal_params->rx_buf_rbm); 3023d5c65159SKalle Valo num_buffs_reaped++; 3024d5c65159SKalle Valo break; 3025d5c65159SKalle Valo } 3026d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3027d5c65159SKalle Valo 3028d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 3029d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3030d5c65159SKalle Valo 3031d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 3032734223d7SBaochen Qiang cookie, 3033734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3034d5c65159SKalle Valo ath11k_hal_srng_src_get_next_entry(ab, srng); 3035d5c65159SKalle Valo num_buffs_reaped++; 3036d5c65159SKalle Valo } 3037d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3038d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3039d5c65159SKalle Valo 3040d5c65159SKalle Valo return num_buffs_reaped; 3041d5c65159SKalle Valo } 3042d5c65159SKalle Valo 3043d5c65159SKalle Valo int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 3044d5c65159SKalle Valo struct napi_struct *napi, int budget) 3045d5c65159SKalle Valo { 30464152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 3047d5c65159SKalle Valo enum hal_rx_mon_status hal_status; 3048d5c65159SKalle Valo struct sk_buff *skb; 3049d5c65159SKalle Valo struct sk_buff_head skb_list; 3050d5c65159SKalle Valo struct hal_rx_mon_ppdu_info ppdu_info; 3051d5c65159SKalle Valo struct ath11k_peer *peer; 3052d5c65159SKalle Valo struct ath11k_sta *arsta; 3053d5c65159SKalle Valo int num_buffs_reaped = 0; 3054ab18e3bcSAnilkumar Kolli u32 rx_buf_sz; 3055ab18e3bcSAnilkumar Kolli u16 log_type = 0; 3056d5c65159SKalle Valo 3057d5c65159SKalle Valo __skb_queue_head_init(&skb_list); 3058d5c65159SKalle Valo 3059d5c65159SKalle Valo num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 3060d5c65159SKalle Valo &skb_list); 3061d5c65159SKalle Valo if (!num_buffs_reaped) 3062d5c65159SKalle Valo goto exit; 3063d5c65159SKalle Valo 3064d5c65159SKalle Valo while ((skb = __skb_dequeue(&skb_list))) { 3065d5c65159SKalle Valo memset(&ppdu_info, 0, sizeof(ppdu_info)); 3066d5c65159SKalle Valo ppdu_info.peer_id = HAL_INVALID_PEERID; 3067d5c65159SKalle Valo 3068ab18e3bcSAnilkumar Kolli if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) { 3069ab18e3bcSAnilkumar Kolli log_type = ATH11K_PKTLOG_TYPE_LITE_RX; 3070ab18e3bcSAnilkumar Kolli rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; 3071ab18e3bcSAnilkumar Kolli } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) { 3072ab18e3bcSAnilkumar Kolli log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF; 3073ab18e3bcSAnilkumar Kolli rx_buf_sz = DP_RX_BUFFER_SIZE; 3074ab18e3bcSAnilkumar Kolli } 3075ab18e3bcSAnilkumar Kolli 3076ab18e3bcSAnilkumar Kolli if (log_type) 3077ab18e3bcSAnilkumar Kolli trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 3078d5c65159SKalle Valo 3079d5c65159SKalle Valo hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb); 3080d5c65159SKalle Valo 3081d5c65159SKalle Valo if (ppdu_info.peer_id == HAL_INVALID_PEERID || 3082d5c65159SKalle Valo hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 3083d5c65159SKalle Valo dev_kfree_skb_any(skb); 3084d5c65159SKalle Valo continue; 3085d5c65159SKalle Valo } 3086d5c65159SKalle Valo 3087d5c65159SKalle Valo rcu_read_lock(); 3088d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 3089d5c65159SKalle Valo peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id); 3090d5c65159SKalle Valo 3091d5c65159SKalle Valo if (!peer || !peer->sta) { 30922dab7d22SJohn Crispin ath11k_dbg(ab, ATH11K_DBG_DATA, 30932dab7d22SJohn Crispin "failed to find the peer with peer_id %d\n", 3094d5c65159SKalle Valo ppdu_info.peer_id); 3095d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 3096d5c65159SKalle Valo rcu_read_unlock(); 3097d5c65159SKalle Valo dev_kfree_skb_any(skb); 3098d5c65159SKalle Valo continue; 3099d5c65159SKalle Valo } 3100d5c65159SKalle Valo 3101d5c65159SKalle Valo arsta = (struct ath11k_sta *)peer->sta->drv_priv; 3102d5c65159SKalle Valo ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info); 3103d5c65159SKalle Valo 3104cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) 3105ab18e3bcSAnilkumar Kolli trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 3106d5c65159SKalle Valo 3107d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 3108d5c65159SKalle Valo rcu_read_unlock(); 3109d5c65159SKalle Valo 3110d5c65159SKalle Valo dev_kfree_skb_any(skb); 3111d5c65159SKalle Valo } 3112d5c65159SKalle Valo exit: 3113d5c65159SKalle Valo return num_buffs_reaped; 3114d5c65159SKalle Valo } 3115d5c65159SKalle Valo 3116243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 3117d5c65159SKalle Valo { 3118243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 3119d5c65159SKalle Valo 3120243874c6SManikanta Pubbisetty spin_lock_bh(&rx_tid->ab->base_lock); 3121243874c6SManikanta Pubbisetty if (rx_tid->last_frag_no && 3122243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 3123243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 3124243874c6SManikanta Pubbisetty return; 3125243874c6SManikanta Pubbisetty } 3126243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3127243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 3128d5c65159SKalle Valo } 3129d5c65159SKalle Valo 3130243874c6SManikanta Pubbisetty int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 3131243874c6SManikanta Pubbisetty { 3132243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3133243874c6SManikanta Pubbisetty struct crypto_shash *tfm; 3134243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 3135243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 3136243874c6SManikanta Pubbisetty int i; 3137d5c65159SKalle Valo 3138243874c6SManikanta Pubbisetty tfm = crypto_alloc_shash("michael_mic", 0, 0); 3139243874c6SManikanta Pubbisetty if (IS_ERR(tfm)) 3140243874c6SManikanta Pubbisetty return PTR_ERR(tfm); 3141d5c65159SKalle Valo 3142243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3143d5c65159SKalle Valo 3144243874c6SManikanta Pubbisetty peer = ath11k_peer_find(ab, vdev_id, peer_mac); 3145243874c6SManikanta Pubbisetty if (!peer) { 3146243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 3147243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3148243874c6SManikanta Pubbisetty return -ENOENT; 3149243874c6SManikanta Pubbisetty } 3150243874c6SManikanta Pubbisetty 3151243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3152243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 3153243874c6SManikanta Pubbisetty rx_tid->ab = ab; 3154243874c6SManikanta Pubbisetty timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 3155243874c6SManikanta Pubbisetty skb_queue_head_init(&rx_tid->rx_frags); 3156243874c6SManikanta Pubbisetty } 3157243874c6SManikanta Pubbisetty 3158243874c6SManikanta Pubbisetty peer->tfm_mmic = tfm; 3159243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3160243874c6SManikanta Pubbisetty 3161243874c6SManikanta Pubbisetty return 0; 3162243874c6SManikanta Pubbisetty } 3163243874c6SManikanta Pubbisetty 3164243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3165243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr, u8 *data, 3166243874c6SManikanta Pubbisetty size_t data_len, u8 *mic) 3167243874c6SManikanta Pubbisetty { 3168243874c6SManikanta Pubbisetty SHASH_DESC_ON_STACK(desc, tfm); 3169243874c6SManikanta Pubbisetty u8 mic_hdr[16] = {0}; 3170243874c6SManikanta Pubbisetty u8 tid = 0; 3171243874c6SManikanta Pubbisetty int ret; 3172243874c6SManikanta Pubbisetty 3173243874c6SManikanta Pubbisetty if (!tfm) 3174243874c6SManikanta Pubbisetty return -EINVAL; 3175243874c6SManikanta Pubbisetty 3176243874c6SManikanta Pubbisetty desc->tfm = tfm; 3177243874c6SManikanta Pubbisetty 3178243874c6SManikanta Pubbisetty ret = crypto_shash_setkey(tfm, key, 8); 3179243874c6SManikanta Pubbisetty if (ret) 3180243874c6SManikanta Pubbisetty goto out; 3181243874c6SManikanta Pubbisetty 3182243874c6SManikanta Pubbisetty ret = crypto_shash_init(desc); 3183243874c6SManikanta Pubbisetty if (ret) 3184243874c6SManikanta Pubbisetty goto out; 3185243874c6SManikanta Pubbisetty 3186243874c6SManikanta Pubbisetty /* TKIP MIC header */ 3187243874c6SManikanta Pubbisetty memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3188243874c6SManikanta Pubbisetty memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3189243874c6SManikanta Pubbisetty if (ieee80211_is_data_qos(hdr->frame_control)) 3190243874c6SManikanta Pubbisetty tid = ieee80211_get_tid(hdr); 3191243874c6SManikanta Pubbisetty mic_hdr[12] = tid; 3192243874c6SManikanta Pubbisetty 3193243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, mic_hdr, 16); 3194243874c6SManikanta Pubbisetty if (ret) 3195243874c6SManikanta Pubbisetty goto out; 3196243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, data, data_len); 3197243874c6SManikanta Pubbisetty if (ret) 3198243874c6SManikanta Pubbisetty goto out; 3199243874c6SManikanta Pubbisetty ret = crypto_shash_final(desc, mic); 3200243874c6SManikanta Pubbisetty out: 3201243874c6SManikanta Pubbisetty shash_desc_zero(desc); 3202d5c65159SKalle Valo return ret; 3203d5c65159SKalle Valo } 3204d5c65159SKalle Valo 3205243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 3206243874c6SManikanta Pubbisetty struct sk_buff *msdu) 3207d5c65159SKalle Valo { 3208243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3209243874c6SManikanta Pubbisetty struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3210243874c6SManikanta Pubbisetty struct ieee80211_key_conf *key_conf; 3211243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3212243874c6SManikanta Pubbisetty u8 mic[IEEE80211_CCMP_MIC_LEN]; 3213243874c6SManikanta Pubbisetty int head_len, tail_len, ret; 3214243874c6SManikanta Pubbisetty size_t data_len; 3215e678fbd4SKarthikeyan Periyasamy u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3216243874c6SManikanta Pubbisetty u8 *key, *data; 3217243874c6SManikanta Pubbisetty u8 key_idx; 3218d5c65159SKalle Valo 3219e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) != 3220e678fbd4SKarthikeyan Periyasamy HAL_ENCRYPT_TYPE_TKIP_MIC) 3221243874c6SManikanta Pubbisetty return 0; 3222d5c65159SKalle Valo 3223e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3224243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3225e678fbd4SKarthikeyan Periyasamy head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3226243874c6SManikanta Pubbisetty tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3227d5c65159SKalle Valo 3228243874c6SManikanta Pubbisetty if (!is_multicast_ether_addr(hdr->addr1)) 3229243874c6SManikanta Pubbisetty key_idx = peer->ucast_keyidx; 3230243874c6SManikanta Pubbisetty else 3231243874c6SManikanta Pubbisetty key_idx = peer->mcast_keyidx; 3232d5c65159SKalle Valo 3233243874c6SManikanta Pubbisetty key_conf = peer->keys[key_idx]; 3234d5c65159SKalle Valo 3235243874c6SManikanta Pubbisetty data = msdu->data + head_len; 3236243874c6SManikanta Pubbisetty data_len = msdu->len - head_len - tail_len; 3237243874c6SManikanta Pubbisetty key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3238d5c65159SKalle Valo 3239243874c6SManikanta Pubbisetty ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3240243874c6SManikanta Pubbisetty if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3241243874c6SManikanta Pubbisetty goto mic_fail; 3242d5c65159SKalle Valo 3243243874c6SManikanta Pubbisetty return 0; 3244243874c6SManikanta Pubbisetty 3245243874c6SManikanta Pubbisetty mic_fail: 3246b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 3247b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 3248243874c6SManikanta Pubbisetty 3249243874c6SManikanta Pubbisetty rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3250243874c6SManikanta Pubbisetty RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3251e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 3252243874c6SManikanta Pubbisetty 3253243874c6SManikanta Pubbisetty ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 3254243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 3255243874c6SManikanta Pubbisetty HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3256243874c6SManikanta Pubbisetty ieee80211_rx(ar->hw, msdu); 3257243874c6SManikanta Pubbisetty return -EINVAL; 3258d5c65159SKalle Valo } 3259d5c65159SKalle Valo 3260243874c6SManikanta Pubbisetty static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 3261243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype, u32 flags) 3262243874c6SManikanta Pubbisetty { 3263243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3264243874c6SManikanta Pubbisetty size_t hdr_len; 3265243874c6SManikanta Pubbisetty size_t crypto_len; 3266e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3267d5c65159SKalle Valo 3268243874c6SManikanta Pubbisetty if (!flags) 3269243874c6SManikanta Pubbisetty return; 3270d5c65159SKalle Valo 3271e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3272243874c6SManikanta Pubbisetty 3273243874c6SManikanta Pubbisetty if (flags & RX_FLAG_MIC_STRIPPED) 3274d5c65159SKalle Valo skb_trim(msdu, msdu->len - 3275d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3276243874c6SManikanta Pubbisetty 3277243874c6SManikanta Pubbisetty if (flags & RX_FLAG_ICV_STRIPPED) 3278243874c6SManikanta Pubbisetty skb_trim(msdu, msdu->len - 3279243874c6SManikanta Pubbisetty ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3280243874c6SManikanta Pubbisetty 3281243874c6SManikanta Pubbisetty if (flags & RX_FLAG_IV_STRIPPED) { 3282243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3283243874c6SManikanta Pubbisetty crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3284243874c6SManikanta Pubbisetty 3285e678fbd4SKarthikeyan Periyasamy memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len, 3286e678fbd4SKarthikeyan Periyasamy (void *)msdu->data + hal_rx_desc_sz, hdr_len); 3287243874c6SManikanta Pubbisetty skb_pull(msdu, crypto_len); 3288d5c65159SKalle Valo } 3289d5c65159SKalle Valo } 3290d5c65159SKalle Valo 3291243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3292243874c6SManikanta Pubbisetty struct ath11k_peer *peer, 3293243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid, 3294243874c6SManikanta Pubbisetty struct sk_buff **defrag_skb) 3295243874c6SManikanta Pubbisetty { 3296243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3297243874c6SManikanta Pubbisetty struct sk_buff *skb, *first_frag, *last_frag; 3298243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3299e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 3300243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype; 3301243874c6SManikanta Pubbisetty bool is_decrypted = false; 3302243874c6SManikanta Pubbisetty int msdu_len = 0; 3303243874c6SManikanta Pubbisetty int extra_space; 3304e678fbd4SKarthikeyan Periyasamy u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3305243874c6SManikanta Pubbisetty 3306243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3307243874c6SManikanta Pubbisetty last_frag = skb_peek_tail(&rx_tid->rx_frags); 3308243874c6SManikanta Pubbisetty 3309243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3310243874c6SManikanta Pubbisetty flags = 0; 3311243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)skb->data; 3312e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3313243874c6SManikanta Pubbisetty 3314e678fbd4SKarthikeyan Periyasamy enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 3315e678fbd4SKarthikeyan Periyasamy if (enctype != HAL_ENCRYPT_TYPE_OPEN) { 3316e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 3317e678fbd4SKarthikeyan Periyasamy is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 3318e678fbd4SKarthikeyan Periyasamy } 3319243874c6SManikanta Pubbisetty 3320243874c6SManikanta Pubbisetty if (is_decrypted) { 3321243874c6SManikanta Pubbisetty if (skb != first_frag) 3322243874c6SManikanta Pubbisetty flags |= RX_FLAG_IV_STRIPPED; 3323243874c6SManikanta Pubbisetty if (skb != last_frag) 3324243874c6SManikanta Pubbisetty flags |= RX_FLAG_ICV_STRIPPED | 3325243874c6SManikanta Pubbisetty RX_FLAG_MIC_STRIPPED; 3326243874c6SManikanta Pubbisetty } 3327243874c6SManikanta Pubbisetty 3328243874c6SManikanta Pubbisetty /* RX fragments are always raw packets */ 3329243874c6SManikanta Pubbisetty if (skb != last_frag) 3330243874c6SManikanta Pubbisetty skb_trim(skb, skb->len - FCS_LEN); 3331243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3332243874c6SManikanta Pubbisetty 3333243874c6SManikanta Pubbisetty if (skb != first_frag) 3334e678fbd4SKarthikeyan Periyasamy skb_pull(skb, hal_rx_desc_sz + 3335243874c6SManikanta Pubbisetty ieee80211_hdrlen(hdr->frame_control)); 3336243874c6SManikanta Pubbisetty msdu_len += skb->len; 3337243874c6SManikanta Pubbisetty } 3338243874c6SManikanta Pubbisetty 3339243874c6SManikanta Pubbisetty extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3340243874c6SManikanta Pubbisetty if (extra_space > 0 && 3341243874c6SManikanta Pubbisetty (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3342243874c6SManikanta Pubbisetty return -ENOMEM; 3343243874c6SManikanta Pubbisetty 3344243874c6SManikanta Pubbisetty __skb_unlink(first_frag, &rx_tid->rx_frags); 3345243874c6SManikanta Pubbisetty while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3346243874c6SManikanta Pubbisetty skb_put_data(first_frag, skb->data, skb->len); 3347243874c6SManikanta Pubbisetty dev_kfree_skb_any(skb); 3348243874c6SManikanta Pubbisetty } 3349243874c6SManikanta Pubbisetty 3350e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3351243874c6SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3352243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3353243874c6SManikanta Pubbisetty 3354243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3355243874c6SManikanta Pubbisetty first_frag = NULL; 3356243874c6SManikanta Pubbisetty 3357243874c6SManikanta Pubbisetty *defrag_skb = first_frag; 3358243874c6SManikanta Pubbisetty return 0; 3359243874c6SManikanta Pubbisetty } 3360243874c6SManikanta Pubbisetty 3361243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3362243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb) 3363243874c6SManikanta Pubbisetty { 3364243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3365243874c6SManikanta Pubbisetty struct ath11k_pdev_dp *dp = &ar->dp; 3366243874c6SManikanta Pubbisetty struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3367243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3368243874c6SManikanta Pubbisetty struct hal_reo_entrance_ring *reo_ent_ring; 3369243874c6SManikanta Pubbisetty struct hal_reo_dest_ring *reo_dest_ring; 3370243874c6SManikanta Pubbisetty struct dp_link_desc_bank *link_desc_banks; 3371243874c6SManikanta Pubbisetty struct hal_rx_msdu_link *msdu_link; 3372243874c6SManikanta Pubbisetty struct hal_rx_msdu_details *msdu0; 3373243874c6SManikanta Pubbisetty struct hal_srng *srng; 3374243874c6SManikanta Pubbisetty dma_addr_t paddr; 3375243874c6SManikanta Pubbisetty u32 desc_bank, msdu_info, mpdu_info; 3376e678fbd4SKarthikeyan Periyasamy u32 dst_idx, cookie, hal_rx_desc_sz; 3377243874c6SManikanta Pubbisetty int ret, buf_id; 3378243874c6SManikanta Pubbisetty 3379e678fbd4SKarthikeyan Periyasamy hal_rx_desc_sz = ab->hw_params.hal_desc_sz; 3380243874c6SManikanta Pubbisetty link_desc_banks = ab->dp.link_desc_banks; 3381243874c6SManikanta Pubbisetty reo_dest_ring = rx_tid->dst_ring_desc; 3382243874c6SManikanta Pubbisetty 3383243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3384243874c6SManikanta Pubbisetty msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3385243874c6SManikanta Pubbisetty (paddr - link_desc_banks[desc_bank].paddr)); 3386243874c6SManikanta Pubbisetty msdu0 = &msdu_link->msdu_link[0]; 3387243874c6SManikanta Pubbisetty dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3388243874c6SManikanta Pubbisetty memset(msdu0, 0, sizeof(*msdu0)); 3389243874c6SManikanta Pubbisetty 3390243874c6SManikanta Pubbisetty msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3391243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3392243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3393243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3394e678fbd4SKarthikeyan Periyasamy defrag_skb->len - hal_rx_desc_sz) | 3395243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3396243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3397243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3398243874c6SManikanta Pubbisetty msdu0->rx_msdu_info.info0 = msdu_info; 3399243874c6SManikanta Pubbisetty 3400243874c6SManikanta Pubbisetty /* change msdu len in hal rx desc */ 3401e678fbd4SKarthikeyan Periyasamy ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3402243874c6SManikanta Pubbisetty 3403243874c6SManikanta Pubbisetty paddr = dma_map_single(ab->dev, defrag_skb->data, 3404243874c6SManikanta Pubbisetty defrag_skb->len + skb_tailroom(defrag_skb), 340586a03dadSBaochen Qiang DMA_TO_DEVICE); 3406243874c6SManikanta Pubbisetty if (dma_mapping_error(ab->dev, paddr)) 3407243874c6SManikanta Pubbisetty return -ENOMEM; 3408243874c6SManikanta Pubbisetty 3409243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3410243874c6SManikanta Pubbisetty buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3411243874c6SManikanta Pubbisetty rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3412243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3413243874c6SManikanta Pubbisetty if (buf_id < 0) { 3414243874c6SManikanta Pubbisetty ret = -ENOMEM; 3415243874c6SManikanta Pubbisetty goto err_unmap_dma; 3416243874c6SManikanta Pubbisetty } 3417243874c6SManikanta Pubbisetty 3418243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3419243874c6SManikanta Pubbisetty cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3420243874c6SManikanta Pubbisetty FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3421243874c6SManikanta Pubbisetty 3422734223d7SBaochen Qiang ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, 3423734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3424243874c6SManikanta Pubbisetty 3425243874c6SManikanta Pubbisetty /* Fill mpdu details into reo entrace ring */ 3426243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3427243874c6SManikanta Pubbisetty 3428243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 3429243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 3430243874c6SManikanta Pubbisetty 3431243874c6SManikanta Pubbisetty reo_ent_ring = (struct hal_reo_entrance_ring *) 3432243874c6SManikanta Pubbisetty ath11k_hal_srng_src_get_next_entry(ab, srng); 3433243874c6SManikanta Pubbisetty if (!reo_ent_ring) { 3434243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3435243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3436243874c6SManikanta Pubbisetty ret = -ENOSPC; 3437243874c6SManikanta Pubbisetty goto err_free_idr; 3438243874c6SManikanta Pubbisetty } 3439243874c6SManikanta Pubbisetty memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3440243874c6SManikanta Pubbisetty 3441243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3442243874c6SManikanta Pubbisetty ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3443243874c6SManikanta Pubbisetty HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3444243874c6SManikanta Pubbisetty 3445243874c6SManikanta Pubbisetty mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3446243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3447243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3448243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3449243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3450243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3451243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3452243874c6SManikanta Pubbisetty 3453243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3454243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3455243874c6SManikanta Pubbisetty reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3456243874c6SManikanta Pubbisetty reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3457243874c6SManikanta Pubbisetty FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3458243874c6SManikanta Pubbisetty reo_dest_ring->info0)) | 3459243874c6SManikanta Pubbisetty FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3460243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3461243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3462243874c6SManikanta Pubbisetty 3463243874c6SManikanta Pubbisetty return 0; 3464243874c6SManikanta Pubbisetty 3465243874c6SManikanta Pubbisetty err_free_idr: 3466243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3467243874c6SManikanta Pubbisetty idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3468243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3469243874c6SManikanta Pubbisetty err_unmap_dma: 3470243874c6SManikanta Pubbisetty dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 347186a03dadSBaochen Qiang DMA_TO_DEVICE); 3472243874c6SManikanta Pubbisetty return ret; 3473243874c6SManikanta Pubbisetty } 3474243874c6SManikanta Pubbisetty 3475e678fbd4SKarthikeyan Periyasamy static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar, 3476e678fbd4SKarthikeyan Periyasamy struct sk_buff *a, struct sk_buff *b) 3477243874c6SManikanta Pubbisetty { 3478243874c6SManikanta Pubbisetty int frag1, frag2; 3479243874c6SManikanta Pubbisetty 3480e678fbd4SKarthikeyan Periyasamy frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a); 3481e678fbd4SKarthikeyan Periyasamy frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b); 3482243874c6SManikanta Pubbisetty 3483243874c6SManikanta Pubbisetty return frag1 - frag2; 3484243874c6SManikanta Pubbisetty } 3485243874c6SManikanta Pubbisetty 3486e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar, 3487e678fbd4SKarthikeyan Periyasamy struct sk_buff_head *frag_list, 3488243874c6SManikanta Pubbisetty struct sk_buff *cur_frag) 3489243874c6SManikanta Pubbisetty { 3490243874c6SManikanta Pubbisetty struct sk_buff *skb; 3491243874c6SManikanta Pubbisetty int cmp; 3492243874c6SManikanta Pubbisetty 3493243874c6SManikanta Pubbisetty skb_queue_walk(frag_list, skb) { 3494e678fbd4SKarthikeyan Periyasamy cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag); 3495243874c6SManikanta Pubbisetty if (cmp < 0) 3496243874c6SManikanta Pubbisetty continue; 3497243874c6SManikanta Pubbisetty __skb_queue_before(frag_list, skb, cur_frag); 3498243874c6SManikanta Pubbisetty return; 3499243874c6SManikanta Pubbisetty } 3500243874c6SManikanta Pubbisetty __skb_queue_tail(frag_list, cur_frag); 3501243874c6SManikanta Pubbisetty } 3502243874c6SManikanta Pubbisetty 3503e678fbd4SKarthikeyan Periyasamy static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb) 3504243874c6SManikanta Pubbisetty { 3505243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3506243874c6SManikanta Pubbisetty u64 pn = 0; 3507243874c6SManikanta Pubbisetty u8 *ehdr; 3508e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3509243874c6SManikanta Pubbisetty 3510e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3511e678fbd4SKarthikeyan Periyasamy ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3512243874c6SManikanta Pubbisetty 3513243874c6SManikanta Pubbisetty pn = ehdr[0]; 3514243874c6SManikanta Pubbisetty pn |= (u64)ehdr[1] << 8; 3515243874c6SManikanta Pubbisetty pn |= (u64)ehdr[4] << 16; 3516243874c6SManikanta Pubbisetty pn |= (u64)ehdr[5] << 24; 3517243874c6SManikanta Pubbisetty pn |= (u64)ehdr[6] << 32; 3518243874c6SManikanta Pubbisetty pn |= (u64)ehdr[7] << 40; 3519243874c6SManikanta Pubbisetty 3520243874c6SManikanta Pubbisetty return pn; 3521243874c6SManikanta Pubbisetty } 3522243874c6SManikanta Pubbisetty 3523243874c6SManikanta Pubbisetty static bool 3524243874c6SManikanta Pubbisetty ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3525243874c6SManikanta Pubbisetty { 3526243874c6SManikanta Pubbisetty enum hal_encrypt_type encrypt_type; 3527243874c6SManikanta Pubbisetty struct sk_buff *first_frag, *skb; 3528243874c6SManikanta Pubbisetty struct hal_rx_desc *desc; 3529243874c6SManikanta Pubbisetty u64 last_pn; 3530243874c6SManikanta Pubbisetty u64 cur_pn; 3531243874c6SManikanta Pubbisetty 3532243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3533243874c6SManikanta Pubbisetty desc = (struct hal_rx_desc *)first_frag->data; 3534243874c6SManikanta Pubbisetty 3535e678fbd4SKarthikeyan Periyasamy encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc); 3536243874c6SManikanta Pubbisetty if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3537243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3538243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3539243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3540243874c6SManikanta Pubbisetty return true; 3541243874c6SManikanta Pubbisetty 3542e678fbd4SKarthikeyan Periyasamy last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag); 3543243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3544243874c6SManikanta Pubbisetty if (skb == first_frag) 3545243874c6SManikanta Pubbisetty continue; 3546243874c6SManikanta Pubbisetty 3547e678fbd4SKarthikeyan Periyasamy cur_pn = ath11k_dp_rx_h_get_pn(ar, skb); 3548243874c6SManikanta Pubbisetty if (cur_pn != last_pn + 1) 3549243874c6SManikanta Pubbisetty return false; 3550243874c6SManikanta Pubbisetty last_pn = cur_pn; 3551243874c6SManikanta Pubbisetty } 3552243874c6SManikanta Pubbisetty return true; 3553243874c6SManikanta Pubbisetty } 3554243874c6SManikanta Pubbisetty 3555243874c6SManikanta Pubbisetty static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3556243874c6SManikanta Pubbisetty struct sk_buff *msdu, 3557243874c6SManikanta Pubbisetty u32 *ring_desc) 3558243874c6SManikanta Pubbisetty { 3559243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3560243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3561243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 3562243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 3563243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb = NULL; 3564243874c6SManikanta Pubbisetty u32 peer_id; 3565243874c6SManikanta Pubbisetty u16 seqno, frag_no; 3566243874c6SManikanta Pubbisetty u8 tid; 3567243874c6SManikanta Pubbisetty int ret = 0; 3568243874c6SManikanta Pubbisetty bool more_frags; 3569210f563bSSriram R bool is_mcbc; 3570243874c6SManikanta Pubbisetty 3571243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)msdu->data; 3572e678fbd4SKarthikeyan Periyasamy peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 3573e678fbd4SKarthikeyan Periyasamy tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc); 3574e678fbd4SKarthikeyan Periyasamy seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 3575e678fbd4SKarthikeyan Periyasamy frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu); 3576e678fbd4SKarthikeyan Periyasamy more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu); 3577210f563bSSriram R is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 3578210f563bSSriram R 3579210f563bSSriram R /* Multicast/Broadcast fragments are not expected */ 3580210f563bSSriram R if (is_mcbc) 3581210f563bSSriram R return -EINVAL; 3582243874c6SManikanta Pubbisetty 3583e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) || 3584e678fbd4SKarthikeyan Periyasamy !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) || 3585243874c6SManikanta Pubbisetty tid > IEEE80211_NUM_TIDS) 3586243874c6SManikanta Pubbisetty return -EINVAL; 3587243874c6SManikanta Pubbisetty 3588243874c6SManikanta Pubbisetty /* received unfragmented packet in reo 3589243874c6SManikanta Pubbisetty * exception ring, this shouldn't happen 3590243874c6SManikanta Pubbisetty * as these packets typically come from 3591243874c6SManikanta Pubbisetty * reo2sw srngs. 3592243874c6SManikanta Pubbisetty */ 3593243874c6SManikanta Pubbisetty if (WARN_ON_ONCE(!frag_no && !more_frags)) 3594243874c6SManikanta Pubbisetty return -EINVAL; 3595243874c6SManikanta Pubbisetty 3596243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3597243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3598243874c6SManikanta Pubbisetty if (!peer) { 3599243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3600243874c6SManikanta Pubbisetty peer_id); 3601243874c6SManikanta Pubbisetty ret = -ENOENT; 3602243874c6SManikanta Pubbisetty goto out_unlock; 3603243874c6SManikanta Pubbisetty } 3604243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 3605243874c6SManikanta Pubbisetty 3606243874c6SManikanta Pubbisetty if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3607243874c6SManikanta Pubbisetty skb_queue_empty(&rx_tid->rx_frags)) { 3608243874c6SManikanta Pubbisetty /* Flush stored fragments and start a new sequence */ 3609243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3610243874c6SManikanta Pubbisetty rx_tid->cur_sn = seqno; 3611243874c6SManikanta Pubbisetty } 3612243874c6SManikanta Pubbisetty 3613243874c6SManikanta Pubbisetty if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3614243874c6SManikanta Pubbisetty /* Fragment already present */ 3615243874c6SManikanta Pubbisetty ret = -EINVAL; 3616243874c6SManikanta Pubbisetty goto out_unlock; 3617243874c6SManikanta Pubbisetty } 3618243874c6SManikanta Pubbisetty 3619243874c6SManikanta Pubbisetty if (frag_no > __fls(rx_tid->rx_frag_bitmap)) 3620243874c6SManikanta Pubbisetty __skb_queue_tail(&rx_tid->rx_frags, msdu); 3621243874c6SManikanta Pubbisetty else 3622e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu); 3623243874c6SManikanta Pubbisetty 3624243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap |= BIT(frag_no); 3625243874c6SManikanta Pubbisetty if (!more_frags) 3626243874c6SManikanta Pubbisetty rx_tid->last_frag_no = frag_no; 3627243874c6SManikanta Pubbisetty 3628243874c6SManikanta Pubbisetty if (frag_no == 0) { 3629243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = kmemdup(ring_desc, 3630243874c6SManikanta Pubbisetty sizeof(*rx_tid->dst_ring_desc), 3631243874c6SManikanta Pubbisetty GFP_ATOMIC); 3632243874c6SManikanta Pubbisetty if (!rx_tid->dst_ring_desc) { 3633243874c6SManikanta Pubbisetty ret = -ENOMEM; 3634243874c6SManikanta Pubbisetty goto out_unlock; 3635243874c6SManikanta Pubbisetty } 3636243874c6SManikanta Pubbisetty } else { 3637243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, ring_desc, 3638243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3639243874c6SManikanta Pubbisetty } 3640243874c6SManikanta Pubbisetty 3641243874c6SManikanta Pubbisetty if (!rx_tid->last_frag_no || 3642243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3643243874c6SManikanta Pubbisetty mod_timer(&rx_tid->frag_timer, jiffies + 3644243874c6SManikanta Pubbisetty ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3645243874c6SManikanta Pubbisetty goto out_unlock; 3646243874c6SManikanta Pubbisetty } 3647243874c6SManikanta Pubbisetty 3648243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3649243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 3650243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3651243874c6SManikanta Pubbisetty 3652243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3653243874c6SManikanta Pubbisetty if (!peer) 3654243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3655243874c6SManikanta Pubbisetty 3656243874c6SManikanta Pubbisetty if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3657243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3658243874c6SManikanta Pubbisetty 3659243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3660243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3661243874c6SManikanta Pubbisetty 3662243874c6SManikanta Pubbisetty if (!defrag_skb) 3663243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3664243874c6SManikanta Pubbisetty 3665243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3666243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3667243874c6SManikanta Pubbisetty 3668243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, false); 3669243874c6SManikanta Pubbisetty goto out_unlock; 3670243874c6SManikanta Pubbisetty 3671243874c6SManikanta Pubbisetty err_frags_cleanup: 3672243874c6SManikanta Pubbisetty dev_kfree_skb_any(defrag_skb); 3673243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3674243874c6SManikanta Pubbisetty out_unlock: 3675243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3676243874c6SManikanta Pubbisetty return ret; 3677243874c6SManikanta Pubbisetty } 3678243874c6SManikanta Pubbisetty 3679d5c65159SKalle Valo static int 3680243874c6SManikanta Pubbisetty ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3681d5c65159SKalle Valo { 3682d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 3683d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3684d5c65159SKalle Valo struct sk_buff *msdu; 3685d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3686d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 3687d7d43782STamizh Chelvam u8 *hdr_status; 3688d5c65159SKalle Valo u16 msdu_len; 3689e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3690d5c65159SKalle Valo 3691d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 3692d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3693d5c65159SKalle Valo if (!msdu) { 3694d5c65159SKalle Valo ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3695d5c65159SKalle Valo buf_id); 3696d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3697d5c65159SKalle Valo return -EINVAL; 3698d5c65159SKalle Valo } 3699d5c65159SKalle Valo 3700d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 3701d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3702d5c65159SKalle Valo 3703d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 3704d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 3705d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 3706d5c65159SKalle Valo DMA_FROM_DEVICE); 3707d5c65159SKalle Valo 3708243874c6SManikanta Pubbisetty if (drop) { 3709d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3710d5c65159SKalle Valo return 0; 3711d5c65159SKalle Valo } 3712d5c65159SKalle Valo 3713d5c65159SKalle Valo rcu_read_lock(); 3714d5c65159SKalle Valo if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3715d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3716d5c65159SKalle Valo goto exit; 3717d5c65159SKalle Valo } 3718d5c65159SKalle Valo 3719d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3720d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3721d5c65159SKalle Valo goto exit; 3722d5c65159SKalle Valo } 3723d5c65159SKalle Valo 3724d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 3725e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc); 3726e678fbd4SKarthikeyan Periyasamy if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3727e678fbd4SKarthikeyan Periyasamy hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 3728d7d43782STamizh Chelvam ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3729d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3730d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 3731d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3732d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 3733d7d43782STamizh Chelvam dev_kfree_skb_any(msdu); 3734d7d43782STamizh Chelvam goto exit; 3735d7d43782STamizh Chelvam } 3736d7d43782STamizh Chelvam 3737e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + msdu_len); 3738d5c65159SKalle Valo 3739243874c6SManikanta Pubbisetty if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3740243874c6SManikanta Pubbisetty dev_kfree_skb_any(msdu); 3741243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3742243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3743243874c6SManikanta Pubbisetty } 3744d5c65159SKalle Valo exit: 3745d5c65159SKalle Valo rcu_read_unlock(); 3746d5c65159SKalle Valo return 0; 3747d5c65159SKalle Valo } 3748d5c65159SKalle Valo 3749d5c65159SKalle Valo int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3750d5c65159SKalle Valo int budget) 3751d5c65159SKalle Valo { 3752293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3753d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks; 3754d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 3755d5c65159SKalle Valo int tot_n_bufs_reaped, quota, ret, i; 3756d5c65159SKalle Valo int n_bufs_reaped[MAX_RADIOS] = {0}; 3757d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 3758d5c65159SKalle Valo struct dp_srng *reo_except; 3759d5c65159SKalle Valo u32 desc_bank, num_msdus; 3760d5c65159SKalle Valo struct hal_srng *srng; 3761d5c65159SKalle Valo struct ath11k_dp *dp; 3762d5c65159SKalle Valo void *link_desc_va; 3763d5c65159SKalle Valo int buf_id, mac_id; 3764d5c65159SKalle Valo struct ath11k *ar; 3765d5c65159SKalle Valo dma_addr_t paddr; 3766d5c65159SKalle Valo u32 *desc; 3767d5c65159SKalle Valo bool is_frag; 3768243874c6SManikanta Pubbisetty u8 drop = 0; 3769d5c65159SKalle Valo 3770d5c65159SKalle Valo tot_n_bufs_reaped = 0; 3771d5c65159SKalle Valo quota = budget; 3772d5c65159SKalle Valo 3773d5c65159SKalle Valo dp = &ab->dp; 3774d5c65159SKalle Valo reo_except = &dp->reo_except_ring; 3775d5c65159SKalle Valo link_desc_banks = dp->link_desc_banks; 3776d5c65159SKalle Valo 3777d5c65159SKalle Valo srng = &ab->hal.srng_list[reo_except->ring_id]; 3778d5c65159SKalle Valo 3779d5c65159SKalle Valo spin_lock_bh(&srng->lock); 3780d5c65159SKalle Valo 3781d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 3782d5c65159SKalle Valo 3783d5c65159SKalle Valo while (budget && 3784d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3785293cb583SJohn Crispin struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3786293cb583SJohn Crispin 3787d5c65159SKalle Valo ab->soc_stats.err_ring_pkts++; 3788d5c65159SKalle Valo ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3789d5c65159SKalle Valo &desc_bank); 3790d5c65159SKalle Valo if (ret) { 3791d5c65159SKalle Valo ath11k_warn(ab, "failed to parse error reo desc %d\n", 3792d5c65159SKalle Valo ret); 3793d5c65159SKalle Valo continue; 3794d5c65159SKalle Valo } 3795d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 3796d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 3797293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3798d5c65159SKalle Valo &rbm); 3799d5c65159SKalle Valo if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 3800734223d7SBaochen Qiang rbm != ab->hw_params.hal_params->rx_buf_rbm) { 3801d5c65159SKalle Valo ab->soc_stats.invalid_rbm++; 3802d5c65159SKalle Valo ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3803d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3804d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_REL_MSDU); 3805d5c65159SKalle Valo continue; 3806d5c65159SKalle Valo } 3807d5c65159SKalle Valo 3808293cb583SJohn Crispin is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3809d5c65159SKalle Valo 3810243874c6SManikanta Pubbisetty /* Process only rx fragments with one msdu per link desc below, and drop 3811243874c6SManikanta Pubbisetty * msdu's indicated due to error reasons. 3812243874c6SManikanta Pubbisetty */ 3813243874c6SManikanta Pubbisetty if (!is_frag || num_msdus > 1) { 3814243874c6SManikanta Pubbisetty drop = 1; 3815d5c65159SKalle Valo /* Return the link desc back to wbm idle list */ 3816d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3817d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3818243874c6SManikanta Pubbisetty } 3819d5c65159SKalle Valo 3820d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 3821d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3822293cb583SJohn Crispin msdu_cookies[i]); 3823d5c65159SKalle Valo 3824d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3825293cb583SJohn Crispin msdu_cookies[i]); 3826d5c65159SKalle Valo 3827d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 3828d5c65159SKalle Valo 3829243874c6SManikanta Pubbisetty if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3830d5c65159SKalle Valo n_bufs_reaped[mac_id]++; 3831d5c65159SKalle Valo tot_n_bufs_reaped++; 3832d5c65159SKalle Valo } 3833d5c65159SKalle Valo } 3834d5c65159SKalle Valo 3835d5c65159SKalle Valo if (tot_n_bufs_reaped >= quota) { 3836d5c65159SKalle Valo tot_n_bufs_reaped = quota; 3837d5c65159SKalle Valo goto exit; 3838d5c65159SKalle Valo } 3839d5c65159SKalle Valo 3840d5c65159SKalle Valo budget = quota - tot_n_bufs_reaped; 3841d5c65159SKalle Valo } 3842d5c65159SKalle Valo 3843d5c65159SKalle Valo exit: 3844d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3845d5c65159SKalle Valo 3846d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3847d5c65159SKalle Valo 3848d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 3849d5c65159SKalle Valo if (!n_bufs_reaped[i]) 3850d5c65159SKalle Valo continue; 3851d5c65159SKalle Valo 3852d5c65159SKalle Valo ar = ab->pdevs[i].ar; 3853d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 3854d5c65159SKalle Valo 3855d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 3856734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3857d5c65159SKalle Valo } 3858d5c65159SKalle Valo 3859d5c65159SKalle Valo return tot_n_bufs_reaped; 3860d5c65159SKalle Valo } 3861d5c65159SKalle Valo 3862d5c65159SKalle Valo static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3863d5c65159SKalle Valo int msdu_len, 3864d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3865d5c65159SKalle Valo { 3866d5c65159SKalle Valo struct sk_buff *skb, *tmp; 3867d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3868d5c65159SKalle Valo int n_buffs; 3869d5c65159SKalle Valo 3870d5c65159SKalle Valo n_buffs = DIV_ROUND_UP(msdu_len, 3871e678fbd4SKarthikeyan Periyasamy (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz)); 3872d5c65159SKalle Valo 3873d5c65159SKalle Valo skb_queue_walk_safe(msdu_list, skb, tmp) { 3874d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3875d5c65159SKalle Valo if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3876d5c65159SKalle Valo rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3877d5c65159SKalle Valo if (!n_buffs) 3878d5c65159SKalle Valo break; 3879d5c65159SKalle Valo __skb_unlink(skb, msdu_list); 3880d5c65159SKalle Valo dev_kfree_skb_any(skb); 3881d5c65159SKalle Valo n_buffs--; 3882d5c65159SKalle Valo } 3883d5c65159SKalle Valo } 3884d5c65159SKalle Valo } 3885d5c65159SKalle Valo 3886d5c65159SKalle Valo static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3887d5c65159SKalle Valo struct ieee80211_rx_status *status, 3888d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3889d5c65159SKalle Valo { 3890d5c65159SKalle Valo u16 msdu_len; 3891d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3892e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 3893d5c65159SKalle Valo u8 l3pad_bytes; 3894d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3895e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3896d5c65159SKalle Valo 3897e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3898d5c65159SKalle Valo 3899e678fbd4SKarthikeyan Periyasamy if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3900d5c65159SKalle Valo /* First buffer will be freed by the caller, so deduct it's length */ 3901e678fbd4SKarthikeyan Periyasamy msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3902d5c65159SKalle Valo ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3903d5c65159SKalle Valo return -EINVAL; 3904d5c65159SKalle Valo } 3905d5c65159SKalle Valo 3906e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc); 3907e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 3908d5c65159SKalle Valo ath11k_warn(ar->ab, 3909d5c65159SKalle Valo "msdu_done bit not set in null_q_des processing\n"); 3910d5c65159SKalle Valo __skb_queue_purge(msdu_list); 3911d5c65159SKalle Valo return -EIO; 3912d5c65159SKalle Valo } 3913d5c65159SKalle Valo 3914d5c65159SKalle Valo /* Handle NULL queue descriptor violations arising out a missing 3915d5c65159SKalle Valo * REO queue for a given peer or a given TID. This typically 3916d5c65159SKalle Valo * may happen if a packet is received on a QOS enabled TID before the 3917d5c65159SKalle Valo * ADDBA negotiation for that TID, when the TID queue is setup. Or 3918d5c65159SKalle Valo * it may also happen for MC/BC frames if they are not routed to the 3919d5c65159SKalle Valo * non-QOS TID queue, in the absence of any other default TID queue. 3920d5c65159SKalle Valo * This error can show up both in a REO destination or WBM release ring. 3921d5c65159SKalle Valo */ 3922d5c65159SKalle Valo 3923e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3924e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3925d5c65159SKalle Valo 3926243874c6SManikanta Pubbisetty if (rxcb->is_frag) { 3927e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 3928243874c6SManikanta Pubbisetty } else { 3929e678fbd4SKarthikeyan Periyasamy l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3930d5c65159SKalle Valo 3931e678fbd4SKarthikeyan Periyasamy if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3932d5c65159SKalle Valo return -EINVAL; 3933d5c65159SKalle Valo 3934e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3935e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3936243874c6SManikanta Pubbisetty } 3937d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3938d5c65159SKalle Valo 3939acc79d98SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3940d5c65159SKalle Valo 3941e678fbd4SKarthikeyan Periyasamy rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc); 3942d5c65159SKalle Valo 3943d5c65159SKalle Valo /* Please note that caller will having the access to msdu and completing 3944d5c65159SKalle Valo * rx with mac80211. Need not worry about cleaning up amsdu_list. 3945d5c65159SKalle Valo */ 3946d5c65159SKalle Valo 3947d5c65159SKalle Valo return 0; 3948d5c65159SKalle Valo } 3949d5c65159SKalle Valo 3950d5c65159SKalle Valo static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3951d5c65159SKalle Valo struct ieee80211_rx_status *status, 3952d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3953d5c65159SKalle Valo { 3954d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3955d5c65159SKalle Valo bool drop = false; 3956d5c65159SKalle Valo 3957d5c65159SKalle Valo ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3958d5c65159SKalle Valo 3959d5c65159SKalle Valo switch (rxcb->err_code) { 3960d5c65159SKalle Valo case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3961d5c65159SKalle Valo if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3962d5c65159SKalle Valo drop = true; 3963d5c65159SKalle Valo break; 39641441b2f2SManikanta Pubbisetty case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 39651441b2f2SManikanta Pubbisetty /* TODO: Do not drop PN failed packets in the driver; 39661441b2f2SManikanta Pubbisetty * instead, it is good to drop such packets in mac80211 39671441b2f2SManikanta Pubbisetty * after incrementing the replay counters. 39681441b2f2SManikanta Pubbisetty */ 39690b294aebSGustavo A. R. Silva fallthrough; 3970d5c65159SKalle Valo default: 3971d5c65159SKalle Valo /* TODO: Review other errors and process them to mac80211 3972d5c65159SKalle Valo * as appropriate. 3973d5c65159SKalle Valo */ 3974d5c65159SKalle Valo drop = true; 3975d5c65159SKalle Valo break; 3976d5c65159SKalle Valo } 3977d5c65159SKalle Valo 3978d5c65159SKalle Valo return drop; 3979d5c65159SKalle Valo } 3980d5c65159SKalle Valo 3981d5c65159SKalle Valo static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3982d5c65159SKalle Valo struct ieee80211_rx_status *status) 3983d5c65159SKalle Valo { 3984d5c65159SKalle Valo u16 msdu_len; 3985d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3986d5c65159SKalle Valo u8 l3pad_bytes; 3987d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3988e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3989d5c65159SKalle Valo 3990e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3991e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3992d5c65159SKalle Valo 3993e678fbd4SKarthikeyan Periyasamy l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3994e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3995e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3996e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3997d5c65159SKalle Valo 3998d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3999d5c65159SKalle Valo 4000d5c65159SKalle Valo status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 4001d5c65159SKalle Valo RX_FLAG_DECRYPTED); 4002d5c65159SKalle Valo 4003d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, desc, 4004d5c65159SKalle Valo HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 4005d5c65159SKalle Valo } 4006d5c65159SKalle Valo 4007d5c65159SKalle Valo static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 4008d5c65159SKalle Valo struct ieee80211_rx_status *status) 4009d5c65159SKalle Valo { 4010d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4011d5c65159SKalle Valo bool drop = false; 4012d5c65159SKalle Valo 4013d5c65159SKalle Valo ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 4014d5c65159SKalle Valo 4015d5c65159SKalle Valo switch (rxcb->err_code) { 4016d5c65159SKalle Valo case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 4017d5c65159SKalle Valo ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 4018d5c65159SKalle Valo break; 4019d5c65159SKalle Valo default: 4020d5c65159SKalle Valo /* TODO: Review other rxdma error code to check if anything is 4021d5c65159SKalle Valo * worth reporting to mac80211 4022d5c65159SKalle Valo */ 4023d5c65159SKalle Valo drop = true; 4024d5c65159SKalle Valo break; 4025d5c65159SKalle Valo } 4026d5c65159SKalle Valo 4027d5c65159SKalle Valo return drop; 4028d5c65159SKalle Valo } 4029d5c65159SKalle Valo 4030d5c65159SKalle Valo static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 4031d5c65159SKalle Valo struct napi_struct *napi, 4032d5c65159SKalle Valo struct sk_buff *msdu, 4033d5c65159SKalle Valo struct sk_buff_head *msdu_list) 4034d5c65159SKalle Valo { 4035d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4036d5c65159SKalle Valo struct ieee80211_rx_status rxs = {0}; 4037d5c65159SKalle Valo bool drop = true; 4038d5c65159SKalle Valo 4039d5c65159SKalle Valo switch (rxcb->err_rel_src) { 4040d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_REO: 4041d5c65159SKalle Valo drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 4042d5c65159SKalle Valo break; 4043d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_RXDMA: 4044d5c65159SKalle Valo drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 4045d5c65159SKalle Valo break; 4046d5c65159SKalle Valo default: 4047d5c65159SKalle Valo /* msdu will get freed */ 4048d5c65159SKalle Valo break; 4049d5c65159SKalle Valo } 4050d5c65159SKalle Valo 4051d5c65159SKalle Valo if (drop) { 4052d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4053d5c65159SKalle Valo return; 4054d5c65159SKalle Valo } 4055d5c65159SKalle Valo 40562167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 4057d5c65159SKalle Valo } 4058d5c65159SKalle Valo 4059d5c65159SKalle Valo int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 4060d5c65159SKalle Valo struct napi_struct *napi, int budget) 4061d5c65159SKalle Valo { 4062d5c65159SKalle Valo struct ath11k *ar; 4063d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 4064d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 4065d5c65159SKalle Valo struct hal_rx_wbm_rel_info err_info; 4066d5c65159SKalle Valo struct hal_srng *srng; 4067d5c65159SKalle Valo struct sk_buff *msdu; 4068d5c65159SKalle Valo struct sk_buff_head msdu_list[MAX_RADIOS]; 4069d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4070d5c65159SKalle Valo u32 *rx_desc; 4071d5c65159SKalle Valo int buf_id, mac_id; 4072d5c65159SKalle Valo int num_buffs_reaped[MAX_RADIOS] = {0}; 4073d5c65159SKalle Valo int total_num_buffs_reaped = 0; 4074d5c65159SKalle Valo int ret, i; 4075d5c65159SKalle Valo 4076b1cc29e9SAnilkumar Kolli for (i = 0; i < ab->num_radios; i++) 4077d5c65159SKalle Valo __skb_queue_head_init(&msdu_list[i]); 4078d5c65159SKalle Valo 4079d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4080d5c65159SKalle Valo 4081d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4082d5c65159SKalle Valo 4083d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4084d5c65159SKalle Valo 4085d5c65159SKalle Valo while (budget) { 4086d5c65159SKalle Valo rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 4087d5c65159SKalle Valo if (!rx_desc) 4088d5c65159SKalle Valo break; 4089d5c65159SKalle Valo 4090d5c65159SKalle Valo ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4091d5c65159SKalle Valo if (ret) { 4092d5c65159SKalle Valo ath11k_warn(ab, 4093d5c65159SKalle Valo "failed to parse rx error in wbm_rel ring desc %d\n", 4094d5c65159SKalle Valo ret); 4095d5c65159SKalle Valo continue; 4096d5c65159SKalle Valo } 4097d5c65159SKalle Valo 4098d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 4099d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 4100d5c65159SKalle Valo 4101d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 4102d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 4103d5c65159SKalle Valo 4104d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4105d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4106d5c65159SKalle Valo if (!msdu) { 4107d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 4108d5c65159SKalle Valo buf_id, mac_id); 4109d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4110d5c65159SKalle Valo continue; 4111d5c65159SKalle Valo } 4112d5c65159SKalle Valo 4113d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4114d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4115d5c65159SKalle Valo 4116d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 4117d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 4118d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 4119d5c65159SKalle Valo DMA_FROM_DEVICE); 4120d5c65159SKalle Valo 4121d5c65159SKalle Valo num_buffs_reaped[mac_id]++; 4122d5c65159SKalle Valo total_num_buffs_reaped++; 4123d5c65159SKalle Valo budget--; 4124d5c65159SKalle Valo 4125d5c65159SKalle Valo if (err_info.push_reason != 4126d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4127d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4128d5c65159SKalle Valo continue; 4129d5c65159SKalle Valo } 4130d5c65159SKalle Valo 4131d5c65159SKalle Valo rxcb->err_rel_src = err_info.err_rel_src; 4132d5c65159SKalle Valo rxcb->err_code = err_info.err_code; 4133d5c65159SKalle Valo rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 4134d5c65159SKalle Valo __skb_queue_tail(&msdu_list[mac_id], msdu); 4135d5c65159SKalle Valo } 4136d5c65159SKalle Valo 4137d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4138d5c65159SKalle Valo 4139d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4140d5c65159SKalle Valo 4141d5c65159SKalle Valo if (!total_num_buffs_reaped) 4142d5c65159SKalle Valo goto done; 4143d5c65159SKalle Valo 4144d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 4145d5c65159SKalle Valo if (!num_buffs_reaped[i]) 4146d5c65159SKalle Valo continue; 4147d5c65159SKalle Valo 4148d5c65159SKalle Valo ar = ab->pdevs[i].ar; 4149d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 4150d5c65159SKalle Valo 4151d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 4152734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 4153d5c65159SKalle Valo } 4154d5c65159SKalle Valo 4155d5c65159SKalle Valo rcu_read_lock(); 4156d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 4157d5c65159SKalle Valo if (!rcu_dereference(ab->pdevs_active[i])) { 4158d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 4159d5c65159SKalle Valo continue; 4160d5c65159SKalle Valo } 4161d5c65159SKalle Valo 4162d5c65159SKalle Valo ar = ab->pdevs[i].ar; 4163d5c65159SKalle Valo 4164d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 4165d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 4166d5c65159SKalle Valo continue; 4167d5c65159SKalle Valo } 4168d5c65159SKalle Valo 4169d5c65159SKalle Valo while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 4170d5c65159SKalle Valo ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 4171d5c65159SKalle Valo } 4172d5c65159SKalle Valo rcu_read_unlock(); 4173d5c65159SKalle Valo done: 4174d5c65159SKalle Valo return total_num_buffs_reaped; 4175d5c65159SKalle Valo } 4176d5c65159SKalle Valo 4177d5c65159SKalle Valo int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 4178d5c65159SKalle Valo { 41794152e420SCarl Huang struct ath11k *ar; 41804152e420SCarl Huang struct dp_srng *err_ring; 41814152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 4182d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 4183d5c65159SKalle Valo struct hal_srng *srng; 4184293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 4185d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 4186d5c65159SKalle Valo enum hal_reo_entr_rxdma_ecode rxdma_err_code; 4187d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4188d5c65159SKalle Valo struct sk_buff *skb; 4189d5c65159SKalle Valo struct hal_reo_entrance_ring *entr_ring; 4190d5c65159SKalle Valo void *desc; 4191d5c65159SKalle Valo int num_buf_freed = 0; 4192d5c65159SKalle Valo int quota = budget; 4193d5c65159SKalle Valo dma_addr_t paddr; 4194d5c65159SKalle Valo u32 desc_bank; 4195d5c65159SKalle Valo void *link_desc_va; 4196d5c65159SKalle Valo int num_msdus; 4197d5c65159SKalle Valo int i; 4198d5c65159SKalle Valo int buf_id; 4199d5c65159SKalle Valo 42004152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 42014152e420SCarl Huang err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params, 42024152e420SCarl Huang mac_id)]; 42034152e420SCarl Huang rx_ring = &ar->dp.rx_refill_buf_ring; 42044152e420SCarl Huang 4205d5c65159SKalle Valo srng = &ab->hal.srng_list[err_ring->ring_id]; 4206d5c65159SKalle Valo 4207d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4208d5c65159SKalle Valo 4209d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4210d5c65159SKalle Valo 4211d5c65159SKalle Valo while (quota-- && 4212d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4213d5c65159SKalle Valo ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 4214d5c65159SKalle Valo 4215d5c65159SKalle Valo entr_ring = (struct hal_reo_entrance_ring *)desc; 4216d5c65159SKalle Valo rxdma_err_code = 4217d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4218d5c65159SKalle Valo entr_ring->info1); 4219d5c65159SKalle Valo ab->soc_stats.rxdma_error[rxdma_err_code]++; 4220d5c65159SKalle Valo 4221d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 4222d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 4223293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 4224293cb583SJohn Crispin msdu_cookies, &rbm); 4225d5c65159SKalle Valo 4226d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4227d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4228293cb583SJohn Crispin msdu_cookies[i]); 4229d5c65159SKalle Valo 4230d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4231d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 4232d5c65159SKalle Valo if (!skb) { 4233d5c65159SKalle Valo ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 4234d5c65159SKalle Valo buf_id); 4235d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4236d5c65159SKalle Valo continue; 4237d5c65159SKalle Valo } 4238d5c65159SKalle Valo 4239d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4240d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4241d5c65159SKalle Valo 4242d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 4243d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 4244d5c65159SKalle Valo skb->len + skb_tailroom(skb), 4245d5c65159SKalle Valo DMA_FROM_DEVICE); 4246d5c65159SKalle Valo dev_kfree_skb_any(skb); 4247d5c65159SKalle Valo 4248d5c65159SKalle Valo num_buf_freed++; 4249d5c65159SKalle Valo } 4250d5c65159SKalle Valo 4251d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 4252d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4253d5c65159SKalle Valo } 4254d5c65159SKalle Valo 4255d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4256d5c65159SKalle Valo 4257d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4258d5c65159SKalle Valo 4259d5c65159SKalle Valo if (num_buf_freed) 4260d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 4261734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 4262d5c65159SKalle Valo 4263d5c65159SKalle Valo return budget - quota; 4264d5c65159SKalle Valo } 4265d5c65159SKalle Valo 4266d5c65159SKalle Valo void ath11k_dp_process_reo_status(struct ath11k_base *ab) 4267d5c65159SKalle Valo { 4268d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 4269d5c65159SKalle Valo struct hal_srng *srng; 4270d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 4271d5c65159SKalle Valo bool found = false; 4272d5c65159SKalle Valo u32 *reo_desc; 4273d5c65159SKalle Valo u16 tag; 4274d5c65159SKalle Valo struct hal_reo_status reo_status; 4275d5c65159SKalle Valo 4276d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4277d5c65159SKalle Valo 4278d5c65159SKalle Valo memset(&reo_status, 0, sizeof(reo_status)); 4279d5c65159SKalle Valo 4280d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4281d5c65159SKalle Valo 4282d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4283d5c65159SKalle Valo 4284d5c65159SKalle Valo while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4285d5c65159SKalle Valo tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 4286d5c65159SKalle Valo 4287d5c65159SKalle Valo switch (tag) { 4288d5c65159SKalle Valo case HAL_REO_GET_QUEUE_STATS_STATUS: 4289d5c65159SKalle Valo ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4290d5c65159SKalle Valo &reo_status); 4291d5c65159SKalle Valo break; 4292d5c65159SKalle Valo case HAL_REO_FLUSH_QUEUE_STATUS: 4293d5c65159SKalle Valo ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4294d5c65159SKalle Valo &reo_status); 4295d5c65159SKalle Valo break; 4296d5c65159SKalle Valo case HAL_REO_FLUSH_CACHE_STATUS: 4297d5c65159SKalle Valo ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4298d5c65159SKalle Valo &reo_status); 4299d5c65159SKalle Valo break; 4300d5c65159SKalle Valo case HAL_REO_UNBLOCK_CACHE_STATUS: 4301d5c65159SKalle Valo ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4302d5c65159SKalle Valo &reo_status); 4303d5c65159SKalle Valo break; 4304d5c65159SKalle Valo case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4305d5c65159SKalle Valo ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4306d5c65159SKalle Valo &reo_status); 4307d5c65159SKalle Valo break; 4308d5c65159SKalle Valo case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4309d5c65159SKalle Valo ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4310d5c65159SKalle Valo &reo_status); 4311d5c65159SKalle Valo break; 4312d5c65159SKalle Valo case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4313d5c65159SKalle Valo ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4314d5c65159SKalle Valo &reo_status); 4315d5c65159SKalle Valo break; 4316d5c65159SKalle Valo default: 4317d5c65159SKalle Valo ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4318d5c65159SKalle Valo continue; 4319d5c65159SKalle Valo } 4320d5c65159SKalle Valo 4321d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 4322d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4323d5c65159SKalle Valo if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4324d5c65159SKalle Valo found = true; 4325d5c65159SKalle Valo list_del(&cmd->list); 4326d5c65159SKalle Valo break; 4327d5c65159SKalle Valo } 4328d5c65159SKalle Valo } 4329d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 4330d5c65159SKalle Valo 4331d5c65159SKalle Valo if (found) { 4332d5c65159SKalle Valo cmd->handler(dp, (void *)&cmd->data, 4333d5c65159SKalle Valo reo_status.uniform_hdr.cmd_status); 4334d5c65159SKalle Valo kfree(cmd); 4335d5c65159SKalle Valo } 4336d5c65159SKalle Valo 4337d5c65159SKalle Valo found = false; 4338d5c65159SKalle Valo } 4339d5c65159SKalle Valo 4340d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4341d5c65159SKalle Valo 4342d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4343d5c65159SKalle Valo } 4344d5c65159SKalle Valo 4345d5c65159SKalle Valo void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4346d5c65159SKalle Valo { 4347d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4348d5c65159SKalle Valo 4349d5c65159SKalle Valo ath11k_dp_rx_pdev_srng_free(ar); 4350d5c65159SKalle Valo ath11k_dp_rxdma_pdev_buf_free(ar); 4351d5c65159SKalle Valo } 4352d5c65159SKalle Valo 4353d5c65159SKalle Valo int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4354d5c65159SKalle Valo { 4355d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4356d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4357d5c65159SKalle Valo u32 ring_id; 43584152e420SCarl Huang int i; 4359d5c65159SKalle Valo int ret; 4360d5c65159SKalle Valo 4361d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4362d5c65159SKalle Valo if (ret) { 4363d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx srngs\n"); 4364d5c65159SKalle Valo return ret; 4365d5c65159SKalle Valo } 4366d5c65159SKalle Valo 4367d5c65159SKalle Valo ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4368d5c65159SKalle Valo if (ret) { 4369d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rxdma ring\n"); 4370d5c65159SKalle Valo return ret; 4371d5c65159SKalle Valo } 4372d5c65159SKalle Valo 4373d5c65159SKalle Valo ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4374d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4375d5c65159SKalle Valo if (ret) { 4376d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4377d5c65159SKalle Valo ret); 4378d5c65159SKalle Valo return ret; 4379d5c65159SKalle Valo } 4380d5c65159SKalle Valo 43814152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) { 43824152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 43834152e420SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id; 43844152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 43854152e420SCarl Huang mac_id + i, HAL_RXDMA_BUF); 4386d5c65159SKalle Valo if (ret) { 43874152e420SCarl Huang ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 43884152e420SCarl Huang i, ret); 4389d5c65159SKalle Valo return ret; 4390d5c65159SKalle Valo } 43914152e420SCarl Huang } 43924152e420SCarl Huang } 43934152e420SCarl Huang 43944152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 43954152e420SCarl Huang ring_id = dp->rxdma_err_dst_ring[i].ring_id; 43964152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 43974152e420SCarl Huang mac_id + i, HAL_RXDMA_DST); 43984152e420SCarl Huang if (ret) { 43994152e420SCarl Huang ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 44004152e420SCarl Huang i, ret); 44014152e420SCarl Huang return ret; 44024152e420SCarl Huang } 44034152e420SCarl Huang } 4404d5c65159SKalle Valo 44057f6fc1ebSCarl Huang if (!ab->hw_params.rxdma1_enable) 44067f6fc1ebSCarl Huang goto config_refill_ring; 44077f6fc1ebSCarl Huang 4408d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4409d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4410d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_BUF); 4411d5c65159SKalle Valo if (ret) { 4412d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4413d5c65159SKalle Valo ret); 4414d5c65159SKalle Valo return ret; 4415d5c65159SKalle Valo } 4416d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4417d5c65159SKalle Valo dp->rxdma_mon_dst_ring.ring_id, 4418d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DST); 4419d5c65159SKalle Valo if (ret) { 4420d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4421d5c65159SKalle Valo ret); 4422d5c65159SKalle Valo return ret; 4423d5c65159SKalle Valo } 4424d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4425d5c65159SKalle Valo dp->rxdma_mon_desc_ring.ring_id, 4426d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DESC); 4427d5c65159SKalle Valo if (ret) { 4428d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4429d5c65159SKalle Valo ret); 4430d5c65159SKalle Valo return ret; 4431d5c65159SKalle Valo } 44327f6fc1ebSCarl Huang 44337f6fc1ebSCarl Huang config_refill_ring: 44344152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 44354152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 44364152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, 4437d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS); 4438d5c65159SKalle Valo if (ret) { 4439d5c65159SKalle Valo ath11k_warn(ab, 44404152e420SCarl Huang "failed to configure mon_status_refill_ring%d %d\n", 44414152e420SCarl Huang i, ret); 4442d5c65159SKalle Valo return ret; 4443d5c65159SKalle Valo } 44444152e420SCarl Huang } 44457f6fc1ebSCarl Huang 4446d5c65159SKalle Valo return 0; 4447d5c65159SKalle Valo } 4448d5c65159SKalle Valo 4449d5c65159SKalle Valo static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4450d5c65159SKalle Valo { 4451d5c65159SKalle Valo if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4452d5c65159SKalle Valo *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4453d5c65159SKalle Valo *total_len -= *frag_len; 4454d5c65159SKalle Valo } else { 4455d5c65159SKalle Valo *frag_len = *total_len; 4456d5c65159SKalle Valo *total_len = 0; 4457d5c65159SKalle Valo } 4458d5c65159SKalle Valo } 4459d5c65159SKalle Valo 4460d5c65159SKalle Valo static 4461d5c65159SKalle Valo int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4462d5c65159SKalle Valo void *p_last_buf_addr_info, 4463d5c65159SKalle Valo u8 mac_id) 4464d5c65159SKalle Valo { 4465d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4466d5c65159SKalle Valo struct dp_srng *dp_srng; 4467d5c65159SKalle Valo void *hal_srng; 4468d5c65159SKalle Valo void *src_srng_desc; 4469d5c65159SKalle Valo int ret = 0; 4470d5c65159SKalle Valo 4471701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4472d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 4473d5c65159SKalle Valo hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4474701e48a4SCarl Huang } else { 4475701e48a4SCarl Huang dp_srng = &ar->ab->dp.wbm_desc_rel_ring; 4476701e48a4SCarl Huang hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4477701e48a4SCarl Huang } 4478d5c65159SKalle Valo 4479d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4480d5c65159SKalle Valo 4481d5c65159SKalle Valo src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4482d5c65159SKalle Valo 4483d5c65159SKalle Valo if (src_srng_desc) { 4484d5c65159SKalle Valo struct ath11k_buffer_addr *src_desc = 4485d5c65159SKalle Valo (struct ath11k_buffer_addr *)src_srng_desc; 4486d5c65159SKalle Valo 4487d5c65159SKalle Valo *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4488d5c65159SKalle Valo } else { 4489d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4490d5c65159SKalle Valo "Monitor Link Desc Ring %d Full", mac_id); 4491d5c65159SKalle Valo ret = -ENOMEM; 4492d5c65159SKalle Valo } 4493d5c65159SKalle Valo 4494d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, hal_srng); 4495d5c65159SKalle Valo return ret; 4496d5c65159SKalle Valo } 4497d5c65159SKalle Valo 4498d5c65159SKalle Valo static 4499d5c65159SKalle Valo void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4500d5c65159SKalle Valo dma_addr_t *paddr, u32 *sw_cookie, 4501701e48a4SCarl Huang u8 *rbm, 4502d5c65159SKalle Valo void **pp_buf_addr_info) 4503d5c65159SKalle Valo { 4504d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = 4505d5c65159SKalle Valo (struct hal_rx_msdu_link *)rx_msdu_link_desc; 4506d5c65159SKalle Valo struct ath11k_buffer_addr *buf_addr_info; 4507d5c65159SKalle Valo 4508d5c65159SKalle Valo buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4509d5c65159SKalle Valo 4510701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 4511d5c65159SKalle Valo 4512d5c65159SKalle Valo *pp_buf_addr_info = (void *)buf_addr_info; 4513d5c65159SKalle Valo } 4514d5c65159SKalle Valo 4515d5c65159SKalle Valo static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4516d5c65159SKalle Valo { 4517d5c65159SKalle Valo if (skb->len > len) { 4518d5c65159SKalle Valo skb_trim(skb, len); 4519d5c65159SKalle Valo } else { 4520d5c65159SKalle Valo if (skb_tailroom(skb) < len - skb->len) { 4521d5c65159SKalle Valo if ((pskb_expand_head(skb, 0, 4522d5c65159SKalle Valo len - skb->len - skb_tailroom(skb), 4523d5c65159SKalle Valo GFP_ATOMIC))) { 4524d5c65159SKalle Valo dev_kfree_skb_any(skb); 4525d5c65159SKalle Valo return -ENOMEM; 4526d5c65159SKalle Valo } 4527d5c65159SKalle Valo } 4528d5c65159SKalle Valo skb_put(skb, (len - skb->len)); 4529d5c65159SKalle Valo } 4530d5c65159SKalle Valo return 0; 4531d5c65159SKalle Valo } 4532d5c65159SKalle Valo 4533d5c65159SKalle Valo static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4534d5c65159SKalle Valo void *msdu_link_desc, 4535d5c65159SKalle Valo struct hal_rx_msdu_list *msdu_list, 4536d5c65159SKalle Valo u16 *num_msdus) 4537d5c65159SKalle Valo { 4538d5c65159SKalle Valo struct hal_rx_msdu_details *msdu_details = NULL; 4539d5c65159SKalle Valo struct rx_msdu_desc *msdu_desc_info = NULL; 4540d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = NULL; 4541d5c65159SKalle Valo int i; 4542d5c65159SKalle Valo u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4543d5c65159SKalle Valo u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4544d5c65159SKalle Valo u8 tmp = 0; 4545d5c65159SKalle Valo 4546d5c65159SKalle Valo msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc; 4547d5c65159SKalle Valo msdu_details = &msdu_link->msdu_link[0]; 4548d5c65159SKalle Valo 4549d5c65159SKalle Valo for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4550d5c65159SKalle Valo if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4551d5c65159SKalle Valo msdu_details[i].buf_addr_info.info0) == 0) { 4552d5c65159SKalle Valo msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4553d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4554d5c65159SKalle Valo ; 4555d5c65159SKalle Valo break; 4556d5c65159SKalle Valo } 4557d5c65159SKalle Valo msdu_desc_info = &msdu_details[i].rx_msdu_info; 4558d5c65159SKalle Valo 4559d5c65159SKalle Valo if (!i) 4560d5c65159SKalle Valo msdu_desc_info->info0 |= first; 4561d5c65159SKalle Valo else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4562d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4563d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4564d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_len = 4565d5c65159SKalle Valo HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4566d5c65159SKalle Valo msdu_list->sw_cookie[i] = 4567d5c65159SKalle Valo FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4568d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4569d5c65159SKalle Valo tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4570d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4571d5c65159SKalle Valo msdu_list->rbm[i] = tmp; 4572d5c65159SKalle Valo } 4573d5c65159SKalle Valo *num_msdus = i; 4574d5c65159SKalle Valo } 4575d5c65159SKalle Valo 4576d5c65159SKalle Valo static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4577d5c65159SKalle Valo u32 *rx_bufs_used) 4578d5c65159SKalle Valo { 4579d5c65159SKalle Valo u32 ret = 0; 4580d5c65159SKalle Valo 4581d5c65159SKalle Valo if ((*ppdu_id < msdu_ppdu_id) && 4582d5c65159SKalle Valo ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4583d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4584d5c65159SKalle Valo ret = msdu_ppdu_id; 4585d5c65159SKalle Valo } else if ((*ppdu_id > msdu_ppdu_id) && 4586d5c65159SKalle Valo ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4587d5c65159SKalle Valo /* mon_dst is behind than mon_status 4588d5c65159SKalle Valo * skip dst_ring and free it 4589d5c65159SKalle Valo */ 4590d5c65159SKalle Valo *rx_bufs_used += 1; 4591d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4592d5c65159SKalle Valo ret = msdu_ppdu_id; 4593d5c65159SKalle Valo } 4594d5c65159SKalle Valo return ret; 4595d5c65159SKalle Valo } 4596d5c65159SKalle Valo 4597d5c65159SKalle Valo static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4598d5c65159SKalle Valo bool *is_frag, u32 *total_len, 4599d5c65159SKalle Valo u32 *frag_len, u32 *msdu_cnt) 4600d5c65159SKalle Valo { 4601d5c65159SKalle Valo if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4602d5c65159SKalle Valo if (!*is_frag) { 4603d5c65159SKalle Valo *total_len = info->msdu_len; 4604d5c65159SKalle Valo *is_frag = true; 4605d5c65159SKalle Valo } 4606d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4607d5c65159SKalle Valo frag_len); 4608d5c65159SKalle Valo } else { 4609d5c65159SKalle Valo if (*is_frag) { 4610d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4611d5c65159SKalle Valo frag_len); 4612d5c65159SKalle Valo } else { 4613d5c65159SKalle Valo *frag_len = info->msdu_len; 4614d5c65159SKalle Valo } 4615d5c65159SKalle Valo *is_frag = false; 4616d5c65159SKalle Valo *msdu_cnt -= 1; 4617d5c65159SKalle Valo } 4618d5c65159SKalle Valo } 4619d5c65159SKalle Valo 4620d5c65159SKalle Valo static u32 4621701e48a4SCarl Huang ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id, 4622d5c65159SKalle Valo void *ring_entry, struct sk_buff **head_msdu, 4623d5c65159SKalle Valo struct sk_buff **tail_msdu, u32 *npackets, 4624d5c65159SKalle Valo u32 *ppdu_id) 4625d5c65159SKalle Valo { 4626d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4627d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4628d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4629d5c65159SKalle Valo struct sk_buff *msdu = NULL, *last = NULL; 4630d5c65159SKalle Valo struct hal_rx_msdu_list msdu_list; 4631d5c65159SKalle Valo void *p_buf_addr_info, *p_last_buf_addr_info; 4632d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4633d5c65159SKalle Valo void *rx_msdu_link_desc; 4634d5c65159SKalle Valo dma_addr_t paddr; 4635d5c65159SKalle Valo u16 num_msdus = 0; 4636d5c65159SKalle Valo u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4637d5c65159SKalle Valo u32 rx_bufs_used = 0, i = 0; 4638d5c65159SKalle Valo u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4639d5c65159SKalle Valo u32 total_len = 0, frag_len = 0; 4640d5c65159SKalle Valo bool is_frag, is_first_msdu; 4641d5c65159SKalle Valo bool drop_mpdu = false; 4642d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4643d5c65159SKalle Valo struct hal_reo_entrance_ring *ent_desc = 4644d5c65159SKalle Valo (struct hal_reo_entrance_ring *)ring_entry; 4645d5c65159SKalle Valo int buf_id; 4646701e48a4SCarl Huang u32 rx_link_buf_info[2]; 4647701e48a4SCarl Huang u8 rbm; 4648701e48a4SCarl Huang 4649701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 4650701e48a4SCarl Huang rx_ring = &dp->rx_refill_buf_ring; 4651d5c65159SKalle Valo 4652d5c65159SKalle Valo ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4653701e48a4SCarl Huang &sw_cookie, 4654701e48a4SCarl Huang &p_last_buf_addr_info, &rbm, 4655d5c65159SKalle Valo &msdu_cnt); 4656d5c65159SKalle Valo 4657d5c65159SKalle Valo if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4658d5c65159SKalle Valo ent_desc->info1) == 4659d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4660d5c65159SKalle Valo u8 rxdma_err = 4661d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4662d5c65159SKalle Valo ent_desc->info1); 4663d5c65159SKalle Valo if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4664d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4665d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4666d5c65159SKalle Valo drop_mpdu = true; 4667d5c65159SKalle Valo pmon->rx_mon_stats.dest_mpdu_drop++; 4668d5c65159SKalle Valo } 4669d5c65159SKalle Valo } 4670d5c65159SKalle Valo 4671d5c65159SKalle Valo is_frag = false; 4672d5c65159SKalle Valo is_first_msdu = true; 4673d5c65159SKalle Valo 4674d5c65159SKalle Valo do { 4675d5c65159SKalle Valo if (pmon->mon_last_linkdesc_paddr == paddr) { 4676d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4677d5c65159SKalle Valo return rx_bufs_used; 4678d5c65159SKalle Valo } 4679d5c65159SKalle Valo 4680701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 4681d5c65159SKalle Valo rx_msdu_link_desc = 4682d5c65159SKalle Valo (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4683d5c65159SKalle Valo (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4684701e48a4SCarl Huang else 4685701e48a4SCarl Huang rx_msdu_link_desc = 4686701e48a4SCarl Huang (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr + 4687701e48a4SCarl Huang (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr); 4688d5c65159SKalle Valo 4689d5c65159SKalle Valo ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4690d5c65159SKalle Valo &num_msdus); 4691d5c65159SKalle Valo 4692d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4693d5c65159SKalle Valo u32 l2_hdr_offset; 4694d5c65159SKalle Valo 4695d5c65159SKalle Valo if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4696d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4697d5c65159SKalle Valo "i %d last_cookie %d is same\n", 4698d5c65159SKalle Valo i, pmon->mon_last_buf_cookie); 4699d5c65159SKalle Valo drop_mpdu = true; 4700d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_buf_cnt++; 4701d5c65159SKalle Valo continue; 4702d5c65159SKalle Valo } 4703d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4704d5c65159SKalle Valo msdu_list.sw_cookie[i]); 4705d5c65159SKalle Valo 4706d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4707d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4708d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4709d5c65159SKalle Valo if (!msdu) { 4710d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4711d5c65159SKalle Valo "msdu_pop: invalid buf_id %d\n", buf_id); 4712d5c65159SKalle Valo break; 4713d5c65159SKalle Valo } 4714d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 4715d5c65159SKalle Valo if (!rxcb->unmapped) { 4716d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 4717d5c65159SKalle Valo msdu->len + 4718d5c65159SKalle Valo skb_tailroom(msdu), 4719d5c65159SKalle Valo DMA_FROM_DEVICE); 4720d5c65159SKalle Valo rxcb->unmapped = 1; 4721d5c65159SKalle Valo } 4722d5c65159SKalle Valo if (drop_mpdu) { 4723d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4724d5c65159SKalle Valo "i %d drop msdu %p *ppdu_id %x\n", 4725d5c65159SKalle Valo i, msdu, *ppdu_id); 4726d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4727d5c65159SKalle Valo msdu = NULL; 4728d5c65159SKalle Valo goto next_msdu; 4729d5c65159SKalle Valo } 4730d5c65159SKalle Valo 4731d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 4732d5c65159SKalle Valo 4733d5c65159SKalle Valo rx_pkt_offset = sizeof(struct hal_rx_desc); 4734e678fbd4SKarthikeyan Periyasamy l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 4735d5c65159SKalle Valo 4736d5c65159SKalle Valo if (is_first_msdu) { 4737e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 4738d5c65159SKalle Valo drop_mpdu = true; 4739d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4740d5c65159SKalle Valo msdu = NULL; 4741d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4742d5c65159SKalle Valo goto next_msdu; 4743d5c65159SKalle Valo } 4744d5c65159SKalle Valo 4745d5c65159SKalle Valo msdu_ppdu_id = 4746e678fbd4SKarthikeyan Periyasamy ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc); 4747d5c65159SKalle Valo 4748d5c65159SKalle Valo if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4749d5c65159SKalle Valo ppdu_id, 47505e02bc73SMiles Hu &rx_bufs_used)) { 47515e02bc73SMiles Hu if (rx_bufs_used) { 47525e02bc73SMiles Hu drop_mpdu = true; 47535e02bc73SMiles Hu dev_kfree_skb_any(msdu); 47545e02bc73SMiles Hu msdu = NULL; 47555e02bc73SMiles Hu goto next_msdu; 47565e02bc73SMiles Hu } 4757d5c65159SKalle Valo return rx_bufs_used; 47585e02bc73SMiles Hu } 4759d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4760d5c65159SKalle Valo is_first_msdu = false; 4761d5c65159SKalle Valo } 4762d5c65159SKalle Valo ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4763d5c65159SKalle Valo &is_frag, &total_len, 4764d5c65159SKalle Valo &frag_len, &msdu_cnt); 4765d5c65159SKalle Valo rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4766d5c65159SKalle Valo 4767d5c65159SKalle Valo ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4768d5c65159SKalle Valo 4769d5c65159SKalle Valo if (!(*head_msdu)) 4770d5c65159SKalle Valo *head_msdu = msdu; 4771d5c65159SKalle Valo else if (last) 4772d5c65159SKalle Valo last->next = msdu; 4773d5c65159SKalle Valo 4774d5c65159SKalle Valo last = msdu; 4775d5c65159SKalle Valo next_msdu: 4776d5c65159SKalle Valo pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4777d5c65159SKalle Valo rx_bufs_used++; 4778d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4779d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4780d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4781d5c65159SKalle Valo } 4782d5c65159SKalle Valo 4783701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm); 4784701e48a4SCarl Huang 4785d5c65159SKalle Valo ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4786701e48a4SCarl Huang &sw_cookie, &rbm, 4787d5c65159SKalle Valo &p_buf_addr_info); 4788d5c65159SKalle Valo 4789701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4790d5c65159SKalle Valo if (ath11k_dp_rx_monitor_link_desc_return(ar, 4791d5c65159SKalle Valo p_last_buf_addr_info, 4792d5c65159SKalle Valo dp->mac_id)) 4793d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4794d5c65159SKalle Valo "dp_rx_monitor_link_desc_return failed"); 4795701e48a4SCarl Huang } else { 4796701e48a4SCarl Huang ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info, 4797701e48a4SCarl Huang HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4798701e48a4SCarl Huang } 4799d5c65159SKalle Valo 4800d5c65159SKalle Valo p_last_buf_addr_info = p_buf_addr_info; 4801d5c65159SKalle Valo 4802d5c65159SKalle Valo } while (paddr && msdu_cnt); 4803d5c65159SKalle Valo 4804d5c65159SKalle Valo if (last) 4805d5c65159SKalle Valo last->next = NULL; 4806d5c65159SKalle Valo 4807d5c65159SKalle Valo *tail_msdu = msdu; 4808d5c65159SKalle Valo 4809d5c65159SKalle Valo if (msdu_cnt == 0) 4810d5c65159SKalle Valo *npackets = 1; 4811d5c65159SKalle Valo 4812d5c65159SKalle Valo return rx_bufs_used; 4813d5c65159SKalle Valo } 4814d5c65159SKalle Valo 4815e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu) 4816d5c65159SKalle Valo { 4817d5c65159SKalle Valo u32 rx_pkt_offset, l2_hdr_offset; 4818d5c65159SKalle Valo 4819e678fbd4SKarthikeyan Periyasamy rx_pkt_offset = ar->ab->hw_params.hal_desc_sz; 4820e678fbd4SKarthikeyan Periyasamy l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, 4821e678fbd4SKarthikeyan Periyasamy (struct hal_rx_desc *)msdu->data); 4822d5c65159SKalle Valo skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4823d5c65159SKalle Valo } 4824d5c65159SKalle Valo 4825d5c65159SKalle Valo static struct sk_buff * 4826d5c65159SKalle Valo ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4827d5c65159SKalle Valo u32 mac_id, struct sk_buff *head_msdu, 4828d5c65159SKalle Valo struct sk_buff *last_msdu, 4829*78726489SP Praneesh struct ieee80211_rx_status *rxs, bool *fcs_err) 4830d5c65159SKalle Valo { 4831e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 48327210b4b7STim Gardner struct sk_buff *msdu, *prev_buf; 4833e678fbd4SKarthikeyan Periyasamy u32 wifi_hdr_len; 4834d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4835d5c65159SKalle Valo char *hdr_desc; 4836e678fbd4SKarthikeyan Periyasamy u8 *dest, decap_format; 4837d5c65159SKalle Valo struct ieee80211_hdr_3addr *wh; 4838e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 4839*78726489SP Praneesh u32 err_bitmap; 4840d5c65159SKalle Valo 4841d5c65159SKalle Valo if (!head_msdu) 4842d5c65159SKalle Valo goto err_merge_fail; 4843d5c65159SKalle Valo 4844d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4845e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc); 4846*78726489SP Praneesh err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 4847*78726489SP Praneesh 4848*78726489SP Praneesh if (err_bitmap & DP_RX_MPDU_ERR_FCS) 4849*78726489SP Praneesh *fcs_err = true; 4850d5c65159SKalle Valo 4851e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention)) 4852d5c65159SKalle Valo return NULL; 4853d5c65159SKalle Valo 4854e678fbd4SKarthikeyan Periyasamy decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc); 4855d5c65159SKalle Valo 4856d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4857d5c65159SKalle Valo 4858d5c65159SKalle Valo if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4859e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_msdus_set_payload(ar, head_msdu); 4860d5c65159SKalle Valo 4861d5c65159SKalle Valo prev_buf = head_msdu; 4862d5c65159SKalle Valo msdu = head_msdu->next; 4863d5c65159SKalle Valo 4864d5c65159SKalle Valo while (msdu) { 4865e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_msdus_set_payload(ar, msdu); 4866d5c65159SKalle Valo 4867d5c65159SKalle Valo prev_buf = msdu; 4868d5c65159SKalle Valo msdu = msdu->next; 4869d5c65159SKalle Valo } 4870d5c65159SKalle Valo 4871d5c65159SKalle Valo prev_buf->next = NULL; 4872d5c65159SKalle Valo 4873d5c65159SKalle Valo skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4874d5c65159SKalle Valo } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4875d5c65159SKalle Valo __le16 qos_field; 4876d5c65159SKalle Valo u8 qos_pkt = 0; 4877d5c65159SKalle Valo 4878d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4879e678fbd4SKarthikeyan Periyasamy hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc); 4880d5c65159SKalle Valo 4881d5c65159SKalle Valo /* Base size */ 4882d5c65159SKalle Valo wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr); 4883d5c65159SKalle Valo wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4884d5c65159SKalle Valo 4885d5c65159SKalle Valo if (ieee80211_is_data_qos(wh->frame_control)) { 4886d5c65159SKalle Valo struct ieee80211_qos_hdr *qwh = 4887d5c65159SKalle Valo (struct ieee80211_qos_hdr *)hdr_desc; 4888d5c65159SKalle Valo 4889d5c65159SKalle Valo qos_field = qwh->qos_ctrl; 4890d5c65159SKalle Valo qos_pkt = 1; 4891d5c65159SKalle Valo } 4892d5c65159SKalle Valo msdu = head_msdu; 4893d5c65159SKalle Valo 4894d5c65159SKalle Valo while (msdu) { 4895d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 4896e678fbd4SKarthikeyan Periyasamy hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc); 4897d5c65159SKalle Valo 4898d5c65159SKalle Valo if (qos_pkt) { 4899d5c65159SKalle Valo dest = skb_push(msdu, sizeof(__le16)); 4900d5c65159SKalle Valo if (!dest) 4901d5c65159SKalle Valo goto err_merge_fail; 4902d5c65159SKalle Valo memcpy(dest, hdr_desc, wifi_hdr_len); 4903d5c65159SKalle Valo memcpy(dest + wifi_hdr_len, 4904d5c65159SKalle Valo (u8 *)&qos_field, sizeof(__le16)); 4905d5c65159SKalle Valo } 4906e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_msdus_set_payload(ar, msdu); 4907d5c65159SKalle Valo prev_buf = msdu; 4908d5c65159SKalle Valo msdu = msdu->next; 4909d5c65159SKalle Valo } 4910d5c65159SKalle Valo dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4911d5c65159SKalle Valo if (!dest) 4912d5c65159SKalle Valo goto err_merge_fail; 4913d5c65159SKalle Valo 4914e678fbd4SKarthikeyan Periyasamy ath11k_dbg(ab, ATH11K_DBG_DATA, 4915d5c65159SKalle Valo "mpdu_buf %pK mpdu_buf->len %u", 4916d5c65159SKalle Valo prev_buf, prev_buf->len); 4917d5c65159SKalle Valo } else { 4918e678fbd4SKarthikeyan Periyasamy ath11k_dbg(ab, ATH11K_DBG_DATA, 4919d5c65159SKalle Valo "decap format %d is not supported!\n", 4920d5c65159SKalle Valo decap_format); 4921d5c65159SKalle Valo goto err_merge_fail; 4922d5c65159SKalle Valo } 4923d5c65159SKalle Valo 4924d5c65159SKalle Valo return head_msdu; 4925d5c65159SKalle Valo 4926d5c65159SKalle Valo err_merge_fail: 4927d5c65159SKalle Valo return NULL; 4928d5c65159SKalle Valo } 4929d5c65159SKalle Valo 4930d5c65159SKalle Valo static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 4931d5c65159SKalle Valo struct sk_buff *head_msdu, 4932d5c65159SKalle Valo struct sk_buff *tail_msdu, 4933d5c65159SKalle Valo struct napi_struct *napi) 4934d5c65159SKalle Valo { 4935d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4936d5c65159SKalle Valo struct sk_buff *mon_skb, *skb_next, *header; 49372167fa60SSriram R struct ieee80211_rx_status *rxs = &dp->rx_status; 4938*78726489SP Praneesh bool fcs_err = false; 4939d5c65159SKalle Valo 4940d5c65159SKalle Valo mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 4941*78726489SP Praneesh tail_msdu, rxs, &fcs_err); 4942d5c65159SKalle Valo 4943d5c65159SKalle Valo if (!mon_skb) 4944d5c65159SKalle Valo goto mon_deliver_fail; 4945d5c65159SKalle Valo 4946d5c65159SKalle Valo header = mon_skb; 4947d5c65159SKalle Valo 4948d5c65159SKalle Valo rxs->flag = 0; 4949*78726489SP Praneesh 4950*78726489SP Praneesh if (fcs_err) 4951*78726489SP Praneesh rxs->flag = RX_FLAG_FAILED_FCS_CRC; 4952*78726489SP Praneesh 4953d5c65159SKalle Valo do { 4954d5c65159SKalle Valo skb_next = mon_skb->next; 4955d5c65159SKalle Valo if (!skb_next) 4956d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_AMSDU_MORE; 4957d5c65159SKalle Valo else 4958d5c65159SKalle Valo rxs->flag |= RX_FLAG_AMSDU_MORE; 4959d5c65159SKalle Valo 4960d5c65159SKalle Valo if (mon_skb == header) { 4961d5c65159SKalle Valo header = NULL; 4962d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 4963d5c65159SKalle Valo } else { 4964d5c65159SKalle Valo rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 4965d5c65159SKalle Valo } 4966d5c65159SKalle Valo rxs->flag |= RX_FLAG_ONLY_MONITOR; 4967d5c65159SKalle Valo 49682167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs); 4969d5c65159SKalle Valo mon_skb = skb_next; 49705e02bc73SMiles Hu } while (mon_skb); 4971d5c65159SKalle Valo rxs->flag = 0; 4972d5c65159SKalle Valo 4973d5c65159SKalle Valo return 0; 4974d5c65159SKalle Valo 4975d5c65159SKalle Valo mon_deliver_fail: 4976d5c65159SKalle Valo mon_skb = head_msdu; 4977d5c65159SKalle Valo while (mon_skb) { 4978d5c65159SKalle Valo skb_next = mon_skb->next; 4979d5c65159SKalle Valo dev_kfree_skb_any(mon_skb); 4980d5c65159SKalle Valo mon_skb = skb_next; 4981d5c65159SKalle Valo } 4982d5c65159SKalle Valo return -EINVAL; 4983d5c65159SKalle Valo } 4984d5c65159SKalle Valo 4985701e48a4SCarl Huang static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id, 4986701e48a4SCarl Huang u32 quota, struct napi_struct *napi) 4987d5c65159SKalle Valo { 4988d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4989d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4990734223d7SBaochen Qiang const struct ath11k_hw_hal_params *hal_params; 4991d5c65159SKalle Valo void *ring_entry; 4992d5c65159SKalle Valo void *mon_dst_srng; 4993d5c65159SKalle Valo u32 ppdu_id; 4994d5c65159SKalle Valo u32 rx_bufs_used; 4995701e48a4SCarl Huang u32 ring_id; 4996d5c65159SKalle Valo struct ath11k_pdev_mon_stats *rx_mon_stats; 4997d5c65159SKalle Valo u32 npackets = 0; 4998d5c65159SKalle Valo 4999701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 5000701e48a4SCarl Huang ring_id = dp->rxdma_mon_dst_ring.ring_id; 5001701e48a4SCarl Huang else 5002701e48a4SCarl Huang ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 5003701e48a4SCarl Huang 5004701e48a4SCarl Huang mon_dst_srng = &ar->ab->hal.srng_list[ring_id]; 5005d5c65159SKalle Valo 5006d5c65159SKalle Valo if (!mon_dst_srng) { 5007d5c65159SKalle Valo ath11k_warn(ar->ab, 5008d5c65159SKalle Valo "HAL Monitor Destination Ring Init Failed -- %pK", 5009d5c65159SKalle Valo mon_dst_srng); 5010d5c65159SKalle Valo return; 5011d5c65159SKalle Valo } 5012d5c65159SKalle Valo 5013d5c65159SKalle Valo spin_lock_bh(&pmon->mon_lock); 5014d5c65159SKalle Valo 5015d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5016d5c65159SKalle Valo 5017d5c65159SKalle Valo ppdu_id = pmon->mon_ppdu_info.ppdu_id; 5018d5c65159SKalle Valo rx_bufs_used = 0; 5019d5c65159SKalle Valo rx_mon_stats = &pmon->rx_mon_stats; 5020d5c65159SKalle Valo 5021d5c65159SKalle Valo while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5022d5c65159SKalle Valo struct sk_buff *head_msdu, *tail_msdu; 5023d5c65159SKalle Valo 5024d5c65159SKalle Valo head_msdu = NULL; 5025d5c65159SKalle Valo tail_msdu = NULL; 5026d5c65159SKalle Valo 5027701e48a4SCarl Huang rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry, 5028d5c65159SKalle Valo &head_msdu, 5029d5c65159SKalle Valo &tail_msdu, 5030d5c65159SKalle Valo &npackets, &ppdu_id); 5031d5c65159SKalle Valo 5032d5c65159SKalle Valo if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 5033d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5034d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 5035d5c65159SKalle Valo "dest_rx: new ppdu_id %x != status ppdu_id %x", 5036d5c65159SKalle Valo ppdu_id, pmon->mon_ppdu_info.ppdu_id); 5037d5c65159SKalle Valo break; 5038d5c65159SKalle Valo } 5039d5c65159SKalle Valo if (head_msdu && tail_msdu) { 5040d5c65159SKalle Valo ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 5041d5c65159SKalle Valo tail_msdu, napi); 5042d5c65159SKalle Valo rx_mon_stats->dest_mpdu_done++; 5043d5c65159SKalle Valo } 5044d5c65159SKalle Valo 5045d5c65159SKalle Valo ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5046d5c65159SKalle Valo mon_dst_srng); 5047d5c65159SKalle Valo } 5048d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5049d5c65159SKalle Valo 5050d5c65159SKalle Valo spin_unlock_bh(&pmon->mon_lock); 5051d5c65159SKalle Valo 5052d5c65159SKalle Valo if (rx_bufs_used) { 5053d5c65159SKalle Valo rx_mon_stats->dest_ppdu_done++; 5054734223d7SBaochen Qiang hal_params = ar->ab->hw_params.hal_params; 5055734223d7SBaochen Qiang 5056701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 5057d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5058d5c65159SKalle Valo &dp->rxdma_mon_buf_ring, 5059d5c65159SKalle Valo rx_bufs_used, 5060734223d7SBaochen Qiang hal_params->rx_buf_rbm); 5061701e48a4SCarl Huang else 5062701e48a4SCarl Huang ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5063701e48a4SCarl Huang &dp->rx_refill_buf_ring, 5064701e48a4SCarl Huang rx_bufs_used, 5065734223d7SBaochen Qiang hal_params->rx_buf_rbm); 5066d5c65159SKalle Valo } 5067d5c65159SKalle Valo } 5068d5c65159SKalle Valo 5069d5c65159SKalle Valo static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar, 5070701e48a4SCarl Huang int mac_id, u32 quota, 5071d5c65159SKalle Valo struct napi_struct *napi) 5072d5c65159SKalle Valo { 5073d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5074d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5075d5c65159SKalle Valo struct hal_rx_mon_ppdu_info *ppdu_info; 5076d5c65159SKalle Valo struct sk_buff *status_skb; 5077d5c65159SKalle Valo u32 tlv_status = HAL_TLV_STATUS_BUF_DONE; 5078d5c65159SKalle Valo struct ath11k_pdev_mon_stats *rx_mon_stats; 5079d5c65159SKalle Valo 5080d5c65159SKalle Valo ppdu_info = &pmon->mon_ppdu_info; 5081d5c65159SKalle Valo rx_mon_stats = &pmon->rx_mon_stats; 5082d5c65159SKalle Valo 5083d5c65159SKalle Valo if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START) 5084d5c65159SKalle Valo return; 5085d5c65159SKalle Valo 5086d5c65159SKalle Valo while (!skb_queue_empty(&pmon->rx_status_q)) { 5087d5c65159SKalle Valo status_skb = skb_dequeue(&pmon->rx_status_q); 5088d5c65159SKalle Valo 5089d5c65159SKalle Valo tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info, 5090d5c65159SKalle Valo status_skb); 5091d5c65159SKalle Valo if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) { 5092d5c65159SKalle Valo rx_mon_stats->status_ppdu_done++; 5093d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 5094701e48a4SCarl Huang ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi); 5095d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5096d5c65159SKalle Valo } 5097d5c65159SKalle Valo dev_kfree_skb_any(status_skb); 5098d5c65159SKalle Valo } 5099d5c65159SKalle Valo } 5100d5c65159SKalle Valo 5101d5c65159SKalle Valo static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id, 5102d5c65159SKalle Valo struct napi_struct *napi, int budget) 5103d5c65159SKalle Valo { 51044152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5105d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5106d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5107d5c65159SKalle Valo int num_buffs_reaped = 0; 5108d5c65159SKalle Valo 5109701e48a4SCarl Huang num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget, 5110d5c65159SKalle Valo &pmon->rx_status_q); 5111d5c65159SKalle Valo if (num_buffs_reaped) 5112701e48a4SCarl Huang ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi); 5113d5c65159SKalle Valo 5114d5c65159SKalle Valo return num_buffs_reaped; 5115d5c65159SKalle Valo } 5116d5c65159SKalle Valo 5117d5c65159SKalle Valo int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 5118d5c65159SKalle Valo struct napi_struct *napi, int budget) 5119d5c65159SKalle Valo { 51204152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5121d5c65159SKalle Valo int ret = 0; 5122d5c65159SKalle Valo 5123689a5e6fSSeevalamuthu Mariappan if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags)) 5124d5c65159SKalle Valo ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget); 5125d5c65159SKalle Valo else 5126d5c65159SKalle Valo ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 5127d5c65159SKalle Valo return ret; 5128d5c65159SKalle Valo } 5129d5c65159SKalle Valo 5130d5c65159SKalle Valo static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 5131d5c65159SKalle Valo { 5132d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5133d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5134d5c65159SKalle Valo 5135d5c65159SKalle Valo skb_queue_head_init(&pmon->rx_status_q); 5136d5c65159SKalle Valo 5137d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5138d5c65159SKalle Valo 5139d5c65159SKalle Valo memset(&pmon->rx_mon_stats, 0, 5140d5c65159SKalle Valo sizeof(pmon->rx_mon_stats)); 5141d5c65159SKalle Valo return 0; 5142d5c65159SKalle Valo } 5143d5c65159SKalle Valo 5144d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 5145d5c65159SKalle Valo { 5146d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5147d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 5148d5c65159SKalle Valo struct hal_srng *mon_desc_srng = NULL; 5149d5c65159SKalle Valo struct dp_srng *dp_srng; 5150d5c65159SKalle Valo int ret = 0; 5151d5c65159SKalle Valo u32 n_link_desc = 0; 5152d5c65159SKalle Valo 5153d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 5154d5c65159SKalle Valo if (ret) { 5155d5c65159SKalle Valo ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 5156d5c65159SKalle Valo return ret; 5157d5c65159SKalle Valo } 5158d5c65159SKalle Valo 51597f6fc1ebSCarl Huang /* if rxdma1_enable is false, no need to setup 51607f6fc1ebSCarl Huang * rxdma_mon_desc_ring. 51617f6fc1ebSCarl Huang */ 51627f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 51637f6fc1ebSCarl Huang return 0; 51647f6fc1ebSCarl Huang 5165d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 5166d5c65159SKalle Valo n_link_desc = dp_srng->size / 5167f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC); 5168d5c65159SKalle Valo mon_desc_srng = 5169d5c65159SKalle Valo &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 5170d5c65159SKalle Valo 5171d5c65159SKalle Valo ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 5172d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 5173d5c65159SKalle Valo n_link_desc); 5174d5c65159SKalle Valo if (ret) { 5175d5c65159SKalle Valo ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 5176d5c65159SKalle Valo return ret; 5177d5c65159SKalle Valo } 5178d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = 0; 5179d5c65159SKalle Valo pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 5180d5c65159SKalle Valo spin_lock_init(&pmon->mon_lock); 51817f6fc1ebSCarl Huang 5182d5c65159SKalle Valo return 0; 5183d5c65159SKalle Valo } 5184d5c65159SKalle Valo 5185d5c65159SKalle Valo static int ath11k_dp_mon_link_free(struct ath11k *ar) 5186d5c65159SKalle Valo { 5187d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5188d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 5189d5c65159SKalle Valo 5190d5c65159SKalle Valo ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 5191d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 5192d5c65159SKalle Valo &dp->rxdma_mon_desc_ring); 5193d5c65159SKalle Valo return 0; 5194d5c65159SKalle Valo } 5195d5c65159SKalle Valo 5196d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 5197d5c65159SKalle Valo { 5198d5c65159SKalle Valo ath11k_dp_mon_link_free(ar); 5199d5c65159SKalle Valo return 0; 5200d5c65159SKalle Valo } 5201840c36faSCarl Huang 5202840c36faSCarl Huang int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab) 5203840c36faSCarl Huang { 5204840c36faSCarl Huang /* start reap timer */ 5205840c36faSCarl Huang mod_timer(&ab->mon_reap_timer, 5206840c36faSCarl Huang jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 5207840c36faSCarl Huang 5208840c36faSCarl Huang return 0; 5209840c36faSCarl Huang } 5210840c36faSCarl Huang 5211840c36faSCarl Huang int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer) 5212840c36faSCarl Huang { 5213840c36faSCarl Huang int ret; 5214840c36faSCarl Huang 5215840c36faSCarl Huang if (stop_timer) 5216840c36faSCarl Huang del_timer_sync(&ab->mon_reap_timer); 5217840c36faSCarl Huang 5218840c36faSCarl Huang /* reap all the monitor related rings */ 5219840c36faSCarl Huang ret = ath11k_dp_purge_mon_ring(ab); 5220840c36faSCarl Huang if (ret) { 5221840c36faSCarl Huang ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 5222840c36faSCarl Huang return ret; 5223840c36faSCarl Huang } 5224840c36faSCarl Huang 5225840c36faSCarl Huang return 0; 5226840c36faSCarl Huang } 5227