1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #include <linux/ieee80211.h> 7acc79d98SSriram R #include <linux/kernel.h> 8acc79d98SSriram R #include <linux/skbuff.h> 9243874c6SManikanta Pubbisetty #include <crypto/hash.h> 10d5c65159SKalle Valo #include "core.h" 11d5c65159SKalle Valo #include "debug.h" 12568f0603SKalle Valo #include "debugfs_htt_stats.h" 13568f0603SKalle Valo #include "debugfs_sta.h" 14d5c65159SKalle Valo #include "hal_desc.h" 15d5c65159SKalle Valo #include "hw.h" 16d5c65159SKalle Valo #include "dp_rx.h" 17d5c65159SKalle Valo #include "hal_rx.h" 18d5c65159SKalle Valo #include "dp_tx.h" 19d5c65159SKalle Valo #include "peer.h" 20d5c65159SKalle Valo 21243874c6SManikanta Pubbisetty #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22243874c6SManikanta Pubbisetty 23d5c65159SKalle Valo static u8 *ath11k_dp_rx_h_80211_hdr(struct hal_rx_desc *desc) 24d5c65159SKalle Valo { 25d5c65159SKalle Valo return desc->hdr_status; 26d5c65159SKalle Valo } 27d5c65159SKalle Valo 28d5c65159SKalle Valo static enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct hal_rx_desc *desc) 29d5c65159SKalle Valo { 30d5c65159SKalle Valo if (!(__le32_to_cpu(desc->mpdu_start.info1) & 31d5c65159SKalle Valo RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID)) 32d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN; 33d5c65159SKalle Valo 34d5c65159SKalle Valo return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 35d5c65159SKalle Valo __le32_to_cpu(desc->mpdu_start.info2)); 36d5c65159SKalle Valo } 37d5c65159SKalle Valo 38243874c6SManikanta Pubbisetty static u8 ath11k_dp_rx_h_msdu_start_decap_type(struct hal_rx_desc *desc) 39d5c65159SKalle Valo { 40243874c6SManikanta Pubbisetty return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 41243874c6SManikanta Pubbisetty __le32_to_cpu(desc->msdu_start.info2)); 42243874c6SManikanta Pubbisetty } 43243874c6SManikanta Pubbisetty 44acc79d98SSriram R static u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct hal_rx_desc *desc) 45acc79d98SSriram R { 46acc79d98SSriram R return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 47acc79d98SSriram R __le32_to_cpu(desc->msdu_start.info2)); 48acc79d98SSriram R } 49acc79d98SSriram R 50243874c6SManikanta Pubbisetty static bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct hal_rx_desc *desc) 51243874c6SManikanta Pubbisetty { 52243874c6SManikanta Pubbisetty return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 53243874c6SManikanta Pubbisetty __le32_to_cpu(desc->mpdu_start.info1)); 54243874c6SManikanta Pubbisetty } 55243874c6SManikanta Pubbisetty 56243874c6SManikanta Pubbisetty static bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct hal_rx_desc *desc) 57243874c6SManikanta Pubbisetty { 58243874c6SManikanta Pubbisetty return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 59243874c6SManikanta Pubbisetty __le32_to_cpu(desc->mpdu_start.info1)); 60243874c6SManikanta Pubbisetty } 61243874c6SManikanta Pubbisetty 62243874c6SManikanta Pubbisetty static bool ath11k_dp_rx_h_mpdu_start_more_frags(struct sk_buff *skb) 63243874c6SManikanta Pubbisetty { 64243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 65243874c6SManikanta Pubbisetty 66243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 67243874c6SManikanta Pubbisetty return ieee80211_has_morefrags(hdr->frame_control); 68243874c6SManikanta Pubbisetty } 69243874c6SManikanta Pubbisetty 70243874c6SManikanta Pubbisetty static u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct sk_buff *skb) 71243874c6SManikanta Pubbisetty { 72243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 73243874c6SManikanta Pubbisetty 74243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 75243874c6SManikanta Pubbisetty return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 76243874c6SManikanta Pubbisetty } 77243874c6SManikanta Pubbisetty 78243874c6SManikanta Pubbisetty static u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct hal_rx_desc *desc) 79243874c6SManikanta Pubbisetty { 80243874c6SManikanta Pubbisetty return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 81243874c6SManikanta Pubbisetty __le32_to_cpu(desc->mpdu_start.info1)); 82d5c65159SKalle Valo } 83d5c65159SKalle Valo 84d5c65159SKalle Valo static bool ath11k_dp_rx_h_attn_msdu_done(struct hal_rx_desc *desc) 85d5c65159SKalle Valo { 86d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 87d5c65159SKalle Valo __le32_to_cpu(desc->attention.info2)); 88d5c65159SKalle Valo } 89d5c65159SKalle Valo 90d5c65159SKalle Valo static bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct hal_rx_desc *desc) 91d5c65159SKalle Valo { 92d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 93d5c65159SKalle Valo __le32_to_cpu(desc->attention.info1)); 94d5c65159SKalle Valo } 95d5c65159SKalle Valo 96d5c65159SKalle Valo static bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct hal_rx_desc *desc) 97d5c65159SKalle Valo { 98d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 99d5c65159SKalle Valo __le32_to_cpu(desc->attention.info1)); 100d5c65159SKalle Valo } 101d5c65159SKalle Valo 102d5c65159SKalle Valo static bool ath11k_dp_rx_h_attn_is_decrypted(struct hal_rx_desc *desc) 103d5c65159SKalle Valo { 104d5c65159SKalle Valo return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 105d5c65159SKalle Valo __le32_to_cpu(desc->attention.info2)) == 106d5c65159SKalle Valo RX_DESC_DECRYPT_STATUS_CODE_OK); 107d5c65159SKalle Valo } 108d5c65159SKalle Valo 109d5c65159SKalle Valo static u32 ath11k_dp_rx_h_attn_mpdu_err(struct hal_rx_desc *desc) 110d5c65159SKalle Valo { 111d5c65159SKalle Valo u32 info = __le32_to_cpu(desc->attention.info1); 112d5c65159SKalle Valo u32 errmap = 0; 113d5c65159SKalle Valo 114d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_FCS_ERR) 115d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_FCS; 116d5c65159SKalle Valo 117d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 118d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_DECRYPT; 119d5c65159SKalle Valo 120d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 121d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 122d5c65159SKalle Valo 123d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 124d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 125d5c65159SKalle Valo 126d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 127d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_OVERFLOW; 128d5c65159SKalle Valo 129d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 130d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 131d5c65159SKalle Valo 132d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 133d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 134d5c65159SKalle Valo 135d5c65159SKalle Valo return errmap; 136d5c65159SKalle Valo } 137d5c65159SKalle Valo 138d5c65159SKalle Valo static u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct hal_rx_desc *desc) 139d5c65159SKalle Valo { 140d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 141d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info1)); 142d5c65159SKalle Valo } 143d5c65159SKalle Valo 144d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_start_sgi(struct hal_rx_desc *desc) 145d5c65159SKalle Valo { 146d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO3_SGI, 147d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info3)); 148d5c65159SKalle Valo } 149d5c65159SKalle Valo 150d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct hal_rx_desc *desc) 151d5c65159SKalle Valo { 152d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 153d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info3)); 154d5c65159SKalle Valo } 155d5c65159SKalle Valo 156d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct hal_rx_desc *desc) 157d5c65159SKalle Valo { 158d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 159d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info3)); 160d5c65159SKalle Valo } 161d5c65159SKalle Valo 162d5c65159SKalle Valo static u32 ath11k_dp_rx_h_msdu_start_freq(struct hal_rx_desc *desc) 163d5c65159SKalle Valo { 164d5c65159SKalle Valo return __le32_to_cpu(desc->msdu_start.phy_meta_data); 165d5c65159SKalle Valo } 166d5c65159SKalle Valo 167d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct hal_rx_desc *desc) 168d5c65159SKalle Valo { 169d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 170d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info3)); 171d5c65159SKalle Valo } 172d5c65159SKalle Valo 173d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_start_nss(struct hal_rx_desc *desc) 174d5c65159SKalle Valo { 175d5c65159SKalle Valo u8 mimo_ss_bitmap = FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 176d5c65159SKalle Valo __le32_to_cpu(desc->msdu_start.info3)); 177d5c65159SKalle Valo 178d5c65159SKalle Valo return hweight8(mimo_ss_bitmap); 179d5c65159SKalle Valo } 180d5c65159SKalle Valo 181243874c6SManikanta Pubbisetty static u8 ath11k_dp_rx_h_mpdu_start_tid(struct hal_rx_desc *desc) 182243874c6SManikanta Pubbisetty { 183243874c6SManikanta Pubbisetty return FIELD_GET(RX_MPDU_START_INFO2_TID, 184243874c6SManikanta Pubbisetty __le32_to_cpu(desc->mpdu_start.info2)); 185243874c6SManikanta Pubbisetty } 186243874c6SManikanta Pubbisetty 187243874c6SManikanta Pubbisetty static u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct hal_rx_desc *desc) 188243874c6SManikanta Pubbisetty { 189243874c6SManikanta Pubbisetty return __le16_to_cpu(desc->mpdu_start.sw_peer_id); 190243874c6SManikanta Pubbisetty } 191243874c6SManikanta Pubbisetty 192d5c65159SKalle Valo static u8 ath11k_dp_rx_h_msdu_end_l3pad(struct hal_rx_desc *desc) 193d5c65159SKalle Valo { 194d5c65159SKalle Valo return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 195d5c65159SKalle Valo __le32_to_cpu(desc->msdu_end.info2)); 196d5c65159SKalle Valo } 197d5c65159SKalle Valo 198d5c65159SKalle Valo static bool ath11k_dp_rx_h_msdu_end_first_msdu(struct hal_rx_desc *desc) 199d5c65159SKalle Valo { 200d5c65159SKalle Valo return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 201d5c65159SKalle Valo __le32_to_cpu(desc->msdu_end.info2)); 202d5c65159SKalle Valo } 203d5c65159SKalle Valo 204d5c65159SKalle Valo static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct hal_rx_desc *desc) 205d5c65159SKalle Valo { 206d5c65159SKalle Valo return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 207d5c65159SKalle Valo __le32_to_cpu(desc->msdu_end.info2)); 208d5c65159SKalle Valo } 209d5c65159SKalle Valo 210d5c65159SKalle Valo static void ath11k_dp_rx_desc_end_tlv_copy(struct hal_rx_desc *fdesc, 211d5c65159SKalle Valo struct hal_rx_desc *ldesc) 212d5c65159SKalle Valo { 213d5c65159SKalle Valo memcpy((u8 *)&fdesc->msdu_end, (u8 *)&ldesc->msdu_end, 214d5c65159SKalle Valo sizeof(struct rx_msdu_end)); 215d5c65159SKalle Valo memcpy((u8 *)&fdesc->attention, (u8 *)&ldesc->attention, 216d5c65159SKalle Valo sizeof(struct rx_attention)); 217d5c65159SKalle Valo memcpy((u8 *)&fdesc->mpdu_end, (u8 *)&ldesc->mpdu_end, 218d5c65159SKalle Valo sizeof(struct rx_mpdu_end)); 219d5c65159SKalle Valo } 220d5c65159SKalle Valo 221d5c65159SKalle Valo static u32 ath11k_dp_rxdesc_get_mpdulen_err(struct hal_rx_desc *rx_desc) 222d5c65159SKalle Valo { 223d5c65159SKalle Valo struct rx_attention *rx_attn; 224d5c65159SKalle Valo 225d5c65159SKalle Valo rx_attn = &rx_desc->attention; 226d5c65159SKalle Valo 227d5c65159SKalle Valo return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 228d5c65159SKalle Valo __le32_to_cpu(rx_attn->info1)); 229d5c65159SKalle Valo } 230d5c65159SKalle Valo 231d5c65159SKalle Valo static u32 ath11k_dp_rxdesc_get_decap_format(struct hal_rx_desc *rx_desc) 232d5c65159SKalle Valo { 233d5c65159SKalle Valo struct rx_msdu_start *rx_msdu_start; 234d5c65159SKalle Valo 235d5c65159SKalle Valo rx_msdu_start = &rx_desc->msdu_start; 236d5c65159SKalle Valo 237d5c65159SKalle Valo return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 238d5c65159SKalle Valo __le32_to_cpu(rx_msdu_start->info2)); 239d5c65159SKalle Valo } 240d5c65159SKalle Valo 241d5c65159SKalle Valo static u8 *ath11k_dp_rxdesc_get_80211hdr(struct hal_rx_desc *rx_desc) 242d5c65159SKalle Valo { 243d5c65159SKalle Valo u8 *rx_pkt_hdr; 244d5c65159SKalle Valo 245d5c65159SKalle Valo rx_pkt_hdr = &rx_desc->msdu_payload[0]; 246d5c65159SKalle Valo 247d5c65159SKalle Valo return rx_pkt_hdr; 248d5c65159SKalle Valo } 249d5c65159SKalle Valo 250d5c65159SKalle Valo static bool ath11k_dp_rxdesc_mpdu_valid(struct hal_rx_desc *rx_desc) 251d5c65159SKalle Valo { 252d5c65159SKalle Valo u32 tlv_tag; 253d5c65159SKalle Valo 254d5c65159SKalle Valo tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, 255d5c65159SKalle Valo __le32_to_cpu(rx_desc->mpdu_start_tag)); 256d5c65159SKalle Valo 2578af40902SJason Yan return tlv_tag == HAL_RX_MPDU_START; 258d5c65159SKalle Valo } 259d5c65159SKalle Valo 260d5c65159SKalle Valo static u32 ath11k_dp_rxdesc_get_ppduid(struct hal_rx_desc *rx_desc) 261d5c65159SKalle Valo { 262d5c65159SKalle Valo return __le16_to_cpu(rx_desc->mpdu_start.phy_ppdu_id); 263d5c65159SKalle Valo } 264d5c65159SKalle Valo 265701e48a4SCarl Huang static void ath11k_dp_service_mon_ring(struct timer_list *t) 266701e48a4SCarl Huang { 267701e48a4SCarl Huang struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer); 268701e48a4SCarl Huang int i; 269701e48a4SCarl Huang 270701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 271701e48a4SCarl Huang ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET); 272701e48a4SCarl Huang 273701e48a4SCarl Huang mod_timer(&ab->mon_reap_timer, jiffies + 274701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 275701e48a4SCarl Huang } 276701e48a4SCarl Huang 277d5c65159SKalle Valo /* Returns number of Rx buffers replenished */ 278d5c65159SKalle Valo int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 279d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 280d5c65159SKalle Valo int req_entries, 28187e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 282d5c65159SKalle Valo { 283d5c65159SKalle Valo struct hal_srng *srng; 284d5c65159SKalle Valo u32 *desc; 285d5c65159SKalle Valo struct sk_buff *skb; 286d5c65159SKalle Valo int num_free; 287d5c65159SKalle Valo int num_remain; 288d5c65159SKalle Valo int buf_id; 289d5c65159SKalle Valo u32 cookie; 290d5c65159SKalle Valo dma_addr_t paddr; 291d5c65159SKalle Valo 292d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 293d5c65159SKalle Valo 294d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 295d5c65159SKalle Valo 296d5c65159SKalle Valo spin_lock_bh(&srng->lock); 297d5c65159SKalle Valo 298d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 299d5c65159SKalle Valo 300d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 301d5c65159SKalle Valo if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 302d5c65159SKalle Valo req_entries = num_free; 303d5c65159SKalle Valo 304d5c65159SKalle Valo req_entries = min(num_free, req_entries); 305d5c65159SKalle Valo num_remain = req_entries; 306d5c65159SKalle Valo 307d5c65159SKalle Valo while (num_remain > 0) { 308d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 309d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 310d5c65159SKalle Valo if (!skb) 311d5c65159SKalle Valo break; 312d5c65159SKalle Valo 313d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 314d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 315d5c65159SKalle Valo skb_pull(skb, 316d5c65159SKalle Valo PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 317d5c65159SKalle Valo skb->data); 318d5c65159SKalle Valo } 319d5c65159SKalle Valo 320d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 321d5c65159SKalle Valo skb->len + skb_tailroom(skb), 322d5c65159SKalle Valo DMA_FROM_DEVICE); 323d5c65159SKalle Valo if (dma_mapping_error(ab->dev, paddr)) 324d5c65159SKalle Valo goto fail_free_skb; 325d5c65159SKalle Valo 326d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 327d5c65159SKalle Valo buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 32887e8497aSGovind Singh rx_ring->bufs_max * 3, GFP_ATOMIC); 329d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 330d5c65159SKalle Valo if (buf_id < 0) 331d5c65159SKalle Valo goto fail_dma_unmap; 332d5c65159SKalle Valo 333d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 334d5c65159SKalle Valo if (!desc) 335d5c65159SKalle Valo goto fail_idr_remove; 336d5c65159SKalle Valo 337d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 338d5c65159SKalle Valo 339d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 340d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 341d5c65159SKalle Valo 342d5c65159SKalle Valo num_remain--; 343d5c65159SKalle Valo 344d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 345d5c65159SKalle Valo } 346d5c65159SKalle Valo 347d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 348d5c65159SKalle Valo 349d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 350d5c65159SKalle Valo 351d5c65159SKalle Valo return req_entries - num_remain; 352d5c65159SKalle Valo 353d5c65159SKalle Valo fail_idr_remove: 354d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 355d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 356d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 357d5c65159SKalle Valo fail_dma_unmap: 358d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 359d5c65159SKalle Valo DMA_FROM_DEVICE); 360d5c65159SKalle Valo fail_free_skb: 361d5c65159SKalle Valo dev_kfree_skb_any(skb); 362d5c65159SKalle Valo 363d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 364d5c65159SKalle Valo 365d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 366d5c65159SKalle Valo 367d5c65159SKalle Valo return req_entries - num_remain; 368d5c65159SKalle Valo } 369d5c65159SKalle Valo 370d5c65159SKalle Valo static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 371d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring) 372d5c65159SKalle Valo { 373d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 374d5c65159SKalle Valo struct sk_buff *skb; 375d5c65159SKalle Valo int buf_id; 376d5c65159SKalle Valo 377d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 378d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 379d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 380d5c65159SKalle Valo /* TODO: Understand where internal driver does this dma_unmap of 381d5c65159SKalle Valo * of rxdma_buffer. 382d5c65159SKalle Valo */ 383d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 384d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 385d5c65159SKalle Valo dev_kfree_skb_any(skb); 386d5c65159SKalle Valo } 387d5c65159SKalle Valo 388d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 389d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 390d5c65159SKalle Valo 3917f6fc1ebSCarl Huang /* if rxdma1_enable is false, mon_status_refill_ring 3927f6fc1ebSCarl Huang * isn't setup, so don't clean. 3937f6fc1ebSCarl Huang */ 3947f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 3957f6fc1ebSCarl Huang return 0; 3967f6fc1ebSCarl Huang 3974152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[0]; 398d5c65159SKalle Valo 399d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 400d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 401d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 402d5c65159SKalle Valo /* XXX: Understand where internal driver does this dma_unmap of 403d5c65159SKalle Valo * of rxdma_buffer. 404d5c65159SKalle Valo */ 405d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 406d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); 407d5c65159SKalle Valo dev_kfree_skb_any(skb); 408d5c65159SKalle Valo } 409d5c65159SKalle Valo 410d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 411d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4127f6fc1ebSCarl Huang 413d5c65159SKalle Valo return 0; 414d5c65159SKalle Valo } 415d5c65159SKalle Valo 416d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 417d5c65159SKalle Valo { 418d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4194152e420SCarl Huang struct ath11k_base *ab = ar->ab; 420d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 4214152e420SCarl Huang int i; 422d5c65159SKalle Valo 423d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 424d5c65159SKalle Valo 425d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 426d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 427d5c65159SKalle Valo 4284152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4294152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 430d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 4314152e420SCarl Huang } 4324152e420SCarl Huang 433d5c65159SKalle Valo return 0; 434d5c65159SKalle Valo } 435d5c65159SKalle Valo 436d5c65159SKalle Valo static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 437d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 438d5c65159SKalle Valo u32 ringtype) 439d5c65159SKalle Valo { 440d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 441d5c65159SKalle Valo int num_entries; 442d5c65159SKalle Valo 443d5c65159SKalle Valo num_entries = rx_ring->refill_buf_ring.size / 444f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, ringtype); 445d5c65159SKalle Valo 446d5c65159SKalle Valo rx_ring->bufs_max = num_entries; 447d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 44887e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 449d5c65159SKalle Valo return 0; 450d5c65159SKalle Valo } 451d5c65159SKalle Valo 452d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 453d5c65159SKalle Valo { 454d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4554152e420SCarl Huang struct ath11k_base *ab = ar->ab; 456d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 4574152e420SCarl Huang int i; 458d5c65159SKalle Valo 459d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 460d5c65159SKalle Valo 4617f6fc1ebSCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 462d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 463d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 4647f6fc1ebSCarl Huang } 465d5c65159SKalle Valo 4664152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4674152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 468d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 4694152e420SCarl Huang } 470d5c65159SKalle Valo 471d5c65159SKalle Valo return 0; 472d5c65159SKalle Valo } 473d5c65159SKalle Valo 474d5c65159SKalle Valo static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 475d5c65159SKalle Valo { 476d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4774152e420SCarl Huang struct ath11k_base *ab = ar->ab; 4784152e420SCarl Huang int i; 479d5c65159SKalle Valo 4804152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 4814152e420SCarl Huang 4824152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4834152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) 4844152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 4854152e420SCarl Huang 4864152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 4874152e420SCarl Huang ath11k_dp_srng_cleanup(ab, 4884152e420SCarl Huang &dp->rx_mon_status_refill_ring[i].refill_buf_ring); 4894152e420SCarl Huang } 4904152e420SCarl Huang 4914152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 492d5c65159SKalle Valo } 493d5c65159SKalle Valo 4949c57d7e3SVasanthakumar Thiagarajan void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 4959c57d7e3SVasanthakumar Thiagarajan { 496acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 4979c57d7e3SVasanthakumar Thiagarajan int i; 4989c57d7e3SVasanthakumar Thiagarajan 499acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) 500acc79d98SSriram R ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 5019c57d7e3SVasanthakumar Thiagarajan } 5029c57d7e3SVasanthakumar Thiagarajan 5039c57d7e3SVasanthakumar Thiagarajan int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 5049c57d7e3SVasanthakumar Thiagarajan { 505acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 5069c57d7e3SVasanthakumar Thiagarajan int ret; 5079c57d7e3SVasanthakumar Thiagarajan int i; 5089c57d7e3SVasanthakumar Thiagarajan 509acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 510acc79d98SSriram R ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 511acc79d98SSriram R HAL_REO_DST, i, 0, 5129c57d7e3SVasanthakumar Thiagarajan DP_REO_DST_RING_SIZE); 5139c57d7e3SVasanthakumar Thiagarajan if (ret) { 514acc79d98SSriram R ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 5159c57d7e3SVasanthakumar Thiagarajan goto err_reo_cleanup; 5169c57d7e3SVasanthakumar Thiagarajan } 5179c57d7e3SVasanthakumar Thiagarajan } 5189c57d7e3SVasanthakumar Thiagarajan 5199c57d7e3SVasanthakumar Thiagarajan return 0; 5209c57d7e3SVasanthakumar Thiagarajan 5219c57d7e3SVasanthakumar Thiagarajan err_reo_cleanup: 5229c57d7e3SVasanthakumar Thiagarajan ath11k_dp_pdev_reo_cleanup(ab); 5239c57d7e3SVasanthakumar Thiagarajan 5249c57d7e3SVasanthakumar Thiagarajan return ret; 5259c57d7e3SVasanthakumar Thiagarajan } 5269c57d7e3SVasanthakumar Thiagarajan 527d5c65159SKalle Valo static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 528d5c65159SKalle Valo { 529d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5304152e420SCarl Huang struct ath11k_base *ab = ar->ab; 531d5c65159SKalle Valo struct dp_srng *srng = NULL; 5324152e420SCarl Huang int i; 533d5c65159SKalle Valo int ret; 534d5c65159SKalle Valo 535d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 536d5c65159SKalle Valo &dp->rx_refill_buf_ring.refill_buf_ring, 537d5c65159SKalle Valo HAL_RXDMA_BUF, 0, 538d5c65159SKalle Valo dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 539d5c65159SKalle Valo if (ret) { 540d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 541d5c65159SKalle Valo return ret; 542d5c65159SKalle Valo } 543d5c65159SKalle Valo 5444152e420SCarl Huang if (ar->ab->hw_params.rx_mac_buf_ring) { 5454152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5464152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, 5474152e420SCarl Huang &dp->rx_mac_buf_ring[i], 5484152e420SCarl Huang HAL_RXDMA_BUF, 1, 5494152e420SCarl Huang dp->mac_id + i, 1024); 550d5c65159SKalle Valo if (ret) { 5514152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n", 5524152e420SCarl Huang i); 553d5c65159SKalle Valo return ret; 554d5c65159SKalle Valo } 5554152e420SCarl Huang } 5564152e420SCarl Huang } 557d5c65159SKalle Valo 5584152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5594152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i], 5604152e420SCarl Huang HAL_RXDMA_DST, 0, dp->mac_id + i, 5614152e420SCarl Huang DP_RXDMA_ERR_DST_RING_SIZE); 5624152e420SCarl Huang if (ret) { 5634152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i); 5644152e420SCarl Huang return ret; 5654152e420SCarl Huang } 5664152e420SCarl Huang } 5674152e420SCarl Huang 5684152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5694152e420SCarl Huang srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 570d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 571d5c65159SKalle Valo srng, 5724152e420SCarl Huang HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i, 573d5c65159SKalle Valo DP_RXDMA_MON_STATUS_RING_SIZE); 574d5c65159SKalle Valo if (ret) { 575d5c65159SKalle Valo ath11k_warn(ar->ab, 5764152e420SCarl Huang "failed to setup rx_mon_status_refill_ring %d\n", i); 577d5c65159SKalle Valo return ret; 578d5c65159SKalle Valo } 5794152e420SCarl Huang } 5807f6fc1ebSCarl Huang 5817f6fc1ebSCarl Huang /* if rxdma1_enable is false, then it doesn't need 5827f6fc1ebSCarl Huang * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring 5837f6fc1ebSCarl Huang * and rxdma_mon_desc_ring. 584701e48a4SCarl Huang * init reap timer for QCA6390. 5857f6fc1ebSCarl Huang */ 586701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) { 587701e48a4SCarl Huang //init mon status buffer reap timer 588701e48a4SCarl Huang timer_setup(&ar->ab->mon_reap_timer, 589701e48a4SCarl Huang ath11k_dp_service_mon_ring, 0); 5907f6fc1ebSCarl Huang return 0; 591701e48a4SCarl Huang } 5927f6fc1ebSCarl Huang 593d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 594d5c65159SKalle Valo &dp->rxdma_mon_buf_ring.refill_buf_ring, 595d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 596d5c65159SKalle Valo DP_RXDMA_MONITOR_BUF_RING_SIZE); 597d5c65159SKalle Valo if (ret) { 598d5c65159SKalle Valo ath11k_warn(ar->ab, 599d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 600d5c65159SKalle Valo return ret; 601d5c65159SKalle Valo } 602d5c65159SKalle Valo 603d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 604d5c65159SKalle Valo HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 605d5c65159SKalle Valo DP_RXDMA_MONITOR_DST_RING_SIZE); 606d5c65159SKalle Valo if (ret) { 607d5c65159SKalle Valo ath11k_warn(ar->ab, 608d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DST\n"); 609d5c65159SKalle Valo return ret; 610d5c65159SKalle Valo } 611d5c65159SKalle Valo 612d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 613d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 614d5c65159SKalle Valo DP_RXDMA_MONITOR_DESC_RING_SIZE); 615d5c65159SKalle Valo if (ret) { 616d5c65159SKalle Valo ath11k_warn(ar->ab, 617d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 618d5c65159SKalle Valo return ret; 619d5c65159SKalle Valo } 620d5c65159SKalle Valo 621d5c65159SKalle Valo return 0; 622d5c65159SKalle Valo } 623d5c65159SKalle Valo 624d5c65159SKalle Valo void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 625d5c65159SKalle Valo { 626d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 627d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 628d5c65159SKalle Valo struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 629d5c65159SKalle Valo 630d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 631d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 632d5c65159SKalle Valo list_del(&cmd->list); 633d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd->data.paddr, 634d5c65159SKalle Valo cmd->data.size, DMA_BIDIRECTIONAL); 635d5c65159SKalle Valo kfree(cmd->data.vaddr); 636d5c65159SKalle Valo kfree(cmd); 637d5c65159SKalle Valo } 638d5c65159SKalle Valo 639d5c65159SKalle Valo list_for_each_entry_safe(cmd_cache, tmp_cache, 640d5c65159SKalle Valo &dp->reo_cmd_cache_flush_list, list) { 641d5c65159SKalle Valo list_del(&cmd_cache->list); 6425cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 643d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd_cache->data.paddr, 644d5c65159SKalle Valo cmd_cache->data.size, DMA_BIDIRECTIONAL); 645d5c65159SKalle Valo kfree(cmd_cache->data.vaddr); 646d5c65159SKalle Valo kfree(cmd_cache); 647d5c65159SKalle Valo } 648d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 649d5c65159SKalle Valo } 650d5c65159SKalle Valo 651d5c65159SKalle Valo static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 652d5c65159SKalle Valo enum hal_reo_cmd_status status) 653d5c65159SKalle Valo { 654d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 655d5c65159SKalle Valo 656d5c65159SKalle Valo if (status != HAL_REO_CMD_SUCCESS) 657d5c65159SKalle Valo ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 658d5c65159SKalle Valo rx_tid->tid, status); 659d5c65159SKalle Valo 660d5c65159SKalle Valo dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 661d5c65159SKalle Valo DMA_BIDIRECTIONAL); 662d5c65159SKalle Valo kfree(rx_tid->vaddr); 663d5c65159SKalle Valo } 664d5c65159SKalle Valo 665d5c65159SKalle Valo static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 666d5c65159SKalle Valo struct dp_rx_tid *rx_tid) 667d5c65159SKalle Valo { 668d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 669d5c65159SKalle Valo unsigned long tot_desc_sz, desc_sz; 670d5c65159SKalle Valo int ret; 671d5c65159SKalle Valo 672d5c65159SKalle Valo tot_desc_sz = rx_tid->size; 673d5c65159SKalle Valo desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 674d5c65159SKalle Valo 675d5c65159SKalle Valo while (tot_desc_sz > desc_sz) { 676d5c65159SKalle Valo tot_desc_sz -= desc_sz; 677d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 678d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 679d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 680d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, &cmd, 681d5c65159SKalle Valo NULL); 682d5c65159SKalle Valo if (ret) 683d5c65159SKalle Valo ath11k_warn(ab, 684d5c65159SKalle Valo "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 685d5c65159SKalle Valo rx_tid->tid, ret); 686d5c65159SKalle Valo } 687d5c65159SKalle Valo 688d5c65159SKalle Valo memset(&cmd, 0, sizeof(cmd)); 689d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 690d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 691d5c65159SKalle Valo cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 692d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 693d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, 694d5c65159SKalle Valo &cmd, ath11k_dp_reo_cmd_free); 695d5c65159SKalle Valo if (ret) { 696d5c65159SKalle Valo ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 697d5c65159SKalle Valo rx_tid->tid, ret); 698d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 699d5c65159SKalle Valo DMA_BIDIRECTIONAL); 700d5c65159SKalle Valo kfree(rx_tid->vaddr); 701d5c65159SKalle Valo } 702d5c65159SKalle Valo } 703d5c65159SKalle Valo 704d5c65159SKalle Valo static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 705d5c65159SKalle Valo enum hal_reo_cmd_status status) 706d5c65159SKalle Valo { 707d5c65159SKalle Valo struct ath11k_base *ab = dp->ab; 708d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 709d5c65159SKalle Valo struct dp_reo_cache_flush_elem *elem, *tmp; 710d5c65159SKalle Valo 711d5c65159SKalle Valo if (status == HAL_REO_CMD_DRAIN) { 712d5c65159SKalle Valo goto free_desc; 713d5c65159SKalle Valo } else if (status != HAL_REO_CMD_SUCCESS) { 714d5c65159SKalle Valo /* Shouldn't happen! Cleanup in case of other failure? */ 715d5c65159SKalle Valo ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 716d5c65159SKalle Valo rx_tid->tid, status); 717d5c65159SKalle Valo return; 718d5c65159SKalle Valo } 719d5c65159SKalle Valo 720d5c65159SKalle Valo elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 721d5c65159SKalle Valo if (!elem) 722d5c65159SKalle Valo goto free_desc; 723d5c65159SKalle Valo 724d5c65159SKalle Valo elem->ts = jiffies; 725d5c65159SKalle Valo memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 726d5c65159SKalle Valo 727d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 728d5c65159SKalle Valo list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 7295cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count++; 730d5c65159SKalle Valo 731d5c65159SKalle Valo /* Flush and invalidate aged REO desc from HW cache */ 732d5c65159SKalle Valo list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 733d5c65159SKalle Valo list) { 7345cb899ddSKarthikeyan Periyasamy if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 7355cb899ddSKarthikeyan Periyasamy time_after(jiffies, elem->ts + 736d5c65159SKalle Valo msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 737d5c65159SKalle Valo list_del(&elem->list); 7385cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 739d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 740d5c65159SKalle Valo 741d5c65159SKalle Valo ath11k_dp_reo_cache_flush(ab, &elem->data); 742d5c65159SKalle Valo kfree(elem); 743d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 744d5c65159SKalle Valo } 745d5c65159SKalle Valo } 746d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 747d5c65159SKalle Valo 748d5c65159SKalle Valo return; 749d5c65159SKalle Valo free_desc: 750d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 751d5c65159SKalle Valo DMA_BIDIRECTIONAL); 752d5c65159SKalle Valo kfree(rx_tid->vaddr); 753d5c65159SKalle Valo } 754d5c65159SKalle Valo 755a36adf54SGovindaraj Saminathan void ath11k_peer_rx_tid_delete(struct ath11k *ar, 756d5c65159SKalle Valo struct ath11k_peer *peer, u8 tid) 757d5c65159SKalle Valo { 758d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 759d5c65159SKalle Valo struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 760d5c65159SKalle Valo int ret; 761d5c65159SKalle Valo 762d5c65159SKalle Valo if (!rx_tid->active) 763d5c65159SKalle Valo return; 764d5c65159SKalle Valo 765d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 766d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 767d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 768d5c65159SKalle Valo cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 769d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 770d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 771d5c65159SKalle Valo ath11k_dp_rx_tid_del_func); 772d5c65159SKalle Valo if (ret) { 773d5c65159SKalle Valo ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 774d5c65159SKalle Valo tid, ret); 775d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 776d5c65159SKalle Valo DMA_BIDIRECTIONAL); 777d5c65159SKalle Valo kfree(rx_tid->vaddr); 778d5c65159SKalle Valo } 779d5c65159SKalle Valo 780d5c65159SKalle Valo rx_tid->active = false; 781d5c65159SKalle Valo } 782d5c65159SKalle Valo 783243874c6SManikanta Pubbisetty static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 784243874c6SManikanta Pubbisetty u32 *link_desc, 785243874c6SManikanta Pubbisetty enum hal_wbm_rel_bm_act action) 786243874c6SManikanta Pubbisetty { 787243874c6SManikanta Pubbisetty struct ath11k_dp *dp = &ab->dp; 788243874c6SManikanta Pubbisetty struct hal_srng *srng; 789243874c6SManikanta Pubbisetty u32 *desc; 790243874c6SManikanta Pubbisetty int ret = 0; 791243874c6SManikanta Pubbisetty 792243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 793243874c6SManikanta Pubbisetty 794243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 795243874c6SManikanta Pubbisetty 796243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 797243874c6SManikanta Pubbisetty 798243874c6SManikanta Pubbisetty desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 799243874c6SManikanta Pubbisetty if (!desc) { 800243874c6SManikanta Pubbisetty ret = -ENOBUFS; 801243874c6SManikanta Pubbisetty goto exit; 802243874c6SManikanta Pubbisetty } 803243874c6SManikanta Pubbisetty 804243874c6SManikanta Pubbisetty ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 805243874c6SManikanta Pubbisetty action); 806243874c6SManikanta Pubbisetty 807243874c6SManikanta Pubbisetty exit: 808243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 809243874c6SManikanta Pubbisetty 810243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 811243874c6SManikanta Pubbisetty 812243874c6SManikanta Pubbisetty return ret; 813243874c6SManikanta Pubbisetty } 814243874c6SManikanta Pubbisetty 815243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 816243874c6SManikanta Pubbisetty { 817243874c6SManikanta Pubbisetty struct ath11k_base *ab = rx_tid->ab; 818243874c6SManikanta Pubbisetty 819243874c6SManikanta Pubbisetty lockdep_assert_held(&ab->base_lock); 820243874c6SManikanta Pubbisetty 821243874c6SManikanta Pubbisetty if (rx_tid->dst_ring_desc) { 822243874c6SManikanta Pubbisetty if (rel_link_desc) 823243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 824243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 825243874c6SManikanta Pubbisetty kfree(rx_tid->dst_ring_desc); 826243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = NULL; 827243874c6SManikanta Pubbisetty } 828243874c6SManikanta Pubbisetty 829243874c6SManikanta Pubbisetty rx_tid->cur_sn = 0; 830243874c6SManikanta Pubbisetty rx_tid->last_frag_no = 0; 831243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap = 0; 832243874c6SManikanta Pubbisetty __skb_queue_purge(&rx_tid->rx_frags); 833243874c6SManikanta Pubbisetty } 834243874c6SManikanta Pubbisetty 835d5c65159SKalle Valo void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 836d5c65159SKalle Valo { 837243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 838d5c65159SKalle Valo int i; 839d5c65159SKalle Valo 840243874c6SManikanta Pubbisetty lockdep_assert_held(&ar->ab->base_lock); 841243874c6SManikanta Pubbisetty 842243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 843243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 844243874c6SManikanta Pubbisetty 845d5c65159SKalle Valo ath11k_peer_rx_tid_delete(ar, peer, i); 846243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 847243874c6SManikanta Pubbisetty 848243874c6SManikanta Pubbisetty spin_unlock_bh(&ar->ab->base_lock); 849243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 850243874c6SManikanta Pubbisetty spin_lock_bh(&ar->ab->base_lock); 851243874c6SManikanta Pubbisetty } 852d5c65159SKalle Valo } 853d5c65159SKalle Valo 854d5c65159SKalle Valo static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 855d5c65159SKalle Valo struct ath11k_peer *peer, 856d5c65159SKalle Valo struct dp_rx_tid *rx_tid, 857fe201947SVenkateswara Naralasetty u32 ba_win_sz, u16 ssn, 858fe201947SVenkateswara Naralasetty bool update_ssn) 859d5c65159SKalle Valo { 860d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 861d5c65159SKalle Valo int ret; 862d5c65159SKalle Valo 863d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 864d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 865d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 866fe201947SVenkateswara Naralasetty cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 867d5c65159SKalle Valo cmd.ba_window_size = ba_win_sz; 868fe201947SVenkateswara Naralasetty 869fe201947SVenkateswara Naralasetty if (update_ssn) { 870fe201947SVenkateswara Naralasetty cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 871d5c65159SKalle Valo cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 872fe201947SVenkateswara Naralasetty } 873d5c65159SKalle Valo 874d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 875d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 876d5c65159SKalle Valo NULL); 877d5c65159SKalle Valo if (ret) { 878d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 879d5c65159SKalle Valo rx_tid->tid, ret); 880d5c65159SKalle Valo return ret; 881d5c65159SKalle Valo } 882d5c65159SKalle Valo 883d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 884d5c65159SKalle Valo 885d5c65159SKalle Valo return 0; 886d5c65159SKalle Valo } 887d5c65159SKalle Valo 888d5c65159SKalle Valo static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 889d5c65159SKalle Valo const u8 *peer_mac, int vdev_id, u8 tid) 890d5c65159SKalle Valo { 891d5c65159SKalle Valo struct ath11k_peer *peer; 892d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 893d5c65159SKalle Valo 894d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 895d5c65159SKalle Valo 896d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 897d5c65159SKalle Valo if (!peer) { 898d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 899d5c65159SKalle Valo goto unlock_exit; 900d5c65159SKalle Valo } 901d5c65159SKalle Valo 902d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 903d5c65159SKalle Valo if (!rx_tid->active) 904d5c65159SKalle Valo goto unlock_exit; 905d5c65159SKalle Valo 906d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 907d5c65159SKalle Valo DMA_BIDIRECTIONAL); 908d5c65159SKalle Valo kfree(rx_tid->vaddr); 909d5c65159SKalle Valo 910d5c65159SKalle Valo rx_tid->active = false; 911d5c65159SKalle Valo 912d5c65159SKalle Valo unlock_exit: 913d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 914d5c65159SKalle Valo } 915d5c65159SKalle Valo 916d5c65159SKalle Valo int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 9171441b2f2SManikanta Pubbisetty u8 tid, u32 ba_win_sz, u16 ssn, 9181441b2f2SManikanta Pubbisetty enum hal_pn_type pn_type) 919d5c65159SKalle Valo { 920d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 921d5c65159SKalle Valo struct ath11k_peer *peer; 922d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 923d5c65159SKalle Valo u32 hw_desc_sz; 924d5c65159SKalle Valo u32 *addr_aligned; 925d5c65159SKalle Valo void *vaddr; 926d5c65159SKalle Valo dma_addr_t paddr; 927d5c65159SKalle Valo int ret; 928d5c65159SKalle Valo 929d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 930d5c65159SKalle Valo 931d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 932d5c65159SKalle Valo if (!peer) { 933d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); 934d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 935d5c65159SKalle Valo return -ENOENT; 936d5c65159SKalle Valo } 937d5c65159SKalle Valo 938d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 939d5c65159SKalle Valo /* Update the tid queue if it is already setup */ 940d5c65159SKalle Valo if (rx_tid->active) { 941d5c65159SKalle Valo paddr = rx_tid->paddr; 942d5c65159SKalle Valo ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 943fe201947SVenkateswara Naralasetty ba_win_sz, ssn, true); 944d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 945d5c65159SKalle Valo if (ret) { 946d5c65159SKalle Valo ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); 947d5c65159SKalle Valo return ret; 948d5c65159SKalle Valo } 949d5c65159SKalle Valo 950d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 951d5c65159SKalle Valo peer_mac, paddr, 952d5c65159SKalle Valo tid, 1, ba_win_sz); 953d5c65159SKalle Valo if (ret) 954d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", 955d5c65159SKalle Valo tid, ret); 956d5c65159SKalle Valo return ret; 957d5c65159SKalle Valo } 958d5c65159SKalle Valo 959d5c65159SKalle Valo rx_tid->tid = tid; 960d5c65159SKalle Valo 961d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 962d5c65159SKalle Valo 963d5c65159SKalle Valo /* TODO: Optimize the memory allocation for qos tid based on the 964d5c65159SKalle Valo * the actual BA window size in REO tid update path. 965d5c65159SKalle Valo */ 966d5c65159SKalle Valo if (tid == HAL_DESC_REO_NON_QOS_TID) 967d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 968d5c65159SKalle Valo else 969d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 970d5c65159SKalle Valo 97169c93f96SWei Yongjun vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 972d5c65159SKalle Valo if (!vaddr) { 973d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 974d5c65159SKalle Valo return -ENOMEM; 975d5c65159SKalle Valo } 976d5c65159SKalle Valo 977d5c65159SKalle Valo addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 978d5c65159SKalle Valo 9791441b2f2SManikanta Pubbisetty ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 9801441b2f2SManikanta Pubbisetty ssn, pn_type); 981d5c65159SKalle Valo 982d5c65159SKalle Valo paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 983d5c65159SKalle Valo DMA_BIDIRECTIONAL); 984d5c65159SKalle Valo 985d5c65159SKalle Valo ret = dma_mapping_error(ab->dev, paddr); 986d5c65159SKalle Valo if (ret) { 987d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 988d5c65159SKalle Valo goto err_mem_free; 989d5c65159SKalle Valo } 990d5c65159SKalle Valo 991d5c65159SKalle Valo rx_tid->vaddr = vaddr; 992d5c65159SKalle Valo rx_tid->paddr = paddr; 993d5c65159SKalle Valo rx_tid->size = hw_desc_sz; 994d5c65159SKalle Valo rx_tid->active = true; 995d5c65159SKalle Valo 996d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 997d5c65159SKalle Valo 998d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 999d5c65159SKalle Valo paddr, tid, 1, ba_win_sz); 1000d5c65159SKalle Valo if (ret) { 1001d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", 1002d5c65159SKalle Valo tid, ret); 1003d5c65159SKalle Valo ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 1004d5c65159SKalle Valo } 1005d5c65159SKalle Valo 1006d5c65159SKalle Valo return ret; 1007d5c65159SKalle Valo 1008d5c65159SKalle Valo err_mem_free: 1009d5c65159SKalle Valo kfree(vaddr); 1010d5c65159SKalle Valo 1011d5c65159SKalle Valo return ret; 1012d5c65159SKalle Valo } 1013d5c65159SKalle Valo 1014d5c65159SKalle Valo int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 1015d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1016d5c65159SKalle Valo { 1017d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1018d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1019d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1020d5c65159SKalle Valo int ret; 1021d5c65159SKalle Valo 1022d5c65159SKalle Valo ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 1023d5c65159SKalle Valo params->tid, params->buf_size, 10241441b2f2SManikanta Pubbisetty params->ssn, arsta->pn_type); 1025d5c65159SKalle Valo if (ret) 1026d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 1027d5c65159SKalle Valo 1028d5c65159SKalle Valo return ret; 1029d5c65159SKalle Valo } 1030d5c65159SKalle Valo 1031d5c65159SKalle Valo int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 1032d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1033d5c65159SKalle Valo { 1034d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1035d5c65159SKalle Valo struct ath11k_peer *peer; 1036d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1037d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1038d5c65159SKalle Valo dma_addr_t paddr; 1039d5c65159SKalle Valo bool active; 1040d5c65159SKalle Valo int ret; 1041d5c65159SKalle Valo 1042d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1043d5c65159SKalle Valo 1044d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 1045d5c65159SKalle Valo if (!peer) { 1046d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1047d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1048d5c65159SKalle Valo return -ENOENT; 1049d5c65159SKalle Valo } 1050d5c65159SKalle Valo 1051d5c65159SKalle Valo paddr = peer->rx_tid[params->tid].paddr; 1052d5c65159SKalle Valo active = peer->rx_tid[params->tid].active; 1053d5c65159SKalle Valo 1054fe201947SVenkateswara Naralasetty if (!active) { 1055d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1056d5c65159SKalle Valo return 0; 1057fe201947SVenkateswara Naralasetty } 1058fe201947SVenkateswara Naralasetty 1059fe201947SVenkateswara Naralasetty ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1060fe201947SVenkateswara Naralasetty spin_unlock_bh(&ab->base_lock); 1061fe201947SVenkateswara Naralasetty if (ret) { 1062fe201947SVenkateswara Naralasetty ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1063fe201947SVenkateswara Naralasetty params->tid, ret); 1064fe201947SVenkateswara Naralasetty return ret; 1065fe201947SVenkateswara Naralasetty } 1066d5c65159SKalle Valo 1067d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1068d5c65159SKalle Valo params->sta->addr, paddr, 1069d5c65159SKalle Valo params->tid, 1, 1); 1070d5c65159SKalle Valo if (ret) 1071d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1072d5c65159SKalle Valo ret); 1073d5c65159SKalle Valo 1074d5c65159SKalle Valo return ret; 1075d5c65159SKalle Valo } 1076d5c65159SKalle Valo 10771441b2f2SManikanta Pubbisetty int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 10781441b2f2SManikanta Pubbisetty const u8 *peer_addr, 10791441b2f2SManikanta Pubbisetty enum set_key_cmd key_cmd, 10801441b2f2SManikanta Pubbisetty struct ieee80211_key_conf *key) 10811441b2f2SManikanta Pubbisetty { 10821441b2f2SManikanta Pubbisetty struct ath11k *ar = arvif->ar; 10831441b2f2SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 10841441b2f2SManikanta Pubbisetty struct ath11k_hal_reo_cmd cmd = {0}; 10851441b2f2SManikanta Pubbisetty struct ath11k_peer *peer; 10861441b2f2SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 10871441b2f2SManikanta Pubbisetty u8 tid; 10881441b2f2SManikanta Pubbisetty int ret = 0; 10891441b2f2SManikanta Pubbisetty 10901441b2f2SManikanta Pubbisetty /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 10911441b2f2SManikanta Pubbisetty * We use mac80211 PN/TSC replay check functionality for bcast/mcast 10921441b2f2SManikanta Pubbisetty * for now. 10931441b2f2SManikanta Pubbisetty */ 10941441b2f2SManikanta Pubbisetty if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 10951441b2f2SManikanta Pubbisetty return 0; 10961441b2f2SManikanta Pubbisetty 10971441b2f2SManikanta Pubbisetty cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 10981441b2f2SManikanta Pubbisetty cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 10991441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_SIZE | 11001441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_VALID | 11011441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_CHECK | 11021441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_SVLD; 11031441b2f2SManikanta Pubbisetty 11041441b2f2SManikanta Pubbisetty switch (key->cipher) { 11051441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_TKIP: 11061441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP: 11071441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP_256: 11081441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP: 11091441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP_256: 11101441b2f2SManikanta Pubbisetty if (key_cmd == SET_KEY) { 11111441b2f2SManikanta Pubbisetty cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 11121441b2f2SManikanta Pubbisetty cmd.pn_size = 48; 11131441b2f2SManikanta Pubbisetty } 11141441b2f2SManikanta Pubbisetty break; 11151441b2f2SManikanta Pubbisetty default: 11161441b2f2SManikanta Pubbisetty break; 11171441b2f2SManikanta Pubbisetty } 11181441b2f2SManikanta Pubbisetty 11191441b2f2SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 11201441b2f2SManikanta Pubbisetty 11211441b2f2SManikanta Pubbisetty peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 11221441b2f2SManikanta Pubbisetty if (!peer) { 11231441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 11241441b2f2SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 11251441b2f2SManikanta Pubbisetty return -ENOENT; 11261441b2f2SManikanta Pubbisetty } 11271441b2f2SManikanta Pubbisetty 11281441b2f2SManikanta Pubbisetty for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 11291441b2f2SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 11301441b2f2SManikanta Pubbisetty if (!rx_tid->active) 11311441b2f2SManikanta Pubbisetty continue; 11321441b2f2SManikanta Pubbisetty cmd.addr_lo = lower_32_bits(rx_tid->paddr); 11331441b2f2SManikanta Pubbisetty cmd.addr_hi = upper_32_bits(rx_tid->paddr); 11341441b2f2SManikanta Pubbisetty ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 11351441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPDATE_RX_QUEUE, 11361441b2f2SManikanta Pubbisetty &cmd, NULL); 11371441b2f2SManikanta Pubbisetty if (ret) { 11381441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 11391441b2f2SManikanta Pubbisetty tid, ret); 11401441b2f2SManikanta Pubbisetty break; 11411441b2f2SManikanta Pubbisetty } 11421441b2f2SManikanta Pubbisetty } 11431441b2f2SManikanta Pubbisetty 11441441b2f2SManikanta Pubbisetty spin_unlock_bh(&ar->ab->base_lock); 11451441b2f2SManikanta Pubbisetty 11461441b2f2SManikanta Pubbisetty return ret; 11471441b2f2SManikanta Pubbisetty } 11481441b2f2SManikanta Pubbisetty 11491441b2f2SManikanta Pubbisetty static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1150d5c65159SKalle Valo u16 peer_id) 1151d5c65159SKalle Valo { 1152d5c65159SKalle Valo int i; 1153d5c65159SKalle Valo 1154d5c65159SKalle Valo for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1155d5c65159SKalle Valo if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1156d5c65159SKalle Valo if (peer_id == ppdu_stats->user_stats[i].peer_id) 1157d5c65159SKalle Valo return i; 1158d5c65159SKalle Valo } else { 1159d5c65159SKalle Valo return i; 1160d5c65159SKalle Valo } 1161d5c65159SKalle Valo } 1162d5c65159SKalle Valo 1163d5c65159SKalle Valo return -EINVAL; 1164d5c65159SKalle Valo } 1165d5c65159SKalle Valo 1166d5c65159SKalle Valo static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1167d5c65159SKalle Valo u16 tag, u16 len, const void *ptr, 1168d5c65159SKalle Valo void *data) 1169d5c65159SKalle Valo { 1170d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1171d5c65159SKalle Valo struct htt_ppdu_user_stats *user_stats; 1172d5c65159SKalle Valo int cur_user; 1173d5c65159SKalle Valo u16 peer_id; 1174d5c65159SKalle Valo 1175d5c65159SKalle Valo ppdu_info = (struct htt_ppdu_stats_info *)data; 1176d5c65159SKalle Valo 1177d5c65159SKalle Valo switch (tag) { 1178d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_COMMON: 1179d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_common)) { 1180d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1181d5c65159SKalle Valo len, tag); 1182d5c65159SKalle Valo return -EINVAL; 1183d5c65159SKalle Valo } 1184d5c65159SKalle Valo memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1185d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_common)); 1186d5c65159SKalle Valo break; 1187d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_RATE: 1188d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1189d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1190d5c65159SKalle Valo len, tag); 1191d5c65159SKalle Valo return -EINVAL; 1192d5c65159SKalle Valo } 1193d5c65159SKalle Valo 1194d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1195d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1196d5c65159SKalle Valo peer_id); 1197d5c65159SKalle Valo if (cur_user < 0) 1198d5c65159SKalle Valo return -EINVAL; 1199d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1200d5c65159SKalle Valo user_stats->peer_id = peer_id; 1201d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1202d5c65159SKalle Valo memcpy((void *)&user_stats->rate, ptr, 1203d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_user_rate)); 1204d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1205d5c65159SKalle Valo break; 1206d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1207d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1208d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1209d5c65159SKalle Valo len, tag); 1210d5c65159SKalle Valo return -EINVAL; 1211d5c65159SKalle Valo } 1212d5c65159SKalle Valo 1213d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1214d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1215d5c65159SKalle Valo peer_id); 1216d5c65159SKalle Valo if (cur_user < 0) 1217d5c65159SKalle Valo return -EINVAL; 1218d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1219d5c65159SKalle Valo user_stats->peer_id = peer_id; 1220d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1221d5c65159SKalle Valo memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1222d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1223d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1224d5c65159SKalle Valo break; 1225d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1226d5c65159SKalle Valo if (len < 1227d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1228d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1229d5c65159SKalle Valo len, tag); 1230d5c65159SKalle Valo return -EINVAL; 1231d5c65159SKalle Valo } 1232d5c65159SKalle Valo 1233d5c65159SKalle Valo peer_id = 1234d5c65159SKalle Valo ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1235d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1236d5c65159SKalle Valo peer_id); 1237d5c65159SKalle Valo if (cur_user < 0) 1238d5c65159SKalle Valo return -EINVAL; 1239d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1240d5c65159SKalle Valo user_stats->peer_id = peer_id; 1241d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1242d5c65159SKalle Valo memcpy((void *)&user_stats->ack_ba, ptr, 1243d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1244d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1245d5c65159SKalle Valo break; 1246d5c65159SKalle Valo } 1247d5c65159SKalle Valo return 0; 1248d5c65159SKalle Valo } 1249d5c65159SKalle Valo 1250d5c65159SKalle Valo int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1251d5c65159SKalle Valo int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1252d5c65159SKalle Valo const void *ptr, void *data), 1253d5c65159SKalle Valo void *data) 1254d5c65159SKalle Valo { 1255d5c65159SKalle Valo const struct htt_tlv *tlv; 1256d5c65159SKalle Valo const void *begin = ptr; 1257d5c65159SKalle Valo u16 tlv_tag, tlv_len; 1258d5c65159SKalle Valo int ret = -EINVAL; 1259d5c65159SKalle Valo 1260d5c65159SKalle Valo while (len > 0) { 1261d5c65159SKalle Valo if (len < sizeof(*tlv)) { 1262d5c65159SKalle Valo ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1263d5c65159SKalle Valo ptr - begin, len, sizeof(*tlv)); 1264d5c65159SKalle Valo return -EINVAL; 1265d5c65159SKalle Valo } 1266d5c65159SKalle Valo tlv = (struct htt_tlv *)ptr; 1267d5c65159SKalle Valo tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1268d5c65159SKalle Valo tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1269d5c65159SKalle Valo ptr += sizeof(*tlv); 1270d5c65159SKalle Valo len -= sizeof(*tlv); 1271d5c65159SKalle Valo 1272d5c65159SKalle Valo if (tlv_len > len) { 1273d5c65159SKalle Valo ath11k_err(ab, "htt tlv parse failure of tag %hhu at byte %zd (%zu bytes left, %hhu expected)\n", 1274d5c65159SKalle Valo tlv_tag, ptr - begin, len, tlv_len); 1275d5c65159SKalle Valo return -EINVAL; 1276d5c65159SKalle Valo } 1277d5c65159SKalle Valo ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1278d5c65159SKalle Valo if (ret == -ENOMEM) 1279d5c65159SKalle Valo return ret; 1280d5c65159SKalle Valo 1281d5c65159SKalle Valo ptr += tlv_len; 1282d5c65159SKalle Valo len -= tlv_len; 1283d5c65159SKalle Valo } 1284d5c65159SKalle Valo return 0; 1285d5c65159SKalle Valo } 1286d5c65159SKalle Valo 12876a0c3702SJohn Crispin static inline u32 ath11k_he_gi_to_nl80211_he_gi(u8 sgi) 12886a0c3702SJohn Crispin { 12896a0c3702SJohn Crispin u32 ret = 0; 12906a0c3702SJohn Crispin 12916a0c3702SJohn Crispin switch (sgi) { 12926a0c3702SJohn Crispin case RX_MSDU_START_SGI_0_8_US: 12936a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_0_8; 12946a0c3702SJohn Crispin break; 12956a0c3702SJohn Crispin case RX_MSDU_START_SGI_1_6_US: 12966a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_1_6; 12976a0c3702SJohn Crispin break; 12986a0c3702SJohn Crispin case RX_MSDU_START_SGI_3_2_US: 12996a0c3702SJohn Crispin ret = NL80211_RATE_INFO_HE_GI_3_2; 13006a0c3702SJohn Crispin break; 13016a0c3702SJohn Crispin } 13026a0c3702SJohn Crispin 13036a0c3702SJohn Crispin return ret; 13046a0c3702SJohn Crispin } 13056a0c3702SJohn Crispin 1306d5c65159SKalle Valo static void 1307d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1308d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats, u8 user) 1309d5c65159SKalle Valo { 1310d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1311d5c65159SKalle Valo struct ath11k_peer *peer; 1312d5c65159SKalle Valo struct ieee80211_sta *sta; 1313d5c65159SKalle Valo struct ath11k_sta *arsta; 1314d5c65159SKalle Valo struct htt_ppdu_stats_user_rate *user_rate; 1315d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1316d5c65159SKalle Valo struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1317d5c65159SKalle Valo struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1318d5c65159SKalle Valo int ret; 13196a0c3702SJohn Crispin u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1320d5c65159SKalle Valo u32 succ_bytes = 0; 1321d5c65159SKalle Valo u16 rate = 0, succ_pkts = 0; 1322d5c65159SKalle Valo u32 tx_duration = 0; 1323b9269a07SVenkateswara Naralasetty u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1324d5c65159SKalle Valo bool is_ampdu = false; 1325d5c65159SKalle Valo 1326d5c65159SKalle Valo if (!usr_stats) 1327d5c65159SKalle Valo return; 1328d5c65159SKalle Valo 1329d5c65159SKalle Valo if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1330d5c65159SKalle Valo return; 1331d5c65159SKalle Valo 1332d5c65159SKalle Valo if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1333d5c65159SKalle Valo is_ampdu = 1334d5c65159SKalle Valo HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1335d5c65159SKalle Valo 1336d5c65159SKalle Valo if (usr_stats->tlv_flags & 1337d5c65159SKalle Valo BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1338d5c65159SKalle Valo succ_bytes = usr_stats->ack_ba.success_bytes; 1339d5c65159SKalle Valo succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1340d5c65159SKalle Valo usr_stats->ack_ba.info); 1341b9269a07SVenkateswara Naralasetty tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1342b9269a07SVenkateswara Naralasetty usr_stats->ack_ba.info); 1343d5c65159SKalle Valo } 1344d5c65159SKalle Valo 1345d5c65159SKalle Valo if (common->fes_duration_us) 1346d5c65159SKalle Valo tx_duration = common->fes_duration_us; 1347d5c65159SKalle Valo 1348d5c65159SKalle Valo user_rate = &usr_stats->rate; 1349d5c65159SKalle Valo flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1350d5c65159SKalle Valo bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1351d5c65159SKalle Valo nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1352d5c65159SKalle Valo mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1353d5c65159SKalle Valo sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 13546a0c3702SJohn Crispin dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1355d5c65159SKalle Valo 1356d5c65159SKalle Valo /* Note: If host configured fixed rates and in some other special 1357d5c65159SKalle Valo * cases, the broadcast/management frames are sent in different rates. 1358d5c65159SKalle Valo * Firmware rate's control to be skipped for this? 1359d5c65159SKalle Valo */ 1360d5c65159SKalle Valo 13616a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) { 13626a0c3702SJohn Crispin ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs); 13636a0c3702SJohn Crispin return; 13646a0c3702SJohn Crispin } 13656a0c3702SJohn Crispin 13666a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 13676a0c3702SJohn Crispin ath11k_warn(ab, "Invalid HE mcs %hhd peer stats", mcs); 13686a0c3702SJohn Crispin return; 13696a0c3702SJohn Crispin } 13706a0c3702SJohn Crispin 13716a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1372d5c65159SKalle Valo ath11k_warn(ab, "Invalid VHT mcs %hhd peer stats", mcs); 1373d5c65159SKalle Valo return; 1374d5c65159SKalle Valo } 1375d5c65159SKalle Valo 13766a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1377d5c65159SKalle Valo ath11k_warn(ab, "Invalid HT mcs %hhd nss %hhd peer stats", 1378d5c65159SKalle Valo mcs, nss); 1379d5c65159SKalle Valo return; 1380d5c65159SKalle Valo } 1381d5c65159SKalle Valo 1382d5c65159SKalle Valo if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1383d5c65159SKalle Valo ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1384d5c65159SKalle Valo flags, 1385d5c65159SKalle Valo &rate_idx, 1386d5c65159SKalle Valo &rate); 1387d5c65159SKalle Valo if (ret < 0) 1388d5c65159SKalle Valo return; 1389d5c65159SKalle Valo } 1390d5c65159SKalle Valo 1391d5c65159SKalle Valo rcu_read_lock(); 1392d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1393d5c65159SKalle Valo peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1394d5c65159SKalle Valo 1395d5c65159SKalle Valo if (!peer || !peer->sta) { 1396d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1397d5c65159SKalle Valo rcu_read_unlock(); 1398d5c65159SKalle Valo return; 1399d5c65159SKalle Valo } 1400d5c65159SKalle Valo 1401d5c65159SKalle Valo sta = peer->sta; 1402d5c65159SKalle Valo arsta = (struct ath11k_sta *)sta->drv_priv; 1403d5c65159SKalle Valo 1404d5c65159SKalle Valo memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1405d5c65159SKalle Valo 1406d5c65159SKalle Valo switch (flags) { 1407d5c65159SKalle Valo case WMI_RATE_PREAMBLE_OFDM: 1408d5c65159SKalle Valo arsta->txrate.legacy = rate; 1409d5c65159SKalle Valo break; 1410d5c65159SKalle Valo case WMI_RATE_PREAMBLE_CCK: 1411d5c65159SKalle Valo arsta->txrate.legacy = rate; 1412d5c65159SKalle Valo break; 1413d5c65159SKalle Valo case WMI_RATE_PREAMBLE_HT: 1414d5c65159SKalle Valo arsta->txrate.mcs = mcs + 8 * (nss - 1); 1415d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1416be43ce64SJohn Crispin if (sgi) 1417d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1418d5c65159SKalle Valo break; 1419d5c65159SKalle Valo case WMI_RATE_PREAMBLE_VHT: 1420d5c65159SKalle Valo arsta->txrate.mcs = mcs; 1421d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1422be43ce64SJohn Crispin if (sgi) 1423d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1424d5c65159SKalle Valo break; 14256a0c3702SJohn Crispin case WMI_RATE_PREAMBLE_HE: 14266a0c3702SJohn Crispin arsta->txrate.mcs = mcs; 14276a0c3702SJohn Crispin arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 14286a0c3702SJohn Crispin arsta->txrate.he_dcm = dcm; 14296a0c3702SJohn Crispin arsta->txrate.he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 14306a0c3702SJohn Crispin arsta->txrate.he_ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc( 14316a0c3702SJohn Crispin (user_rate->ru_end - 14326a0c3702SJohn Crispin user_rate->ru_start) + 1); 14336a0c3702SJohn Crispin break; 1434d5c65159SKalle Valo } 1435d5c65159SKalle Valo 1436d5c65159SKalle Valo arsta->txrate.nss = nss; 143739e81c6aSTamizh chelvam arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1438a9e945eaSVenkateswara Naralasetty arsta->tx_duration += tx_duration; 1439d5c65159SKalle Valo memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1440d5c65159SKalle Valo 1441b9269a07SVenkateswara Naralasetty /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1442b9269a07SVenkateswara Naralasetty * So skip peer stats update for mgmt packets. 1443b9269a07SVenkateswara Naralasetty */ 1444b9269a07SVenkateswara Naralasetty if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1445d5c65159SKalle Valo memset(peer_stats, 0, sizeof(*peer_stats)); 1446d5c65159SKalle Valo peer_stats->succ_pkts = succ_pkts; 1447d5c65159SKalle Valo peer_stats->succ_bytes = succ_bytes; 1448d5c65159SKalle Valo peer_stats->is_ampdu = is_ampdu; 1449d5c65159SKalle Valo peer_stats->duration = tx_duration; 1450d5c65159SKalle Valo peer_stats->ba_fails = 1451d5c65159SKalle Valo HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1452d5c65159SKalle Valo HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1453d5c65159SKalle Valo 1454cb4e57dbSKalle Valo if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 1455568f0603SKalle Valo ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 1456b9269a07SVenkateswara Naralasetty } 1457d5c65159SKalle Valo 1458d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1459d5c65159SKalle Valo rcu_read_unlock(); 1460d5c65159SKalle Valo } 1461d5c65159SKalle Valo 1462d5c65159SKalle Valo static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1463d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats) 1464d5c65159SKalle Valo { 1465d5c65159SKalle Valo u8 user; 1466d5c65159SKalle Valo 1467d5c65159SKalle Valo for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1468d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1469d5c65159SKalle Valo } 1470d5c65159SKalle Valo 1471d5c65159SKalle Valo static 1472d5c65159SKalle Valo struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1473d5c65159SKalle Valo u32 ppdu_id) 1474d5c65159SKalle Valo { 1475269663f1SDan Carpenter struct htt_ppdu_stats_info *ppdu_info; 1476d5c65159SKalle Valo 1477d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1478d5c65159SKalle Valo if (!list_empty(&ar->ppdu_stats_info)) { 1479d5c65159SKalle Valo list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1480269663f1SDan Carpenter if (ppdu_info->ppdu_id == ppdu_id) { 1481d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1482d5c65159SKalle Valo return ppdu_info; 1483d5c65159SKalle Valo } 1484d5c65159SKalle Valo } 1485d5c65159SKalle Valo 1486d5c65159SKalle Valo if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1487d5c65159SKalle Valo ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1488d5c65159SKalle Valo typeof(*ppdu_info), list); 1489d5c65159SKalle Valo list_del(&ppdu_info->list); 1490d5c65159SKalle Valo ar->ppdu_stat_list_depth--; 1491d5c65159SKalle Valo ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1492d5c65159SKalle Valo kfree(ppdu_info); 1493d5c65159SKalle Valo } 1494d5c65159SKalle Valo } 1495d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1496d5c65159SKalle Valo 14976a8be1baSWen Gong ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1498d5c65159SKalle Valo if (!ppdu_info) 1499d5c65159SKalle Valo return NULL; 1500d5c65159SKalle Valo 1501d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1502d5c65159SKalle Valo list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1503d5c65159SKalle Valo ar->ppdu_stat_list_depth++; 1504d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1505d5c65159SKalle Valo 1506d5c65159SKalle Valo return ppdu_info; 1507d5c65159SKalle Valo } 1508d5c65159SKalle Valo 1509d5c65159SKalle Valo static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1510d5c65159SKalle Valo struct sk_buff *skb) 1511d5c65159SKalle Valo { 1512d5c65159SKalle Valo struct ath11k_htt_ppdu_stats_msg *msg; 1513d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1514d5c65159SKalle Valo struct ath11k *ar; 1515d5c65159SKalle Valo int ret; 1516d5c65159SKalle Valo u8 pdev_id; 1517d5c65159SKalle Valo u32 ppdu_id, len; 1518d5c65159SKalle Valo 1519d5c65159SKalle Valo msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1520d5c65159SKalle Valo len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1521d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1522d5c65159SKalle Valo ppdu_id = msg->ppdu_id; 1523d5c65159SKalle Valo 1524d5c65159SKalle Valo rcu_read_lock(); 1525d5c65159SKalle Valo ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1526d5c65159SKalle Valo if (!ar) { 1527d5c65159SKalle Valo ret = -EINVAL; 1528d5c65159SKalle Valo goto exit; 1529d5c65159SKalle Valo } 1530d5c65159SKalle Valo 1531cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) 1532d5c65159SKalle Valo trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1533d5c65159SKalle Valo 1534d5c65159SKalle Valo ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1535d5c65159SKalle Valo if (!ppdu_info) { 1536d5c65159SKalle Valo ret = -EINVAL; 1537d5c65159SKalle Valo goto exit; 1538d5c65159SKalle Valo } 1539d5c65159SKalle Valo 1540d5c65159SKalle Valo ppdu_info->ppdu_id = ppdu_id; 1541d5c65159SKalle Valo ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1542d5c65159SKalle Valo ath11k_htt_tlv_ppdu_stats_parse, 1543d5c65159SKalle Valo (void *)ppdu_info); 1544d5c65159SKalle Valo if (ret) { 1545d5c65159SKalle Valo ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1546d5c65159SKalle Valo goto exit; 1547d5c65159SKalle Valo } 1548d5c65159SKalle Valo 1549d5c65159SKalle Valo exit: 1550d5c65159SKalle Valo rcu_read_unlock(); 1551d5c65159SKalle Valo 1552d5c65159SKalle Valo return ret; 1553d5c65159SKalle Valo } 1554d5c65159SKalle Valo 1555d5c65159SKalle Valo static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1556d5c65159SKalle Valo { 1557d5c65159SKalle Valo struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1558443d2ee7SAnilkumar Kolli struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1559d5c65159SKalle Valo struct ath11k *ar; 1560d5c65159SKalle Valo u8 pdev_id; 1561d5c65159SKalle Valo 1562d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1563d0f390eaSAnilkumar Kolli ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1564d0f390eaSAnilkumar Kolli if (!ar) { 1565d0f390eaSAnilkumar Kolli ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1566d0f390eaSAnilkumar Kolli return; 1567d0f390eaSAnilkumar Kolli } 1568d5c65159SKalle Valo 156921c1b063SMaharaja Kennadyrajan trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 157021c1b063SMaharaja Kennadyrajan ar->ab->pktlog_defs_checksum); 1571d5c65159SKalle Valo } 1572d5c65159SKalle Valo 1573678e8414SSriram R static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1574678e8414SSriram R struct sk_buff *skb) 1575678e8414SSriram R { 1576678e8414SSriram R u32 *data = (u32 *)skb->data; 157771fbc847SSriram R u8 pdev_id, ring_type, ring_id, pdev_idx; 1578678e8414SSriram R u16 hp, tp; 1579678e8414SSriram R u32 backpressure_time; 158071fbc847SSriram R struct ath11k_bp_stats *bp_stats; 1581678e8414SSriram R 1582678e8414SSriram R pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1583678e8414SSriram R ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1584678e8414SSriram R ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1585678e8414SSriram R ++data; 1586678e8414SSriram R 1587678e8414SSriram R hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1588678e8414SSriram R tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1589678e8414SSriram R ++data; 1590678e8414SSriram R 1591678e8414SSriram R backpressure_time = *data; 1592678e8414SSriram R 1593678e8414SSriram R ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1594678e8414SSriram R pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 159571fbc847SSriram R 159671fbc847SSriram R if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { 159771fbc847SSriram R if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) 159871fbc847SSriram R return; 159971fbc847SSriram R 160071fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; 160171fbc847SSriram R } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { 160271fbc847SSriram R pdev_idx = DP_HW2SW_MACID(pdev_id); 160371fbc847SSriram R 160471fbc847SSriram R if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) 160571fbc847SSriram R return; 160671fbc847SSriram R 160771fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; 160871fbc847SSriram R } else { 160971fbc847SSriram R ath11k_warn(ab, "unknown ring type received in htt bp event %d\n", 161071fbc847SSriram R ring_type); 161171fbc847SSriram R return; 161271fbc847SSriram R } 161371fbc847SSriram R 161471fbc847SSriram R spin_lock_bh(&ab->base_lock); 161571fbc847SSriram R bp_stats->hp = hp; 161671fbc847SSriram R bp_stats->tp = tp; 161771fbc847SSriram R bp_stats->count++; 161871fbc847SSriram R bp_stats->jiffies = jiffies; 161971fbc847SSriram R spin_unlock_bh(&ab->base_lock); 1620678e8414SSriram R } 1621678e8414SSriram R 1622d5c65159SKalle Valo void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1623d5c65159SKalle Valo struct sk_buff *skb) 1624d5c65159SKalle Valo { 1625d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 1626d5c65159SKalle Valo struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1627d5c65159SKalle Valo enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1628d5c65159SKalle Valo u16 peer_id; 1629d5c65159SKalle Valo u8 vdev_id; 1630d5c65159SKalle Valo u8 mac_addr[ETH_ALEN]; 1631d5c65159SKalle Valo u16 peer_mac_h16; 1632d5c65159SKalle Valo u16 ast_hash; 1633d5c65159SKalle Valo 1634d5c65159SKalle Valo ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1635d5c65159SKalle Valo 1636d5c65159SKalle Valo switch (type) { 1637d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: 1638d5c65159SKalle Valo dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1639d5c65159SKalle Valo resp->version_msg.version); 1640d5c65159SKalle Valo dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1641d5c65159SKalle Valo resp->version_msg.version); 1642d5c65159SKalle Valo complete(&dp->htt_tgt_version_received); 1643d5c65159SKalle Valo break; 1644d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: 1645a6275302SCarl Huang vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1646a6275302SCarl Huang resp->peer_map_ev.info); 1647a6275302SCarl Huang peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1648a6275302SCarl Huang resp->peer_map_ev.info); 1649a6275302SCarl Huang peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1650a6275302SCarl Huang resp->peer_map_ev.info1); 1651a6275302SCarl Huang ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1652a6275302SCarl Huang peer_mac_h16, mac_addr); 1653a6275302SCarl Huang ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0); 1654a6275302SCarl Huang break; 165513ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_MAP2: 1656d5c65159SKalle Valo vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1657d5c65159SKalle Valo resp->peer_map_ev.info); 1658d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1659d5c65159SKalle Valo resp->peer_map_ev.info); 1660d5c65159SKalle Valo peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1661d5c65159SKalle Valo resp->peer_map_ev.info1); 1662d5c65159SKalle Valo ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1663d5c65159SKalle Valo peer_mac_h16, mac_addr); 1664d5c65159SKalle Valo ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 16650f37fbf4SAnilkumar Kolli resp->peer_map_ev.info2); 1666d5c65159SKalle Valo ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash); 1667d5c65159SKalle Valo break; 1668d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: 166913ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1670d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1671d5c65159SKalle Valo resp->peer_unmap_ev.info); 1672d5c65159SKalle Valo ath11k_peer_unmap_event(ab, peer_id); 1673d5c65159SKalle Valo break; 1674d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1675d5c65159SKalle Valo ath11k_htt_pull_ppdu_stats(ab, skb); 1676d5c65159SKalle Valo break; 1677d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1678568f0603SKalle Valo ath11k_debugfs_htt_ext_stats_handler(ab, skb); 1679d5c65159SKalle Valo break; 1680d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PKTLOG: 1681d5c65159SKalle Valo ath11k_htt_pktlog(ab, skb); 1682d5c65159SKalle Valo break; 1683678e8414SSriram R case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1684678e8414SSriram R ath11k_htt_backpressure_event_handler(ab, skb); 1685678e8414SSriram R break; 1686d5c65159SKalle Valo default: 1687d5c65159SKalle Valo ath11k_warn(ab, "htt event %d not handled\n", type); 1688d5c65159SKalle Valo break; 1689d5c65159SKalle Valo } 1690d5c65159SKalle Valo 1691d5c65159SKalle Valo dev_kfree_skb_any(skb); 1692d5c65159SKalle Valo } 1693d5c65159SKalle Valo 1694d5c65159SKalle Valo static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1695d5c65159SKalle Valo struct sk_buff_head *msdu_list, 1696d5c65159SKalle Valo struct sk_buff *first, struct sk_buff *last, 1697d5c65159SKalle Valo u8 l3pad_bytes, int msdu_len) 1698d5c65159SKalle Valo { 1699d5c65159SKalle Valo struct sk_buff *skb; 1700d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1701d2f510faSSriram R int buf_first_hdr_len, buf_first_len; 1702d5c65159SKalle Valo struct hal_rx_desc *ldesc; 1703d5c65159SKalle Valo int space_extra; 1704d5c65159SKalle Valo int rem_len; 1705d5c65159SKalle Valo int buf_len; 1706d5c65159SKalle Valo 1707d2f510faSSriram R /* As the msdu is spread across multiple rx buffers, 1708d2f510faSSriram R * find the offset to the start of msdu for computing 1709d2f510faSSriram R * the length of the msdu in the first buffer. 1710d2f510faSSriram R */ 1711d2f510faSSriram R buf_first_hdr_len = HAL_RX_DESC_SIZE + l3pad_bytes; 1712d2f510faSSriram R buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1713d2f510faSSriram R 1714d2f510faSSriram R if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1715d2f510faSSriram R skb_put(first, buf_first_hdr_len + msdu_len); 1716d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1717d5c65159SKalle Valo return 0; 1718d5c65159SKalle Valo } 1719d5c65159SKalle Valo 1720d5c65159SKalle Valo ldesc = (struct hal_rx_desc *)last->data; 1721d5c65159SKalle Valo rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ldesc); 1722d5c65159SKalle Valo rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ldesc); 1723d5c65159SKalle Valo 1724d5c65159SKalle Valo /* MSDU spans over multiple buffers because the length of the MSDU 1725d5c65159SKalle Valo * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1726d5c65159SKalle Valo * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1727d5c65159SKalle Valo */ 1728d5c65159SKalle Valo skb_put(first, DP_RX_BUFFER_SIZE); 1729d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1730d5c65159SKalle Valo 173130679ec4SKarthikeyan Periyasamy /* When an MSDU spread over multiple buffers attention, MSDU_END and 173230679ec4SKarthikeyan Periyasamy * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 173330679ec4SKarthikeyan Periyasamy */ 173430679ec4SKarthikeyan Periyasamy ath11k_dp_rx_desc_end_tlv_copy(rxcb->rx_desc, ldesc); 173530679ec4SKarthikeyan Periyasamy 1736d2f510faSSriram R space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1737d5c65159SKalle Valo if (space_extra > 0 && 1738d5c65159SKalle Valo (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1739d5c65159SKalle Valo /* Free up all buffers of the MSDU */ 1740d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1741d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1742d5c65159SKalle Valo if (!rxcb->is_continuation) { 1743d5c65159SKalle Valo dev_kfree_skb_any(skb); 1744d5c65159SKalle Valo break; 1745d5c65159SKalle Valo } 1746d5c65159SKalle Valo dev_kfree_skb_any(skb); 1747d5c65159SKalle Valo } 1748d5c65159SKalle Valo return -ENOMEM; 1749d5c65159SKalle Valo } 1750d5c65159SKalle Valo 1751d2f510faSSriram R rem_len = msdu_len - buf_first_len; 1752d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1753d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1754d5c65159SKalle Valo if (rxcb->is_continuation) 1755d5c65159SKalle Valo buf_len = DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE; 1756d5c65159SKalle Valo else 1757d5c65159SKalle Valo buf_len = rem_len; 1758d5c65159SKalle Valo 1759d5c65159SKalle Valo if (buf_len > (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)) { 1760d5c65159SKalle Valo WARN_ON_ONCE(1); 1761d5c65159SKalle Valo dev_kfree_skb_any(skb); 1762d5c65159SKalle Valo return -EINVAL; 1763d5c65159SKalle Valo } 1764d5c65159SKalle Valo 1765d5c65159SKalle Valo skb_put(skb, buf_len + HAL_RX_DESC_SIZE); 1766d5c65159SKalle Valo skb_pull(skb, HAL_RX_DESC_SIZE); 1767d5c65159SKalle Valo skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1768d5c65159SKalle Valo buf_len); 1769d5c65159SKalle Valo dev_kfree_skb_any(skb); 1770d5c65159SKalle Valo 1771d5c65159SKalle Valo rem_len -= buf_len; 1772d5c65159SKalle Valo if (!rxcb->is_continuation) 1773d5c65159SKalle Valo break; 1774d5c65159SKalle Valo } 1775d5c65159SKalle Valo 1776d5c65159SKalle Valo return 0; 1777d5c65159SKalle Valo } 1778d5c65159SKalle Valo 1779d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1780d5c65159SKalle Valo struct sk_buff *first) 1781d5c65159SKalle Valo { 1782d5c65159SKalle Valo struct sk_buff *skb; 1783d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1784d5c65159SKalle Valo 1785d5c65159SKalle Valo if (!rxcb->is_continuation) 1786d5c65159SKalle Valo return first; 1787d5c65159SKalle Valo 1788d5c65159SKalle Valo skb_queue_walk(msdu_list, skb) { 1789d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1790d5c65159SKalle Valo if (!rxcb->is_continuation) 1791d5c65159SKalle Valo return skb; 1792d5c65159SKalle Valo } 1793d5c65159SKalle Valo 1794d5c65159SKalle Valo return NULL; 1795d5c65159SKalle Valo } 1796d5c65159SKalle Valo 1797d5c65159SKalle Valo static void ath11k_dp_rx_h_csum_offload(struct sk_buff *msdu) 1798d5c65159SKalle Valo { 1799d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1800d5c65159SKalle Valo bool ip_csum_fail, l4_csum_fail; 1801d5c65159SKalle Valo 1802d5c65159SKalle Valo ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rxcb->rx_desc); 1803d5c65159SKalle Valo l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rxcb->rx_desc); 1804d5c65159SKalle Valo 1805d5c65159SKalle Valo msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1806d5c65159SKalle Valo CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1807d5c65159SKalle Valo } 1808d5c65159SKalle Valo 1809d5c65159SKalle Valo static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1810d5c65159SKalle Valo enum hal_encrypt_type enctype) 1811d5c65159SKalle Valo { 1812d5c65159SKalle Valo switch (enctype) { 1813d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1814d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1815d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1816d5c65159SKalle Valo return 0; 1817d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1818d5c65159SKalle Valo return IEEE80211_CCMP_MIC_LEN; 1819d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1820d5c65159SKalle Valo return IEEE80211_CCMP_256_MIC_LEN; 1821d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1822d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1823d5c65159SKalle Valo return IEEE80211_GCMP_MIC_LEN; 1824d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1825d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1826d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1827d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1828d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1829d5c65159SKalle Valo break; 1830d5c65159SKalle Valo } 1831d5c65159SKalle Valo 1832d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1833d5c65159SKalle Valo return 0; 1834d5c65159SKalle Valo } 1835d5c65159SKalle Valo 1836d5c65159SKalle Valo static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1837d5c65159SKalle Valo enum hal_encrypt_type enctype) 1838d5c65159SKalle Valo { 1839d5c65159SKalle Valo switch (enctype) { 1840d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1841d5c65159SKalle Valo return 0; 1842d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1843d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1844d5c65159SKalle Valo return IEEE80211_TKIP_IV_LEN; 1845d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1846d5c65159SKalle Valo return IEEE80211_CCMP_HDR_LEN; 1847d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1848d5c65159SKalle Valo return IEEE80211_CCMP_256_HDR_LEN; 1849d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1850d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1851d5c65159SKalle Valo return IEEE80211_GCMP_HDR_LEN; 1852d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1853d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1854d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1855d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1856d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1857d5c65159SKalle Valo break; 1858d5c65159SKalle Valo } 1859d5c65159SKalle Valo 1860d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1861d5c65159SKalle Valo return 0; 1862d5c65159SKalle Valo } 1863d5c65159SKalle Valo 1864d5c65159SKalle Valo static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1865d5c65159SKalle Valo enum hal_encrypt_type enctype) 1866d5c65159SKalle Valo { 1867d5c65159SKalle Valo switch (enctype) { 1868d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1869d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1870d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1871d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1872d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1873d5c65159SKalle Valo return 0; 1874d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1875d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1876d5c65159SKalle Valo return IEEE80211_TKIP_ICV_LEN; 1877d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1878d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1879d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1880d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1881d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1882d5c65159SKalle Valo break; 1883d5c65159SKalle Valo } 1884d5c65159SKalle Valo 1885d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1886d5c65159SKalle Valo return 0; 1887d5c65159SKalle Valo } 1888d5c65159SKalle Valo 1889d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1890d5c65159SKalle Valo struct sk_buff *msdu, 1891d5c65159SKalle Valo u8 *first_hdr, 1892d5c65159SKalle Valo enum hal_encrypt_type enctype, 1893d5c65159SKalle Valo struct ieee80211_rx_status *status) 1894d5c65159SKalle Valo { 1895acc79d98SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1896acc79d98SSriram R u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1897d5c65159SKalle Valo struct ieee80211_hdr *hdr; 1898d5c65159SKalle Valo size_t hdr_len; 1899d5c65159SKalle Valo u8 da[ETH_ALEN]; 1900d5c65159SKalle Valo u8 sa[ETH_ALEN]; 1901acc79d98SSriram R u16 qos_ctl = 0; 1902acc79d98SSriram R u8 *qos; 1903d5c65159SKalle Valo 1904acc79d98SSriram R /* copy SA & DA and pull decapped header */ 1905d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 1906acc79d98SSriram R hdr_len = ieee80211_hdrlen(hdr->frame_control); 1907d5c65159SKalle Valo ether_addr_copy(da, ieee80211_get_DA(hdr)); 1908d5c65159SKalle Valo ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1909d5c65159SKalle Valo skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1910d5c65159SKalle Valo 1911acc79d98SSriram R if (rxcb->is_first_msdu) { 1912acc79d98SSriram R /* original 802.11 header is valid for the first msdu 1913acc79d98SSriram R * hence we can reuse the same header 1914acc79d98SSriram R */ 1915d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 1916d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 1917d5c65159SKalle Valo 1918acc79d98SSriram R /* Each A-MSDU subframe will be reported as a separate MSDU, 1919acc79d98SSriram R * so strip the A-MSDU bit from QoS Ctl. 1920acc79d98SSriram R */ 1921acc79d98SSriram R if (ieee80211_is_data_qos(hdr->frame_control)) { 1922acc79d98SSriram R qos = ieee80211_get_qos_ctl(hdr); 1923acc79d98SSriram R qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 1924acc79d98SSriram R } 1925acc79d98SSriram R } else { 1926acc79d98SSriram R /* Rebuild qos header if this is a middle/last msdu */ 1927acc79d98SSriram R hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1928acc79d98SSriram R 1929acc79d98SSriram R /* Reset the order bit as the HT_Control header is stripped */ 1930acc79d98SSriram R hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1931acc79d98SSriram R 1932acc79d98SSriram R qos_ctl = rxcb->tid; 1933acc79d98SSriram R 1934acc79d98SSriram R if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(rxcb->rx_desc)) 1935acc79d98SSriram R qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 1936acc79d98SSriram R 1937acc79d98SSriram R /* TODO Add other QoS ctl fields when required */ 1938acc79d98SSriram R 1939acc79d98SSriram R /* copy decap header before overwriting for reuse below */ 1940acc79d98SSriram R memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 1941acc79d98SSriram R } 1942acc79d98SSriram R 1943d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 1944d5c65159SKalle Valo memcpy(skb_push(msdu, 1945d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 1946d5c65159SKalle Valo (void *)hdr + hdr_len, 1947d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 1948d5c65159SKalle Valo } 1949d5c65159SKalle Valo 1950acc79d98SSriram R if (!rxcb->is_first_msdu) { 1951acc79d98SSriram R memcpy(skb_push(msdu, 1952acc79d98SSriram R IEEE80211_QOS_CTL_LEN), &qos_ctl, 1953acc79d98SSriram R IEEE80211_QOS_CTL_LEN); 1954acc79d98SSriram R memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 1955acc79d98SSriram R return; 1956acc79d98SSriram R } 1957acc79d98SSriram R 1958d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 1959d5c65159SKalle Valo 1960d5c65159SKalle Valo /* original 802.11 header has a different DA and in 1961d5c65159SKalle Valo * case of 4addr it may also have different SA 1962d5c65159SKalle Valo */ 1963d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 1964d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 1965d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 1966d5c65159SKalle Valo } 1967d5c65159SKalle Valo 1968d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 1969d5c65159SKalle Valo enum hal_encrypt_type enctype, 1970d5c65159SKalle Valo struct ieee80211_rx_status *status, 1971d5c65159SKalle Valo bool decrypted) 1972d5c65159SKalle Valo { 1973d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1974d5c65159SKalle Valo struct ieee80211_hdr *hdr; 1975d5c65159SKalle Valo size_t hdr_len; 1976d5c65159SKalle Valo size_t crypto_len; 1977d5c65159SKalle Valo 1978d5c65159SKalle Valo if (!rxcb->is_first_msdu || 1979d5c65159SKalle Valo !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 1980d5c65159SKalle Valo WARN_ON_ONCE(1); 1981d5c65159SKalle Valo return; 1982d5c65159SKalle Valo } 1983d5c65159SKalle Valo 1984d5c65159SKalle Valo skb_trim(msdu, msdu->len - FCS_LEN); 1985d5c65159SKalle Valo 1986d5c65159SKalle Valo if (!decrypted) 1987d5c65159SKalle Valo return; 1988d5c65159SKalle Valo 1989d5c65159SKalle Valo hdr = (void *)msdu->data; 1990d5c65159SKalle Valo 1991d5c65159SKalle Valo /* Tail */ 1992d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 1993d5c65159SKalle Valo skb_trim(msdu, msdu->len - 1994d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 1995d5c65159SKalle Valo 1996d5c65159SKalle Valo skb_trim(msdu, msdu->len - 1997d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 1998d5c65159SKalle Valo } else { 1999d5c65159SKalle Valo /* MIC */ 2000d5c65159SKalle Valo if (status->flag & RX_FLAG_MIC_STRIPPED) 2001d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2002d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2003d5c65159SKalle Valo 2004d5c65159SKalle Valo /* ICV */ 2005d5c65159SKalle Valo if (status->flag & RX_FLAG_ICV_STRIPPED) 2006d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2007d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2008d5c65159SKalle Valo } 2009d5c65159SKalle Valo 2010d5c65159SKalle Valo /* MMIC */ 2011d5c65159SKalle Valo if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2012d5c65159SKalle Valo !ieee80211_has_morefrags(hdr->frame_control) && 2013d5c65159SKalle Valo enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2014d5c65159SKalle Valo skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2015d5c65159SKalle Valo 2016d5c65159SKalle Valo /* Head */ 2017d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 2018d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2019d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2020d5c65159SKalle Valo 2021d5c65159SKalle Valo memmove((void *)msdu->data + crypto_len, 2022d5c65159SKalle Valo (void *)msdu->data, hdr_len); 2023d5c65159SKalle Valo skb_pull(msdu, crypto_len); 2024d5c65159SKalle Valo } 2025d5c65159SKalle Valo } 2026d5c65159SKalle Valo 2027d5c65159SKalle Valo static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 2028d5c65159SKalle Valo struct sk_buff *msdu, 2029d5c65159SKalle Valo enum hal_encrypt_type enctype) 2030d5c65159SKalle Valo { 2031d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2032d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2033d5c65159SKalle Valo size_t hdr_len, crypto_len; 2034d5c65159SKalle Valo void *rfc1042; 2035d5c65159SKalle Valo bool is_amsdu; 2036d5c65159SKalle Valo 2037d5c65159SKalle Valo is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 2038d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(rxcb->rx_desc); 2039d5c65159SKalle Valo rfc1042 = hdr; 2040d5c65159SKalle Valo 2041d5c65159SKalle Valo if (rxcb->is_first_msdu) { 2042d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2043d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2044d5c65159SKalle Valo 2045d5c65159SKalle Valo rfc1042 += hdr_len + crypto_len; 2046d5c65159SKalle Valo } 2047d5c65159SKalle Valo 2048d5c65159SKalle Valo if (is_amsdu) 2049d5c65159SKalle Valo rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 2050d5c65159SKalle Valo 2051d5c65159SKalle Valo return rfc1042; 2052d5c65159SKalle Valo } 2053d5c65159SKalle Valo 2054d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 2055d5c65159SKalle Valo struct sk_buff *msdu, 2056d5c65159SKalle Valo u8 *first_hdr, 2057d5c65159SKalle Valo enum hal_encrypt_type enctype, 2058d5c65159SKalle Valo struct ieee80211_rx_status *status) 2059d5c65159SKalle Valo { 2060d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2061d5c65159SKalle Valo struct ethhdr *eth; 2062d5c65159SKalle Valo size_t hdr_len; 2063d5c65159SKalle Valo u8 da[ETH_ALEN]; 2064d5c65159SKalle Valo u8 sa[ETH_ALEN]; 2065d5c65159SKalle Valo void *rfc1042; 2066d5c65159SKalle Valo 2067d5c65159SKalle Valo rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 2068d5c65159SKalle Valo if (WARN_ON_ONCE(!rfc1042)) 2069d5c65159SKalle Valo return; 2070d5c65159SKalle Valo 2071d5c65159SKalle Valo /* pull decapped header and copy SA & DA */ 2072d5c65159SKalle Valo eth = (struct ethhdr *)msdu->data; 2073d5c65159SKalle Valo ether_addr_copy(da, eth->h_dest); 2074d5c65159SKalle Valo ether_addr_copy(sa, eth->h_source); 2075d5c65159SKalle Valo skb_pull(msdu, sizeof(struct ethhdr)); 2076d5c65159SKalle Valo 2077d5c65159SKalle Valo /* push rfc1042/llc/snap */ 2078d5c65159SKalle Valo memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 2079d5c65159SKalle Valo sizeof(struct ath11k_dp_rfc1042_hdr)); 2080d5c65159SKalle Valo 2081d5c65159SKalle Valo /* push original 802.11 header */ 2082d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 2083d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2084d5c65159SKalle Valo 2085d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2086d5c65159SKalle Valo memcpy(skb_push(msdu, 2087d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 2088d5c65159SKalle Valo (void *)hdr + hdr_len, 2089d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 2090d5c65159SKalle Valo } 2091d5c65159SKalle Valo 2092d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2093d5c65159SKalle Valo 2094d5c65159SKalle Valo /* original 802.11 header has a different DA and in 2095d5c65159SKalle Valo * case of 4addr it may also have different SA 2096d5c65159SKalle Valo */ 2097d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 2098d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 2099d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 2100d5c65159SKalle Valo } 2101d5c65159SKalle Valo 2102d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 2103d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2104d5c65159SKalle Valo enum hal_encrypt_type enctype, 2105d5c65159SKalle Valo struct ieee80211_rx_status *status, 2106d5c65159SKalle Valo bool decrypted) 2107d5c65159SKalle Valo { 2108d5c65159SKalle Valo u8 *first_hdr; 2109d5c65159SKalle Valo u8 decap; 2110d5c65159SKalle Valo 2111d5c65159SKalle Valo first_hdr = ath11k_dp_rx_h_80211_hdr(rx_desc); 2112243874c6SManikanta Pubbisetty decap = ath11k_dp_rx_h_msdu_start_decap_type(rx_desc); 2113d5c65159SKalle Valo 2114d5c65159SKalle Valo switch (decap) { 2115d5c65159SKalle Valo case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2116d5c65159SKalle Valo ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2117d5c65159SKalle Valo enctype, status); 2118d5c65159SKalle Valo break; 2119d5c65159SKalle Valo case DP_RX_DECAP_TYPE_RAW: 2120d5c65159SKalle Valo ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2121d5c65159SKalle Valo decrypted); 2122d5c65159SKalle Valo break; 2123d5c65159SKalle Valo case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2124acc79d98SSriram R /* TODO undecap support for middle/last msdu's of amsdu */ 2125d5c65159SKalle Valo ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2126d5c65159SKalle Valo enctype, status); 2127d5c65159SKalle Valo break; 2128d5c65159SKalle Valo case DP_RX_DECAP_TYPE_8023: 2129d5c65159SKalle Valo /* TODO: Handle undecap for these formats */ 2130d5c65159SKalle Valo break; 2131d5c65159SKalle Valo } 2132d5c65159SKalle Valo } 2133d5c65159SKalle Valo 2134d5c65159SKalle Valo static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2135acc79d98SSriram R struct sk_buff *msdu, 2136d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2137d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2138d5c65159SKalle Valo { 2139acc79d98SSriram R bool fill_crypto_hdr, mcast; 2140d5c65159SKalle Valo enum hal_encrypt_type enctype; 2141acc79d98SSriram R bool is_decrypted = false; 2142acc79d98SSriram R struct ieee80211_hdr *hdr; 2143acc79d98SSriram R struct ath11k_peer *peer; 2144d5c65159SKalle Valo u32 err_bitmap; 2145d5c65159SKalle Valo 2146acc79d98SSriram R hdr = (struct ieee80211_hdr *)msdu->data; 2147d5c65159SKalle Valo 21481441b2f2SManikanta Pubbisetty /* PN for multicast packets will be checked in mac80211 */ 2149acc79d98SSriram R 2150acc79d98SSriram R mcast = is_multicast_ether_addr(hdr->addr1); 2151acc79d98SSriram R fill_crypto_hdr = mcast; 21521441b2f2SManikanta Pubbisetty 2153acc79d98SSriram R spin_lock_bh(&ar->ab->base_lock); 2154acc79d98SSriram R peer = ath11k_peer_find_by_addr(ar->ab, hdr->addr2); 2155acc79d98SSriram R if (peer) { 2156acc79d98SSriram R if (mcast) 2157acc79d98SSriram R enctype = peer->sec_type_grp; 2158acc79d98SSriram R else 2159acc79d98SSriram R enctype = peer->sec_type; 2160acc79d98SSriram R } else { 2161acc79d98SSriram R enctype = HAL_ENCRYPT_TYPE_OPEN; 2162acc79d98SSriram R } 2163acc79d98SSriram R spin_unlock_bh(&ar->ab->base_lock); 2164d5c65159SKalle Valo 2165acc79d98SSriram R err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_desc); 2166aa2092a9SVenkateswara Naralasetty if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2167aa2092a9SVenkateswara Naralasetty is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc); 2168d5c65159SKalle Valo 2169acc79d98SSriram R /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2170d5c65159SKalle Valo rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2171d5c65159SKalle Valo RX_FLAG_MMIC_ERROR | 2172d5c65159SKalle Valo RX_FLAG_DECRYPTED | 2173d5c65159SKalle Valo RX_FLAG_IV_STRIPPED | 2174d5c65159SKalle Valo RX_FLAG_MMIC_STRIPPED); 2175d5c65159SKalle Valo 2176d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2177d5c65159SKalle Valo rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2178d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2179d5c65159SKalle Valo rx_status->flag |= RX_FLAG_MMIC_ERROR; 2180d5c65159SKalle Valo 21811441b2f2SManikanta Pubbisetty if (is_decrypted) { 21821441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 21831441b2f2SManikanta Pubbisetty 21841441b2f2SManikanta Pubbisetty if (fill_crypto_hdr) 21851441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_MIC_STRIPPED | 21861441b2f2SManikanta Pubbisetty RX_FLAG_ICV_STRIPPED; 21871441b2f2SManikanta Pubbisetty else 21881441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_IV_STRIPPED | 21891441b2f2SManikanta Pubbisetty RX_FLAG_PN_VALIDATED; 21901441b2f2SManikanta Pubbisetty } 2191d5c65159SKalle Valo 2192d5c65159SKalle Valo ath11k_dp_rx_h_csum_offload(msdu); 2193d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2194d5c65159SKalle Valo enctype, rx_status, is_decrypted); 21951441b2f2SManikanta Pubbisetty 21961441b2f2SManikanta Pubbisetty if (!is_decrypted || fill_crypto_hdr) 2197acc79d98SSriram R return; 21981441b2f2SManikanta Pubbisetty 21991441b2f2SManikanta Pubbisetty hdr = (void *)msdu->data; 22001441b2f2SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2201d5c65159SKalle Valo } 2202d5c65159SKalle Valo 2203d5c65159SKalle Valo static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2204d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2205d5c65159SKalle Valo { 2206d5c65159SKalle Valo struct ieee80211_supported_band *sband; 2207d5c65159SKalle Valo enum rx_msdu_start_pkt_type pkt_type; 2208d5c65159SKalle Valo u8 bw; 2209d5c65159SKalle Valo u8 rate_mcs, nss; 2210d5c65159SKalle Valo u8 sgi; 2211d5c65159SKalle Valo bool is_cck; 2212d5c65159SKalle Valo 2213d5c65159SKalle Valo pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(rx_desc); 2214d5c65159SKalle Valo bw = ath11k_dp_rx_h_msdu_start_rx_bw(rx_desc); 2215d5c65159SKalle Valo rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(rx_desc); 2216d5c65159SKalle Valo nss = ath11k_dp_rx_h_msdu_start_nss(rx_desc); 2217d5c65159SKalle Valo sgi = ath11k_dp_rx_h_msdu_start_sgi(rx_desc); 2218d5c65159SKalle Valo 2219d5c65159SKalle Valo switch (pkt_type) { 2220d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11A: 2221d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11B: 2222d5c65159SKalle Valo is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2223d5c65159SKalle Valo sband = &ar->mac.sbands[rx_status->band]; 2224d5c65159SKalle Valo rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2225d5c65159SKalle Valo is_cck); 2226d5c65159SKalle Valo break; 2227d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11N: 2228d5c65159SKalle Valo rx_status->encoding = RX_ENC_HT; 2229d5c65159SKalle Valo if (rate_mcs > ATH11K_HT_MCS_MAX) { 2230d5c65159SKalle Valo ath11k_warn(ar->ab, 2231d5c65159SKalle Valo "Received with invalid mcs in HT mode %d\n", 2232d5c65159SKalle Valo rate_mcs); 2233d5c65159SKalle Valo break; 2234d5c65159SKalle Valo } 2235d5c65159SKalle Valo rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2236d5c65159SKalle Valo if (sgi) 2237d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 223839e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2239d5c65159SKalle Valo break; 2240d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AC: 2241d5c65159SKalle Valo rx_status->encoding = RX_ENC_VHT; 2242d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2243d5c65159SKalle Valo if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2244d5c65159SKalle Valo ath11k_warn(ar->ab, 2245d5c65159SKalle Valo "Received with invalid mcs in VHT mode %d\n", 2246d5c65159SKalle Valo rate_mcs); 2247d5c65159SKalle Valo break; 2248d5c65159SKalle Valo } 2249d5c65159SKalle Valo rx_status->nss = nss; 2250d5c65159SKalle Valo if (sgi) 2251d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 225239e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2253d5c65159SKalle Valo break; 2254d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AX: 2255d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2256d5c65159SKalle Valo if (rate_mcs > ATH11K_HE_MCS_MAX) { 2257d5c65159SKalle Valo ath11k_warn(ar->ab, 2258d5c65159SKalle Valo "Received with invalid mcs in HE mode %d\n", 2259d5c65159SKalle Valo rate_mcs); 2260d5c65159SKalle Valo break; 2261d5c65159SKalle Valo } 2262d5c65159SKalle Valo rx_status->encoding = RX_ENC_HE; 2263d5c65159SKalle Valo rx_status->nss = nss; 22646a0c3702SJohn Crispin rx_status->he_gi = ath11k_he_gi_to_nl80211_he_gi(sgi); 226539e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2266d5c65159SKalle Valo break; 2267d5c65159SKalle Valo } 2268d5c65159SKalle Valo } 2269d5c65159SKalle Valo 2270d5c65159SKalle Valo static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2271d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2272d5c65159SKalle Valo { 2273d5c65159SKalle Valo u8 channel_num; 22745dcf42f8SPradeep Kumar Chitrapu u32 center_freq; 2275d5c65159SKalle Valo 2276d5c65159SKalle Valo rx_status->freq = 0; 2277d5c65159SKalle Valo rx_status->rate_idx = 0; 2278d5c65159SKalle Valo rx_status->nss = 0; 2279d5c65159SKalle Valo rx_status->encoding = RX_ENC_LEGACY; 2280d5c65159SKalle Valo rx_status->bw = RATE_INFO_BW_20; 2281d5c65159SKalle Valo 2282d5c65159SKalle Valo rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2283d5c65159SKalle Valo 2284d5c65159SKalle Valo channel_num = ath11k_dp_rx_h_msdu_start_freq(rx_desc); 22855dcf42f8SPradeep Kumar Chitrapu center_freq = ath11k_dp_rx_h_msdu_start_freq(rx_desc) >> 16; 2286d5c65159SKalle Valo 22875dcf42f8SPradeep Kumar Chitrapu if (center_freq >= 5935 && center_freq <= 7105) { 22885dcf42f8SPradeep Kumar Chitrapu rx_status->band = NL80211_BAND_6GHZ; 22895dcf42f8SPradeep Kumar Chitrapu } else if (channel_num >= 1 && channel_num <= 14) { 2290d5c65159SKalle Valo rx_status->band = NL80211_BAND_2GHZ; 2291d5c65159SKalle Valo } else if (channel_num >= 36 && channel_num <= 173) { 2292d5c65159SKalle Valo rx_status->band = NL80211_BAND_5GHZ; 2293d5c65159SKalle Valo } else { 2294de06b2f7SVenkateswara Naralasetty spin_lock_bh(&ar->data_lock); 2295de06b2f7SVenkateswara Naralasetty rx_status->band = ar->rx_channel->band; 2296de06b2f7SVenkateswara Naralasetty channel_num = 2297de06b2f7SVenkateswara Naralasetty ieee80211_frequency_to_channel(ar->rx_channel->center_freq); 2298de06b2f7SVenkateswara Naralasetty spin_unlock_bh(&ar->data_lock); 2299de06b2f7SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2300de06b2f7SVenkateswara Naralasetty rx_desc, sizeof(struct hal_rx_desc)); 2301d5c65159SKalle Valo } 2302d5c65159SKalle Valo 2303d5c65159SKalle Valo rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2304d5c65159SKalle Valo rx_status->band); 2305d5c65159SKalle Valo 2306d5c65159SKalle Valo ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2307d5c65159SKalle Valo } 2308d5c65159SKalle Valo 2309d5c65159SKalle Valo static char *ath11k_print_get_tid(struct ieee80211_hdr *hdr, char *out, 2310d5c65159SKalle Valo size_t size) 2311d5c65159SKalle Valo { 2312d5c65159SKalle Valo u8 *qc; 2313d5c65159SKalle Valo int tid; 2314d5c65159SKalle Valo 2315d5c65159SKalle Valo if (!ieee80211_is_data_qos(hdr->frame_control)) 2316d5c65159SKalle Valo return ""; 2317d5c65159SKalle Valo 2318d5c65159SKalle Valo qc = ieee80211_get_qos_ctl(hdr); 2319d5c65159SKalle Valo tid = *qc & IEEE80211_QOS_CTL_TID_MASK; 2320d5c65159SKalle Valo snprintf(out, size, "tid %d", tid); 2321d5c65159SKalle Valo 2322d5c65159SKalle Valo return out; 2323d5c65159SKalle Valo } 2324d5c65159SKalle Valo 2325d5c65159SKalle Valo static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 2326d5c65159SKalle Valo struct sk_buff *msdu) 2327d5c65159SKalle Valo { 2328e4eb7b5cSJohn Crispin static const struct ieee80211_radiotap_he known = { 232993634c61SJohn Crispin .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 233093634c61SJohn Crispin IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2331e4eb7b5cSJohn Crispin .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2332e4eb7b5cSJohn Crispin }; 2333d5c65159SKalle Valo struct ieee80211_rx_status *status; 2334d5c65159SKalle Valo struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data; 2335e4eb7b5cSJohn Crispin struct ieee80211_radiotap_he *he = NULL; 2336d5c65159SKalle Valo char tid[32]; 2337d5c65159SKalle Valo 2338d5c65159SKalle Valo status = IEEE80211_SKB_RXCB(msdu); 2339e4eb7b5cSJohn Crispin if (status->encoding == RX_ENC_HE) { 2340e4eb7b5cSJohn Crispin he = skb_push(msdu, sizeof(known)); 2341e4eb7b5cSJohn Crispin memcpy(he, &known, sizeof(known)); 2342e4eb7b5cSJohn Crispin status->flag |= RX_FLAG_RADIOTAP_HE; 2343e4eb7b5cSJohn Crispin } 2344d5c65159SKalle Valo 2345d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 2346d5c65159SKalle Valo "rx skb %pK len %u peer %pM %s %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2347d5c65159SKalle Valo msdu, 2348d5c65159SKalle Valo msdu->len, 2349d5c65159SKalle Valo ieee80211_get_SA(hdr), 2350d5c65159SKalle Valo ath11k_print_get_tid(hdr, tid, sizeof(tid)), 2351d5c65159SKalle Valo is_multicast_ether_addr(ieee80211_get_DA(hdr)) ? 2352d5c65159SKalle Valo "mcast" : "ucast", 2353d5c65159SKalle Valo (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4, 2354d5c65159SKalle Valo (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2355d5c65159SKalle Valo (status->encoding == RX_ENC_HT) ? "ht" : "", 2356d5c65159SKalle Valo (status->encoding == RX_ENC_VHT) ? "vht" : "", 2357d5c65159SKalle Valo (status->encoding == RX_ENC_HE) ? "he" : "", 2358d5c65159SKalle Valo (status->bw == RATE_INFO_BW_40) ? "40" : "", 2359d5c65159SKalle Valo (status->bw == RATE_INFO_BW_80) ? "80" : "", 2360d5c65159SKalle Valo (status->bw == RATE_INFO_BW_160) ? "160" : "", 2361d5c65159SKalle Valo status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2362d5c65159SKalle Valo status->rate_idx, 2363d5c65159SKalle Valo status->nss, 2364d5c65159SKalle Valo status->freq, 2365d5c65159SKalle Valo status->band, status->flag, 2366d5c65159SKalle Valo !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2367d5c65159SKalle Valo !!(status->flag & RX_FLAG_MMIC_ERROR), 2368d5c65159SKalle Valo !!(status->flag & RX_FLAG_AMSDU_MORE)); 2369d5c65159SKalle Valo 2370aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ", 2371aa2092a9SVenkateswara Naralasetty msdu->data, msdu->len); 2372aa2092a9SVenkateswara Naralasetty 2373d5c65159SKalle Valo /* TODO: trace rx packet */ 2374d5c65159SKalle Valo 2375d5c65159SKalle Valo ieee80211_rx_napi(ar->hw, NULL, msdu, napi); 2376d5c65159SKalle Valo } 2377d5c65159SKalle Valo 2378acc79d98SSriram R static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2379acc79d98SSriram R struct sk_buff *msdu, 2380acc79d98SSriram R struct sk_buff_head *msdu_list) 2381d5c65159SKalle Valo { 2382acc79d98SSriram R struct hal_rx_desc *rx_desc, *lrx_desc; 2383acc79d98SSriram R struct ieee80211_rx_status rx_status = {0}; 2384d5c65159SKalle Valo struct ieee80211_rx_status *status; 2385acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2386acc79d98SSriram R struct ieee80211_hdr *hdr; 2387acc79d98SSriram R struct sk_buff *last_buf; 2388acc79d98SSriram R u8 l3_pad_bytes; 2389d7d43782STamizh Chelvam u8 *hdr_status; 2390acc79d98SSriram R u16 msdu_len; 2391acc79d98SSriram R int ret; 2392d5c65159SKalle Valo 2393acc79d98SSriram R last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2394acc79d98SSriram R if (!last_buf) { 2395acc79d98SSriram R ath11k_warn(ar->ab, 2396acc79d98SSriram R "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2397acc79d98SSriram R ret = -EIO; 2398acc79d98SSriram R goto free_out; 2399d5c65159SKalle Valo } 2400acc79d98SSriram R 2401acc79d98SSriram R rx_desc = (struct hal_rx_desc *)msdu->data; 2402acc79d98SSriram R lrx_desc = (struct hal_rx_desc *)last_buf->data; 2403acc79d98SSriram R if (!ath11k_dp_rx_h_attn_msdu_done(lrx_desc)) { 2404acc79d98SSriram R ath11k_warn(ar->ab, "msdu_done bit in attention is not set\n"); 2405acc79d98SSriram R ret = -EIO; 2406acc79d98SSriram R goto free_out; 2407acc79d98SSriram R } 2408acc79d98SSriram R 2409acc79d98SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 2410acc79d98SSriram R rxcb->rx_desc = rx_desc; 2411acc79d98SSriram R msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc); 2412acc79d98SSriram R l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(lrx_desc); 2413acc79d98SSriram R 2414acc79d98SSriram R if (rxcb->is_frag) { 2415acc79d98SSriram R skb_pull(msdu, HAL_RX_DESC_SIZE); 2416acc79d98SSriram R } else if (!rxcb->is_continuation) { 2417acc79d98SSriram R if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) { 2418d7d43782STamizh Chelvam hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc); 2419acc79d98SSriram R ret = -EINVAL; 2420acc79d98SSriram R ath11k_warn(ar->ab, "invalid msdu len %u\n", msdu_len); 2421d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2422d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 2423d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2424d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 2425acc79d98SSriram R goto free_out; 2426acc79d98SSriram R } 2427acc79d98SSriram R skb_put(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes + msdu_len); 2428acc79d98SSriram R skb_pull(msdu, HAL_RX_DESC_SIZE + l3_pad_bytes); 2429acc79d98SSriram R } else { 2430acc79d98SSriram R ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2431acc79d98SSriram R msdu, last_buf, 2432acc79d98SSriram R l3_pad_bytes, msdu_len); 2433acc79d98SSriram R if (ret) { 2434acc79d98SSriram R ath11k_warn(ar->ab, 2435acc79d98SSriram R "failed to coalesce msdu rx buffer%d\n", ret); 2436acc79d98SSriram R goto free_out; 2437acc79d98SSriram R } 2438acc79d98SSriram R } 2439acc79d98SSriram R 2440acc79d98SSriram R hdr = (struct ieee80211_hdr *)msdu->data; 2441acc79d98SSriram R 2442acc79d98SSriram R /* Process only data frames */ 2443acc79d98SSriram R if (!ieee80211_is_data(hdr->frame_control)) 2444acc79d98SSriram R return -EINVAL; 2445acc79d98SSriram R 2446acc79d98SSriram R ath11k_dp_rx_h_ppdu(ar, rx_desc, &rx_status); 2447acc79d98SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, &rx_status); 2448acc79d98SSriram R 2449acc79d98SSriram R rx_status.flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2450d5c65159SKalle Valo 2451d5c65159SKalle Valo status = IEEE80211_SKB_RXCB(msdu); 2452acc79d98SSriram R *status = rx_status; 2453acc79d98SSriram R return 0; 2454acc79d98SSriram R 2455acc79d98SSriram R free_out: 2456acc79d98SSriram R return ret; 2457d5c65159SKalle Valo } 2458d5c65159SKalle Valo 2459acc79d98SSriram R static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2460d5c65159SKalle Valo struct napi_struct *napi, 2461acc79d98SSriram R struct sk_buff_head *msdu_list, 2462acc79d98SSriram R int *quota, int ring_id) 2463d5c65159SKalle Valo { 2464acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2465d5c65159SKalle Valo struct sk_buff *msdu; 2466acc79d98SSriram R struct ath11k *ar; 2467acc79d98SSriram R u8 mac_id; 2468acc79d98SSriram R int ret; 2469d5c65159SKalle Valo 2470acc79d98SSriram R if (skb_queue_empty(msdu_list)) 2471d5c65159SKalle Valo return; 2472d5c65159SKalle Valo 2473d5c65159SKalle Valo rcu_read_lock(); 2474d5c65159SKalle Valo 2475acc79d98SSriram R while (*quota && (msdu = __skb_dequeue(msdu_list))) { 2476acc79d98SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 2477acc79d98SSriram R mac_id = rxcb->mac_id; 2478acc79d98SSriram R ar = ab->pdevs[mac_id].ar; 2479acc79d98SSriram R if (!rcu_dereference(ab->pdevs_active[mac_id])) { 2480acc79d98SSriram R dev_kfree_skb_any(msdu); 2481acc79d98SSriram R continue; 2482acc79d98SSriram R } 2483acc79d98SSriram R 2484acc79d98SSriram R if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 2485acc79d98SSriram R dev_kfree_skb_any(msdu); 2486acc79d98SSriram R continue; 2487acc79d98SSriram R } 2488acc79d98SSriram R 2489acc79d98SSriram R ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list); 2490acc79d98SSriram R if (ret) { 2491acc79d98SSriram R ath11k_dbg(ab, ATH11K_DBG_DATA, 2492acc79d98SSriram R "Unable to process msdu %d", ret); 2493d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2494d5c65159SKalle Valo continue; 2495d5c65159SKalle Valo } 2496d5c65159SKalle Valo 2497d5c65159SKalle Valo ath11k_dp_rx_deliver_msdu(ar, napi, msdu); 2498d5c65159SKalle Valo (*quota)--; 2499d5c65159SKalle Valo } 2500acc79d98SSriram R 2501d5c65159SKalle Valo rcu_read_unlock(); 2502d5c65159SKalle Valo } 2503d5c65159SKalle Valo 2504acc79d98SSriram R int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2505acc79d98SSriram R struct napi_struct *napi, int budget) 2506d5c65159SKalle Valo { 2507acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 2508acc79d98SSriram R struct dp_rxdma_ring *rx_ring; 2509acc79d98SSriram R int num_buffs_reaped[MAX_RADIOS] = {0}; 2510acc79d98SSriram R struct sk_buff_head msdu_list; 2511acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2512acc79d98SSriram R int total_msdu_reaped = 0; 2513d5c65159SKalle Valo struct hal_srng *srng; 2514d5c65159SKalle Valo struct sk_buff *msdu; 2515d5c65159SKalle Valo int quota = budget; 2516d5c65159SKalle Valo bool done = false; 2517acc79d98SSriram R int buf_id, mac_id; 2518acc79d98SSriram R struct ath11k *ar; 2519acc79d98SSriram R u32 *rx_desc; 2520acc79d98SSriram R int i; 2521d5c65159SKalle Valo 2522d5c65159SKalle Valo __skb_queue_head_init(&msdu_list); 2523d5c65159SKalle Valo 2524acc79d98SSriram R srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2525d5c65159SKalle Valo 2526d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2527d5c65159SKalle Valo 2528d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2529d5c65159SKalle Valo 2530d5c65159SKalle Valo try_again: 2531d5c65159SKalle Valo while ((rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 25327395fb49SManikanta Pubbisetty struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc; 2533293cb583SJohn Crispin enum hal_reo_dest_ring_push_reason push_reason; 2534293cb583SJohn Crispin u32 cookie; 2535d5c65159SKalle Valo 2536293cb583SJohn Crispin cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 25377395fb49SManikanta Pubbisetty desc.buf_addr_info.info1); 2538d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2539293cb583SJohn Crispin cookie); 2540acc79d98SSriram R mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2541acc79d98SSriram R 2542acc79d98SSriram R ar = ab->pdevs[mac_id].ar; 2543acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2544d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2545d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 2546d5c65159SKalle Valo if (!msdu) { 2547d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2548d5c65159SKalle Valo buf_id); 2549d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2550d5c65159SKalle Valo continue; 2551d5c65159SKalle Valo } 2552d5c65159SKalle Valo 2553d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2554d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2555d5c65159SKalle Valo 2556d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 2557d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 2558d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 2559d5c65159SKalle Valo DMA_FROM_DEVICE); 2560d5c65159SKalle Valo 2561acc79d98SSriram R num_buffs_reaped[mac_id]++; 2562acc79d98SSriram R total_msdu_reaped++; 2563d5c65159SKalle Valo 2564293cb583SJohn Crispin push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 25657395fb49SManikanta Pubbisetty desc.info0); 2566293cb583SJohn Crispin if (push_reason != 2567d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2568d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2569acc79d98SSriram R ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2570d5c65159SKalle Valo continue; 2571d5c65159SKalle Valo } 2572d5c65159SKalle Valo 25737395fb49SManikanta Pubbisetty rxcb->is_first_msdu = !!(desc.rx_msdu_info.info0 & 2574293cb583SJohn Crispin RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 25757395fb49SManikanta Pubbisetty rxcb->is_last_msdu = !!(desc.rx_msdu_info.info0 & 2576293cb583SJohn Crispin RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 25777395fb49SManikanta Pubbisetty rxcb->is_continuation = !!(desc.rx_msdu_info.info0 & 2578293cb583SJohn Crispin RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2579d5c65159SKalle Valo rxcb->mac_id = mac_id; 2580acc79d98SSriram R rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 25817395fb49SManikanta Pubbisetty desc.info0); 2582acc79d98SSriram R 2583d5c65159SKalle Valo __skb_queue_tail(&msdu_list, msdu); 2584d5c65159SKalle Valo 2585acc79d98SSriram R if (total_msdu_reaped >= quota && !rxcb->is_continuation) { 2586d5c65159SKalle Valo done = true; 2587d5c65159SKalle Valo break; 2588d5c65159SKalle Valo } 2589d5c65159SKalle Valo } 2590d5c65159SKalle Valo 2591d5c65159SKalle Valo /* Hw might have updated the head pointer after we cached it. 2592d5c65159SKalle Valo * In this case, even though there are entries in the ring we'll 2593d5c65159SKalle Valo * get rx_desc NULL. Give the read another try with updated cached 2594d5c65159SKalle Valo * head pointer so that we can reap complete MPDU in the current 2595d5c65159SKalle Valo * rx processing. 2596d5c65159SKalle Valo */ 2597d5c65159SKalle Valo if (!done && ath11k_hal_srng_dst_num_free(ab, srng, true)) { 2598d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2599d5c65159SKalle Valo goto try_again; 2600d5c65159SKalle Valo } 2601d5c65159SKalle Valo 2602d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2603d5c65159SKalle Valo 2604d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2605d5c65159SKalle Valo 2606acc79d98SSriram R if (!total_msdu_reaped) 2607d5c65159SKalle Valo goto exit; 2608d5c65159SKalle Valo 2609acc79d98SSriram R for (i = 0; i < ab->num_radios; i++) { 2610acc79d98SSriram R if (!num_buffs_reaped[i]) 2611d5c65159SKalle Valo continue; 2612acc79d98SSriram R 2613acc79d98SSriram R ar = ab->pdevs[i].ar; 2614acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2615acc79d98SSriram R 2616acc79d98SSriram R ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 261787e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 2618d5c65159SKalle Valo } 2619d5c65159SKalle Valo 2620acc79d98SSriram R ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2621acc79d98SSriram R "a, ring_id); 2622d5c65159SKalle Valo 2623d5c65159SKalle Valo exit: 2624d5c65159SKalle Valo return budget - quota; 2625d5c65159SKalle Valo } 2626d5c65159SKalle Valo 2627d5c65159SKalle Valo static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2628d5c65159SKalle Valo struct hal_rx_mon_ppdu_info *ppdu_info) 2629d5c65159SKalle Valo { 2630d5c65159SKalle Valo struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2631d5c65159SKalle Valo u32 num_msdu; 2632d5c65159SKalle Valo 2633d5c65159SKalle Valo if (!rx_stats) 2634d5c65159SKalle Valo return; 2635d5c65159SKalle Valo 2636d5c65159SKalle Valo num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2637d5c65159SKalle Valo ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2638d5c65159SKalle Valo 2639d5c65159SKalle Valo rx_stats->num_msdu += num_msdu; 2640d5c65159SKalle Valo rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2641d5c65159SKalle Valo ppdu_info->tcp_ack_msdu_count; 2642d5c65159SKalle Valo rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2643d5c65159SKalle Valo rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2644d5c65159SKalle Valo 2645d5c65159SKalle Valo if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2646d5c65159SKalle Valo ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2647d5c65159SKalle Valo ppdu_info->nss = 1; 2648d5c65159SKalle Valo ppdu_info->mcs = HAL_RX_MAX_MCS; 2649d5c65159SKalle Valo ppdu_info->tid = IEEE80211_NUM_TIDS; 2650d5c65159SKalle Valo } 2651d5c65159SKalle Valo 2652d5c65159SKalle Valo if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2653d5c65159SKalle Valo rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2654d5c65159SKalle Valo 2655d5c65159SKalle Valo if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2656d5c65159SKalle Valo rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2657d5c65159SKalle Valo 2658d5c65159SKalle Valo if (ppdu_info->gi < HAL_RX_GI_MAX) 2659d5c65159SKalle Valo rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2660d5c65159SKalle Valo 2661d5c65159SKalle Valo if (ppdu_info->bw < HAL_RX_BW_MAX) 2662d5c65159SKalle Valo rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2663d5c65159SKalle Valo 2664d5c65159SKalle Valo if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2665d5c65159SKalle Valo rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2666d5c65159SKalle Valo 2667d5c65159SKalle Valo if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2668d5c65159SKalle Valo rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2669d5c65159SKalle Valo 2670d5c65159SKalle Valo if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2671d5c65159SKalle Valo rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2672d5c65159SKalle Valo 2673d5c65159SKalle Valo if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2674d5c65159SKalle Valo rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2675d5c65159SKalle Valo 2676d5c65159SKalle Valo if (ppdu_info->is_stbc) 2677d5c65159SKalle Valo rx_stats->stbc_count += num_msdu; 2678d5c65159SKalle Valo 2679d5c65159SKalle Valo if (ppdu_info->beamformed) 2680d5c65159SKalle Valo rx_stats->beamformed_count += num_msdu; 2681d5c65159SKalle Valo 2682d5c65159SKalle Valo if (ppdu_info->num_mpdu_fcs_ok > 1) 2683d5c65159SKalle Valo rx_stats->ampdu_msdu_count += num_msdu; 2684d5c65159SKalle Valo else 2685d5c65159SKalle Valo rx_stats->non_ampdu_msdu_count += num_msdu; 2686d5c65159SKalle Valo 2687d5c65159SKalle Valo rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2688d5c65159SKalle Valo rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 26896a0c3702SJohn Crispin rx_stats->dcm_count += ppdu_info->dcm; 26906a0c3702SJohn Crispin rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2691d5c65159SKalle Valo 2692d5c65159SKalle Valo arsta->rssi_comb = ppdu_info->rssi_comb; 2693d5c65159SKalle Valo rx_stats->rx_duration += ppdu_info->rx_duration; 2694d5c65159SKalle Valo arsta->rx_duration = rx_stats->rx_duration; 2695d5c65159SKalle Valo } 2696d5c65159SKalle Valo 2697d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2698d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 269987e8497aSGovind Singh int *buf_id) 2700d5c65159SKalle Valo { 2701d5c65159SKalle Valo struct sk_buff *skb; 2702d5c65159SKalle Valo dma_addr_t paddr; 2703d5c65159SKalle Valo 2704d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2705d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 2706d5c65159SKalle Valo 2707d5c65159SKalle Valo if (!skb) 2708d5c65159SKalle Valo goto fail_alloc_skb; 2709d5c65159SKalle Valo 2710d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 2711d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 2712d5c65159SKalle Valo skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2713d5c65159SKalle Valo skb->data); 2714d5c65159SKalle Valo } 2715d5c65159SKalle Valo 2716d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 2717d5c65159SKalle Valo skb->len + skb_tailroom(skb), 2718d5c65159SKalle Valo DMA_BIDIRECTIONAL); 2719d5c65159SKalle Valo if (unlikely(dma_mapping_error(ab->dev, paddr))) 2720d5c65159SKalle Valo goto fail_free_skb; 2721d5c65159SKalle Valo 2722d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2723d5c65159SKalle Valo *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 272487e8497aSGovind Singh rx_ring->bufs_max, GFP_ATOMIC); 2725d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2726d5c65159SKalle Valo if (*buf_id < 0) 2727d5c65159SKalle Valo goto fail_dma_unmap; 2728d5c65159SKalle Valo 2729d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 2730d5c65159SKalle Valo return skb; 2731d5c65159SKalle Valo 2732d5c65159SKalle Valo fail_dma_unmap: 2733d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2734d5c65159SKalle Valo DMA_BIDIRECTIONAL); 2735d5c65159SKalle Valo fail_free_skb: 2736d5c65159SKalle Valo dev_kfree_skb_any(skb); 2737d5c65159SKalle Valo fail_alloc_skb: 2738d5c65159SKalle Valo return NULL; 2739d5c65159SKalle Valo } 2740d5c65159SKalle Valo 2741d5c65159SKalle Valo int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2742d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 2743d5c65159SKalle Valo int req_entries, 274487e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 2745d5c65159SKalle Valo { 2746d5c65159SKalle Valo struct hal_srng *srng; 2747d5c65159SKalle Valo u32 *desc; 2748d5c65159SKalle Valo struct sk_buff *skb; 2749d5c65159SKalle Valo int num_free; 2750d5c65159SKalle Valo int num_remain; 2751d5c65159SKalle Valo int buf_id; 2752d5c65159SKalle Valo u32 cookie; 2753d5c65159SKalle Valo dma_addr_t paddr; 2754d5c65159SKalle Valo 2755d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 2756d5c65159SKalle Valo 2757d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2758d5c65159SKalle Valo 2759d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2760d5c65159SKalle Valo 2761d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2762d5c65159SKalle Valo 2763d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2764d5c65159SKalle Valo 2765d5c65159SKalle Valo req_entries = min(num_free, req_entries); 2766d5c65159SKalle Valo num_remain = req_entries; 2767d5c65159SKalle Valo 2768d5c65159SKalle Valo while (num_remain > 0) { 2769d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 277087e8497aSGovind Singh &buf_id); 2771d5c65159SKalle Valo if (!skb) 2772d5c65159SKalle Valo break; 2773d5c65159SKalle Valo paddr = ATH11K_SKB_RXCB(skb)->paddr; 2774d5c65159SKalle Valo 2775d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2776d5c65159SKalle Valo if (!desc) 2777d5c65159SKalle Valo goto fail_desc_get; 2778d5c65159SKalle Valo 2779d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2780d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2781d5c65159SKalle Valo 2782d5c65159SKalle Valo num_remain--; 2783d5c65159SKalle Valo 2784d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2785d5c65159SKalle Valo } 2786d5c65159SKalle Valo 2787d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2788d5c65159SKalle Valo 2789d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2790d5c65159SKalle Valo 2791d5c65159SKalle Valo return req_entries - num_remain; 2792d5c65159SKalle Valo 2793d5c65159SKalle Valo fail_desc_get: 2794d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2795d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2796d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2797d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2798d5c65159SKalle Valo DMA_BIDIRECTIONAL); 2799d5c65159SKalle Valo dev_kfree_skb_any(skb); 2800d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2801d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2802d5c65159SKalle Valo 2803d5c65159SKalle Valo return req_entries - num_remain; 2804d5c65159SKalle Valo } 2805d5c65159SKalle Valo 2806d5c65159SKalle Valo static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2807d5c65159SKalle Valo int *budget, struct sk_buff_head *skb_list) 2808d5c65159SKalle Valo { 28094152e420SCarl Huang struct ath11k *ar; 28104152e420SCarl Huang struct ath11k_pdev_dp *dp; 28114152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 2812d5c65159SKalle Valo struct hal_srng *srng; 2813d5c65159SKalle Valo void *rx_mon_status_desc; 2814d5c65159SKalle Valo struct sk_buff *skb; 2815d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 2816d5c65159SKalle Valo struct hal_tlv_hdr *tlv; 2817d5c65159SKalle Valo u32 cookie; 28184152e420SCarl Huang int buf_id, srng_id; 2819d5c65159SKalle Valo dma_addr_t paddr; 2820d5c65159SKalle Valo u8 rbm; 2821d5c65159SKalle Valo int num_buffs_reaped = 0; 2822d5c65159SKalle Valo 28234152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 28244152e420SCarl Huang dp = &ar->dp; 28254152e420SCarl Huang srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id); 28264152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 28274152e420SCarl Huang 2828d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2829d5c65159SKalle Valo 2830d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2831d5c65159SKalle Valo 2832d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2833d5c65159SKalle Valo while (*budget) { 2834d5c65159SKalle Valo *budget -= 1; 2835d5c65159SKalle Valo rx_mon_status_desc = 2836d5c65159SKalle Valo ath11k_hal_srng_src_peek(ab, srng); 2837d5c65159SKalle Valo if (!rx_mon_status_desc) 2838d5c65159SKalle Valo break; 2839d5c65159SKalle Valo 2840d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 2841d5c65159SKalle Valo &cookie, &rbm); 2842d5c65159SKalle Valo if (paddr) { 2843d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 2844d5c65159SKalle Valo 2845d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2846d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 2847d5c65159SKalle Valo if (!skb) { 2848d5c65159SKalle Valo ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 2849d5c65159SKalle Valo buf_id); 2850d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 285132a2be49SMiles Hu goto move_next; 2852d5c65159SKalle Valo } 2853d5c65159SKalle Valo 2854d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2855d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2856d5c65159SKalle Valo 2857d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 2858d5c65159SKalle Valo 2859d5c65159SKalle Valo dma_sync_single_for_cpu(ab->dev, rxcb->paddr, 2860d5c65159SKalle Valo skb->len + skb_tailroom(skb), 2861d5c65159SKalle Valo DMA_FROM_DEVICE); 2862d5c65159SKalle Valo 2863d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 2864d5c65159SKalle Valo skb->len + skb_tailroom(skb), 2865d5c65159SKalle Valo DMA_BIDIRECTIONAL); 2866d5c65159SKalle Valo 2867d5c65159SKalle Valo tlv = (struct hal_tlv_hdr *)skb->data; 2868d5c65159SKalle Valo if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 2869d5c65159SKalle Valo HAL_RX_STATUS_BUFFER_DONE) { 287032a2be49SMiles Hu ath11k_warn(ab, "mon status DONE not set %lx\n", 287132a2be49SMiles Hu FIELD_GET(HAL_TLV_HDR_TAG, 287232a2be49SMiles Hu tlv->tl)); 287332a2be49SMiles Hu dev_kfree_skb_any(skb); 287432a2be49SMiles Hu goto move_next; 2875d5c65159SKalle Valo } 2876d5c65159SKalle Valo 2877d5c65159SKalle Valo __skb_queue_tail(skb_list, skb); 2878d5c65159SKalle Valo } 287932a2be49SMiles Hu move_next: 2880d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 288187e8497aSGovind Singh &buf_id); 2882d5c65159SKalle Valo 2883d5c65159SKalle Valo if (!skb) { 2884d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 2885d5c65159SKalle Valo HAL_RX_BUF_RBM_SW3_BM); 2886d5c65159SKalle Valo num_buffs_reaped++; 2887d5c65159SKalle Valo break; 2888d5c65159SKalle Valo } 2889d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 2890d5c65159SKalle Valo 2891d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2892d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2893d5c65159SKalle Valo 2894d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 2895d5c65159SKalle Valo cookie, HAL_RX_BUF_RBM_SW3_BM); 2896d5c65159SKalle Valo ath11k_hal_srng_src_get_next_entry(ab, srng); 2897d5c65159SKalle Valo num_buffs_reaped++; 2898d5c65159SKalle Valo } 2899d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2900d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2901d5c65159SKalle Valo 2902d5c65159SKalle Valo return num_buffs_reaped; 2903d5c65159SKalle Valo } 2904d5c65159SKalle Valo 2905d5c65159SKalle Valo int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 2906d5c65159SKalle Valo struct napi_struct *napi, int budget) 2907d5c65159SKalle Valo { 29084152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 2909d5c65159SKalle Valo enum hal_rx_mon_status hal_status; 2910d5c65159SKalle Valo struct sk_buff *skb; 2911d5c65159SKalle Valo struct sk_buff_head skb_list; 2912d5c65159SKalle Valo struct hal_rx_mon_ppdu_info ppdu_info; 2913d5c65159SKalle Valo struct ath11k_peer *peer; 2914d5c65159SKalle Valo struct ath11k_sta *arsta; 2915d5c65159SKalle Valo int num_buffs_reaped = 0; 2916d5c65159SKalle Valo 2917d5c65159SKalle Valo __skb_queue_head_init(&skb_list); 2918d5c65159SKalle Valo 2919d5c65159SKalle Valo num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 2920d5c65159SKalle Valo &skb_list); 2921d5c65159SKalle Valo if (!num_buffs_reaped) 2922d5c65159SKalle Valo goto exit; 2923d5c65159SKalle Valo 2924d5c65159SKalle Valo while ((skb = __skb_dequeue(&skb_list))) { 2925d5c65159SKalle Valo memset(&ppdu_info, 0, sizeof(ppdu_info)); 2926d5c65159SKalle Valo ppdu_info.peer_id = HAL_INVALID_PEERID; 2927d5c65159SKalle Valo 2928cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) 2929d5c65159SKalle Valo trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE); 2930d5c65159SKalle Valo 2931d5c65159SKalle Valo hal_status = ath11k_hal_rx_parse_mon_status(ab, &ppdu_info, skb); 2932d5c65159SKalle Valo 2933d5c65159SKalle Valo if (ppdu_info.peer_id == HAL_INVALID_PEERID || 2934d5c65159SKalle Valo hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 2935d5c65159SKalle Valo dev_kfree_skb_any(skb); 2936d5c65159SKalle Valo continue; 2937d5c65159SKalle Valo } 2938d5c65159SKalle Valo 2939d5c65159SKalle Valo rcu_read_lock(); 2940d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 2941d5c65159SKalle Valo peer = ath11k_peer_find_by_id(ab, ppdu_info.peer_id); 2942d5c65159SKalle Valo 2943d5c65159SKalle Valo if (!peer || !peer->sta) { 29442dab7d22SJohn Crispin ath11k_dbg(ab, ATH11K_DBG_DATA, 29452dab7d22SJohn Crispin "failed to find the peer with peer_id %d\n", 2946d5c65159SKalle Valo ppdu_info.peer_id); 2947d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 2948d5c65159SKalle Valo rcu_read_unlock(); 2949d5c65159SKalle Valo dev_kfree_skb_any(skb); 2950d5c65159SKalle Valo continue; 2951d5c65159SKalle Valo } 2952d5c65159SKalle Valo 2953d5c65159SKalle Valo arsta = (struct ath11k_sta *)peer->sta->drv_priv; 2954d5c65159SKalle Valo ath11k_dp_rx_update_peer_stats(arsta, &ppdu_info); 2955d5c65159SKalle Valo 2956cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) 2957d5c65159SKalle Valo trace_ath11k_htt_rxdesc(ar, skb->data, DP_RX_BUFFER_SIZE); 2958d5c65159SKalle Valo 2959d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 2960d5c65159SKalle Valo rcu_read_unlock(); 2961d5c65159SKalle Valo 2962d5c65159SKalle Valo dev_kfree_skb_any(skb); 2963d5c65159SKalle Valo } 2964d5c65159SKalle Valo exit: 2965d5c65159SKalle Valo return num_buffs_reaped; 2966d5c65159SKalle Valo } 2967d5c65159SKalle Valo 2968243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 2969d5c65159SKalle Valo { 2970243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2971d5c65159SKalle Valo 2972243874c6SManikanta Pubbisetty spin_lock_bh(&rx_tid->ab->base_lock); 2973243874c6SManikanta Pubbisetty if (rx_tid->last_frag_no && 2974243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2975243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 2976243874c6SManikanta Pubbisetty return; 2977243874c6SManikanta Pubbisetty } 2978243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 2979243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 2980d5c65159SKalle Valo } 2981d5c65159SKalle Valo 2982243874c6SManikanta Pubbisetty int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 2983243874c6SManikanta Pubbisetty { 2984243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 2985243874c6SManikanta Pubbisetty struct crypto_shash *tfm; 2986243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 2987243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 2988243874c6SManikanta Pubbisetty int i; 2989d5c65159SKalle Valo 2990243874c6SManikanta Pubbisetty tfm = crypto_alloc_shash("michael_mic", 0, 0); 2991243874c6SManikanta Pubbisetty if (IS_ERR(tfm)) 2992243874c6SManikanta Pubbisetty return PTR_ERR(tfm); 2993d5c65159SKalle Valo 2994243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 2995d5c65159SKalle Valo 2996243874c6SManikanta Pubbisetty peer = ath11k_peer_find(ab, vdev_id, peer_mac); 2997243874c6SManikanta Pubbisetty if (!peer) { 2998243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 2999243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3000243874c6SManikanta Pubbisetty return -ENOENT; 3001243874c6SManikanta Pubbisetty } 3002243874c6SManikanta Pubbisetty 3003243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3004243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 3005243874c6SManikanta Pubbisetty rx_tid->ab = ab; 3006243874c6SManikanta Pubbisetty timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 3007243874c6SManikanta Pubbisetty skb_queue_head_init(&rx_tid->rx_frags); 3008243874c6SManikanta Pubbisetty } 3009243874c6SManikanta Pubbisetty 3010243874c6SManikanta Pubbisetty peer->tfm_mmic = tfm; 3011243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3012243874c6SManikanta Pubbisetty 3013243874c6SManikanta Pubbisetty return 0; 3014243874c6SManikanta Pubbisetty } 3015243874c6SManikanta Pubbisetty 3016243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3017243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr, u8 *data, 3018243874c6SManikanta Pubbisetty size_t data_len, u8 *mic) 3019243874c6SManikanta Pubbisetty { 3020243874c6SManikanta Pubbisetty SHASH_DESC_ON_STACK(desc, tfm); 3021243874c6SManikanta Pubbisetty u8 mic_hdr[16] = {0}; 3022243874c6SManikanta Pubbisetty u8 tid = 0; 3023243874c6SManikanta Pubbisetty int ret; 3024243874c6SManikanta Pubbisetty 3025243874c6SManikanta Pubbisetty if (!tfm) 3026243874c6SManikanta Pubbisetty return -EINVAL; 3027243874c6SManikanta Pubbisetty 3028243874c6SManikanta Pubbisetty desc->tfm = tfm; 3029243874c6SManikanta Pubbisetty 3030243874c6SManikanta Pubbisetty ret = crypto_shash_setkey(tfm, key, 8); 3031243874c6SManikanta Pubbisetty if (ret) 3032243874c6SManikanta Pubbisetty goto out; 3033243874c6SManikanta Pubbisetty 3034243874c6SManikanta Pubbisetty ret = crypto_shash_init(desc); 3035243874c6SManikanta Pubbisetty if (ret) 3036243874c6SManikanta Pubbisetty goto out; 3037243874c6SManikanta Pubbisetty 3038243874c6SManikanta Pubbisetty /* TKIP MIC header */ 3039243874c6SManikanta Pubbisetty memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3040243874c6SManikanta Pubbisetty memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3041243874c6SManikanta Pubbisetty if (ieee80211_is_data_qos(hdr->frame_control)) 3042243874c6SManikanta Pubbisetty tid = ieee80211_get_tid(hdr); 3043243874c6SManikanta Pubbisetty mic_hdr[12] = tid; 3044243874c6SManikanta Pubbisetty 3045243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, mic_hdr, 16); 3046243874c6SManikanta Pubbisetty if (ret) 3047243874c6SManikanta Pubbisetty goto out; 3048243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, data, data_len); 3049243874c6SManikanta Pubbisetty if (ret) 3050243874c6SManikanta Pubbisetty goto out; 3051243874c6SManikanta Pubbisetty ret = crypto_shash_final(desc, mic); 3052243874c6SManikanta Pubbisetty out: 3053243874c6SManikanta Pubbisetty shash_desc_zero(desc); 3054d5c65159SKalle Valo return ret; 3055d5c65159SKalle Valo } 3056d5c65159SKalle Valo 3057243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 3058243874c6SManikanta Pubbisetty struct sk_buff *msdu) 3059d5c65159SKalle Valo { 3060243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3061243874c6SManikanta Pubbisetty struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3062243874c6SManikanta Pubbisetty struct ieee80211_key_conf *key_conf; 3063243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3064243874c6SManikanta Pubbisetty u8 mic[IEEE80211_CCMP_MIC_LEN]; 3065243874c6SManikanta Pubbisetty int head_len, tail_len, ret; 3066243874c6SManikanta Pubbisetty size_t data_len; 3067243874c6SManikanta Pubbisetty u32 hdr_len; 3068243874c6SManikanta Pubbisetty u8 *key, *data; 3069243874c6SManikanta Pubbisetty u8 key_idx; 3070d5c65159SKalle Valo 3071243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_mpdu_start_enctype(rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 3072243874c6SManikanta Pubbisetty return 0; 3073d5c65159SKalle Valo 3074243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE); 3075243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3076243874c6SManikanta Pubbisetty head_len = hdr_len + HAL_RX_DESC_SIZE + IEEE80211_TKIP_IV_LEN; 3077243874c6SManikanta Pubbisetty tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3078d5c65159SKalle Valo 3079243874c6SManikanta Pubbisetty if (!is_multicast_ether_addr(hdr->addr1)) 3080243874c6SManikanta Pubbisetty key_idx = peer->ucast_keyidx; 3081243874c6SManikanta Pubbisetty else 3082243874c6SManikanta Pubbisetty key_idx = peer->mcast_keyidx; 3083d5c65159SKalle Valo 3084243874c6SManikanta Pubbisetty key_conf = peer->keys[key_idx]; 3085d5c65159SKalle Valo 3086243874c6SManikanta Pubbisetty data = msdu->data + head_len; 3087243874c6SManikanta Pubbisetty data_len = msdu->len - head_len - tail_len; 3088243874c6SManikanta Pubbisetty key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3089d5c65159SKalle Valo 3090243874c6SManikanta Pubbisetty ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3091243874c6SManikanta Pubbisetty if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3092243874c6SManikanta Pubbisetty goto mic_fail; 3093d5c65159SKalle Valo 3094243874c6SManikanta Pubbisetty return 0; 3095243874c6SManikanta Pubbisetty 3096243874c6SManikanta Pubbisetty mic_fail: 3097b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 3098b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 3099243874c6SManikanta Pubbisetty 3100243874c6SManikanta Pubbisetty rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3101243874c6SManikanta Pubbisetty RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3102243874c6SManikanta Pubbisetty skb_pull(msdu, HAL_RX_DESC_SIZE); 3103243874c6SManikanta Pubbisetty 3104243874c6SManikanta Pubbisetty ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 3105243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 3106243874c6SManikanta Pubbisetty HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3107243874c6SManikanta Pubbisetty ieee80211_rx(ar->hw, msdu); 3108243874c6SManikanta Pubbisetty return -EINVAL; 3109d5c65159SKalle Valo } 3110d5c65159SKalle Valo 3111243874c6SManikanta Pubbisetty static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 3112243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype, u32 flags) 3113243874c6SManikanta Pubbisetty { 3114243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3115243874c6SManikanta Pubbisetty size_t hdr_len; 3116243874c6SManikanta Pubbisetty size_t crypto_len; 3117d5c65159SKalle Valo 3118243874c6SManikanta Pubbisetty if (!flags) 3119243874c6SManikanta Pubbisetty return; 3120d5c65159SKalle Valo 3121243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(msdu->data + HAL_RX_DESC_SIZE); 3122243874c6SManikanta Pubbisetty 3123243874c6SManikanta Pubbisetty if (flags & RX_FLAG_MIC_STRIPPED) 3124d5c65159SKalle Valo skb_trim(msdu, msdu->len - 3125d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3126243874c6SManikanta Pubbisetty 3127243874c6SManikanta Pubbisetty if (flags & RX_FLAG_ICV_STRIPPED) 3128243874c6SManikanta Pubbisetty skb_trim(msdu, msdu->len - 3129243874c6SManikanta Pubbisetty ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3130243874c6SManikanta Pubbisetty 3131243874c6SManikanta Pubbisetty if (flags & RX_FLAG_IV_STRIPPED) { 3132243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3133243874c6SManikanta Pubbisetty crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3134243874c6SManikanta Pubbisetty 3135243874c6SManikanta Pubbisetty memmove((void *)msdu->data + HAL_RX_DESC_SIZE + crypto_len, 3136243874c6SManikanta Pubbisetty (void *)msdu->data + HAL_RX_DESC_SIZE, hdr_len); 3137243874c6SManikanta Pubbisetty skb_pull(msdu, crypto_len); 3138d5c65159SKalle Valo } 3139d5c65159SKalle Valo } 3140d5c65159SKalle Valo 3141243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3142243874c6SManikanta Pubbisetty struct ath11k_peer *peer, 3143243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid, 3144243874c6SManikanta Pubbisetty struct sk_buff **defrag_skb) 3145243874c6SManikanta Pubbisetty { 3146243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3147243874c6SManikanta Pubbisetty struct sk_buff *skb, *first_frag, *last_frag; 3148243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3149243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype; 3150243874c6SManikanta Pubbisetty bool is_decrypted = false; 3151243874c6SManikanta Pubbisetty int msdu_len = 0; 3152243874c6SManikanta Pubbisetty int extra_space; 3153243874c6SManikanta Pubbisetty u32 flags; 3154243874c6SManikanta Pubbisetty 3155243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3156243874c6SManikanta Pubbisetty last_frag = skb_peek_tail(&rx_tid->rx_frags); 3157243874c6SManikanta Pubbisetty 3158243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3159243874c6SManikanta Pubbisetty flags = 0; 3160243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)skb->data; 3161243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 3162243874c6SManikanta Pubbisetty 3163243874c6SManikanta Pubbisetty enctype = ath11k_dp_rx_h_mpdu_start_enctype(rx_desc); 3164243874c6SManikanta Pubbisetty if (enctype != HAL_ENCRYPT_TYPE_OPEN) 3165243874c6SManikanta Pubbisetty is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_desc); 3166243874c6SManikanta Pubbisetty 3167243874c6SManikanta Pubbisetty if (is_decrypted) { 3168243874c6SManikanta Pubbisetty if (skb != first_frag) 3169243874c6SManikanta Pubbisetty flags |= RX_FLAG_IV_STRIPPED; 3170243874c6SManikanta Pubbisetty if (skb != last_frag) 3171243874c6SManikanta Pubbisetty flags |= RX_FLAG_ICV_STRIPPED | 3172243874c6SManikanta Pubbisetty RX_FLAG_MIC_STRIPPED; 3173243874c6SManikanta Pubbisetty } 3174243874c6SManikanta Pubbisetty 3175243874c6SManikanta Pubbisetty /* RX fragments are always raw packets */ 3176243874c6SManikanta Pubbisetty if (skb != last_frag) 3177243874c6SManikanta Pubbisetty skb_trim(skb, skb->len - FCS_LEN); 3178243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3179243874c6SManikanta Pubbisetty 3180243874c6SManikanta Pubbisetty if (skb != first_frag) 3181243874c6SManikanta Pubbisetty skb_pull(skb, HAL_RX_DESC_SIZE + 3182243874c6SManikanta Pubbisetty ieee80211_hdrlen(hdr->frame_control)); 3183243874c6SManikanta Pubbisetty msdu_len += skb->len; 3184243874c6SManikanta Pubbisetty } 3185243874c6SManikanta Pubbisetty 3186243874c6SManikanta Pubbisetty extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3187243874c6SManikanta Pubbisetty if (extra_space > 0 && 3188243874c6SManikanta Pubbisetty (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3189243874c6SManikanta Pubbisetty return -ENOMEM; 3190243874c6SManikanta Pubbisetty 3191243874c6SManikanta Pubbisetty __skb_unlink(first_frag, &rx_tid->rx_frags); 3192243874c6SManikanta Pubbisetty while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3193243874c6SManikanta Pubbisetty skb_put_data(first_frag, skb->data, skb->len); 3194243874c6SManikanta Pubbisetty dev_kfree_skb_any(skb); 3195243874c6SManikanta Pubbisetty } 3196243874c6SManikanta Pubbisetty 3197243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(first_frag->data + HAL_RX_DESC_SIZE); 3198243874c6SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3199243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3200243874c6SManikanta Pubbisetty 3201243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3202243874c6SManikanta Pubbisetty first_frag = NULL; 3203243874c6SManikanta Pubbisetty 3204243874c6SManikanta Pubbisetty *defrag_skb = first_frag; 3205243874c6SManikanta Pubbisetty return 0; 3206243874c6SManikanta Pubbisetty } 3207243874c6SManikanta Pubbisetty 3208243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3209243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb) 3210243874c6SManikanta Pubbisetty { 3211243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3212243874c6SManikanta Pubbisetty struct ath11k_pdev_dp *dp = &ar->dp; 3213243874c6SManikanta Pubbisetty struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3214243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3215243874c6SManikanta Pubbisetty struct hal_reo_entrance_ring *reo_ent_ring; 3216243874c6SManikanta Pubbisetty struct hal_reo_dest_ring *reo_dest_ring; 3217243874c6SManikanta Pubbisetty struct dp_link_desc_bank *link_desc_banks; 3218243874c6SManikanta Pubbisetty struct hal_rx_msdu_link *msdu_link; 3219243874c6SManikanta Pubbisetty struct hal_rx_msdu_details *msdu0; 3220243874c6SManikanta Pubbisetty struct hal_srng *srng; 3221243874c6SManikanta Pubbisetty dma_addr_t paddr; 3222243874c6SManikanta Pubbisetty u32 desc_bank, msdu_info, mpdu_info; 3223243874c6SManikanta Pubbisetty u32 dst_idx, cookie; 3224243874c6SManikanta Pubbisetty u32 *msdu_len_offset; 3225243874c6SManikanta Pubbisetty int ret, buf_id; 3226243874c6SManikanta Pubbisetty 3227243874c6SManikanta Pubbisetty link_desc_banks = ab->dp.link_desc_banks; 3228243874c6SManikanta Pubbisetty reo_dest_ring = rx_tid->dst_ring_desc; 3229243874c6SManikanta Pubbisetty 3230243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3231243874c6SManikanta Pubbisetty msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3232243874c6SManikanta Pubbisetty (paddr - link_desc_banks[desc_bank].paddr)); 3233243874c6SManikanta Pubbisetty msdu0 = &msdu_link->msdu_link[0]; 3234243874c6SManikanta Pubbisetty dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3235243874c6SManikanta Pubbisetty memset(msdu0, 0, sizeof(*msdu0)); 3236243874c6SManikanta Pubbisetty 3237243874c6SManikanta Pubbisetty msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3238243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3239243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3240243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3241243874c6SManikanta Pubbisetty defrag_skb->len - HAL_RX_DESC_SIZE) | 3242243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3243243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3244243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3245243874c6SManikanta Pubbisetty msdu0->rx_msdu_info.info0 = msdu_info; 3246243874c6SManikanta Pubbisetty 3247243874c6SManikanta Pubbisetty /* change msdu len in hal rx desc */ 3248243874c6SManikanta Pubbisetty msdu_len_offset = (u32 *)&rx_desc->msdu_start; 3249243874c6SManikanta Pubbisetty *msdu_len_offset &= ~(RX_MSDU_START_INFO1_MSDU_LENGTH); 3250243874c6SManikanta Pubbisetty *msdu_len_offset |= defrag_skb->len - HAL_RX_DESC_SIZE; 3251243874c6SManikanta Pubbisetty 3252243874c6SManikanta Pubbisetty paddr = dma_map_single(ab->dev, defrag_skb->data, 3253243874c6SManikanta Pubbisetty defrag_skb->len + skb_tailroom(defrag_skb), 3254243874c6SManikanta Pubbisetty DMA_FROM_DEVICE); 3255243874c6SManikanta Pubbisetty if (dma_mapping_error(ab->dev, paddr)) 3256243874c6SManikanta Pubbisetty return -ENOMEM; 3257243874c6SManikanta Pubbisetty 3258243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3259243874c6SManikanta Pubbisetty buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3260243874c6SManikanta Pubbisetty rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3261243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3262243874c6SManikanta Pubbisetty if (buf_id < 0) { 3263243874c6SManikanta Pubbisetty ret = -ENOMEM; 3264243874c6SManikanta Pubbisetty goto err_unmap_dma; 3265243874c6SManikanta Pubbisetty } 3266243874c6SManikanta Pubbisetty 3267243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3268243874c6SManikanta Pubbisetty cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3269243874c6SManikanta Pubbisetty FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3270243874c6SManikanta Pubbisetty 3271243874c6SManikanta Pubbisetty ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, HAL_RX_BUF_RBM_SW3_BM); 3272243874c6SManikanta Pubbisetty 3273243874c6SManikanta Pubbisetty /* Fill mpdu details into reo entrace ring */ 3274243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3275243874c6SManikanta Pubbisetty 3276243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 3277243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 3278243874c6SManikanta Pubbisetty 3279243874c6SManikanta Pubbisetty reo_ent_ring = (struct hal_reo_entrance_ring *) 3280243874c6SManikanta Pubbisetty ath11k_hal_srng_src_get_next_entry(ab, srng); 3281243874c6SManikanta Pubbisetty if (!reo_ent_ring) { 3282243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3283243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3284243874c6SManikanta Pubbisetty ret = -ENOSPC; 3285243874c6SManikanta Pubbisetty goto err_free_idr; 3286243874c6SManikanta Pubbisetty } 3287243874c6SManikanta Pubbisetty memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3288243874c6SManikanta Pubbisetty 3289243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3290243874c6SManikanta Pubbisetty ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3291243874c6SManikanta Pubbisetty HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3292243874c6SManikanta Pubbisetty 3293243874c6SManikanta Pubbisetty mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3294243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3295243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3296243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3297243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3298243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3299243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3300243874c6SManikanta Pubbisetty 3301243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3302243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3303243874c6SManikanta Pubbisetty reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3304243874c6SManikanta Pubbisetty reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3305243874c6SManikanta Pubbisetty FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3306243874c6SManikanta Pubbisetty reo_dest_ring->info0)) | 3307243874c6SManikanta Pubbisetty FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3308243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3309243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3310243874c6SManikanta Pubbisetty 3311243874c6SManikanta Pubbisetty return 0; 3312243874c6SManikanta Pubbisetty 3313243874c6SManikanta Pubbisetty err_free_idr: 3314243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3315243874c6SManikanta Pubbisetty idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3316243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3317243874c6SManikanta Pubbisetty err_unmap_dma: 3318243874c6SManikanta Pubbisetty dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3319243874c6SManikanta Pubbisetty DMA_FROM_DEVICE); 3320243874c6SManikanta Pubbisetty return ret; 3321243874c6SManikanta Pubbisetty } 3322243874c6SManikanta Pubbisetty 3323243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_cmp_frags(struct sk_buff *a, struct sk_buff *b) 3324243874c6SManikanta Pubbisetty { 3325243874c6SManikanta Pubbisetty int frag1, frag2; 3326243874c6SManikanta Pubbisetty 3327243874c6SManikanta Pubbisetty frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(a); 3328243874c6SManikanta Pubbisetty frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(b); 3329243874c6SManikanta Pubbisetty 3330243874c6SManikanta Pubbisetty return frag1 - frag2; 3331243874c6SManikanta Pubbisetty } 3332243874c6SManikanta Pubbisetty 3333243874c6SManikanta Pubbisetty static void ath11k_dp_rx_h_sort_frags(struct sk_buff_head *frag_list, 3334243874c6SManikanta Pubbisetty struct sk_buff *cur_frag) 3335243874c6SManikanta Pubbisetty { 3336243874c6SManikanta Pubbisetty struct sk_buff *skb; 3337243874c6SManikanta Pubbisetty int cmp; 3338243874c6SManikanta Pubbisetty 3339243874c6SManikanta Pubbisetty skb_queue_walk(frag_list, skb) { 3340243874c6SManikanta Pubbisetty cmp = ath11k_dp_rx_h_cmp_frags(skb, cur_frag); 3341243874c6SManikanta Pubbisetty if (cmp < 0) 3342243874c6SManikanta Pubbisetty continue; 3343243874c6SManikanta Pubbisetty __skb_queue_before(frag_list, skb, cur_frag); 3344243874c6SManikanta Pubbisetty return; 3345243874c6SManikanta Pubbisetty } 3346243874c6SManikanta Pubbisetty __skb_queue_tail(frag_list, cur_frag); 3347243874c6SManikanta Pubbisetty } 3348243874c6SManikanta Pubbisetty 3349243874c6SManikanta Pubbisetty static u64 ath11k_dp_rx_h_get_pn(struct sk_buff *skb) 3350243874c6SManikanta Pubbisetty { 3351243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3352243874c6SManikanta Pubbisetty u64 pn = 0; 3353243874c6SManikanta Pubbisetty u8 *ehdr; 3354243874c6SManikanta Pubbisetty 3355243874c6SManikanta Pubbisetty hdr = (struct ieee80211_hdr *)(skb->data + HAL_RX_DESC_SIZE); 3356243874c6SManikanta Pubbisetty ehdr = skb->data + HAL_RX_DESC_SIZE + ieee80211_hdrlen(hdr->frame_control); 3357243874c6SManikanta Pubbisetty 3358243874c6SManikanta Pubbisetty pn = ehdr[0]; 3359243874c6SManikanta Pubbisetty pn |= (u64)ehdr[1] << 8; 3360243874c6SManikanta Pubbisetty pn |= (u64)ehdr[4] << 16; 3361243874c6SManikanta Pubbisetty pn |= (u64)ehdr[5] << 24; 3362243874c6SManikanta Pubbisetty pn |= (u64)ehdr[6] << 32; 3363243874c6SManikanta Pubbisetty pn |= (u64)ehdr[7] << 40; 3364243874c6SManikanta Pubbisetty 3365243874c6SManikanta Pubbisetty return pn; 3366243874c6SManikanta Pubbisetty } 3367243874c6SManikanta Pubbisetty 3368243874c6SManikanta Pubbisetty static bool 3369243874c6SManikanta Pubbisetty ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3370243874c6SManikanta Pubbisetty { 3371243874c6SManikanta Pubbisetty enum hal_encrypt_type encrypt_type; 3372243874c6SManikanta Pubbisetty struct sk_buff *first_frag, *skb; 3373243874c6SManikanta Pubbisetty struct hal_rx_desc *desc; 3374243874c6SManikanta Pubbisetty u64 last_pn; 3375243874c6SManikanta Pubbisetty u64 cur_pn; 3376243874c6SManikanta Pubbisetty 3377243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3378243874c6SManikanta Pubbisetty desc = (struct hal_rx_desc *)first_frag->data; 3379243874c6SManikanta Pubbisetty 3380243874c6SManikanta Pubbisetty encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(desc); 3381243874c6SManikanta Pubbisetty if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3382243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3383243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3384243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3385243874c6SManikanta Pubbisetty return true; 3386243874c6SManikanta Pubbisetty 3387243874c6SManikanta Pubbisetty last_pn = ath11k_dp_rx_h_get_pn(first_frag); 3388243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3389243874c6SManikanta Pubbisetty if (skb == first_frag) 3390243874c6SManikanta Pubbisetty continue; 3391243874c6SManikanta Pubbisetty 3392243874c6SManikanta Pubbisetty cur_pn = ath11k_dp_rx_h_get_pn(skb); 3393243874c6SManikanta Pubbisetty if (cur_pn != last_pn + 1) 3394243874c6SManikanta Pubbisetty return false; 3395243874c6SManikanta Pubbisetty last_pn = cur_pn; 3396243874c6SManikanta Pubbisetty } 3397243874c6SManikanta Pubbisetty return true; 3398243874c6SManikanta Pubbisetty } 3399243874c6SManikanta Pubbisetty 3400243874c6SManikanta Pubbisetty static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3401243874c6SManikanta Pubbisetty struct sk_buff *msdu, 3402243874c6SManikanta Pubbisetty u32 *ring_desc) 3403243874c6SManikanta Pubbisetty { 3404243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3405243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3406243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 3407243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 3408243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb = NULL; 3409243874c6SManikanta Pubbisetty u32 peer_id; 3410243874c6SManikanta Pubbisetty u16 seqno, frag_no; 3411243874c6SManikanta Pubbisetty u8 tid; 3412243874c6SManikanta Pubbisetty int ret = 0; 3413243874c6SManikanta Pubbisetty bool more_frags; 3414243874c6SManikanta Pubbisetty 3415243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)msdu->data; 3416243874c6SManikanta Pubbisetty peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(rx_desc); 3417243874c6SManikanta Pubbisetty tid = ath11k_dp_rx_h_mpdu_start_tid(rx_desc); 3418243874c6SManikanta Pubbisetty seqno = ath11k_dp_rx_h_mpdu_start_seq_no(rx_desc); 3419243874c6SManikanta Pubbisetty frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(msdu); 3420243874c6SManikanta Pubbisetty more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(msdu); 3421243874c6SManikanta Pubbisetty 3422243874c6SManikanta Pubbisetty if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(rx_desc) || 3423243874c6SManikanta Pubbisetty !ath11k_dp_rx_h_mpdu_start_fc_valid(rx_desc) || 3424243874c6SManikanta Pubbisetty tid > IEEE80211_NUM_TIDS) 3425243874c6SManikanta Pubbisetty return -EINVAL; 3426243874c6SManikanta Pubbisetty 3427243874c6SManikanta Pubbisetty /* received unfragmented packet in reo 3428243874c6SManikanta Pubbisetty * exception ring, this shouldn't happen 3429243874c6SManikanta Pubbisetty * as these packets typically come from 3430243874c6SManikanta Pubbisetty * reo2sw srngs. 3431243874c6SManikanta Pubbisetty */ 3432243874c6SManikanta Pubbisetty if (WARN_ON_ONCE(!frag_no && !more_frags)) 3433243874c6SManikanta Pubbisetty return -EINVAL; 3434243874c6SManikanta Pubbisetty 3435243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3436243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3437243874c6SManikanta Pubbisetty if (!peer) { 3438243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3439243874c6SManikanta Pubbisetty peer_id); 3440243874c6SManikanta Pubbisetty ret = -ENOENT; 3441243874c6SManikanta Pubbisetty goto out_unlock; 3442243874c6SManikanta Pubbisetty } 3443243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 3444243874c6SManikanta Pubbisetty 3445243874c6SManikanta Pubbisetty if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3446243874c6SManikanta Pubbisetty skb_queue_empty(&rx_tid->rx_frags)) { 3447243874c6SManikanta Pubbisetty /* Flush stored fragments and start a new sequence */ 3448243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3449243874c6SManikanta Pubbisetty rx_tid->cur_sn = seqno; 3450243874c6SManikanta Pubbisetty } 3451243874c6SManikanta Pubbisetty 3452243874c6SManikanta Pubbisetty if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3453243874c6SManikanta Pubbisetty /* Fragment already present */ 3454243874c6SManikanta Pubbisetty ret = -EINVAL; 3455243874c6SManikanta Pubbisetty goto out_unlock; 3456243874c6SManikanta Pubbisetty } 3457243874c6SManikanta Pubbisetty 3458243874c6SManikanta Pubbisetty if (frag_no > __fls(rx_tid->rx_frag_bitmap)) 3459243874c6SManikanta Pubbisetty __skb_queue_tail(&rx_tid->rx_frags, msdu); 3460243874c6SManikanta Pubbisetty else 3461243874c6SManikanta Pubbisetty ath11k_dp_rx_h_sort_frags(&rx_tid->rx_frags, msdu); 3462243874c6SManikanta Pubbisetty 3463243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap |= BIT(frag_no); 3464243874c6SManikanta Pubbisetty if (!more_frags) 3465243874c6SManikanta Pubbisetty rx_tid->last_frag_no = frag_no; 3466243874c6SManikanta Pubbisetty 3467243874c6SManikanta Pubbisetty if (frag_no == 0) { 3468243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = kmemdup(ring_desc, 3469243874c6SManikanta Pubbisetty sizeof(*rx_tid->dst_ring_desc), 3470243874c6SManikanta Pubbisetty GFP_ATOMIC); 3471243874c6SManikanta Pubbisetty if (!rx_tid->dst_ring_desc) { 3472243874c6SManikanta Pubbisetty ret = -ENOMEM; 3473243874c6SManikanta Pubbisetty goto out_unlock; 3474243874c6SManikanta Pubbisetty } 3475243874c6SManikanta Pubbisetty } else { 3476243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, ring_desc, 3477243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3478243874c6SManikanta Pubbisetty } 3479243874c6SManikanta Pubbisetty 3480243874c6SManikanta Pubbisetty if (!rx_tid->last_frag_no || 3481243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3482243874c6SManikanta Pubbisetty mod_timer(&rx_tid->frag_timer, jiffies + 3483243874c6SManikanta Pubbisetty ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3484243874c6SManikanta Pubbisetty goto out_unlock; 3485243874c6SManikanta Pubbisetty } 3486243874c6SManikanta Pubbisetty 3487243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3488243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 3489243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3490243874c6SManikanta Pubbisetty 3491243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3492243874c6SManikanta Pubbisetty if (!peer) 3493243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3494243874c6SManikanta Pubbisetty 3495243874c6SManikanta Pubbisetty if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3496243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3497243874c6SManikanta Pubbisetty 3498243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3499243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3500243874c6SManikanta Pubbisetty 3501243874c6SManikanta Pubbisetty if (!defrag_skb) 3502243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3503243874c6SManikanta Pubbisetty 3504243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3505243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3506243874c6SManikanta Pubbisetty 3507243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, false); 3508243874c6SManikanta Pubbisetty goto out_unlock; 3509243874c6SManikanta Pubbisetty 3510243874c6SManikanta Pubbisetty err_frags_cleanup: 3511243874c6SManikanta Pubbisetty dev_kfree_skb_any(defrag_skb); 3512243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3513243874c6SManikanta Pubbisetty out_unlock: 3514243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3515243874c6SManikanta Pubbisetty return ret; 3516243874c6SManikanta Pubbisetty } 3517243874c6SManikanta Pubbisetty 3518d5c65159SKalle Valo static int 3519243874c6SManikanta Pubbisetty ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3520d5c65159SKalle Valo { 3521d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 3522d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3523d5c65159SKalle Valo struct sk_buff *msdu; 3524d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3525d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 3526d7d43782STamizh Chelvam u8 *hdr_status; 3527d5c65159SKalle Valo u16 msdu_len; 3528d5c65159SKalle Valo 3529d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 3530d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3531d5c65159SKalle Valo if (!msdu) { 3532d5c65159SKalle Valo ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3533d5c65159SKalle Valo buf_id); 3534d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3535d5c65159SKalle Valo return -EINVAL; 3536d5c65159SKalle Valo } 3537d5c65159SKalle Valo 3538d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 3539d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3540d5c65159SKalle Valo 3541d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 3542d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 3543d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 3544d5c65159SKalle Valo DMA_FROM_DEVICE); 3545d5c65159SKalle Valo 3546243874c6SManikanta Pubbisetty if (drop) { 3547d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3548d5c65159SKalle Valo return 0; 3549d5c65159SKalle Valo } 3550d5c65159SKalle Valo 3551d5c65159SKalle Valo rcu_read_lock(); 3552d5c65159SKalle Valo if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3553d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3554d5c65159SKalle Valo goto exit; 3555d5c65159SKalle Valo } 3556d5c65159SKalle Valo 3557d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3558d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3559d5c65159SKalle Valo goto exit; 3560d5c65159SKalle Valo } 3561d5c65159SKalle Valo 3562d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 3563d5c65159SKalle Valo msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(rx_desc); 3564d7d43782STamizh Chelvam if ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE) { 3565d7d43782STamizh Chelvam hdr_status = ath11k_dp_rx_h_80211_hdr(rx_desc); 3566d7d43782STamizh Chelvam ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3567d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3568d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 3569d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3570d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 3571d7d43782STamizh Chelvam dev_kfree_skb_any(msdu); 3572d7d43782STamizh Chelvam goto exit; 3573d7d43782STamizh Chelvam } 3574d7d43782STamizh Chelvam 3575d5c65159SKalle Valo skb_put(msdu, HAL_RX_DESC_SIZE + msdu_len); 3576d5c65159SKalle Valo 3577243874c6SManikanta Pubbisetty if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3578243874c6SManikanta Pubbisetty dev_kfree_skb_any(msdu); 3579243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3580243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3581243874c6SManikanta Pubbisetty } 3582d5c65159SKalle Valo exit: 3583d5c65159SKalle Valo rcu_read_unlock(); 3584d5c65159SKalle Valo return 0; 3585d5c65159SKalle Valo } 3586d5c65159SKalle Valo 3587d5c65159SKalle Valo int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3588d5c65159SKalle Valo int budget) 3589d5c65159SKalle Valo { 3590293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3591d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks; 3592d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 3593d5c65159SKalle Valo int tot_n_bufs_reaped, quota, ret, i; 3594d5c65159SKalle Valo int n_bufs_reaped[MAX_RADIOS] = {0}; 3595d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 3596d5c65159SKalle Valo struct dp_srng *reo_except; 3597d5c65159SKalle Valo u32 desc_bank, num_msdus; 3598d5c65159SKalle Valo struct hal_srng *srng; 3599d5c65159SKalle Valo struct ath11k_dp *dp; 3600d5c65159SKalle Valo void *link_desc_va; 3601d5c65159SKalle Valo int buf_id, mac_id; 3602d5c65159SKalle Valo struct ath11k *ar; 3603d5c65159SKalle Valo dma_addr_t paddr; 3604d5c65159SKalle Valo u32 *desc; 3605d5c65159SKalle Valo bool is_frag; 3606243874c6SManikanta Pubbisetty u8 drop = 0; 3607d5c65159SKalle Valo 3608d5c65159SKalle Valo tot_n_bufs_reaped = 0; 3609d5c65159SKalle Valo quota = budget; 3610d5c65159SKalle Valo 3611d5c65159SKalle Valo dp = &ab->dp; 3612d5c65159SKalle Valo reo_except = &dp->reo_except_ring; 3613d5c65159SKalle Valo link_desc_banks = dp->link_desc_banks; 3614d5c65159SKalle Valo 3615d5c65159SKalle Valo srng = &ab->hal.srng_list[reo_except->ring_id]; 3616d5c65159SKalle Valo 3617d5c65159SKalle Valo spin_lock_bh(&srng->lock); 3618d5c65159SKalle Valo 3619d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 3620d5c65159SKalle Valo 3621d5c65159SKalle Valo while (budget && 3622d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3623293cb583SJohn Crispin struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3624293cb583SJohn Crispin 3625d5c65159SKalle Valo ab->soc_stats.err_ring_pkts++; 3626d5c65159SKalle Valo ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3627d5c65159SKalle Valo &desc_bank); 3628d5c65159SKalle Valo if (ret) { 3629d5c65159SKalle Valo ath11k_warn(ab, "failed to parse error reo desc %d\n", 3630d5c65159SKalle Valo ret); 3631d5c65159SKalle Valo continue; 3632d5c65159SKalle Valo } 3633d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 3634d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 3635293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3636d5c65159SKalle Valo &rbm); 3637d5c65159SKalle Valo if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 3638d5c65159SKalle Valo rbm != HAL_RX_BUF_RBM_SW3_BM) { 3639d5c65159SKalle Valo ab->soc_stats.invalid_rbm++; 3640d5c65159SKalle Valo ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3641d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3642d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_REL_MSDU); 3643d5c65159SKalle Valo continue; 3644d5c65159SKalle Valo } 3645d5c65159SKalle Valo 3646293cb583SJohn Crispin is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3647d5c65159SKalle Valo 3648243874c6SManikanta Pubbisetty /* Process only rx fragments with one msdu per link desc below, and drop 3649243874c6SManikanta Pubbisetty * msdu's indicated due to error reasons. 3650243874c6SManikanta Pubbisetty */ 3651243874c6SManikanta Pubbisetty if (!is_frag || num_msdus > 1) { 3652243874c6SManikanta Pubbisetty drop = 1; 3653d5c65159SKalle Valo /* Return the link desc back to wbm idle list */ 3654d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3655d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3656243874c6SManikanta Pubbisetty } 3657d5c65159SKalle Valo 3658d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 3659d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3660293cb583SJohn Crispin msdu_cookies[i]); 3661d5c65159SKalle Valo 3662d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3663293cb583SJohn Crispin msdu_cookies[i]); 3664d5c65159SKalle Valo 3665d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 3666d5c65159SKalle Valo 3667243874c6SManikanta Pubbisetty if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3668d5c65159SKalle Valo n_bufs_reaped[mac_id]++; 3669d5c65159SKalle Valo tot_n_bufs_reaped++; 3670d5c65159SKalle Valo } 3671d5c65159SKalle Valo } 3672d5c65159SKalle Valo 3673d5c65159SKalle Valo if (tot_n_bufs_reaped >= quota) { 3674d5c65159SKalle Valo tot_n_bufs_reaped = quota; 3675d5c65159SKalle Valo goto exit; 3676d5c65159SKalle Valo } 3677d5c65159SKalle Valo 3678d5c65159SKalle Valo budget = quota - tot_n_bufs_reaped; 3679d5c65159SKalle Valo } 3680d5c65159SKalle Valo 3681d5c65159SKalle Valo exit: 3682d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3683d5c65159SKalle Valo 3684d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3685d5c65159SKalle Valo 3686d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 3687d5c65159SKalle Valo if (!n_bufs_reaped[i]) 3688d5c65159SKalle Valo continue; 3689d5c65159SKalle Valo 3690d5c65159SKalle Valo ar = ab->pdevs[i].ar; 3691d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 3692d5c65159SKalle Valo 3693d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 369487e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 3695d5c65159SKalle Valo } 3696d5c65159SKalle Valo 3697d5c65159SKalle Valo return tot_n_bufs_reaped; 3698d5c65159SKalle Valo } 3699d5c65159SKalle Valo 3700d5c65159SKalle Valo static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3701d5c65159SKalle Valo int msdu_len, 3702d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3703d5c65159SKalle Valo { 3704d5c65159SKalle Valo struct sk_buff *skb, *tmp; 3705d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3706d5c65159SKalle Valo int n_buffs; 3707d5c65159SKalle Valo 3708d5c65159SKalle Valo n_buffs = DIV_ROUND_UP(msdu_len, 3709d5c65159SKalle Valo (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE)); 3710d5c65159SKalle Valo 3711d5c65159SKalle Valo skb_queue_walk_safe(msdu_list, skb, tmp) { 3712d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3713d5c65159SKalle Valo if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3714d5c65159SKalle Valo rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3715d5c65159SKalle Valo if (!n_buffs) 3716d5c65159SKalle Valo break; 3717d5c65159SKalle Valo __skb_unlink(skb, msdu_list); 3718d5c65159SKalle Valo dev_kfree_skb_any(skb); 3719d5c65159SKalle Valo n_buffs--; 3720d5c65159SKalle Valo } 3721d5c65159SKalle Valo } 3722d5c65159SKalle Valo } 3723d5c65159SKalle Valo 3724d5c65159SKalle Valo static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3725d5c65159SKalle Valo struct ieee80211_rx_status *status, 3726d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3727d5c65159SKalle Valo { 3728d5c65159SKalle Valo u16 msdu_len; 3729d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3730d5c65159SKalle Valo u8 l3pad_bytes; 3731d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3732d5c65159SKalle Valo 3733d5c65159SKalle Valo msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc); 3734d5c65159SKalle Valo 3735243874c6SManikanta Pubbisetty if (!rxcb->is_frag && ((msdu_len + HAL_RX_DESC_SIZE) > DP_RX_BUFFER_SIZE)) { 3736d5c65159SKalle Valo /* First buffer will be freed by the caller, so deduct it's length */ 3737d5c65159SKalle Valo msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE); 3738d5c65159SKalle Valo ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3739d5c65159SKalle Valo return -EINVAL; 3740d5c65159SKalle Valo } 3741d5c65159SKalle Valo 3742d5c65159SKalle Valo if (!ath11k_dp_rx_h_attn_msdu_done(desc)) { 3743d5c65159SKalle Valo ath11k_warn(ar->ab, 3744d5c65159SKalle Valo "msdu_done bit not set in null_q_des processing\n"); 3745d5c65159SKalle Valo __skb_queue_purge(msdu_list); 3746d5c65159SKalle Valo return -EIO; 3747d5c65159SKalle Valo } 3748d5c65159SKalle Valo 3749d5c65159SKalle Valo /* Handle NULL queue descriptor violations arising out a missing 3750d5c65159SKalle Valo * REO queue for a given peer or a given TID. This typically 3751d5c65159SKalle Valo * may happen if a packet is received on a QOS enabled TID before the 3752d5c65159SKalle Valo * ADDBA negotiation for that TID, when the TID queue is setup. Or 3753d5c65159SKalle Valo * it may also happen for MC/BC frames if they are not routed to the 3754d5c65159SKalle Valo * non-QOS TID queue, in the absence of any other default TID queue. 3755d5c65159SKalle Valo * This error can show up both in a REO destination or WBM release ring. 3756d5c65159SKalle Valo */ 3757d5c65159SKalle Valo 3758d5c65159SKalle Valo rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc); 3759d5c65159SKalle Valo rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc); 3760d5c65159SKalle Valo 3761243874c6SManikanta Pubbisetty if (rxcb->is_frag) { 3762243874c6SManikanta Pubbisetty skb_pull(msdu, HAL_RX_DESC_SIZE); 3763243874c6SManikanta Pubbisetty } else { 3764d5c65159SKalle Valo l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc); 3765d5c65159SKalle Valo 3766d5c65159SKalle Valo if ((HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3767d5c65159SKalle Valo return -EINVAL; 3768d5c65159SKalle Valo 3769d5c65159SKalle Valo skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len); 3770d5c65159SKalle Valo skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes); 3771243874c6SManikanta Pubbisetty } 3772d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3773d5c65159SKalle Valo 3774acc79d98SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3775d5c65159SKalle Valo 3776acc79d98SSriram R rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(desc); 3777d5c65159SKalle Valo 3778d5c65159SKalle Valo /* Please note that caller will having the access to msdu and completing 3779d5c65159SKalle Valo * rx with mac80211. Need not worry about cleaning up amsdu_list. 3780d5c65159SKalle Valo */ 3781d5c65159SKalle Valo 3782d5c65159SKalle Valo return 0; 3783d5c65159SKalle Valo } 3784d5c65159SKalle Valo 3785d5c65159SKalle Valo static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3786d5c65159SKalle Valo struct ieee80211_rx_status *status, 3787d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3788d5c65159SKalle Valo { 3789d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3790d5c65159SKalle Valo bool drop = false; 3791d5c65159SKalle Valo 3792d5c65159SKalle Valo ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3793d5c65159SKalle Valo 3794d5c65159SKalle Valo switch (rxcb->err_code) { 3795d5c65159SKalle Valo case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3796d5c65159SKalle Valo if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3797d5c65159SKalle Valo drop = true; 3798d5c65159SKalle Valo break; 37991441b2f2SManikanta Pubbisetty case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 38001441b2f2SManikanta Pubbisetty /* TODO: Do not drop PN failed packets in the driver; 38011441b2f2SManikanta Pubbisetty * instead, it is good to drop such packets in mac80211 38021441b2f2SManikanta Pubbisetty * after incrementing the replay counters. 38031441b2f2SManikanta Pubbisetty */ 38040b294aebSGustavo A. R. Silva fallthrough; 3805d5c65159SKalle Valo default: 3806d5c65159SKalle Valo /* TODO: Review other errors and process them to mac80211 3807d5c65159SKalle Valo * as appropriate. 3808d5c65159SKalle Valo */ 3809d5c65159SKalle Valo drop = true; 3810d5c65159SKalle Valo break; 3811d5c65159SKalle Valo } 3812d5c65159SKalle Valo 3813d5c65159SKalle Valo return drop; 3814d5c65159SKalle Valo } 3815d5c65159SKalle Valo 3816d5c65159SKalle Valo static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3817d5c65159SKalle Valo struct ieee80211_rx_status *status) 3818d5c65159SKalle Valo { 3819d5c65159SKalle Valo u16 msdu_len; 3820d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3821d5c65159SKalle Valo u8 l3pad_bytes; 3822d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3823d5c65159SKalle Valo 3824d5c65159SKalle Valo rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(desc); 3825d5c65159SKalle Valo rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(desc); 3826d5c65159SKalle Valo 3827d5c65159SKalle Valo l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(desc); 3828d5c65159SKalle Valo msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(desc); 3829d5c65159SKalle Valo skb_put(msdu, HAL_RX_DESC_SIZE + l3pad_bytes + msdu_len); 3830d5c65159SKalle Valo skb_pull(msdu, HAL_RX_DESC_SIZE + l3pad_bytes); 3831d5c65159SKalle Valo 3832d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3833d5c65159SKalle Valo 3834d5c65159SKalle Valo status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3835d5c65159SKalle Valo RX_FLAG_DECRYPTED); 3836d5c65159SKalle Valo 3837d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, desc, 3838d5c65159SKalle Valo HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3839d5c65159SKalle Valo } 3840d5c65159SKalle Valo 3841d5c65159SKalle Valo static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 3842d5c65159SKalle Valo struct ieee80211_rx_status *status) 3843d5c65159SKalle Valo { 3844d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3845d5c65159SKalle Valo bool drop = false; 3846d5c65159SKalle Valo 3847d5c65159SKalle Valo ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3848d5c65159SKalle Valo 3849d5c65159SKalle Valo switch (rxcb->err_code) { 3850d5c65159SKalle Valo case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3851d5c65159SKalle Valo ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3852d5c65159SKalle Valo break; 3853d5c65159SKalle Valo default: 3854d5c65159SKalle Valo /* TODO: Review other rxdma error code to check if anything is 3855d5c65159SKalle Valo * worth reporting to mac80211 3856d5c65159SKalle Valo */ 3857d5c65159SKalle Valo drop = true; 3858d5c65159SKalle Valo break; 3859d5c65159SKalle Valo } 3860d5c65159SKalle Valo 3861d5c65159SKalle Valo return drop; 3862d5c65159SKalle Valo } 3863d5c65159SKalle Valo 3864d5c65159SKalle Valo static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 3865d5c65159SKalle Valo struct napi_struct *napi, 3866d5c65159SKalle Valo struct sk_buff *msdu, 3867d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3868d5c65159SKalle Valo { 3869d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3870d5c65159SKalle Valo struct ieee80211_rx_status rxs = {0}; 3871d5c65159SKalle Valo struct ieee80211_rx_status *status; 3872d5c65159SKalle Valo bool drop = true; 3873d5c65159SKalle Valo 3874d5c65159SKalle Valo switch (rxcb->err_rel_src) { 3875d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_REO: 3876d5c65159SKalle Valo drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3877d5c65159SKalle Valo break; 3878d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_RXDMA: 3879d5c65159SKalle Valo drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3880d5c65159SKalle Valo break; 3881d5c65159SKalle Valo default: 3882d5c65159SKalle Valo /* msdu will get freed */ 3883d5c65159SKalle Valo break; 3884d5c65159SKalle Valo } 3885d5c65159SKalle Valo 3886d5c65159SKalle Valo if (drop) { 3887d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3888d5c65159SKalle Valo return; 3889d5c65159SKalle Valo } 3890d5c65159SKalle Valo 3891d5c65159SKalle Valo status = IEEE80211_SKB_RXCB(msdu); 3892d5c65159SKalle Valo *status = rxs; 3893d5c65159SKalle Valo 3894d5c65159SKalle Valo ath11k_dp_rx_deliver_msdu(ar, napi, msdu); 3895d5c65159SKalle Valo } 3896d5c65159SKalle Valo 3897d5c65159SKalle Valo int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 3898d5c65159SKalle Valo struct napi_struct *napi, int budget) 3899d5c65159SKalle Valo { 3900d5c65159SKalle Valo struct ath11k *ar; 3901d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 3902d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 3903d5c65159SKalle Valo struct hal_rx_wbm_rel_info err_info; 3904d5c65159SKalle Valo struct hal_srng *srng; 3905d5c65159SKalle Valo struct sk_buff *msdu; 3906d5c65159SKalle Valo struct sk_buff_head msdu_list[MAX_RADIOS]; 3907d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3908d5c65159SKalle Valo u32 *rx_desc; 3909d5c65159SKalle Valo int buf_id, mac_id; 3910d5c65159SKalle Valo int num_buffs_reaped[MAX_RADIOS] = {0}; 3911d5c65159SKalle Valo int total_num_buffs_reaped = 0; 3912d5c65159SKalle Valo int ret, i; 3913d5c65159SKalle Valo 3914b1cc29e9SAnilkumar Kolli for (i = 0; i < ab->num_radios; i++) 3915d5c65159SKalle Valo __skb_queue_head_init(&msdu_list[i]); 3916d5c65159SKalle Valo 3917d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3918d5c65159SKalle Valo 3919d5c65159SKalle Valo spin_lock_bh(&srng->lock); 3920d5c65159SKalle Valo 3921d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 3922d5c65159SKalle Valo 3923d5c65159SKalle Valo while (budget) { 3924d5c65159SKalle Valo rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 3925d5c65159SKalle Valo if (!rx_desc) 3926d5c65159SKalle Valo break; 3927d5c65159SKalle Valo 3928d5c65159SKalle Valo ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3929d5c65159SKalle Valo if (ret) { 3930d5c65159SKalle Valo ath11k_warn(ab, 3931d5c65159SKalle Valo "failed to parse rx error in wbm_rel ring desc %d\n", 3932d5c65159SKalle Valo ret); 3933d5c65159SKalle Valo continue; 3934d5c65159SKalle Valo } 3935d5c65159SKalle Valo 3936d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 3937d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 3938d5c65159SKalle Valo 3939d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 3940d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 3941d5c65159SKalle Valo 3942d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 3943d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3944d5c65159SKalle Valo if (!msdu) { 3945d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 3946d5c65159SKalle Valo buf_id, mac_id); 3947d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3948d5c65159SKalle Valo continue; 3949d5c65159SKalle Valo } 3950d5c65159SKalle Valo 3951d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 3952d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3953d5c65159SKalle Valo 3954d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 3955d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 3956d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 3957d5c65159SKalle Valo DMA_FROM_DEVICE); 3958d5c65159SKalle Valo 3959d5c65159SKalle Valo num_buffs_reaped[mac_id]++; 3960d5c65159SKalle Valo total_num_buffs_reaped++; 3961d5c65159SKalle Valo budget--; 3962d5c65159SKalle Valo 3963d5c65159SKalle Valo if (err_info.push_reason != 3964d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3965d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3966d5c65159SKalle Valo continue; 3967d5c65159SKalle Valo } 3968d5c65159SKalle Valo 3969d5c65159SKalle Valo rxcb->err_rel_src = err_info.err_rel_src; 3970d5c65159SKalle Valo rxcb->err_code = err_info.err_code; 3971d5c65159SKalle Valo rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 3972d5c65159SKalle Valo __skb_queue_tail(&msdu_list[mac_id], msdu); 3973d5c65159SKalle Valo } 3974d5c65159SKalle Valo 3975d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3976d5c65159SKalle Valo 3977d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3978d5c65159SKalle Valo 3979d5c65159SKalle Valo if (!total_num_buffs_reaped) 3980d5c65159SKalle Valo goto done; 3981d5c65159SKalle Valo 3982d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 3983d5c65159SKalle Valo if (!num_buffs_reaped[i]) 3984d5c65159SKalle Valo continue; 3985d5c65159SKalle Valo 3986d5c65159SKalle Valo ar = ab->pdevs[i].ar; 3987d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 3988d5c65159SKalle Valo 3989d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 399087e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 3991d5c65159SKalle Valo } 3992d5c65159SKalle Valo 3993d5c65159SKalle Valo rcu_read_lock(); 3994d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 3995d5c65159SKalle Valo if (!rcu_dereference(ab->pdevs_active[i])) { 3996d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 3997d5c65159SKalle Valo continue; 3998d5c65159SKalle Valo } 3999d5c65159SKalle Valo 4000d5c65159SKalle Valo ar = ab->pdevs[i].ar; 4001d5c65159SKalle Valo 4002d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 4003d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 4004d5c65159SKalle Valo continue; 4005d5c65159SKalle Valo } 4006d5c65159SKalle Valo 4007d5c65159SKalle Valo while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 4008d5c65159SKalle Valo ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 4009d5c65159SKalle Valo } 4010d5c65159SKalle Valo rcu_read_unlock(); 4011d5c65159SKalle Valo done: 4012d5c65159SKalle Valo return total_num_buffs_reaped; 4013d5c65159SKalle Valo } 4014d5c65159SKalle Valo 4015d5c65159SKalle Valo int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 4016d5c65159SKalle Valo { 40174152e420SCarl Huang struct ath11k *ar; 40184152e420SCarl Huang struct dp_srng *err_ring; 40194152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 4020d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 4021d5c65159SKalle Valo struct hal_srng *srng; 4022293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 4023d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 4024d5c65159SKalle Valo enum hal_reo_entr_rxdma_ecode rxdma_err_code; 4025d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4026d5c65159SKalle Valo struct sk_buff *skb; 4027d5c65159SKalle Valo struct hal_reo_entrance_ring *entr_ring; 4028d5c65159SKalle Valo void *desc; 4029d5c65159SKalle Valo int num_buf_freed = 0; 4030d5c65159SKalle Valo int quota = budget; 4031d5c65159SKalle Valo dma_addr_t paddr; 4032d5c65159SKalle Valo u32 desc_bank; 4033d5c65159SKalle Valo void *link_desc_va; 4034d5c65159SKalle Valo int num_msdus; 4035d5c65159SKalle Valo int i; 4036d5c65159SKalle Valo int buf_id; 4037d5c65159SKalle Valo 40384152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 40394152e420SCarl Huang err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params, 40404152e420SCarl Huang mac_id)]; 40414152e420SCarl Huang rx_ring = &ar->dp.rx_refill_buf_ring; 40424152e420SCarl Huang 4043d5c65159SKalle Valo srng = &ab->hal.srng_list[err_ring->ring_id]; 4044d5c65159SKalle Valo 4045d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4046d5c65159SKalle Valo 4047d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4048d5c65159SKalle Valo 4049d5c65159SKalle Valo while (quota-- && 4050d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4051d5c65159SKalle Valo ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 4052d5c65159SKalle Valo 4053d5c65159SKalle Valo entr_ring = (struct hal_reo_entrance_ring *)desc; 4054d5c65159SKalle Valo rxdma_err_code = 4055d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4056d5c65159SKalle Valo entr_ring->info1); 4057d5c65159SKalle Valo ab->soc_stats.rxdma_error[rxdma_err_code]++; 4058d5c65159SKalle Valo 4059d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 4060d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 4061293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 4062293cb583SJohn Crispin msdu_cookies, &rbm); 4063d5c65159SKalle Valo 4064d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4065d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4066293cb583SJohn Crispin msdu_cookies[i]); 4067d5c65159SKalle Valo 4068d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4069d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 4070d5c65159SKalle Valo if (!skb) { 4071d5c65159SKalle Valo ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 4072d5c65159SKalle Valo buf_id); 4073d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4074d5c65159SKalle Valo continue; 4075d5c65159SKalle Valo } 4076d5c65159SKalle Valo 4077d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4078d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4079d5c65159SKalle Valo 4080d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 4081d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 4082d5c65159SKalle Valo skb->len + skb_tailroom(skb), 4083d5c65159SKalle Valo DMA_FROM_DEVICE); 4084d5c65159SKalle Valo dev_kfree_skb_any(skb); 4085d5c65159SKalle Valo 4086d5c65159SKalle Valo num_buf_freed++; 4087d5c65159SKalle Valo } 4088d5c65159SKalle Valo 4089d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 4090d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4091d5c65159SKalle Valo } 4092d5c65159SKalle Valo 4093d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4094d5c65159SKalle Valo 4095d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4096d5c65159SKalle Valo 4097d5c65159SKalle Valo if (num_buf_freed) 4098d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 409987e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 4100d5c65159SKalle Valo 4101d5c65159SKalle Valo return budget - quota; 4102d5c65159SKalle Valo } 4103d5c65159SKalle Valo 4104d5c65159SKalle Valo void ath11k_dp_process_reo_status(struct ath11k_base *ab) 4105d5c65159SKalle Valo { 4106d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 4107d5c65159SKalle Valo struct hal_srng *srng; 4108d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 4109d5c65159SKalle Valo bool found = false; 4110d5c65159SKalle Valo u32 *reo_desc; 4111d5c65159SKalle Valo u16 tag; 4112d5c65159SKalle Valo struct hal_reo_status reo_status; 4113d5c65159SKalle Valo 4114d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4115d5c65159SKalle Valo 4116d5c65159SKalle Valo memset(&reo_status, 0, sizeof(reo_status)); 4117d5c65159SKalle Valo 4118d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4119d5c65159SKalle Valo 4120d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4121d5c65159SKalle Valo 4122d5c65159SKalle Valo while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4123d5c65159SKalle Valo tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 4124d5c65159SKalle Valo 4125d5c65159SKalle Valo switch (tag) { 4126d5c65159SKalle Valo case HAL_REO_GET_QUEUE_STATS_STATUS: 4127d5c65159SKalle Valo ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4128d5c65159SKalle Valo &reo_status); 4129d5c65159SKalle Valo break; 4130d5c65159SKalle Valo case HAL_REO_FLUSH_QUEUE_STATUS: 4131d5c65159SKalle Valo ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4132d5c65159SKalle Valo &reo_status); 4133d5c65159SKalle Valo break; 4134d5c65159SKalle Valo case HAL_REO_FLUSH_CACHE_STATUS: 4135d5c65159SKalle Valo ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4136d5c65159SKalle Valo &reo_status); 4137d5c65159SKalle Valo break; 4138d5c65159SKalle Valo case HAL_REO_UNBLOCK_CACHE_STATUS: 4139d5c65159SKalle Valo ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4140d5c65159SKalle Valo &reo_status); 4141d5c65159SKalle Valo break; 4142d5c65159SKalle Valo case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4143d5c65159SKalle Valo ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4144d5c65159SKalle Valo &reo_status); 4145d5c65159SKalle Valo break; 4146d5c65159SKalle Valo case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4147d5c65159SKalle Valo ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4148d5c65159SKalle Valo &reo_status); 4149d5c65159SKalle Valo break; 4150d5c65159SKalle Valo case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4151d5c65159SKalle Valo ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4152d5c65159SKalle Valo &reo_status); 4153d5c65159SKalle Valo break; 4154d5c65159SKalle Valo default: 4155d5c65159SKalle Valo ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4156d5c65159SKalle Valo continue; 4157d5c65159SKalle Valo } 4158d5c65159SKalle Valo 4159d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 4160d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4161d5c65159SKalle Valo if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4162d5c65159SKalle Valo found = true; 4163d5c65159SKalle Valo list_del(&cmd->list); 4164d5c65159SKalle Valo break; 4165d5c65159SKalle Valo } 4166d5c65159SKalle Valo } 4167d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 4168d5c65159SKalle Valo 4169d5c65159SKalle Valo if (found) { 4170d5c65159SKalle Valo cmd->handler(dp, (void *)&cmd->data, 4171d5c65159SKalle Valo reo_status.uniform_hdr.cmd_status); 4172d5c65159SKalle Valo kfree(cmd); 4173d5c65159SKalle Valo } 4174d5c65159SKalle Valo 4175d5c65159SKalle Valo found = false; 4176d5c65159SKalle Valo } 4177d5c65159SKalle Valo 4178d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4179d5c65159SKalle Valo 4180d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4181d5c65159SKalle Valo } 4182d5c65159SKalle Valo 4183d5c65159SKalle Valo void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4184d5c65159SKalle Valo { 4185d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4186d5c65159SKalle Valo 4187d5c65159SKalle Valo ath11k_dp_rx_pdev_srng_free(ar); 4188d5c65159SKalle Valo ath11k_dp_rxdma_pdev_buf_free(ar); 4189d5c65159SKalle Valo } 4190d5c65159SKalle Valo 4191d5c65159SKalle Valo int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4192d5c65159SKalle Valo { 4193d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4194d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4195d5c65159SKalle Valo u32 ring_id; 41964152e420SCarl Huang int i; 4197d5c65159SKalle Valo int ret; 4198d5c65159SKalle Valo 4199d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4200d5c65159SKalle Valo if (ret) { 4201d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx srngs\n"); 4202d5c65159SKalle Valo return ret; 4203d5c65159SKalle Valo } 4204d5c65159SKalle Valo 4205d5c65159SKalle Valo ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4206d5c65159SKalle Valo if (ret) { 4207d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rxdma ring\n"); 4208d5c65159SKalle Valo return ret; 4209d5c65159SKalle Valo } 4210d5c65159SKalle Valo 4211d5c65159SKalle Valo ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4212d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4213d5c65159SKalle Valo if (ret) { 4214d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4215d5c65159SKalle Valo ret); 4216d5c65159SKalle Valo return ret; 4217d5c65159SKalle Valo } 4218d5c65159SKalle Valo 42194152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) { 42204152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 42214152e420SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id; 42224152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 42234152e420SCarl Huang mac_id + i, HAL_RXDMA_BUF); 4224d5c65159SKalle Valo if (ret) { 42254152e420SCarl Huang ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 42264152e420SCarl Huang i, ret); 4227d5c65159SKalle Valo return ret; 4228d5c65159SKalle Valo } 42294152e420SCarl Huang } 42304152e420SCarl Huang } 42314152e420SCarl Huang 42324152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 42334152e420SCarl Huang ring_id = dp->rxdma_err_dst_ring[i].ring_id; 42344152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 42354152e420SCarl Huang mac_id + i, HAL_RXDMA_DST); 42364152e420SCarl Huang if (ret) { 42374152e420SCarl Huang ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 42384152e420SCarl Huang i, ret); 42394152e420SCarl Huang return ret; 42404152e420SCarl Huang } 42414152e420SCarl Huang } 4242d5c65159SKalle Valo 42437f6fc1ebSCarl Huang if (!ab->hw_params.rxdma1_enable) 42447f6fc1ebSCarl Huang goto config_refill_ring; 42457f6fc1ebSCarl Huang 4246d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4247d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4248d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_BUF); 4249d5c65159SKalle Valo if (ret) { 4250d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4251d5c65159SKalle Valo ret); 4252d5c65159SKalle Valo return ret; 4253d5c65159SKalle Valo } 4254d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4255d5c65159SKalle Valo dp->rxdma_mon_dst_ring.ring_id, 4256d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DST); 4257d5c65159SKalle Valo if (ret) { 4258d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4259d5c65159SKalle Valo ret); 4260d5c65159SKalle Valo return ret; 4261d5c65159SKalle Valo } 4262d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4263d5c65159SKalle Valo dp->rxdma_mon_desc_ring.ring_id, 4264d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DESC); 4265d5c65159SKalle Valo if (ret) { 4266d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4267d5c65159SKalle Valo ret); 4268d5c65159SKalle Valo return ret; 4269d5c65159SKalle Valo } 42707f6fc1ebSCarl Huang 42717f6fc1ebSCarl Huang config_refill_ring: 42724152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 42734152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 42744152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, 4275d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS); 4276d5c65159SKalle Valo if (ret) { 4277d5c65159SKalle Valo ath11k_warn(ab, 42784152e420SCarl Huang "failed to configure mon_status_refill_ring%d %d\n", 42794152e420SCarl Huang i, ret); 4280d5c65159SKalle Valo return ret; 4281d5c65159SKalle Valo } 42824152e420SCarl Huang } 42837f6fc1ebSCarl Huang 4284d5c65159SKalle Valo return 0; 4285d5c65159SKalle Valo } 4286d5c65159SKalle Valo 4287d5c65159SKalle Valo static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4288d5c65159SKalle Valo { 4289d5c65159SKalle Valo if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4290d5c65159SKalle Valo *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4291d5c65159SKalle Valo *total_len -= *frag_len; 4292d5c65159SKalle Valo } else { 4293d5c65159SKalle Valo *frag_len = *total_len; 4294d5c65159SKalle Valo *total_len = 0; 4295d5c65159SKalle Valo } 4296d5c65159SKalle Valo } 4297d5c65159SKalle Valo 4298d5c65159SKalle Valo static 4299d5c65159SKalle Valo int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4300d5c65159SKalle Valo void *p_last_buf_addr_info, 4301d5c65159SKalle Valo u8 mac_id) 4302d5c65159SKalle Valo { 4303d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4304d5c65159SKalle Valo struct dp_srng *dp_srng; 4305d5c65159SKalle Valo void *hal_srng; 4306d5c65159SKalle Valo void *src_srng_desc; 4307d5c65159SKalle Valo int ret = 0; 4308d5c65159SKalle Valo 4309701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4310d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 4311d5c65159SKalle Valo hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4312701e48a4SCarl Huang } else { 4313701e48a4SCarl Huang dp_srng = &ar->ab->dp.wbm_desc_rel_ring; 4314701e48a4SCarl Huang hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4315701e48a4SCarl Huang } 4316d5c65159SKalle Valo 4317d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4318d5c65159SKalle Valo 4319d5c65159SKalle Valo src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4320d5c65159SKalle Valo 4321d5c65159SKalle Valo if (src_srng_desc) { 4322d5c65159SKalle Valo struct ath11k_buffer_addr *src_desc = 4323d5c65159SKalle Valo (struct ath11k_buffer_addr *)src_srng_desc; 4324d5c65159SKalle Valo 4325d5c65159SKalle Valo *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4326d5c65159SKalle Valo } else { 4327d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4328d5c65159SKalle Valo "Monitor Link Desc Ring %d Full", mac_id); 4329d5c65159SKalle Valo ret = -ENOMEM; 4330d5c65159SKalle Valo } 4331d5c65159SKalle Valo 4332d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, hal_srng); 4333d5c65159SKalle Valo return ret; 4334d5c65159SKalle Valo } 4335d5c65159SKalle Valo 4336d5c65159SKalle Valo static 4337d5c65159SKalle Valo void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4338d5c65159SKalle Valo dma_addr_t *paddr, u32 *sw_cookie, 4339701e48a4SCarl Huang u8 *rbm, 4340d5c65159SKalle Valo void **pp_buf_addr_info) 4341d5c65159SKalle Valo { 4342d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = 4343d5c65159SKalle Valo (struct hal_rx_msdu_link *)rx_msdu_link_desc; 4344d5c65159SKalle Valo struct ath11k_buffer_addr *buf_addr_info; 4345d5c65159SKalle Valo 4346d5c65159SKalle Valo buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4347d5c65159SKalle Valo 4348701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 4349d5c65159SKalle Valo 4350d5c65159SKalle Valo *pp_buf_addr_info = (void *)buf_addr_info; 4351d5c65159SKalle Valo } 4352d5c65159SKalle Valo 4353d5c65159SKalle Valo static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4354d5c65159SKalle Valo { 4355d5c65159SKalle Valo if (skb->len > len) { 4356d5c65159SKalle Valo skb_trim(skb, len); 4357d5c65159SKalle Valo } else { 4358d5c65159SKalle Valo if (skb_tailroom(skb) < len - skb->len) { 4359d5c65159SKalle Valo if ((pskb_expand_head(skb, 0, 4360d5c65159SKalle Valo len - skb->len - skb_tailroom(skb), 4361d5c65159SKalle Valo GFP_ATOMIC))) { 4362d5c65159SKalle Valo dev_kfree_skb_any(skb); 4363d5c65159SKalle Valo return -ENOMEM; 4364d5c65159SKalle Valo } 4365d5c65159SKalle Valo } 4366d5c65159SKalle Valo skb_put(skb, (len - skb->len)); 4367d5c65159SKalle Valo } 4368d5c65159SKalle Valo return 0; 4369d5c65159SKalle Valo } 4370d5c65159SKalle Valo 4371d5c65159SKalle Valo static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4372d5c65159SKalle Valo void *msdu_link_desc, 4373d5c65159SKalle Valo struct hal_rx_msdu_list *msdu_list, 4374d5c65159SKalle Valo u16 *num_msdus) 4375d5c65159SKalle Valo { 4376d5c65159SKalle Valo struct hal_rx_msdu_details *msdu_details = NULL; 4377d5c65159SKalle Valo struct rx_msdu_desc *msdu_desc_info = NULL; 4378d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = NULL; 4379d5c65159SKalle Valo int i; 4380d5c65159SKalle Valo u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4381d5c65159SKalle Valo u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4382d5c65159SKalle Valo u8 tmp = 0; 4383d5c65159SKalle Valo 4384d5c65159SKalle Valo msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc; 4385d5c65159SKalle Valo msdu_details = &msdu_link->msdu_link[0]; 4386d5c65159SKalle Valo 4387d5c65159SKalle Valo for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4388d5c65159SKalle Valo if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4389d5c65159SKalle Valo msdu_details[i].buf_addr_info.info0) == 0) { 4390d5c65159SKalle Valo msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4391d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4392d5c65159SKalle Valo ; 4393d5c65159SKalle Valo break; 4394d5c65159SKalle Valo } 4395d5c65159SKalle Valo msdu_desc_info = &msdu_details[i].rx_msdu_info; 4396d5c65159SKalle Valo 4397d5c65159SKalle Valo if (!i) 4398d5c65159SKalle Valo msdu_desc_info->info0 |= first; 4399d5c65159SKalle Valo else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4400d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4401d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4402d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_len = 4403d5c65159SKalle Valo HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4404d5c65159SKalle Valo msdu_list->sw_cookie[i] = 4405d5c65159SKalle Valo FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4406d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4407d5c65159SKalle Valo tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4408d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4409d5c65159SKalle Valo msdu_list->rbm[i] = tmp; 4410d5c65159SKalle Valo } 4411d5c65159SKalle Valo *num_msdus = i; 4412d5c65159SKalle Valo } 4413d5c65159SKalle Valo 4414d5c65159SKalle Valo static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4415d5c65159SKalle Valo u32 *rx_bufs_used) 4416d5c65159SKalle Valo { 4417d5c65159SKalle Valo u32 ret = 0; 4418d5c65159SKalle Valo 4419d5c65159SKalle Valo if ((*ppdu_id < msdu_ppdu_id) && 4420d5c65159SKalle Valo ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4421d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4422d5c65159SKalle Valo ret = msdu_ppdu_id; 4423d5c65159SKalle Valo } else if ((*ppdu_id > msdu_ppdu_id) && 4424d5c65159SKalle Valo ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4425d5c65159SKalle Valo /* mon_dst is behind than mon_status 4426d5c65159SKalle Valo * skip dst_ring and free it 4427d5c65159SKalle Valo */ 4428d5c65159SKalle Valo *rx_bufs_used += 1; 4429d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4430d5c65159SKalle Valo ret = msdu_ppdu_id; 4431d5c65159SKalle Valo } 4432d5c65159SKalle Valo return ret; 4433d5c65159SKalle Valo } 4434d5c65159SKalle Valo 4435d5c65159SKalle Valo static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4436d5c65159SKalle Valo bool *is_frag, u32 *total_len, 4437d5c65159SKalle Valo u32 *frag_len, u32 *msdu_cnt) 4438d5c65159SKalle Valo { 4439d5c65159SKalle Valo if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4440d5c65159SKalle Valo if (!*is_frag) { 4441d5c65159SKalle Valo *total_len = info->msdu_len; 4442d5c65159SKalle Valo *is_frag = true; 4443d5c65159SKalle Valo } 4444d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4445d5c65159SKalle Valo frag_len); 4446d5c65159SKalle Valo } else { 4447d5c65159SKalle Valo if (*is_frag) { 4448d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4449d5c65159SKalle Valo frag_len); 4450d5c65159SKalle Valo } else { 4451d5c65159SKalle Valo *frag_len = info->msdu_len; 4452d5c65159SKalle Valo } 4453d5c65159SKalle Valo *is_frag = false; 4454d5c65159SKalle Valo *msdu_cnt -= 1; 4455d5c65159SKalle Valo } 4456d5c65159SKalle Valo } 4457d5c65159SKalle Valo 4458d5c65159SKalle Valo static u32 4459701e48a4SCarl Huang ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id, 4460d5c65159SKalle Valo void *ring_entry, struct sk_buff **head_msdu, 4461d5c65159SKalle Valo struct sk_buff **tail_msdu, u32 *npackets, 4462d5c65159SKalle Valo u32 *ppdu_id) 4463d5c65159SKalle Valo { 4464d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4465d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4466d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4467d5c65159SKalle Valo struct sk_buff *msdu = NULL, *last = NULL; 4468d5c65159SKalle Valo struct hal_rx_msdu_list msdu_list; 4469d5c65159SKalle Valo void *p_buf_addr_info, *p_last_buf_addr_info; 4470d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4471d5c65159SKalle Valo void *rx_msdu_link_desc; 4472d5c65159SKalle Valo dma_addr_t paddr; 4473d5c65159SKalle Valo u16 num_msdus = 0; 4474d5c65159SKalle Valo u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4475d5c65159SKalle Valo u32 rx_bufs_used = 0, i = 0; 4476d5c65159SKalle Valo u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4477d5c65159SKalle Valo u32 total_len = 0, frag_len = 0; 4478d5c65159SKalle Valo bool is_frag, is_first_msdu; 4479d5c65159SKalle Valo bool drop_mpdu = false; 4480d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4481d5c65159SKalle Valo struct hal_reo_entrance_ring *ent_desc = 4482d5c65159SKalle Valo (struct hal_reo_entrance_ring *)ring_entry; 4483d5c65159SKalle Valo int buf_id; 4484701e48a4SCarl Huang u32 rx_link_buf_info[2]; 4485701e48a4SCarl Huang u8 rbm; 4486701e48a4SCarl Huang 4487701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 4488701e48a4SCarl Huang rx_ring = &dp->rx_refill_buf_ring; 4489d5c65159SKalle Valo 4490d5c65159SKalle Valo ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4491701e48a4SCarl Huang &sw_cookie, 4492701e48a4SCarl Huang &p_last_buf_addr_info, &rbm, 4493d5c65159SKalle Valo &msdu_cnt); 4494d5c65159SKalle Valo 4495d5c65159SKalle Valo if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4496d5c65159SKalle Valo ent_desc->info1) == 4497d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4498d5c65159SKalle Valo u8 rxdma_err = 4499d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4500d5c65159SKalle Valo ent_desc->info1); 4501d5c65159SKalle Valo if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4502d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4503d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4504d5c65159SKalle Valo drop_mpdu = true; 4505d5c65159SKalle Valo pmon->rx_mon_stats.dest_mpdu_drop++; 4506d5c65159SKalle Valo } 4507d5c65159SKalle Valo } 4508d5c65159SKalle Valo 4509d5c65159SKalle Valo is_frag = false; 4510d5c65159SKalle Valo is_first_msdu = true; 4511d5c65159SKalle Valo 4512d5c65159SKalle Valo do { 4513d5c65159SKalle Valo if (pmon->mon_last_linkdesc_paddr == paddr) { 4514d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4515d5c65159SKalle Valo return rx_bufs_used; 4516d5c65159SKalle Valo } 4517d5c65159SKalle Valo 4518701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 4519d5c65159SKalle Valo rx_msdu_link_desc = 4520d5c65159SKalle Valo (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4521d5c65159SKalle Valo (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4522701e48a4SCarl Huang else 4523701e48a4SCarl Huang rx_msdu_link_desc = 4524701e48a4SCarl Huang (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr + 4525701e48a4SCarl Huang (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr); 4526d5c65159SKalle Valo 4527d5c65159SKalle Valo ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4528d5c65159SKalle Valo &num_msdus); 4529d5c65159SKalle Valo 4530d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4531d5c65159SKalle Valo u32 l2_hdr_offset; 4532d5c65159SKalle Valo 4533d5c65159SKalle Valo if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4534d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4535d5c65159SKalle Valo "i %d last_cookie %d is same\n", 4536d5c65159SKalle Valo i, pmon->mon_last_buf_cookie); 4537d5c65159SKalle Valo drop_mpdu = true; 4538d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_buf_cnt++; 4539d5c65159SKalle Valo continue; 4540d5c65159SKalle Valo } 4541d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4542d5c65159SKalle Valo msdu_list.sw_cookie[i]); 4543d5c65159SKalle Valo 4544d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4545d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4546d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4547d5c65159SKalle Valo if (!msdu) { 4548d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4549d5c65159SKalle Valo "msdu_pop: invalid buf_id %d\n", buf_id); 4550d5c65159SKalle Valo break; 4551d5c65159SKalle Valo } 4552d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 4553d5c65159SKalle Valo if (!rxcb->unmapped) { 4554d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 4555d5c65159SKalle Valo msdu->len + 4556d5c65159SKalle Valo skb_tailroom(msdu), 4557d5c65159SKalle Valo DMA_FROM_DEVICE); 4558d5c65159SKalle Valo rxcb->unmapped = 1; 4559d5c65159SKalle Valo } 4560d5c65159SKalle Valo if (drop_mpdu) { 4561d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4562d5c65159SKalle Valo "i %d drop msdu %p *ppdu_id %x\n", 4563d5c65159SKalle Valo i, msdu, *ppdu_id); 4564d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4565d5c65159SKalle Valo msdu = NULL; 4566d5c65159SKalle Valo goto next_msdu; 4567d5c65159SKalle Valo } 4568d5c65159SKalle Valo 4569d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 4570d5c65159SKalle Valo 4571d5c65159SKalle Valo rx_pkt_offset = sizeof(struct hal_rx_desc); 4572d5c65159SKalle Valo l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(rx_desc); 4573d5c65159SKalle Valo 4574d5c65159SKalle Valo if (is_first_msdu) { 4575d5c65159SKalle Valo if (!ath11k_dp_rxdesc_mpdu_valid(rx_desc)) { 4576d5c65159SKalle Valo drop_mpdu = true; 4577d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4578d5c65159SKalle Valo msdu = NULL; 4579d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4580d5c65159SKalle Valo goto next_msdu; 4581d5c65159SKalle Valo } 4582d5c65159SKalle Valo 4583d5c65159SKalle Valo msdu_ppdu_id = 4584d5c65159SKalle Valo ath11k_dp_rxdesc_get_ppduid(rx_desc); 4585d5c65159SKalle Valo 4586d5c65159SKalle Valo if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4587d5c65159SKalle Valo ppdu_id, 45885e02bc73SMiles Hu &rx_bufs_used)) { 45895e02bc73SMiles Hu if (rx_bufs_used) { 45905e02bc73SMiles Hu drop_mpdu = true; 45915e02bc73SMiles Hu dev_kfree_skb_any(msdu); 45925e02bc73SMiles Hu msdu = NULL; 45935e02bc73SMiles Hu goto next_msdu; 45945e02bc73SMiles Hu } 4595d5c65159SKalle Valo return rx_bufs_used; 45965e02bc73SMiles Hu } 4597d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4598d5c65159SKalle Valo is_first_msdu = false; 4599d5c65159SKalle Valo } 4600d5c65159SKalle Valo ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4601d5c65159SKalle Valo &is_frag, &total_len, 4602d5c65159SKalle Valo &frag_len, &msdu_cnt); 4603d5c65159SKalle Valo rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4604d5c65159SKalle Valo 4605d5c65159SKalle Valo ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4606d5c65159SKalle Valo 4607d5c65159SKalle Valo if (!(*head_msdu)) 4608d5c65159SKalle Valo *head_msdu = msdu; 4609d5c65159SKalle Valo else if (last) 4610d5c65159SKalle Valo last->next = msdu; 4611d5c65159SKalle Valo 4612d5c65159SKalle Valo last = msdu; 4613d5c65159SKalle Valo next_msdu: 4614d5c65159SKalle Valo pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4615d5c65159SKalle Valo rx_bufs_used++; 4616d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4617d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4618d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4619d5c65159SKalle Valo } 4620d5c65159SKalle Valo 4621701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm); 4622701e48a4SCarl Huang 4623d5c65159SKalle Valo ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4624701e48a4SCarl Huang &sw_cookie, &rbm, 4625d5c65159SKalle Valo &p_buf_addr_info); 4626d5c65159SKalle Valo 4627701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4628d5c65159SKalle Valo if (ath11k_dp_rx_monitor_link_desc_return(ar, 4629d5c65159SKalle Valo p_last_buf_addr_info, 4630d5c65159SKalle Valo dp->mac_id)) 4631d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4632d5c65159SKalle Valo "dp_rx_monitor_link_desc_return failed"); 4633701e48a4SCarl Huang } else { 4634701e48a4SCarl Huang ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info, 4635701e48a4SCarl Huang HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4636701e48a4SCarl Huang } 4637d5c65159SKalle Valo 4638d5c65159SKalle Valo p_last_buf_addr_info = p_buf_addr_info; 4639d5c65159SKalle Valo 4640d5c65159SKalle Valo } while (paddr && msdu_cnt); 4641d5c65159SKalle Valo 4642d5c65159SKalle Valo if (last) 4643d5c65159SKalle Valo last->next = NULL; 4644d5c65159SKalle Valo 4645d5c65159SKalle Valo *tail_msdu = msdu; 4646d5c65159SKalle Valo 4647d5c65159SKalle Valo if (msdu_cnt == 0) 4648d5c65159SKalle Valo *npackets = 1; 4649d5c65159SKalle Valo 4650d5c65159SKalle Valo return rx_bufs_used; 4651d5c65159SKalle Valo } 4652d5c65159SKalle Valo 4653d5c65159SKalle Valo static void ath11k_dp_rx_msdus_set_payload(struct sk_buff *msdu) 4654d5c65159SKalle Valo { 4655d5c65159SKalle Valo u32 rx_pkt_offset, l2_hdr_offset; 4656d5c65159SKalle Valo 4657d5c65159SKalle Valo rx_pkt_offset = sizeof(struct hal_rx_desc); 4658d5c65159SKalle Valo l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad((struct hal_rx_desc *)msdu->data); 4659d5c65159SKalle Valo skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4660d5c65159SKalle Valo } 4661d5c65159SKalle Valo 4662d5c65159SKalle Valo static struct sk_buff * 4663d5c65159SKalle Valo ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4664d5c65159SKalle Valo u32 mac_id, struct sk_buff *head_msdu, 4665d5c65159SKalle Valo struct sk_buff *last_msdu, 4666d5c65159SKalle Valo struct ieee80211_rx_status *rxs) 4667d5c65159SKalle Valo { 4668d5c65159SKalle Valo struct sk_buff *msdu, *mpdu_buf, *prev_buf; 4669d5c65159SKalle Valo u32 decap_format, wifi_hdr_len; 4670d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4671d5c65159SKalle Valo char *hdr_desc; 4672d5c65159SKalle Valo u8 *dest; 4673d5c65159SKalle Valo struct ieee80211_hdr_3addr *wh; 4674d5c65159SKalle Valo 4675d5c65159SKalle Valo mpdu_buf = NULL; 4676d5c65159SKalle Valo 4677d5c65159SKalle Valo if (!head_msdu) 4678d5c65159SKalle Valo goto err_merge_fail; 4679d5c65159SKalle Valo 4680d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4681d5c65159SKalle Valo 4682d5c65159SKalle Valo if (ath11k_dp_rxdesc_get_mpdulen_err(rx_desc)) 4683d5c65159SKalle Valo return NULL; 4684d5c65159SKalle Valo 4685d5c65159SKalle Valo decap_format = ath11k_dp_rxdesc_get_decap_format(rx_desc); 4686d5c65159SKalle Valo 4687d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4688d5c65159SKalle Valo 4689d5c65159SKalle Valo if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4690d5c65159SKalle Valo ath11k_dp_rx_msdus_set_payload(head_msdu); 4691d5c65159SKalle Valo 4692d5c65159SKalle Valo prev_buf = head_msdu; 4693d5c65159SKalle Valo msdu = head_msdu->next; 4694d5c65159SKalle Valo 4695d5c65159SKalle Valo while (msdu) { 4696d5c65159SKalle Valo ath11k_dp_rx_msdus_set_payload(msdu); 4697d5c65159SKalle Valo 4698d5c65159SKalle Valo prev_buf = msdu; 4699d5c65159SKalle Valo msdu = msdu->next; 4700d5c65159SKalle Valo } 4701d5c65159SKalle Valo 4702d5c65159SKalle Valo prev_buf->next = NULL; 4703d5c65159SKalle Valo 4704d5c65159SKalle Valo skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4705d5c65159SKalle Valo } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4706d5c65159SKalle Valo __le16 qos_field; 4707d5c65159SKalle Valo u8 qos_pkt = 0; 4708d5c65159SKalle Valo 4709d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4710d5c65159SKalle Valo hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc); 4711d5c65159SKalle Valo 4712d5c65159SKalle Valo /* Base size */ 4713d5c65159SKalle Valo wifi_hdr_len = sizeof(struct ieee80211_hdr_3addr); 4714d5c65159SKalle Valo wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4715d5c65159SKalle Valo 4716d5c65159SKalle Valo if (ieee80211_is_data_qos(wh->frame_control)) { 4717d5c65159SKalle Valo struct ieee80211_qos_hdr *qwh = 4718d5c65159SKalle Valo (struct ieee80211_qos_hdr *)hdr_desc; 4719d5c65159SKalle Valo 4720d5c65159SKalle Valo qos_field = qwh->qos_ctrl; 4721d5c65159SKalle Valo qos_pkt = 1; 4722d5c65159SKalle Valo } 4723d5c65159SKalle Valo msdu = head_msdu; 4724d5c65159SKalle Valo 4725d5c65159SKalle Valo while (msdu) { 4726d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 4727d5c65159SKalle Valo hdr_desc = ath11k_dp_rxdesc_get_80211hdr(rx_desc); 4728d5c65159SKalle Valo 4729d5c65159SKalle Valo if (qos_pkt) { 4730d5c65159SKalle Valo dest = skb_push(msdu, sizeof(__le16)); 4731d5c65159SKalle Valo if (!dest) 4732d5c65159SKalle Valo goto err_merge_fail; 4733d5c65159SKalle Valo memcpy(dest, hdr_desc, wifi_hdr_len); 4734d5c65159SKalle Valo memcpy(dest + wifi_hdr_len, 4735d5c65159SKalle Valo (u8 *)&qos_field, sizeof(__le16)); 4736d5c65159SKalle Valo } 4737d5c65159SKalle Valo ath11k_dp_rx_msdus_set_payload(msdu); 4738d5c65159SKalle Valo prev_buf = msdu; 4739d5c65159SKalle Valo msdu = msdu->next; 4740d5c65159SKalle Valo } 4741d5c65159SKalle Valo dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4742d5c65159SKalle Valo if (!dest) 4743d5c65159SKalle Valo goto err_merge_fail; 4744d5c65159SKalle Valo 4745d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4746d5c65159SKalle Valo "mpdu_buf %pK mpdu_buf->len %u", 4747d5c65159SKalle Valo prev_buf, prev_buf->len); 4748d5c65159SKalle Valo } else { 4749d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4750d5c65159SKalle Valo "decap format %d is not supported!\n", 4751d5c65159SKalle Valo decap_format); 4752d5c65159SKalle Valo goto err_merge_fail; 4753d5c65159SKalle Valo } 4754d5c65159SKalle Valo 4755d5c65159SKalle Valo return head_msdu; 4756d5c65159SKalle Valo 4757d5c65159SKalle Valo err_merge_fail: 4758d5c65159SKalle Valo if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) { 4759d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4760d5c65159SKalle Valo "err_merge_fail mpdu_buf %pK", mpdu_buf); 4761d5c65159SKalle Valo /* Free the head buffer */ 4762d5c65159SKalle Valo dev_kfree_skb_any(mpdu_buf); 4763d5c65159SKalle Valo } 4764d5c65159SKalle Valo return NULL; 4765d5c65159SKalle Valo } 4766d5c65159SKalle Valo 4767d5c65159SKalle Valo static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 4768d5c65159SKalle Valo struct sk_buff *head_msdu, 4769d5c65159SKalle Valo struct sk_buff *tail_msdu, 4770d5c65159SKalle Valo struct napi_struct *napi) 4771d5c65159SKalle Valo { 4772d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4773d5c65159SKalle Valo struct sk_buff *mon_skb, *skb_next, *header; 4774d5c65159SKalle Valo struct ieee80211_rx_status *rxs = &dp->rx_status, *status; 4775d5c65159SKalle Valo 4776d5c65159SKalle Valo mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 4777d5c65159SKalle Valo tail_msdu, rxs); 4778d5c65159SKalle Valo 4779d5c65159SKalle Valo if (!mon_skb) 4780d5c65159SKalle Valo goto mon_deliver_fail; 4781d5c65159SKalle Valo 4782d5c65159SKalle Valo header = mon_skb; 4783d5c65159SKalle Valo 4784d5c65159SKalle Valo rxs->flag = 0; 4785d5c65159SKalle Valo do { 4786d5c65159SKalle Valo skb_next = mon_skb->next; 4787d5c65159SKalle Valo if (!skb_next) 4788d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_AMSDU_MORE; 4789d5c65159SKalle Valo else 4790d5c65159SKalle Valo rxs->flag |= RX_FLAG_AMSDU_MORE; 4791d5c65159SKalle Valo 4792d5c65159SKalle Valo if (mon_skb == header) { 4793d5c65159SKalle Valo header = NULL; 4794d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 4795d5c65159SKalle Valo } else { 4796d5c65159SKalle Valo rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 4797d5c65159SKalle Valo } 4798d5c65159SKalle Valo rxs->flag |= RX_FLAG_ONLY_MONITOR; 4799d5c65159SKalle Valo 4800d5c65159SKalle Valo status = IEEE80211_SKB_RXCB(mon_skb); 4801d5c65159SKalle Valo *status = *rxs; 4802d5c65159SKalle Valo 4803d5c65159SKalle Valo ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb); 4804d5c65159SKalle Valo mon_skb = skb_next; 48055e02bc73SMiles Hu } while (mon_skb); 4806d5c65159SKalle Valo rxs->flag = 0; 4807d5c65159SKalle Valo 4808d5c65159SKalle Valo return 0; 4809d5c65159SKalle Valo 4810d5c65159SKalle Valo mon_deliver_fail: 4811d5c65159SKalle Valo mon_skb = head_msdu; 4812d5c65159SKalle Valo while (mon_skb) { 4813d5c65159SKalle Valo skb_next = mon_skb->next; 4814d5c65159SKalle Valo dev_kfree_skb_any(mon_skb); 4815d5c65159SKalle Valo mon_skb = skb_next; 4816d5c65159SKalle Valo } 4817d5c65159SKalle Valo return -EINVAL; 4818d5c65159SKalle Valo } 4819d5c65159SKalle Valo 4820701e48a4SCarl Huang static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id, 4821701e48a4SCarl Huang u32 quota, struct napi_struct *napi) 4822d5c65159SKalle Valo { 4823d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4824d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4825d5c65159SKalle Valo void *ring_entry; 4826d5c65159SKalle Valo void *mon_dst_srng; 4827d5c65159SKalle Valo u32 ppdu_id; 4828d5c65159SKalle Valo u32 rx_bufs_used; 4829701e48a4SCarl Huang u32 ring_id; 4830d5c65159SKalle Valo struct ath11k_pdev_mon_stats *rx_mon_stats; 4831d5c65159SKalle Valo u32 npackets = 0; 4832d5c65159SKalle Valo 4833701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 4834701e48a4SCarl Huang ring_id = dp->rxdma_mon_dst_ring.ring_id; 4835701e48a4SCarl Huang else 4836701e48a4SCarl Huang ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 4837701e48a4SCarl Huang 4838701e48a4SCarl Huang mon_dst_srng = &ar->ab->hal.srng_list[ring_id]; 4839d5c65159SKalle Valo 4840d5c65159SKalle Valo if (!mon_dst_srng) { 4841d5c65159SKalle Valo ath11k_warn(ar->ab, 4842d5c65159SKalle Valo "HAL Monitor Destination Ring Init Failed -- %pK", 4843d5c65159SKalle Valo mon_dst_srng); 4844d5c65159SKalle Valo return; 4845d5c65159SKalle Valo } 4846d5c65159SKalle Valo 4847d5c65159SKalle Valo spin_lock_bh(&pmon->mon_lock); 4848d5c65159SKalle Valo 4849d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 4850d5c65159SKalle Valo 4851d5c65159SKalle Valo ppdu_id = pmon->mon_ppdu_info.ppdu_id; 4852d5c65159SKalle Valo rx_bufs_used = 0; 4853d5c65159SKalle Valo rx_mon_stats = &pmon->rx_mon_stats; 4854d5c65159SKalle Valo 4855d5c65159SKalle Valo while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 4856d5c65159SKalle Valo struct sk_buff *head_msdu, *tail_msdu; 4857d5c65159SKalle Valo 4858d5c65159SKalle Valo head_msdu = NULL; 4859d5c65159SKalle Valo tail_msdu = NULL; 4860d5c65159SKalle Valo 4861701e48a4SCarl Huang rx_bufs_used += ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry, 4862d5c65159SKalle Valo &head_msdu, 4863d5c65159SKalle Valo &tail_msdu, 4864d5c65159SKalle Valo &npackets, &ppdu_id); 4865d5c65159SKalle Valo 4866d5c65159SKalle Valo if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 4867d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4868d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4869d5c65159SKalle Valo "dest_rx: new ppdu_id %x != status ppdu_id %x", 4870d5c65159SKalle Valo ppdu_id, pmon->mon_ppdu_info.ppdu_id); 4871d5c65159SKalle Valo break; 4872d5c65159SKalle Valo } 4873d5c65159SKalle Valo if (head_msdu && tail_msdu) { 4874d5c65159SKalle Valo ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 4875d5c65159SKalle Valo tail_msdu, napi); 4876d5c65159SKalle Valo rx_mon_stats->dest_mpdu_done++; 4877d5c65159SKalle Valo } 4878d5c65159SKalle Valo 4879d5c65159SKalle Valo ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 4880d5c65159SKalle Valo mon_dst_srng); 4881d5c65159SKalle Valo } 4882d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 4883d5c65159SKalle Valo 4884d5c65159SKalle Valo spin_unlock_bh(&pmon->mon_lock); 4885d5c65159SKalle Valo 4886d5c65159SKalle Valo if (rx_bufs_used) { 4887d5c65159SKalle Valo rx_mon_stats->dest_ppdu_done++; 4888701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 4889d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 4890d5c65159SKalle Valo &dp->rxdma_mon_buf_ring, 4891d5c65159SKalle Valo rx_bufs_used, 489287e8497aSGovind Singh HAL_RX_BUF_RBM_SW3_BM); 4893701e48a4SCarl Huang else 4894701e48a4SCarl Huang ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 4895701e48a4SCarl Huang &dp->rx_refill_buf_ring, 4896701e48a4SCarl Huang rx_bufs_used, 4897701e48a4SCarl Huang HAL_RX_BUF_RBM_SW3_BM); 4898d5c65159SKalle Valo } 4899d5c65159SKalle Valo } 4900d5c65159SKalle Valo 4901d5c65159SKalle Valo static void ath11k_dp_rx_mon_status_process_tlv(struct ath11k *ar, 4902701e48a4SCarl Huang int mac_id, u32 quota, 4903d5c65159SKalle Valo struct napi_struct *napi) 4904d5c65159SKalle Valo { 4905d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4906d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4907d5c65159SKalle Valo struct hal_rx_mon_ppdu_info *ppdu_info; 4908d5c65159SKalle Valo struct sk_buff *status_skb; 4909d5c65159SKalle Valo u32 tlv_status = HAL_TLV_STATUS_BUF_DONE; 4910d5c65159SKalle Valo struct ath11k_pdev_mon_stats *rx_mon_stats; 4911d5c65159SKalle Valo 4912d5c65159SKalle Valo ppdu_info = &pmon->mon_ppdu_info; 4913d5c65159SKalle Valo rx_mon_stats = &pmon->rx_mon_stats; 4914d5c65159SKalle Valo 4915d5c65159SKalle Valo if (pmon->mon_ppdu_status != DP_PPDU_STATUS_START) 4916d5c65159SKalle Valo return; 4917d5c65159SKalle Valo 4918d5c65159SKalle Valo while (!skb_queue_empty(&pmon->rx_status_q)) { 4919d5c65159SKalle Valo status_skb = skb_dequeue(&pmon->rx_status_q); 4920d5c65159SKalle Valo 4921d5c65159SKalle Valo tlv_status = ath11k_hal_rx_parse_mon_status(ar->ab, ppdu_info, 4922d5c65159SKalle Valo status_skb); 4923d5c65159SKalle Valo if (tlv_status == HAL_TLV_STATUS_PPDU_DONE) { 4924d5c65159SKalle Valo rx_mon_stats->status_ppdu_done++; 4925d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 4926701e48a4SCarl Huang ath11k_dp_rx_mon_dest_process(ar, mac_id, quota, napi); 4927d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4928d5c65159SKalle Valo } 4929d5c65159SKalle Valo dev_kfree_skb_any(status_skb); 4930d5c65159SKalle Valo } 4931d5c65159SKalle Valo } 4932d5c65159SKalle Valo 4933d5c65159SKalle Valo static int ath11k_dp_mon_process_rx(struct ath11k_base *ab, int mac_id, 4934d5c65159SKalle Valo struct napi_struct *napi, int budget) 4935d5c65159SKalle Valo { 49364152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 4937d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4938d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4939d5c65159SKalle Valo int num_buffs_reaped = 0; 4940d5c65159SKalle Valo 4941701e48a4SCarl Huang num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ar->ab, mac_id, &budget, 4942d5c65159SKalle Valo &pmon->rx_status_q); 4943d5c65159SKalle Valo if (num_buffs_reaped) 4944701e48a4SCarl Huang ath11k_dp_rx_mon_status_process_tlv(ar, mac_id, budget, napi); 4945d5c65159SKalle Valo 4946d5c65159SKalle Valo return num_buffs_reaped; 4947d5c65159SKalle Valo } 4948d5c65159SKalle Valo 4949d5c65159SKalle Valo int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 4950d5c65159SKalle Valo struct napi_struct *napi, int budget) 4951d5c65159SKalle Valo { 49524152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 4953d5c65159SKalle Valo int ret = 0; 4954d5c65159SKalle Valo 4955d5c65159SKalle Valo if (test_bit(ATH11K_FLAG_MONITOR_ENABLED, &ar->monitor_flags)) 4956d5c65159SKalle Valo ret = ath11k_dp_mon_process_rx(ab, mac_id, napi, budget); 4957d5c65159SKalle Valo else 4958d5c65159SKalle Valo ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 4959d5c65159SKalle Valo return ret; 4960d5c65159SKalle Valo } 4961d5c65159SKalle Valo 4962d5c65159SKalle Valo static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 4963d5c65159SKalle Valo { 4964d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4965d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4966d5c65159SKalle Valo 4967d5c65159SKalle Valo skb_queue_head_init(&pmon->rx_status_q); 4968d5c65159SKalle Valo 4969d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4970d5c65159SKalle Valo 4971d5c65159SKalle Valo memset(&pmon->rx_mon_stats, 0, 4972d5c65159SKalle Valo sizeof(pmon->rx_mon_stats)); 4973d5c65159SKalle Valo return 0; 4974d5c65159SKalle Valo } 4975d5c65159SKalle Valo 4976d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 4977d5c65159SKalle Valo { 4978d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4979d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 4980d5c65159SKalle Valo struct hal_srng *mon_desc_srng = NULL; 4981d5c65159SKalle Valo struct dp_srng *dp_srng; 4982d5c65159SKalle Valo int ret = 0; 4983d5c65159SKalle Valo u32 n_link_desc = 0; 4984d5c65159SKalle Valo 4985d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 4986d5c65159SKalle Valo if (ret) { 4987d5c65159SKalle Valo ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4988d5c65159SKalle Valo return ret; 4989d5c65159SKalle Valo } 4990d5c65159SKalle Valo 49917f6fc1ebSCarl Huang /* if rxdma1_enable is false, no need to setup 49927f6fc1ebSCarl Huang * rxdma_mon_desc_ring. 49937f6fc1ebSCarl Huang */ 49947f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 49957f6fc1ebSCarl Huang return 0; 49967f6fc1ebSCarl Huang 4997d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 4998d5c65159SKalle Valo n_link_desc = dp_srng->size / 4999f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC); 5000d5c65159SKalle Valo mon_desc_srng = 5001d5c65159SKalle Valo &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 5002d5c65159SKalle Valo 5003d5c65159SKalle Valo ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 5004d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 5005d5c65159SKalle Valo n_link_desc); 5006d5c65159SKalle Valo if (ret) { 5007d5c65159SKalle Valo ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 5008d5c65159SKalle Valo return ret; 5009d5c65159SKalle Valo } 5010d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = 0; 5011d5c65159SKalle Valo pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 5012d5c65159SKalle Valo spin_lock_init(&pmon->mon_lock); 50137f6fc1ebSCarl Huang 5014d5c65159SKalle Valo return 0; 5015d5c65159SKalle Valo } 5016d5c65159SKalle Valo 5017d5c65159SKalle Valo static int ath11k_dp_mon_link_free(struct ath11k *ar) 5018d5c65159SKalle Valo { 5019d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5020d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 5021d5c65159SKalle Valo 5022d5c65159SKalle Valo ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 5023d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 5024d5c65159SKalle Valo &dp->rxdma_mon_desc_ring); 5025d5c65159SKalle Valo return 0; 5026d5c65159SKalle Valo } 5027d5c65159SKalle Valo 5028d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 5029d5c65159SKalle Valo { 5030d5c65159SKalle Valo ath11k_dp_mon_link_free(ar); 5031d5c65159SKalle Valo return 0; 5032d5c65159SKalle Valo } 5033