1d5c65159SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #include <linux/ieee80211.h> 7acc79d98SSriram R #include <linux/kernel.h> 8acc79d98SSriram R #include <linux/skbuff.h> 9243874c6SManikanta Pubbisetty #include <crypto/hash.h> 10d5c65159SKalle Valo #include "core.h" 11d5c65159SKalle Valo #include "debug.h" 12568f0603SKalle Valo #include "debugfs_htt_stats.h" 13568f0603SKalle Valo #include "debugfs_sta.h" 14d5c65159SKalle Valo #include "hal_desc.h" 15d5c65159SKalle Valo #include "hw.h" 16d5c65159SKalle Valo #include "dp_rx.h" 17d5c65159SKalle Valo #include "hal_rx.h" 18d5c65159SKalle Valo #include "dp_tx.h" 19d5c65159SKalle Valo #include "peer.h" 20d5c65159SKalle Valo 21243874c6SManikanta Pubbisetty #define ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22243874c6SManikanta Pubbisetty 235e76fe03SP Praneesh static inline 245e76fe03SP Praneesh u8 *ath11k_dp_rx_h_80211_hdr(struct ath11k_base *ab, struct hal_rx_desc *desc) 25d5c65159SKalle Valo { 26e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_hdr_status(desc); 27d5c65159SKalle Valo } 28d5c65159SKalle Valo 295e76fe03SP Praneesh static inline 305e76fe03SP Praneesh enum hal_encrypt_type ath11k_dp_rx_h_mpdu_start_enctype(struct ath11k_base *ab, 31e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 32d5c65159SKalle Valo { 33e678fbd4SKarthikeyan Periyasamy if (!ab->hw_params.hw_ops->rx_desc_encrypt_valid(desc)) 34d5c65159SKalle Valo return HAL_ENCRYPT_TYPE_OPEN; 35d5c65159SKalle Valo 36e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_encrypt_type(desc); 37d5c65159SKalle Valo } 38d5c65159SKalle Valo 395e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_decap_type(struct ath11k_base *ab, 40e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 41d5c65159SKalle Valo { 42e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_decap_type(desc); 43243874c6SManikanta Pubbisetty } 44243874c6SManikanta Pubbisetty 455e76fe03SP Praneesh static inline 46b3febdccSP Praneesh bool ath11k_dp_rx_h_msdu_start_ldpc_support(struct ath11k_base *ab, 47b3febdccSP Praneesh struct hal_rx_desc *desc) 48b3febdccSP Praneesh { 49b3febdccSP Praneesh return ab->hw_params.hw_ops->rx_desc_get_ldpc_support(desc); 50b3febdccSP Praneesh } 51b3febdccSP Praneesh 52b3febdccSP Praneesh static inline 535e76fe03SP Praneesh u8 ath11k_dp_rx_h_msdu_start_mesh_ctl_present(struct ath11k_base *ab, 54e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 55acc79d98SSriram R { 56e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mesh_ctl(desc); 57acc79d98SSriram R } 58acc79d98SSriram R 595e76fe03SP Praneesh static inline 605e76fe03SP Praneesh bool ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(struct ath11k_base *ab, 61e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 62243874c6SManikanta Pubbisetty { 63e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 64243874c6SManikanta Pubbisetty } 65243874c6SManikanta Pubbisetty 665e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_mpdu_start_fc_valid(struct ath11k_base *ab, 67e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 68243874c6SManikanta Pubbisetty { 69e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_fc_valid(desc); 70243874c6SManikanta Pubbisetty } 71243874c6SManikanta Pubbisetty 725e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_mpdu_start_more_frags(struct ath11k_base *ab, 73e678fbd4SKarthikeyan Periyasamy struct sk_buff *skb) 74243874c6SManikanta Pubbisetty { 75243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 76243874c6SManikanta Pubbisetty 77e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 78243874c6SManikanta Pubbisetty return ieee80211_has_morefrags(hdr->frame_control); 79243874c6SManikanta Pubbisetty } 80243874c6SManikanta Pubbisetty 815e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_frag_no(struct ath11k_base *ab, 82e678fbd4SKarthikeyan Periyasamy struct sk_buff *skb) 83243874c6SManikanta Pubbisetty { 84243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 85243874c6SManikanta Pubbisetty 86e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params.hal_desc_sz); 87243874c6SManikanta Pubbisetty return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 88243874c6SManikanta Pubbisetty } 89243874c6SManikanta Pubbisetty 905e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_seq_no(struct ath11k_base *ab, 91e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 92243874c6SManikanta Pubbisetty { 93e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_start_seq_no(desc); 94d5c65159SKalle Valo } 95d5c65159SKalle Valo 965e76fe03SP Praneesh static inline void *ath11k_dp_rx_get_attention(struct ath11k_base *ab, 97e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 98e678fbd4SKarthikeyan Periyasamy { 99e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_attention(desc); 100e678fbd4SKarthikeyan Periyasamy } 101e678fbd4SKarthikeyan Periyasamy 1025e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_msdu_done(struct rx_attention *attn) 103d5c65159SKalle Valo { 104d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO2_MSDU_DONE, 105e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info2)); 106d5c65159SKalle Valo } 107d5c65159SKalle Valo 1085e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_l4_cksum_fail(struct rx_attention *attn) 109d5c65159SKalle Valo { 110d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL, 111e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 112d5c65159SKalle Valo } 113d5c65159SKalle Valo 1145e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_ip_cksum_fail(struct rx_attention *attn) 115d5c65159SKalle Valo { 116d5c65159SKalle Valo return !!FIELD_GET(RX_ATTENTION_INFO1_IP_CKSUM_FAIL, 117e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 118d5c65159SKalle Valo } 119d5c65159SKalle Valo 1205e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_attn_is_decrypted(struct rx_attention *attn) 121d5c65159SKalle Valo { 122d5c65159SKalle Valo return (FIELD_GET(RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE, 123e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info2)) == 124d5c65159SKalle Valo RX_DESC_DECRYPT_STATUS_CODE_OK); 125d5c65159SKalle Valo } 126d5c65159SKalle Valo 127e678fbd4SKarthikeyan Periyasamy static u32 ath11k_dp_rx_h_attn_mpdu_err(struct rx_attention *attn) 128d5c65159SKalle Valo { 129e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(attn->info1); 130d5c65159SKalle Valo u32 errmap = 0; 131d5c65159SKalle Valo 132d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_FCS_ERR) 133d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_FCS; 134d5c65159SKalle Valo 135d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_DECRYPT_ERR) 136d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_DECRYPT; 137d5c65159SKalle Valo 138d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_TKIP_MIC_ERR) 139d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_TKIP_MIC; 140d5c65159SKalle Valo 141d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_A_MSDU_ERROR) 142d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_AMSDU_ERR; 143d5c65159SKalle Valo 144d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_OVERFLOW_ERR) 145d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_OVERFLOW; 146d5c65159SKalle Valo 147d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MSDU_LEN_ERR) 148d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MSDU_LEN; 149d5c65159SKalle Valo 150d5c65159SKalle Valo if (info & RX_ATTENTION_INFO1_MPDU_LEN_ERR) 151d5c65159SKalle Valo errmap |= DP_RX_MPDU_ERR_MPDU_LEN; 152d5c65159SKalle Valo 153d5c65159SKalle Valo return errmap; 154d5c65159SKalle Valo } 155d5c65159SKalle Valo 156cd18ed4cSBaochen Qiang static bool ath11k_dp_rx_h_attn_msdu_len_err(struct ath11k_base *ab, 157cd18ed4cSBaochen Qiang struct hal_rx_desc *desc) 158cd18ed4cSBaochen Qiang { 159cd18ed4cSBaochen Qiang struct rx_attention *rx_attention; 160cd18ed4cSBaochen Qiang u32 errmap; 161cd18ed4cSBaochen Qiang 162cd18ed4cSBaochen Qiang rx_attention = ath11k_dp_rx_get_attention(ab, desc); 163cd18ed4cSBaochen Qiang errmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 164cd18ed4cSBaochen Qiang 165cd18ed4cSBaochen Qiang return errmap & DP_RX_MPDU_ERR_MSDU_LEN; 166cd18ed4cSBaochen Qiang } 167cd18ed4cSBaochen Qiang 1685e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_msdu_start_msdu_len(struct ath11k_base *ab, 169e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 170d5c65159SKalle Valo { 171e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_len(desc); 172d5c65159SKalle Valo } 173d5c65159SKalle Valo 1745e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_sgi(struct ath11k_base *ab, 175e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 176d5c65159SKalle Valo { 177e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_sgi(desc); 178d5c65159SKalle Valo } 179d5c65159SKalle Valo 1805e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_rate_mcs(struct ath11k_base *ab, 181e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 182d5c65159SKalle Valo { 183e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_rate_mcs(desc); 184d5c65159SKalle Valo } 185d5c65159SKalle Valo 1865e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_rx_bw(struct ath11k_base *ab, 187e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 188d5c65159SKalle Valo { 189e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_rx_bw(desc); 190d5c65159SKalle Valo } 191d5c65159SKalle Valo 1925e76fe03SP Praneesh static inline u32 ath11k_dp_rx_h_msdu_start_freq(struct ath11k_base *ab, 193e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 194d5c65159SKalle Valo { 195e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_freq(desc); 196d5c65159SKalle Valo } 197d5c65159SKalle Valo 1985e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_pkt_type(struct ath11k_base *ab, 199e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 200d5c65159SKalle Valo { 201e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_msdu_pkt_type(desc); 202d5c65159SKalle Valo } 203d5c65159SKalle Valo 2045e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_start_nss(struct ath11k_base *ab, 205e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 206d5c65159SKalle Valo { 207e678fbd4SKarthikeyan Periyasamy return hweight8(ab->hw_params.hw_ops->rx_desc_get_msdu_nss(desc)); 208d5c65159SKalle Valo } 209d5c65159SKalle Valo 2105e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_mpdu_start_tid(struct ath11k_base *ab, 211e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 212243874c6SManikanta Pubbisetty { 213e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_tid(desc); 214243874c6SManikanta Pubbisetty } 215243874c6SManikanta Pubbisetty 2165e76fe03SP Praneesh static inline u16 ath11k_dp_rx_h_mpdu_start_peer_id(struct ath11k_base *ab, 217e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 218243874c6SManikanta Pubbisetty { 219e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_peer_id(desc); 220243874c6SManikanta Pubbisetty } 221243874c6SManikanta Pubbisetty 2225e76fe03SP Praneesh static inline u8 ath11k_dp_rx_h_msdu_end_l3pad(struct ath11k_base *ab, 223e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 224d5c65159SKalle Valo { 225e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_l3_pad_bytes(desc); 226d5c65159SKalle Valo } 227d5c65159SKalle Valo 2285e76fe03SP Praneesh static inline bool ath11k_dp_rx_h_msdu_end_first_msdu(struct ath11k_base *ab, 229e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 230d5c65159SKalle Valo { 231e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_first_msdu(desc); 232d5c65159SKalle Valo } 233d5c65159SKalle Valo 234e678fbd4SKarthikeyan Periyasamy static bool ath11k_dp_rx_h_msdu_end_last_msdu(struct ath11k_base *ab, 235e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc) 236d5c65159SKalle Valo { 237e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_last_msdu(desc); 238d5c65159SKalle Valo } 239d5c65159SKalle Valo 240e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_desc_end_tlv_copy(struct ath11k_base *ab, 241e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *fdesc, 242d5c65159SKalle Valo struct hal_rx_desc *ldesc) 243d5c65159SKalle Valo { 244e678fbd4SKarthikeyan Periyasamy ab->hw_params.hw_ops->rx_desc_copy_attn_end_tlv(fdesc, ldesc); 245d5c65159SKalle Valo } 246d5c65159SKalle Valo 2475e76fe03SP Praneesh static inline u32 ath11k_dp_rxdesc_get_mpdulen_err(struct rx_attention *attn) 248d5c65159SKalle Valo { 249d5c65159SKalle Valo return FIELD_GET(RX_ATTENTION_INFO1_MPDU_LEN_ERR, 250e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(attn->info1)); 251d5c65159SKalle Valo } 252d5c65159SKalle Valo 2535e76fe03SP Praneesh static inline u8 *ath11k_dp_rxdesc_get_80211hdr(struct ath11k_base *ab, 254e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 255d5c65159SKalle Valo { 256d5c65159SKalle Valo u8 *rx_pkt_hdr; 257d5c65159SKalle Valo 258e678fbd4SKarthikeyan Periyasamy rx_pkt_hdr = ab->hw_params.hw_ops->rx_desc_get_msdu_payload(rx_desc); 259d5c65159SKalle Valo 260d5c65159SKalle Valo return rx_pkt_hdr; 261d5c65159SKalle Valo } 262d5c65159SKalle Valo 2635e76fe03SP Praneesh static inline bool ath11k_dp_rxdesc_mpdu_valid(struct ath11k_base *ab, 264e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 265d5c65159SKalle Valo { 266d5c65159SKalle Valo u32 tlv_tag; 267d5c65159SKalle Valo 268e678fbd4SKarthikeyan Periyasamy tlv_tag = ab->hw_params.hw_ops->rx_desc_get_mpdu_start_tag(rx_desc); 269d5c65159SKalle Valo 2708af40902SJason Yan return tlv_tag == HAL_RX_MPDU_START; 271d5c65159SKalle Valo } 272d5c65159SKalle Valo 2735e76fe03SP Praneesh static inline u32 ath11k_dp_rxdesc_get_ppduid(struct ath11k_base *ab, 274e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *rx_desc) 275d5c65159SKalle Valo { 276e678fbd4SKarthikeyan Periyasamy return ab->hw_params.hw_ops->rx_desc_get_mpdu_ppdu_id(rx_desc); 277e678fbd4SKarthikeyan Periyasamy } 278e678fbd4SKarthikeyan Periyasamy 2795e76fe03SP Praneesh static inline void ath11k_dp_rxdesc_set_msdu_len(struct ath11k_base *ab, 280e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *desc, 281e678fbd4SKarthikeyan Periyasamy u16 len) 282e678fbd4SKarthikeyan Periyasamy { 283e678fbd4SKarthikeyan Periyasamy ab->hw_params.hw_ops->rx_desc_set_msdu_len(desc, len); 284d5c65159SKalle Valo } 285d5c65159SKalle Valo 286210f563bSSriram R static bool ath11k_dp_rx_h_attn_is_mcbc(struct ath11k_base *ab, 287210f563bSSriram R struct hal_rx_desc *desc) 288210f563bSSriram R { 289210f563bSSriram R struct rx_attention *attn = ath11k_dp_rx_get_attention(ab, desc); 290210f563bSSriram R 291210f563bSSriram R return ath11k_dp_rx_h_msdu_end_first_msdu(ab, desc) && 292210f563bSSriram R (!!FIELD_GET(RX_ATTENTION_INFO1_MCAST_BCAST, 293210f563bSSriram R __le32_to_cpu(attn->info1))); 294210f563bSSriram R } 295210f563bSSriram R 2962167fa60SSriram R static bool ath11k_dp_rxdesc_mac_addr2_valid(struct ath11k_base *ab, 2972167fa60SSriram R struct hal_rx_desc *desc) 2982167fa60SSriram R { 2992167fa60SSriram R return ab->hw_params.hw_ops->rx_desc_mac_addr2_valid(desc); 3002167fa60SSriram R } 3012167fa60SSriram R 3022167fa60SSriram R static u8 *ath11k_dp_rxdesc_mpdu_start_addr2(struct ath11k_base *ab, 3032167fa60SSriram R struct hal_rx_desc *desc) 3042167fa60SSriram R { 3052167fa60SSriram R return ab->hw_params.hw_ops->rx_desc_mpdu_start_addr2(desc); 3062167fa60SSriram R } 3072167fa60SSriram R 308701e48a4SCarl Huang static void ath11k_dp_service_mon_ring(struct timer_list *t) 309701e48a4SCarl Huang { 310701e48a4SCarl Huang struct ath11k_base *ab = from_timer(ab, t, mon_reap_timer); 311701e48a4SCarl Huang int i; 312701e48a4SCarl Huang 313701e48a4SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 314701e48a4SCarl Huang ath11k_dp_rx_process_mon_rings(ab, i, NULL, DP_MON_SERVICE_BUDGET); 315701e48a4SCarl Huang 316701e48a4SCarl Huang mod_timer(&ab->mon_reap_timer, jiffies + 317701e48a4SCarl Huang msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 318701e48a4SCarl Huang } 319701e48a4SCarl Huang 320840c36faSCarl Huang static int ath11k_dp_purge_mon_ring(struct ath11k_base *ab) 321840c36faSCarl Huang { 322840c36faSCarl Huang int i, reaped = 0; 323840c36faSCarl Huang unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 324840c36faSCarl Huang 325840c36faSCarl Huang do { 326840c36faSCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) 327840c36faSCarl Huang reaped += ath11k_dp_rx_process_mon_rings(ab, i, 328840c36faSCarl Huang NULL, 329840c36faSCarl Huang DP_MON_SERVICE_BUDGET); 330840c36faSCarl Huang 331840c36faSCarl Huang /* nothing more to reap */ 332840c36faSCarl Huang if (reaped < DP_MON_SERVICE_BUDGET) 333840c36faSCarl Huang return 0; 334840c36faSCarl Huang 335840c36faSCarl Huang } while (time_before(jiffies, timeout)); 336840c36faSCarl Huang 337840c36faSCarl Huang ath11k_warn(ab, "dp mon ring purge timeout"); 338840c36faSCarl Huang 339840c36faSCarl Huang return -ETIMEDOUT; 340840c36faSCarl Huang } 341840c36faSCarl Huang 342d5c65159SKalle Valo /* Returns number of Rx buffers replenished */ 343d5c65159SKalle Valo int ath11k_dp_rxbufs_replenish(struct ath11k_base *ab, int mac_id, 344d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 345d5c65159SKalle Valo int req_entries, 34687e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 347d5c65159SKalle Valo { 348d5c65159SKalle Valo struct hal_srng *srng; 349d5c65159SKalle Valo u32 *desc; 350d5c65159SKalle Valo struct sk_buff *skb; 351d5c65159SKalle Valo int num_free; 352d5c65159SKalle Valo int num_remain; 353d5c65159SKalle Valo int buf_id; 354d5c65159SKalle Valo u32 cookie; 355d5c65159SKalle Valo dma_addr_t paddr; 356d5c65159SKalle Valo 357d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 358d5c65159SKalle Valo 359d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 360d5c65159SKalle Valo 361d5c65159SKalle Valo spin_lock_bh(&srng->lock); 362d5c65159SKalle Valo 363d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 364d5c65159SKalle Valo 365d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 366d5c65159SKalle Valo if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 367d5c65159SKalle Valo req_entries = num_free; 368d5c65159SKalle Valo 369d5c65159SKalle Valo req_entries = min(num_free, req_entries); 370d5c65159SKalle Valo num_remain = req_entries; 371d5c65159SKalle Valo 372d5c65159SKalle Valo while (num_remain > 0) { 373d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 374d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 375d5c65159SKalle Valo if (!skb) 376d5c65159SKalle Valo break; 377d5c65159SKalle Valo 378d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 379d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 380d5c65159SKalle Valo skb_pull(skb, 381d5c65159SKalle Valo PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 382d5c65159SKalle Valo skb->data); 383d5c65159SKalle Valo } 384d5c65159SKalle Valo 385d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 386d5c65159SKalle Valo skb->len + skb_tailroom(skb), 387d5c65159SKalle Valo DMA_FROM_DEVICE); 388d5c65159SKalle Valo if (dma_mapping_error(ab->dev, paddr)) 389d5c65159SKalle Valo goto fail_free_skb; 390d5c65159SKalle Valo 391d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 392d5c65159SKalle Valo buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 39387e8497aSGovind Singh rx_ring->bufs_max * 3, GFP_ATOMIC); 394d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 395d5c65159SKalle Valo if (buf_id < 0) 396d5c65159SKalle Valo goto fail_dma_unmap; 397d5c65159SKalle Valo 398d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 399d5c65159SKalle Valo if (!desc) 400d5c65159SKalle Valo goto fail_idr_remove; 401d5c65159SKalle Valo 402d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 403d5c65159SKalle Valo 404d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 405d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 406d5c65159SKalle Valo 407d5c65159SKalle Valo num_remain--; 408d5c65159SKalle Valo 409d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 410d5c65159SKalle Valo } 411d5c65159SKalle Valo 412d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 413d5c65159SKalle Valo 414d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 415d5c65159SKalle Valo 416d5c65159SKalle Valo return req_entries - num_remain; 417d5c65159SKalle Valo 418d5c65159SKalle Valo fail_idr_remove: 419d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 420d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 421d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 422d5c65159SKalle Valo fail_dma_unmap: 423d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 424d5c65159SKalle Valo DMA_FROM_DEVICE); 425d5c65159SKalle Valo fail_free_skb: 426d5c65159SKalle Valo dev_kfree_skb_any(skb); 427d5c65159SKalle Valo 428d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 429d5c65159SKalle Valo 430d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 431d5c65159SKalle Valo 432d5c65159SKalle Valo return req_entries - num_remain; 433d5c65159SKalle Valo } 434d5c65159SKalle Valo 435d5c65159SKalle Valo static int ath11k_dp_rxdma_buf_ring_free(struct ath11k *ar, 436d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring) 437d5c65159SKalle Valo { 438d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 439d5c65159SKalle Valo struct sk_buff *skb; 440d5c65159SKalle Valo int buf_id; 441d5c65159SKalle Valo 442d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 443d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 444d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 44516f283f0SKalle Valo /* TODO: Understand where internal driver does this dma_unmap 446d5c65159SKalle Valo * of rxdma_buffer. 447d5c65159SKalle Valo */ 448d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 449d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 450d5c65159SKalle Valo dev_kfree_skb_any(skb); 451d5c65159SKalle Valo } 452d5c65159SKalle Valo 453d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 454d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 455d5c65159SKalle Valo 4567f6fc1ebSCarl Huang /* if rxdma1_enable is false, mon_status_refill_ring 4577f6fc1ebSCarl Huang * isn't setup, so don't clean. 4587f6fc1ebSCarl Huang */ 4597f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 4607f6fc1ebSCarl Huang return 0; 4617f6fc1ebSCarl Huang 4624152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[0]; 463d5c65159SKalle Valo 464d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 465d5c65159SKalle Valo idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 466d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 46716f283f0SKalle Valo /* XXX: Understand where internal driver does this dma_unmap 468d5c65159SKalle Valo * of rxdma_buffer. 469d5c65159SKalle Valo */ 470d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, ATH11K_SKB_RXCB(skb)->paddr, 471d5c65159SKalle Valo skb->len + skb_tailroom(skb), DMA_BIDIRECTIONAL); 472d5c65159SKalle Valo dev_kfree_skb_any(skb); 473d5c65159SKalle Valo } 474d5c65159SKalle Valo 475d5c65159SKalle Valo idr_destroy(&rx_ring->bufs_idr); 476d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4777f6fc1ebSCarl Huang 478d5c65159SKalle Valo return 0; 479d5c65159SKalle Valo } 480d5c65159SKalle Valo 481d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_free(struct ath11k *ar) 482d5c65159SKalle Valo { 483d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4844152e420SCarl Huang struct ath11k_base *ab = ar->ab; 485d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 4864152e420SCarl Huang int i; 487d5c65159SKalle Valo 488d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 489d5c65159SKalle Valo 490d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 491d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 492d5c65159SKalle Valo 4934152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 4944152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 495d5c65159SKalle Valo ath11k_dp_rxdma_buf_ring_free(ar, rx_ring); 4964152e420SCarl Huang } 4974152e420SCarl Huang 498d5c65159SKalle Valo return 0; 499d5c65159SKalle Valo } 500d5c65159SKalle Valo 501d5c65159SKalle Valo static int ath11k_dp_rxdma_ring_buf_setup(struct ath11k *ar, 502d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 503d5c65159SKalle Valo u32 ringtype) 504d5c65159SKalle Valo { 505d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 506d5c65159SKalle Valo int num_entries; 507d5c65159SKalle Valo 508d5c65159SKalle Valo num_entries = rx_ring->refill_buf_ring.size / 509f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, ringtype); 510d5c65159SKalle Valo 511d5c65159SKalle Valo rx_ring->bufs_max = num_entries; 512d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, rx_ring, num_entries, 513734223d7SBaochen Qiang ar->ab->hw_params.hal_params->rx_buf_rbm); 514d5c65159SKalle Valo return 0; 515d5c65159SKalle Valo } 516d5c65159SKalle Valo 517d5c65159SKalle Valo static int ath11k_dp_rxdma_pdev_buf_setup(struct ath11k *ar) 518d5c65159SKalle Valo { 519d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5204152e420SCarl Huang struct ath11k_base *ab = ar->ab; 521d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 5224152e420SCarl Huang int i; 523d5c65159SKalle Valo 524d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_BUF); 525d5c65159SKalle Valo 5267f6fc1ebSCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 527d5c65159SKalle Valo rx_ring = &dp->rxdma_mon_buf_ring; 528d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_BUF); 5297f6fc1ebSCarl Huang } 530d5c65159SKalle Valo 5314152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5324152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[i]; 533d5c65159SKalle Valo ath11k_dp_rxdma_ring_buf_setup(ar, rx_ring, HAL_RXDMA_MONITOR_STATUS); 5344152e420SCarl Huang } 535d5c65159SKalle Valo 536d5c65159SKalle Valo return 0; 537d5c65159SKalle Valo } 538d5c65159SKalle Valo 539d5c65159SKalle Valo static void ath11k_dp_rx_pdev_srng_free(struct ath11k *ar) 540d5c65159SKalle Valo { 541d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5424152e420SCarl Huang struct ath11k_base *ab = ar->ab; 5434152e420SCarl Huang int i; 544d5c65159SKalle Valo 5454152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 5464152e420SCarl Huang 5474152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 5484152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) 5494152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 5504152e420SCarl Huang 5514152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 5524152e420SCarl Huang ath11k_dp_srng_cleanup(ab, 5534152e420SCarl Huang &dp->rx_mon_status_refill_ring[i].refill_buf_ring); 5544152e420SCarl Huang } 5554152e420SCarl Huang 5564152e420SCarl Huang ath11k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 557d5c65159SKalle Valo } 558d5c65159SKalle Valo 5599c57d7e3SVasanthakumar Thiagarajan void ath11k_dp_pdev_reo_cleanup(struct ath11k_base *ab) 5609c57d7e3SVasanthakumar Thiagarajan { 561acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 5629c57d7e3SVasanthakumar Thiagarajan int i; 5639c57d7e3SVasanthakumar Thiagarajan 564acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) 565acc79d98SSriram R ath11k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 5669c57d7e3SVasanthakumar Thiagarajan } 5679c57d7e3SVasanthakumar Thiagarajan 5689c57d7e3SVasanthakumar Thiagarajan int ath11k_dp_pdev_reo_setup(struct ath11k_base *ab) 5699c57d7e3SVasanthakumar Thiagarajan { 570acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 5719c57d7e3SVasanthakumar Thiagarajan int ret; 5729c57d7e3SVasanthakumar Thiagarajan int i; 5739c57d7e3SVasanthakumar Thiagarajan 574acc79d98SSriram R for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 575acc79d98SSriram R ret = ath11k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 576acc79d98SSriram R HAL_REO_DST, i, 0, 5779c57d7e3SVasanthakumar Thiagarajan DP_REO_DST_RING_SIZE); 5789c57d7e3SVasanthakumar Thiagarajan if (ret) { 579acc79d98SSriram R ath11k_warn(ab, "failed to setup reo_dst_ring\n"); 5809c57d7e3SVasanthakumar Thiagarajan goto err_reo_cleanup; 5819c57d7e3SVasanthakumar Thiagarajan } 5829c57d7e3SVasanthakumar Thiagarajan } 5839c57d7e3SVasanthakumar Thiagarajan 5849c57d7e3SVasanthakumar Thiagarajan return 0; 5859c57d7e3SVasanthakumar Thiagarajan 5869c57d7e3SVasanthakumar Thiagarajan err_reo_cleanup: 5879c57d7e3SVasanthakumar Thiagarajan ath11k_dp_pdev_reo_cleanup(ab); 5889c57d7e3SVasanthakumar Thiagarajan 5899c57d7e3SVasanthakumar Thiagarajan return ret; 5909c57d7e3SVasanthakumar Thiagarajan } 5919c57d7e3SVasanthakumar Thiagarajan 592d5c65159SKalle Valo static int ath11k_dp_rx_pdev_srng_alloc(struct ath11k *ar) 593d5c65159SKalle Valo { 594d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5954152e420SCarl Huang struct ath11k_base *ab = ar->ab; 596d5c65159SKalle Valo struct dp_srng *srng = NULL; 5974152e420SCarl Huang int i; 598d5c65159SKalle Valo int ret; 599d5c65159SKalle Valo 600d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 601d5c65159SKalle Valo &dp->rx_refill_buf_ring.refill_buf_ring, 602d5c65159SKalle Valo HAL_RXDMA_BUF, 0, 603d5c65159SKalle Valo dp->mac_id, DP_RXDMA_BUF_RING_SIZE); 604d5c65159SKalle Valo if (ret) { 605d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx_refill_buf_ring\n"); 606d5c65159SKalle Valo return ret; 607d5c65159SKalle Valo } 608d5c65159SKalle Valo 6094152e420SCarl Huang if (ar->ab->hw_params.rx_mac_buf_ring) { 6104152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6114152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, 6124152e420SCarl Huang &dp->rx_mac_buf_ring[i], 6134152e420SCarl Huang HAL_RXDMA_BUF, 1, 6144152e420SCarl Huang dp->mac_id + i, 1024); 615d5c65159SKalle Valo if (ret) { 6164152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rx_mac_buf_ring %d\n", 6174152e420SCarl Huang i); 618d5c65159SKalle Valo return ret; 619d5c65159SKalle Valo } 6204152e420SCarl Huang } 6214152e420SCarl Huang } 622d5c65159SKalle Valo 6234152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6244152e420SCarl Huang ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_err_dst_ring[i], 6254152e420SCarl Huang HAL_RXDMA_DST, 0, dp->mac_id + i, 6264152e420SCarl Huang DP_RXDMA_ERR_DST_RING_SIZE); 6274152e420SCarl Huang if (ret) { 6284152e420SCarl Huang ath11k_warn(ar->ab, "failed to setup rxdma_err_dst_ring %d\n", i); 6294152e420SCarl Huang return ret; 6304152e420SCarl Huang } 6314152e420SCarl Huang } 6324152e420SCarl Huang 6334152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 6344152e420SCarl Huang srng = &dp->rx_mon_status_refill_ring[i].refill_buf_ring; 635d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 636d5c65159SKalle Valo srng, 6374152e420SCarl Huang HAL_RXDMA_MONITOR_STATUS, 0, dp->mac_id + i, 638d5c65159SKalle Valo DP_RXDMA_MON_STATUS_RING_SIZE); 639d5c65159SKalle Valo if (ret) { 640d5c65159SKalle Valo ath11k_warn(ar->ab, 6414152e420SCarl Huang "failed to setup rx_mon_status_refill_ring %d\n", i); 642d5c65159SKalle Valo return ret; 643d5c65159SKalle Valo } 6444152e420SCarl Huang } 6457f6fc1ebSCarl Huang 6467f6fc1ebSCarl Huang /* if rxdma1_enable is false, then it doesn't need 6477f6fc1ebSCarl Huang * to setup rxdam_mon_buf_ring, rxdma_mon_dst_ring 6487f6fc1ebSCarl Huang * and rxdma_mon_desc_ring. 649701e48a4SCarl Huang * init reap timer for QCA6390. 6507f6fc1ebSCarl Huang */ 651701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) { 652701e48a4SCarl Huang //init mon status buffer reap timer 653701e48a4SCarl Huang timer_setup(&ar->ab->mon_reap_timer, 654701e48a4SCarl Huang ath11k_dp_service_mon_ring, 0); 6557f6fc1ebSCarl Huang return 0; 656701e48a4SCarl Huang } 6577f6fc1ebSCarl Huang 658d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, 659d5c65159SKalle Valo &dp->rxdma_mon_buf_ring.refill_buf_ring, 660d5c65159SKalle Valo HAL_RXDMA_MONITOR_BUF, 0, dp->mac_id, 661d5c65159SKalle Valo DP_RXDMA_MONITOR_BUF_RING_SIZE); 662d5c65159SKalle Valo if (ret) { 663d5c65159SKalle Valo ath11k_warn(ar->ab, 664d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 665d5c65159SKalle Valo return ret; 666d5c65159SKalle Valo } 667d5c65159SKalle Valo 668d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_dst_ring, 669d5c65159SKalle Valo HAL_RXDMA_MONITOR_DST, 0, dp->mac_id, 670d5c65159SKalle Valo DP_RXDMA_MONITOR_DST_RING_SIZE); 671d5c65159SKalle Valo if (ret) { 672d5c65159SKalle Valo ath11k_warn(ar->ab, 673d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DST\n"); 674d5c65159SKalle Valo return ret; 675d5c65159SKalle Valo } 676d5c65159SKalle Valo 677d5c65159SKalle Valo ret = ath11k_dp_srng_setup(ar->ab, &dp->rxdma_mon_desc_ring, 678d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 0, dp->mac_id, 679d5c65159SKalle Valo DP_RXDMA_MONITOR_DESC_RING_SIZE); 680d5c65159SKalle Valo if (ret) { 681d5c65159SKalle Valo ath11k_warn(ar->ab, 682d5c65159SKalle Valo "failed to setup HAL_RXDMA_MONITOR_DESC\n"); 683d5c65159SKalle Valo return ret; 684d5c65159SKalle Valo } 685d5c65159SKalle Valo 686d5c65159SKalle Valo return 0; 687d5c65159SKalle Valo } 688d5c65159SKalle Valo 689d5c65159SKalle Valo void ath11k_dp_reo_cmd_list_cleanup(struct ath11k_base *ab) 690d5c65159SKalle Valo { 691d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 692d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 693d5c65159SKalle Valo struct dp_reo_cache_flush_elem *cmd_cache, *tmp_cache; 694d5c65159SKalle Valo 695d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 696d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 697d5c65159SKalle Valo list_del(&cmd->list); 698d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd->data.paddr, 699d5c65159SKalle Valo cmd->data.size, DMA_BIDIRECTIONAL); 700d5c65159SKalle Valo kfree(cmd->data.vaddr); 701d5c65159SKalle Valo kfree(cmd); 702d5c65159SKalle Valo } 703d5c65159SKalle Valo 704d5c65159SKalle Valo list_for_each_entry_safe(cmd_cache, tmp_cache, 705d5c65159SKalle Valo &dp->reo_cmd_cache_flush_list, list) { 706d5c65159SKalle Valo list_del(&cmd_cache->list); 7075cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 708d5c65159SKalle Valo dma_unmap_single(ab->dev, cmd_cache->data.paddr, 709d5c65159SKalle Valo cmd_cache->data.size, DMA_BIDIRECTIONAL); 710d5c65159SKalle Valo kfree(cmd_cache->data.vaddr); 711d5c65159SKalle Valo kfree(cmd_cache); 712d5c65159SKalle Valo } 713d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 714d5c65159SKalle Valo } 715d5c65159SKalle Valo 716d5c65159SKalle Valo static void ath11k_dp_reo_cmd_free(struct ath11k_dp *dp, void *ctx, 717d5c65159SKalle Valo enum hal_reo_cmd_status status) 718d5c65159SKalle Valo { 719d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 720d5c65159SKalle Valo 721d5c65159SKalle Valo if (status != HAL_REO_CMD_SUCCESS) 722d5c65159SKalle Valo ath11k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 723d5c65159SKalle Valo rx_tid->tid, status); 724d5c65159SKalle Valo 725d5c65159SKalle Valo dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 726d5c65159SKalle Valo DMA_BIDIRECTIONAL); 727d5c65159SKalle Valo kfree(rx_tid->vaddr); 728d5c65159SKalle Valo } 729d5c65159SKalle Valo 730d5c65159SKalle Valo static void ath11k_dp_reo_cache_flush(struct ath11k_base *ab, 731d5c65159SKalle Valo struct dp_rx_tid *rx_tid) 732d5c65159SKalle Valo { 733d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 734d5c65159SKalle Valo unsigned long tot_desc_sz, desc_sz; 735d5c65159SKalle Valo int ret; 736d5c65159SKalle Valo 737d5c65159SKalle Valo tot_desc_sz = rx_tid->size; 738d5c65159SKalle Valo desc_sz = ath11k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 739d5c65159SKalle Valo 740d5c65159SKalle Valo while (tot_desc_sz > desc_sz) { 741d5c65159SKalle Valo tot_desc_sz -= desc_sz; 742d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 743d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 744d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 745d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, &cmd, 746d5c65159SKalle Valo NULL); 747d5c65159SKalle Valo if (ret) 748d5c65159SKalle Valo ath11k_warn(ab, 749d5c65159SKalle Valo "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 750d5c65159SKalle Valo rx_tid->tid, ret); 751d5c65159SKalle Valo } 752d5c65159SKalle Valo 753d5c65159SKalle Valo memset(&cmd, 0, sizeof(cmd)); 754d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 755d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 756d5c65159SKalle Valo cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 757d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 758d5c65159SKalle Valo HAL_REO_CMD_FLUSH_CACHE, 759d5c65159SKalle Valo &cmd, ath11k_dp_reo_cmd_free); 760d5c65159SKalle Valo if (ret) { 761d5c65159SKalle Valo ath11k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 762d5c65159SKalle Valo rx_tid->tid, ret); 763d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 764d5c65159SKalle Valo DMA_BIDIRECTIONAL); 765d5c65159SKalle Valo kfree(rx_tid->vaddr); 766d5c65159SKalle Valo } 767d5c65159SKalle Valo } 768d5c65159SKalle Valo 769d5c65159SKalle Valo static void ath11k_dp_rx_tid_del_func(struct ath11k_dp *dp, void *ctx, 770d5c65159SKalle Valo enum hal_reo_cmd_status status) 771d5c65159SKalle Valo { 772d5c65159SKalle Valo struct ath11k_base *ab = dp->ab; 773d5c65159SKalle Valo struct dp_rx_tid *rx_tid = ctx; 774d5c65159SKalle Valo struct dp_reo_cache_flush_elem *elem, *tmp; 775d5c65159SKalle Valo 776d5c65159SKalle Valo if (status == HAL_REO_CMD_DRAIN) { 777d5c65159SKalle Valo goto free_desc; 778d5c65159SKalle Valo } else if (status != HAL_REO_CMD_SUCCESS) { 779d5c65159SKalle Valo /* Shouldn't happen! Cleanup in case of other failure? */ 780d5c65159SKalle Valo ath11k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 781d5c65159SKalle Valo rx_tid->tid, status); 782d5c65159SKalle Valo return; 783d5c65159SKalle Valo } 784d5c65159SKalle Valo 785d5c65159SKalle Valo elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 786d5c65159SKalle Valo if (!elem) 787d5c65159SKalle Valo goto free_desc; 788d5c65159SKalle Valo 789d5c65159SKalle Valo elem->ts = jiffies; 790d5c65159SKalle Valo memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 791d5c65159SKalle Valo 792d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 793d5c65159SKalle Valo list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 7945cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count++; 795d5c65159SKalle Valo 796d5c65159SKalle Valo /* Flush and invalidate aged REO desc from HW cache */ 797d5c65159SKalle Valo list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 798d5c65159SKalle Valo list) { 7995cb899ddSKarthikeyan Periyasamy if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || 8005cb899ddSKarthikeyan Periyasamy time_after(jiffies, elem->ts + 801d5c65159SKalle Valo msecs_to_jiffies(DP_REO_DESC_FREE_TIMEOUT_MS))) { 802d5c65159SKalle Valo list_del(&elem->list); 8035cb899ddSKarthikeyan Periyasamy dp->reo_cmd_cache_flush_count--; 804d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 805d5c65159SKalle Valo 806d5c65159SKalle Valo ath11k_dp_reo_cache_flush(ab, &elem->data); 807d5c65159SKalle Valo kfree(elem); 808d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 809d5c65159SKalle Valo } 810d5c65159SKalle Valo } 811d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 812d5c65159SKalle Valo 813d5c65159SKalle Valo return; 814d5c65159SKalle Valo free_desc: 815d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 816d5c65159SKalle Valo DMA_BIDIRECTIONAL); 817d5c65159SKalle Valo kfree(rx_tid->vaddr); 818d5c65159SKalle Valo } 819d5c65159SKalle Valo 820a36adf54SGovindaraj Saminathan void ath11k_peer_rx_tid_delete(struct ath11k *ar, 821d5c65159SKalle Valo struct ath11k_peer *peer, u8 tid) 822d5c65159SKalle Valo { 823d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 824d5c65159SKalle Valo struct dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 825d5c65159SKalle Valo int ret; 826d5c65159SKalle Valo 827d5c65159SKalle Valo if (!rx_tid->active) 828d5c65159SKalle Valo return; 829d5c65159SKalle Valo 830d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 831d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 832d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 833d5c65159SKalle Valo cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; 834d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 835d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 836d5c65159SKalle Valo ath11k_dp_rx_tid_del_func); 837d5c65159SKalle Valo if (ret) { 838d5c65159SKalle Valo ath11k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 839d5c65159SKalle Valo tid, ret); 840d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 841d5c65159SKalle Valo DMA_BIDIRECTIONAL); 842d5c65159SKalle Valo kfree(rx_tid->vaddr); 843d5c65159SKalle Valo } 844d5c65159SKalle Valo 845d5c65159SKalle Valo rx_tid->active = false; 846d5c65159SKalle Valo } 847d5c65159SKalle Valo 848243874c6SManikanta Pubbisetty static int ath11k_dp_rx_link_desc_return(struct ath11k_base *ab, 849243874c6SManikanta Pubbisetty u32 *link_desc, 850243874c6SManikanta Pubbisetty enum hal_wbm_rel_bm_act action) 851243874c6SManikanta Pubbisetty { 852243874c6SManikanta Pubbisetty struct ath11k_dp *dp = &ab->dp; 853243874c6SManikanta Pubbisetty struct hal_srng *srng; 854243874c6SManikanta Pubbisetty u32 *desc; 855243874c6SManikanta Pubbisetty int ret = 0; 856243874c6SManikanta Pubbisetty 857243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 858243874c6SManikanta Pubbisetty 859243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 860243874c6SManikanta Pubbisetty 861243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 862243874c6SManikanta Pubbisetty 863243874c6SManikanta Pubbisetty desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 864243874c6SManikanta Pubbisetty if (!desc) { 865243874c6SManikanta Pubbisetty ret = -ENOBUFS; 866243874c6SManikanta Pubbisetty goto exit; 867243874c6SManikanta Pubbisetty } 868243874c6SManikanta Pubbisetty 869243874c6SManikanta Pubbisetty ath11k_hal_rx_msdu_link_desc_set(ab, (void *)desc, (void *)link_desc, 870243874c6SManikanta Pubbisetty action); 871243874c6SManikanta Pubbisetty 872243874c6SManikanta Pubbisetty exit: 873243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 874243874c6SManikanta Pubbisetty 875243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 876243874c6SManikanta Pubbisetty 877243874c6SManikanta Pubbisetty return ret; 878243874c6SManikanta Pubbisetty } 879243874c6SManikanta Pubbisetty 880243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frags_cleanup(struct dp_rx_tid *rx_tid, bool rel_link_desc) 881243874c6SManikanta Pubbisetty { 882243874c6SManikanta Pubbisetty struct ath11k_base *ab = rx_tid->ab; 883243874c6SManikanta Pubbisetty 884243874c6SManikanta Pubbisetty lockdep_assert_held(&ab->base_lock); 885243874c6SManikanta Pubbisetty 886243874c6SManikanta Pubbisetty if (rx_tid->dst_ring_desc) { 887243874c6SManikanta Pubbisetty if (rel_link_desc) 888243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, (u32 *)rx_tid->dst_ring_desc, 889243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 890243874c6SManikanta Pubbisetty kfree(rx_tid->dst_ring_desc); 891243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = NULL; 892243874c6SManikanta Pubbisetty } 893243874c6SManikanta Pubbisetty 894243874c6SManikanta Pubbisetty rx_tid->cur_sn = 0; 895243874c6SManikanta Pubbisetty rx_tid->last_frag_no = 0; 896243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap = 0; 897243874c6SManikanta Pubbisetty __skb_queue_purge(&rx_tid->rx_frags); 898243874c6SManikanta Pubbisetty } 899243874c6SManikanta Pubbisetty 900c3944a56SSriram R void ath11k_peer_frags_flush(struct ath11k *ar, struct ath11k_peer *peer) 901c3944a56SSriram R { 902c3944a56SSriram R struct dp_rx_tid *rx_tid; 903c3944a56SSriram R int i; 904c3944a56SSriram R 905c3944a56SSriram R lockdep_assert_held(&ar->ab->base_lock); 906c3944a56SSriram R 907c3944a56SSriram R for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 908c3944a56SSriram R rx_tid = &peer->rx_tid[i]; 909c3944a56SSriram R 910c3944a56SSriram R spin_unlock_bh(&ar->ab->base_lock); 911c3944a56SSriram R del_timer_sync(&rx_tid->frag_timer); 912c3944a56SSriram R spin_lock_bh(&ar->ab->base_lock); 913c3944a56SSriram R 914c3944a56SSriram R ath11k_dp_rx_frags_cleanup(rx_tid, true); 915c3944a56SSriram R } 916c3944a56SSriram R } 917c3944a56SSriram R 918d5c65159SKalle Valo void ath11k_peer_rx_tid_cleanup(struct ath11k *ar, struct ath11k_peer *peer) 919d5c65159SKalle Valo { 920243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 921d5c65159SKalle Valo int i; 922d5c65159SKalle Valo 923243874c6SManikanta Pubbisetty lockdep_assert_held(&ar->ab->base_lock); 924243874c6SManikanta Pubbisetty 925243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 926243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 927243874c6SManikanta Pubbisetty 928d5c65159SKalle Valo ath11k_peer_rx_tid_delete(ar, peer, i); 929243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 930243874c6SManikanta Pubbisetty 931243874c6SManikanta Pubbisetty spin_unlock_bh(&ar->ab->base_lock); 932243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 933243874c6SManikanta Pubbisetty spin_lock_bh(&ar->ab->base_lock); 934243874c6SManikanta Pubbisetty } 935d5c65159SKalle Valo } 936d5c65159SKalle Valo 937d5c65159SKalle Valo static int ath11k_peer_rx_tid_reo_update(struct ath11k *ar, 938d5c65159SKalle Valo struct ath11k_peer *peer, 939d5c65159SKalle Valo struct dp_rx_tid *rx_tid, 940fe201947SVenkateswara Naralasetty u32 ba_win_sz, u16 ssn, 941fe201947SVenkateswara Naralasetty bool update_ssn) 942d5c65159SKalle Valo { 943d5c65159SKalle Valo struct ath11k_hal_reo_cmd cmd = {0}; 944d5c65159SKalle Valo int ret; 945d5c65159SKalle Valo 946d5c65159SKalle Valo cmd.addr_lo = lower_32_bits(rx_tid->paddr); 947d5c65159SKalle Valo cmd.addr_hi = upper_32_bits(rx_tid->paddr); 948d5c65159SKalle Valo cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 949fe201947SVenkateswara Naralasetty cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 950d5c65159SKalle Valo cmd.ba_window_size = ba_win_sz; 951fe201947SVenkateswara Naralasetty 952fe201947SVenkateswara Naralasetty if (update_ssn) { 953fe201947SVenkateswara Naralasetty cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 954d5c65159SKalle Valo cmd.upd2 = FIELD_PREP(HAL_REO_CMD_UPD2_SSN, ssn); 955fe201947SVenkateswara Naralasetty } 956d5c65159SKalle Valo 957d5c65159SKalle Valo ret = ath11k_dp_tx_send_reo_cmd(ar->ab, rx_tid, 958d5c65159SKalle Valo HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 959d5c65159SKalle Valo NULL); 960d5c65159SKalle Valo if (ret) { 961d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 962d5c65159SKalle Valo rx_tid->tid, ret); 963d5c65159SKalle Valo return ret; 964d5c65159SKalle Valo } 965d5c65159SKalle Valo 966d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 967d5c65159SKalle Valo 968d5c65159SKalle Valo return 0; 969d5c65159SKalle Valo } 970d5c65159SKalle Valo 971d5c65159SKalle Valo static void ath11k_dp_rx_tid_mem_free(struct ath11k_base *ab, 972d5c65159SKalle Valo const u8 *peer_mac, int vdev_id, u8 tid) 973d5c65159SKalle Valo { 974d5c65159SKalle Valo struct ath11k_peer *peer; 975d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 976d5c65159SKalle Valo 977d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 978d5c65159SKalle Valo 979d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 980d5c65159SKalle Valo if (!peer) { 981d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to free up rx tid mem\n"); 982d5c65159SKalle Valo goto unlock_exit; 983d5c65159SKalle Valo } 984d5c65159SKalle Valo 985d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 986d5c65159SKalle Valo if (!rx_tid->active) 987d5c65159SKalle Valo goto unlock_exit; 988d5c65159SKalle Valo 989d5c65159SKalle Valo dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 990d5c65159SKalle Valo DMA_BIDIRECTIONAL); 991d5c65159SKalle Valo kfree(rx_tid->vaddr); 992d5c65159SKalle Valo 993d5c65159SKalle Valo rx_tid->active = false; 994d5c65159SKalle Valo 995d5c65159SKalle Valo unlock_exit: 996d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 997d5c65159SKalle Valo } 998d5c65159SKalle Valo 999d5c65159SKalle Valo int ath11k_peer_rx_tid_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id, 10001441b2f2SManikanta Pubbisetty u8 tid, u32 ba_win_sz, u16 ssn, 10011441b2f2SManikanta Pubbisetty enum hal_pn_type pn_type) 1002d5c65159SKalle Valo { 1003d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1004d5c65159SKalle Valo struct ath11k_peer *peer; 1005d5c65159SKalle Valo struct dp_rx_tid *rx_tid; 1006d5c65159SKalle Valo u32 hw_desc_sz; 1007d5c65159SKalle Valo u32 *addr_aligned; 1008d5c65159SKalle Valo void *vaddr; 1009d5c65159SKalle Valo dma_addr_t paddr; 1010d5c65159SKalle Valo int ret; 1011d5c65159SKalle Valo 1012d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1013d5c65159SKalle Valo 1014d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, peer_mac); 1015d5c65159SKalle Valo if (!peer) { 1016d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to set up rx tid\n"); 1017d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1018d5c65159SKalle Valo return -ENOENT; 1019d5c65159SKalle Valo } 1020d5c65159SKalle Valo 1021d5c65159SKalle Valo rx_tid = &peer->rx_tid[tid]; 1022d5c65159SKalle Valo /* Update the tid queue if it is already setup */ 1023d5c65159SKalle Valo if (rx_tid->active) { 1024d5c65159SKalle Valo paddr = rx_tid->paddr; 1025d5c65159SKalle Valo ret = ath11k_peer_rx_tid_reo_update(ar, peer, rx_tid, 1026fe201947SVenkateswara Naralasetty ba_win_sz, ssn, true); 1027d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1028d5c65159SKalle Valo if (ret) { 1029d5c65159SKalle Valo ath11k_warn(ab, "failed to update reo for rx tid %d\n", tid); 1030d5c65159SKalle Valo return ret; 1031d5c65159SKalle Valo } 1032d5c65159SKalle Valo 1033d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1034d5c65159SKalle Valo peer_mac, paddr, 1035d5c65159SKalle Valo tid, 1, ba_win_sz); 1036d5c65159SKalle Valo if (ret) 1037d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi command to update rx reorder queue, tid :%d (%d)\n", 1038d5c65159SKalle Valo tid, ret); 1039d5c65159SKalle Valo return ret; 1040d5c65159SKalle Valo } 1041d5c65159SKalle Valo 1042d5c65159SKalle Valo rx_tid->tid = tid; 1043d5c65159SKalle Valo 1044d5c65159SKalle Valo rx_tid->ba_win_sz = ba_win_sz; 1045d5c65159SKalle Valo 104616f283f0SKalle Valo /* TODO: Optimize the memory allocation for qos tid based on 1047d5c65159SKalle Valo * the actual BA window size in REO tid update path. 1048d5c65159SKalle Valo */ 1049d5c65159SKalle Valo if (tid == HAL_DESC_REO_NON_QOS_TID) 1050d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(ba_win_sz, tid); 1051d5c65159SKalle Valo else 1052d5c65159SKalle Valo hw_desc_sz = ath11k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1053d5c65159SKalle Valo 105469c93f96SWei Yongjun vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1055d5c65159SKalle Valo if (!vaddr) { 1056d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1057d5c65159SKalle Valo return -ENOMEM; 1058d5c65159SKalle Valo } 1059d5c65159SKalle Valo 1060d5c65159SKalle Valo addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1061d5c65159SKalle Valo 10621441b2f2SManikanta Pubbisetty ath11k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 10631441b2f2SManikanta Pubbisetty ssn, pn_type); 1064d5c65159SKalle Valo 1065d5c65159SKalle Valo paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1066d5c65159SKalle Valo DMA_BIDIRECTIONAL); 1067d5c65159SKalle Valo 1068d5c65159SKalle Valo ret = dma_mapping_error(ab->dev, paddr); 1069d5c65159SKalle Valo if (ret) { 1070d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1071d5c65159SKalle Valo goto err_mem_free; 1072d5c65159SKalle Valo } 1073d5c65159SKalle Valo 1074d5c65159SKalle Valo rx_tid->vaddr = vaddr; 1075d5c65159SKalle Valo rx_tid->paddr = paddr; 1076d5c65159SKalle Valo rx_tid->size = hw_desc_sz; 1077d5c65159SKalle Valo rx_tid->active = true; 1078d5c65159SKalle Valo 1079d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1080d5c65159SKalle Valo 1081d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1082d5c65159SKalle Valo paddr, tid, 1, ba_win_sz); 1083d5c65159SKalle Valo if (ret) { 1084d5c65159SKalle Valo ath11k_warn(ar->ab, "failed to setup rx reorder queue, tid :%d (%d)\n", 1085d5c65159SKalle Valo tid, ret); 1086d5c65159SKalle Valo ath11k_dp_rx_tid_mem_free(ab, peer_mac, vdev_id, tid); 1087d5c65159SKalle Valo } 1088d5c65159SKalle Valo 1089d5c65159SKalle Valo return ret; 1090d5c65159SKalle Valo 1091d5c65159SKalle Valo err_mem_free: 1092d5c65159SKalle Valo kfree(vaddr); 1093d5c65159SKalle Valo 1094d5c65159SKalle Valo return ret; 1095d5c65159SKalle Valo } 1096d5c65159SKalle Valo 1097d5c65159SKalle Valo int ath11k_dp_rx_ampdu_start(struct ath11k *ar, 1098d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1099d5c65159SKalle Valo { 1100d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1101d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1102d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1103d5c65159SKalle Valo int ret; 1104d5c65159SKalle Valo 1105d5c65159SKalle Valo ret = ath11k_peer_rx_tid_setup(ar, params->sta->addr, vdev_id, 1106d5c65159SKalle Valo params->tid, params->buf_size, 11071441b2f2SManikanta Pubbisetty params->ssn, arsta->pn_type); 1108d5c65159SKalle Valo if (ret) 1109d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx tid %d\n", ret); 1110d5c65159SKalle Valo 1111d5c65159SKalle Valo return ret; 1112d5c65159SKalle Valo } 1113d5c65159SKalle Valo 1114d5c65159SKalle Valo int ath11k_dp_rx_ampdu_stop(struct ath11k *ar, 1115d5c65159SKalle Valo struct ieee80211_ampdu_params *params) 1116d5c65159SKalle Valo { 1117d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1118d5c65159SKalle Valo struct ath11k_peer *peer; 1119d5c65159SKalle Valo struct ath11k_sta *arsta = (void *)params->sta->drv_priv; 1120d5c65159SKalle Valo int vdev_id = arsta->arvif->vdev_id; 1121d5c65159SKalle Valo dma_addr_t paddr; 1122d5c65159SKalle Valo bool active; 1123d5c65159SKalle Valo int ret; 1124d5c65159SKalle Valo 1125d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1126d5c65159SKalle Valo 1127d5c65159SKalle Valo peer = ath11k_peer_find(ab, vdev_id, params->sta->addr); 1128d5c65159SKalle Valo if (!peer) { 1129d5c65159SKalle Valo ath11k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1130d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1131d5c65159SKalle Valo return -ENOENT; 1132d5c65159SKalle Valo } 1133d5c65159SKalle Valo 1134d5c65159SKalle Valo paddr = peer->rx_tid[params->tid].paddr; 1135d5c65159SKalle Valo active = peer->rx_tid[params->tid].active; 1136d5c65159SKalle Valo 1137fe201947SVenkateswara Naralasetty if (!active) { 1138d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1139d5c65159SKalle Valo return 0; 1140fe201947SVenkateswara Naralasetty } 1141fe201947SVenkateswara Naralasetty 1142fe201947SVenkateswara Naralasetty ret = ath11k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1143fe201947SVenkateswara Naralasetty spin_unlock_bh(&ab->base_lock); 1144fe201947SVenkateswara Naralasetty if (ret) { 1145fe201947SVenkateswara Naralasetty ath11k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1146fe201947SVenkateswara Naralasetty params->tid, ret); 1147fe201947SVenkateswara Naralasetty return ret; 1148fe201947SVenkateswara Naralasetty } 1149d5c65159SKalle Valo 1150d5c65159SKalle Valo ret = ath11k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 1151d5c65159SKalle Valo params->sta->addr, paddr, 1152d5c65159SKalle Valo params->tid, 1, 1); 1153d5c65159SKalle Valo if (ret) 1154d5c65159SKalle Valo ath11k_warn(ab, "failed to send wmi to delete rx tid %d\n", 1155d5c65159SKalle Valo ret); 1156d5c65159SKalle Valo 1157d5c65159SKalle Valo return ret; 1158d5c65159SKalle Valo } 1159d5c65159SKalle Valo 11601441b2f2SManikanta Pubbisetty int ath11k_dp_peer_rx_pn_replay_config(struct ath11k_vif *arvif, 11611441b2f2SManikanta Pubbisetty const u8 *peer_addr, 11621441b2f2SManikanta Pubbisetty enum set_key_cmd key_cmd, 11631441b2f2SManikanta Pubbisetty struct ieee80211_key_conf *key) 11641441b2f2SManikanta Pubbisetty { 11651441b2f2SManikanta Pubbisetty struct ath11k *ar = arvif->ar; 11661441b2f2SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 11671441b2f2SManikanta Pubbisetty struct ath11k_hal_reo_cmd cmd = {0}; 11681441b2f2SManikanta Pubbisetty struct ath11k_peer *peer; 11691441b2f2SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 11701441b2f2SManikanta Pubbisetty u8 tid; 11711441b2f2SManikanta Pubbisetty int ret = 0; 11721441b2f2SManikanta Pubbisetty 11731441b2f2SManikanta Pubbisetty /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 11741441b2f2SManikanta Pubbisetty * We use mac80211 PN/TSC replay check functionality for bcast/mcast 11751441b2f2SManikanta Pubbisetty * for now. 11761441b2f2SManikanta Pubbisetty */ 11771441b2f2SManikanta Pubbisetty if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 11781441b2f2SManikanta Pubbisetty return 0; 11791441b2f2SManikanta Pubbisetty 11801441b2f2SManikanta Pubbisetty cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS; 11811441b2f2SManikanta Pubbisetty cmd.upd0 |= HAL_REO_CMD_UPD0_PN | 11821441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_SIZE | 11831441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_VALID | 11841441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_PN_CHECK | 11851441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPD0_SVLD; 11861441b2f2SManikanta Pubbisetty 11871441b2f2SManikanta Pubbisetty switch (key->cipher) { 11881441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_TKIP: 11891441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP: 11901441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_CCMP_256: 11911441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP: 11921441b2f2SManikanta Pubbisetty case WLAN_CIPHER_SUITE_GCMP_256: 11931441b2f2SManikanta Pubbisetty if (key_cmd == SET_KEY) { 11941441b2f2SManikanta Pubbisetty cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 11951441b2f2SManikanta Pubbisetty cmd.pn_size = 48; 11961441b2f2SManikanta Pubbisetty } 11971441b2f2SManikanta Pubbisetty break; 11981441b2f2SManikanta Pubbisetty default: 11991441b2f2SManikanta Pubbisetty break; 12001441b2f2SManikanta Pubbisetty } 12011441b2f2SManikanta Pubbisetty 12021441b2f2SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 12031441b2f2SManikanta Pubbisetty 12041441b2f2SManikanta Pubbisetty peer = ath11k_peer_find(ab, arvif->vdev_id, peer_addr); 12051441b2f2SManikanta Pubbisetty if (!peer) { 12061441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to configure pn replay detection\n"); 12071441b2f2SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 12081441b2f2SManikanta Pubbisetty return -ENOENT; 12091441b2f2SManikanta Pubbisetty } 12101441b2f2SManikanta Pubbisetty 12111441b2f2SManikanta Pubbisetty for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 12121441b2f2SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 12131441b2f2SManikanta Pubbisetty if (!rx_tid->active) 12141441b2f2SManikanta Pubbisetty continue; 12151441b2f2SManikanta Pubbisetty cmd.addr_lo = lower_32_bits(rx_tid->paddr); 12161441b2f2SManikanta Pubbisetty cmd.addr_hi = upper_32_bits(rx_tid->paddr); 12171441b2f2SManikanta Pubbisetty ret = ath11k_dp_tx_send_reo_cmd(ab, rx_tid, 12181441b2f2SManikanta Pubbisetty HAL_REO_CMD_UPDATE_RX_QUEUE, 12191441b2f2SManikanta Pubbisetty &cmd, NULL); 12201441b2f2SManikanta Pubbisetty if (ret) { 12211441b2f2SManikanta Pubbisetty ath11k_warn(ab, "failed to configure rx tid %d queue for pn replay detection %d\n", 12221441b2f2SManikanta Pubbisetty tid, ret); 12231441b2f2SManikanta Pubbisetty break; 12241441b2f2SManikanta Pubbisetty } 12251441b2f2SManikanta Pubbisetty } 12261441b2f2SManikanta Pubbisetty 1227abdcd4cbSDan Carpenter spin_unlock_bh(&ab->base_lock); 12281441b2f2SManikanta Pubbisetty 12291441b2f2SManikanta Pubbisetty return ret; 12301441b2f2SManikanta Pubbisetty } 12311441b2f2SManikanta Pubbisetty 12321441b2f2SManikanta Pubbisetty static inline int ath11k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1233d5c65159SKalle Valo u16 peer_id) 1234d5c65159SKalle Valo { 1235d5c65159SKalle Valo int i; 1236d5c65159SKalle Valo 1237d5c65159SKalle Valo for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1238d5c65159SKalle Valo if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1239d5c65159SKalle Valo if (peer_id == ppdu_stats->user_stats[i].peer_id) 1240d5c65159SKalle Valo return i; 1241d5c65159SKalle Valo } else { 1242d5c65159SKalle Valo return i; 1243d5c65159SKalle Valo } 1244d5c65159SKalle Valo } 1245d5c65159SKalle Valo 1246d5c65159SKalle Valo return -EINVAL; 1247d5c65159SKalle Valo } 1248d5c65159SKalle Valo 1249d5c65159SKalle Valo static int ath11k_htt_tlv_ppdu_stats_parse(struct ath11k_base *ab, 1250d5c65159SKalle Valo u16 tag, u16 len, const void *ptr, 1251d5c65159SKalle Valo void *data) 1252d5c65159SKalle Valo { 1253d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1254d5c65159SKalle Valo struct htt_ppdu_user_stats *user_stats; 1255d5c65159SKalle Valo int cur_user; 1256d5c65159SKalle Valo u16 peer_id; 1257d5c65159SKalle Valo 1258d5c65159SKalle Valo ppdu_info = (struct htt_ppdu_stats_info *)data; 1259d5c65159SKalle Valo 1260d5c65159SKalle Valo switch (tag) { 1261d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_COMMON: 1262d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_common)) { 1263d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1264d5c65159SKalle Valo len, tag); 1265d5c65159SKalle Valo return -EINVAL; 1266d5c65159SKalle Valo } 1267d5c65159SKalle Valo memcpy((void *)&ppdu_info->ppdu_stats.common, ptr, 1268d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_common)); 1269d5c65159SKalle Valo break; 1270d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_RATE: 1271d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1272d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1273d5c65159SKalle Valo len, tag); 1274d5c65159SKalle Valo return -EINVAL; 1275d5c65159SKalle Valo } 1276d5c65159SKalle Valo 1277d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_user_rate *)ptr)->sw_peer_id; 1278d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1279d5c65159SKalle Valo peer_id); 1280d5c65159SKalle Valo if (cur_user < 0) 1281d5c65159SKalle Valo return -EINVAL; 1282d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1283d5c65159SKalle Valo user_stats->peer_id = peer_id; 1284d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1285d5c65159SKalle Valo memcpy((void *)&user_stats->rate, ptr, 1286d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_user_rate)); 1287d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1288d5c65159SKalle Valo break; 1289d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1290d5c65159SKalle Valo if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1291d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1292d5c65159SKalle Valo len, tag); 1293d5c65159SKalle Valo return -EINVAL; 1294d5c65159SKalle Valo } 1295d5c65159SKalle Valo 1296d5c65159SKalle Valo peer_id = ((struct htt_ppdu_stats_usr_cmpltn_cmn *)ptr)->sw_peer_id; 1297d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1298d5c65159SKalle Valo peer_id); 1299d5c65159SKalle Valo if (cur_user < 0) 1300d5c65159SKalle Valo return -EINVAL; 1301d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1302d5c65159SKalle Valo user_stats->peer_id = peer_id; 1303d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1304d5c65159SKalle Valo memcpy((void *)&user_stats->cmpltn_cmn, ptr, 1305d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1306d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1307d5c65159SKalle Valo break; 1308d5c65159SKalle Valo case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1309d5c65159SKalle Valo if (len < 1310d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1311d5c65159SKalle Valo ath11k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1312d5c65159SKalle Valo len, tag); 1313d5c65159SKalle Valo return -EINVAL; 1314d5c65159SKalle Valo } 1315d5c65159SKalle Valo 1316d5c65159SKalle Valo peer_id = 1317d5c65159SKalle Valo ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->sw_peer_id; 1318d5c65159SKalle Valo cur_user = ath11k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1319d5c65159SKalle Valo peer_id); 1320d5c65159SKalle Valo if (cur_user < 0) 1321d5c65159SKalle Valo return -EINVAL; 1322d5c65159SKalle Valo user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1323d5c65159SKalle Valo user_stats->peer_id = peer_id; 1324d5c65159SKalle Valo user_stats->is_valid_peer_id = true; 1325d5c65159SKalle Valo memcpy((void *)&user_stats->ack_ba, ptr, 1326d5c65159SKalle Valo sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1327d5c65159SKalle Valo user_stats->tlv_flags |= BIT(tag); 1328d5c65159SKalle Valo break; 1329d5c65159SKalle Valo } 1330d5c65159SKalle Valo return 0; 1331d5c65159SKalle Valo } 1332d5c65159SKalle Valo 1333d5c65159SKalle Valo int ath11k_dp_htt_tlv_iter(struct ath11k_base *ab, const void *ptr, size_t len, 1334d5c65159SKalle Valo int (*iter)(struct ath11k_base *ar, u16 tag, u16 len, 1335d5c65159SKalle Valo const void *ptr, void *data), 1336d5c65159SKalle Valo void *data) 1337d5c65159SKalle Valo { 1338d5c65159SKalle Valo const struct htt_tlv *tlv; 1339d5c65159SKalle Valo const void *begin = ptr; 1340d5c65159SKalle Valo u16 tlv_tag, tlv_len; 1341d5c65159SKalle Valo int ret = -EINVAL; 1342d5c65159SKalle Valo 1343d5c65159SKalle Valo while (len > 0) { 1344d5c65159SKalle Valo if (len < sizeof(*tlv)) { 1345d5c65159SKalle Valo ath11k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1346d5c65159SKalle Valo ptr - begin, len, sizeof(*tlv)); 1347d5c65159SKalle Valo return -EINVAL; 1348d5c65159SKalle Valo } 1349d5c65159SKalle Valo tlv = (struct htt_tlv *)ptr; 1350d5c65159SKalle Valo tlv_tag = FIELD_GET(HTT_TLV_TAG, tlv->header); 1351d5c65159SKalle Valo tlv_len = FIELD_GET(HTT_TLV_LEN, tlv->header); 1352d5c65159SKalle Valo ptr += sizeof(*tlv); 1353d5c65159SKalle Valo len -= sizeof(*tlv); 1354d5c65159SKalle Valo 1355d5c65159SKalle Valo if (tlv_len > len) { 1356bb2d2dfdSTom Rix ath11k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1357d5c65159SKalle Valo tlv_tag, ptr - begin, len, tlv_len); 1358d5c65159SKalle Valo return -EINVAL; 1359d5c65159SKalle Valo } 1360d5c65159SKalle Valo ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1361d5c65159SKalle Valo if (ret == -ENOMEM) 1362d5c65159SKalle Valo return ret; 1363d5c65159SKalle Valo 1364d5c65159SKalle Valo ptr += tlv_len; 1365d5c65159SKalle Valo len -= tlv_len; 1366d5c65159SKalle Valo } 1367d5c65159SKalle Valo return 0; 1368d5c65159SKalle Valo } 1369d5c65159SKalle Valo 1370d5c65159SKalle Valo static void 1371d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(struct ath11k *ar, 1372d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats, u8 user) 1373d5c65159SKalle Valo { 1374d5c65159SKalle Valo struct ath11k_base *ab = ar->ab; 1375d5c65159SKalle Valo struct ath11k_peer *peer; 1376d5c65159SKalle Valo struct ieee80211_sta *sta; 1377d5c65159SKalle Valo struct ath11k_sta *arsta; 1378d5c65159SKalle Valo struct htt_ppdu_stats_user_rate *user_rate; 1379d5c65159SKalle Valo struct ath11k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1380d5c65159SKalle Valo struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1381d5c65159SKalle Valo struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1382d5c65159SKalle Valo int ret; 13836a0c3702SJohn Crispin u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1384d5c65159SKalle Valo u32 succ_bytes = 0; 1385d5c65159SKalle Valo u16 rate = 0, succ_pkts = 0; 1386d5c65159SKalle Valo u32 tx_duration = 0; 1387b9269a07SVenkateswara Naralasetty u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1388d5c65159SKalle Valo bool is_ampdu = false; 1389d5c65159SKalle Valo 1390d5c65159SKalle Valo if (!usr_stats) 1391d5c65159SKalle Valo return; 1392d5c65159SKalle Valo 1393d5c65159SKalle Valo if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1394d5c65159SKalle Valo return; 1395d5c65159SKalle Valo 1396d5c65159SKalle Valo if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1397d5c65159SKalle Valo is_ampdu = 1398d5c65159SKalle Valo HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1399d5c65159SKalle Valo 1400d5c65159SKalle Valo if (usr_stats->tlv_flags & 1401d5c65159SKalle Valo BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1402d5c65159SKalle Valo succ_bytes = usr_stats->ack_ba.success_bytes; 1403d5c65159SKalle Valo succ_pkts = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M, 1404d5c65159SKalle Valo usr_stats->ack_ba.info); 1405b9269a07SVenkateswara Naralasetty tid = FIELD_GET(HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM, 1406b9269a07SVenkateswara Naralasetty usr_stats->ack_ba.info); 1407d5c65159SKalle Valo } 1408d5c65159SKalle Valo 1409d5c65159SKalle Valo if (common->fes_duration_us) 1410d5c65159SKalle Valo tx_duration = common->fes_duration_us; 1411d5c65159SKalle Valo 1412d5c65159SKalle Valo user_rate = &usr_stats->rate; 1413d5c65159SKalle Valo flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1414d5c65159SKalle Valo bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1415d5c65159SKalle Valo nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1416d5c65159SKalle Valo mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1417d5c65159SKalle Valo sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 14186a0c3702SJohn Crispin dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1419d5c65159SKalle Valo 1420d5c65159SKalle Valo /* Note: If host configured fixed rates and in some other special 1421d5c65159SKalle Valo * cases, the broadcast/management frames are sent in different rates. 1422d5c65159SKalle Valo * Firmware rate's control to be skipped for this? 1423d5c65159SKalle Valo */ 1424d5c65159SKalle Valo 14256a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH11K_HE_MCS_MAX) { 1426bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 14276a0c3702SJohn Crispin return; 14286a0c3702SJohn Crispin } 14296a0c3702SJohn Crispin 14306a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH11K_VHT_MCS_MAX) { 1431bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1432d5c65159SKalle Valo return; 1433d5c65159SKalle Valo } 1434d5c65159SKalle Valo 14356a0c3702SJohn Crispin if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH11K_HT_MCS_MAX || nss < 1)) { 1436bb2d2dfdSTom Rix ath11k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1437d5c65159SKalle Valo mcs, nss); 1438d5c65159SKalle Valo return; 1439d5c65159SKalle Valo } 1440d5c65159SKalle Valo 1441d5c65159SKalle Valo if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1442d5c65159SKalle Valo ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs, 1443d5c65159SKalle Valo flags, 1444d5c65159SKalle Valo &rate_idx, 1445d5c65159SKalle Valo &rate); 1446d5c65159SKalle Valo if (ret < 0) 1447d5c65159SKalle Valo return; 1448d5c65159SKalle Valo } 1449d5c65159SKalle Valo 1450d5c65159SKalle Valo rcu_read_lock(); 1451d5c65159SKalle Valo spin_lock_bh(&ab->base_lock); 1452d5c65159SKalle Valo peer = ath11k_peer_find_by_id(ab, usr_stats->peer_id); 1453d5c65159SKalle Valo 1454d5c65159SKalle Valo if (!peer || !peer->sta) { 1455d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1456d5c65159SKalle Valo rcu_read_unlock(); 1457d5c65159SKalle Valo return; 1458d5c65159SKalle Valo } 1459d5c65159SKalle Valo 1460d5c65159SKalle Valo sta = peer->sta; 1461d5c65159SKalle Valo arsta = (struct ath11k_sta *)sta->drv_priv; 1462d5c65159SKalle Valo 1463d5c65159SKalle Valo memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1464d5c65159SKalle Valo 1465d5c65159SKalle Valo switch (flags) { 1466d5c65159SKalle Valo case WMI_RATE_PREAMBLE_OFDM: 1467d5c65159SKalle Valo arsta->txrate.legacy = rate; 1468d5c65159SKalle Valo break; 1469d5c65159SKalle Valo case WMI_RATE_PREAMBLE_CCK: 1470d5c65159SKalle Valo arsta->txrate.legacy = rate; 1471d5c65159SKalle Valo break; 1472d5c65159SKalle Valo case WMI_RATE_PREAMBLE_HT: 1473d5c65159SKalle Valo arsta->txrate.mcs = mcs + 8 * (nss - 1); 1474d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1475be43ce64SJohn Crispin if (sgi) 1476d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1477d5c65159SKalle Valo break; 1478d5c65159SKalle Valo case WMI_RATE_PREAMBLE_VHT: 1479d5c65159SKalle Valo arsta->txrate.mcs = mcs; 1480d5c65159SKalle Valo arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1481be43ce64SJohn Crispin if (sgi) 1482d5c65159SKalle Valo arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1483d5c65159SKalle Valo break; 14846a0c3702SJohn Crispin case WMI_RATE_PREAMBLE_HE: 14856a0c3702SJohn Crispin arsta->txrate.mcs = mcs; 14866a0c3702SJohn Crispin arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 14876a0c3702SJohn Crispin arsta->txrate.he_dcm = dcm; 14881b8bb94cSWen Gong arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 14891b8bb94cSWen Gong arsta->txrate.he_ru_alloc = ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc 14901b8bb94cSWen Gong ((user_rate->ru_end - 14916a0c3702SJohn Crispin user_rate->ru_start) + 1); 14926a0c3702SJohn Crispin break; 1493d5c65159SKalle Valo } 1494d5c65159SKalle Valo 1495d5c65159SKalle Valo arsta->txrate.nss = nss; 14961b8bb94cSWen Gong 149739e81c6aSTamizh chelvam arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw); 1498a9e945eaSVenkateswara Naralasetty arsta->tx_duration += tx_duration; 1499d5c65159SKalle Valo memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1500d5c65159SKalle Valo 1501b9269a07SVenkateswara Naralasetty /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1502b9269a07SVenkateswara Naralasetty * So skip peer stats update for mgmt packets. 1503b9269a07SVenkateswara Naralasetty */ 1504b9269a07SVenkateswara Naralasetty if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1505d5c65159SKalle Valo memset(peer_stats, 0, sizeof(*peer_stats)); 1506d5c65159SKalle Valo peer_stats->succ_pkts = succ_pkts; 1507d5c65159SKalle Valo peer_stats->succ_bytes = succ_bytes; 1508d5c65159SKalle Valo peer_stats->is_ampdu = is_ampdu; 1509d5c65159SKalle Valo peer_stats->duration = tx_duration; 1510d5c65159SKalle Valo peer_stats->ba_fails = 1511d5c65159SKalle Valo HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1512d5c65159SKalle Valo HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1513d5c65159SKalle Valo 1514cb4e57dbSKalle Valo if (ath11k_debugfs_is_extd_tx_stats_enabled(ar)) 1515568f0603SKalle Valo ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); 1516b9269a07SVenkateswara Naralasetty } 1517d5c65159SKalle Valo 1518d5c65159SKalle Valo spin_unlock_bh(&ab->base_lock); 1519d5c65159SKalle Valo rcu_read_unlock(); 1520d5c65159SKalle Valo } 1521d5c65159SKalle Valo 1522d5c65159SKalle Valo static void ath11k_htt_update_ppdu_stats(struct ath11k *ar, 1523d5c65159SKalle Valo struct htt_ppdu_stats *ppdu_stats) 1524d5c65159SKalle Valo { 1525d5c65159SKalle Valo u8 user; 1526d5c65159SKalle Valo 1527d5c65159SKalle Valo for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1528d5c65159SKalle Valo ath11k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1529d5c65159SKalle Valo } 1530d5c65159SKalle Valo 1531d5c65159SKalle Valo static 1532d5c65159SKalle Valo struct htt_ppdu_stats_info *ath11k_dp_htt_get_ppdu_desc(struct ath11k *ar, 1533d5c65159SKalle Valo u32 ppdu_id) 1534d5c65159SKalle Valo { 1535269663f1SDan Carpenter struct htt_ppdu_stats_info *ppdu_info; 1536d5c65159SKalle Valo 1537d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1538d5c65159SKalle Valo if (!list_empty(&ar->ppdu_stats_info)) { 1539d5c65159SKalle Valo list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1540269663f1SDan Carpenter if (ppdu_info->ppdu_id == ppdu_id) { 1541d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1542d5c65159SKalle Valo return ppdu_info; 1543d5c65159SKalle Valo } 1544d5c65159SKalle Valo } 1545d5c65159SKalle Valo 1546d5c65159SKalle Valo if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1547d5c65159SKalle Valo ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1548d5c65159SKalle Valo typeof(*ppdu_info), list); 1549d5c65159SKalle Valo list_del(&ppdu_info->list); 1550d5c65159SKalle Valo ar->ppdu_stat_list_depth--; 1551d5c65159SKalle Valo ath11k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1552d5c65159SKalle Valo kfree(ppdu_info); 1553d5c65159SKalle Valo } 1554d5c65159SKalle Valo } 1555d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1556d5c65159SKalle Valo 15576a8be1baSWen Gong ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1558d5c65159SKalle Valo if (!ppdu_info) 1559d5c65159SKalle Valo return NULL; 1560d5c65159SKalle Valo 1561d5c65159SKalle Valo spin_lock_bh(&ar->data_lock); 1562d5c65159SKalle Valo list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1563d5c65159SKalle Valo ar->ppdu_stat_list_depth++; 1564d5c65159SKalle Valo spin_unlock_bh(&ar->data_lock); 1565d5c65159SKalle Valo 1566d5c65159SKalle Valo return ppdu_info; 1567d5c65159SKalle Valo } 1568d5c65159SKalle Valo 1569d5c65159SKalle Valo static int ath11k_htt_pull_ppdu_stats(struct ath11k_base *ab, 1570d5c65159SKalle Valo struct sk_buff *skb) 1571d5c65159SKalle Valo { 1572d5c65159SKalle Valo struct ath11k_htt_ppdu_stats_msg *msg; 1573d5c65159SKalle Valo struct htt_ppdu_stats_info *ppdu_info; 1574d5c65159SKalle Valo struct ath11k *ar; 1575d5c65159SKalle Valo int ret; 1576d5c65159SKalle Valo u8 pdev_id; 1577d5c65159SKalle Valo u32 ppdu_id, len; 1578d5c65159SKalle Valo 1579d5c65159SKalle Valo msg = (struct ath11k_htt_ppdu_stats_msg *)skb->data; 1580d5c65159SKalle Valo len = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE, msg->info); 1581d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, msg->info); 1582d5c65159SKalle Valo ppdu_id = msg->ppdu_id; 1583d5c65159SKalle Valo 1584d5c65159SKalle Valo rcu_read_lock(); 1585d5c65159SKalle Valo ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1586d5c65159SKalle Valo if (!ar) { 1587d5c65159SKalle Valo ret = -EINVAL; 1588d5c65159SKalle Valo goto exit; 1589d5c65159SKalle Valo } 1590d5c65159SKalle Valo 1591cb4e57dbSKalle Valo if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) 1592d5c65159SKalle Valo trace_ath11k_htt_ppdu_stats(ar, skb->data, len); 1593d5c65159SKalle Valo 1594d5c65159SKalle Valo ppdu_info = ath11k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1595d5c65159SKalle Valo if (!ppdu_info) { 1596d5c65159SKalle Valo ret = -EINVAL; 1597d5c65159SKalle Valo goto exit; 1598d5c65159SKalle Valo } 1599d5c65159SKalle Valo 1600d5c65159SKalle Valo ppdu_info->ppdu_id = ppdu_id; 1601d5c65159SKalle Valo ret = ath11k_dp_htt_tlv_iter(ab, msg->data, len, 1602d5c65159SKalle Valo ath11k_htt_tlv_ppdu_stats_parse, 1603d5c65159SKalle Valo (void *)ppdu_info); 1604d5c65159SKalle Valo if (ret) { 1605d5c65159SKalle Valo ath11k_warn(ab, "Failed to parse tlv %d\n", ret); 1606d5c65159SKalle Valo goto exit; 1607d5c65159SKalle Valo } 1608d5c65159SKalle Valo 1609d5c65159SKalle Valo exit: 1610d5c65159SKalle Valo rcu_read_unlock(); 1611d5c65159SKalle Valo 1612d5c65159SKalle Valo return ret; 1613d5c65159SKalle Valo } 1614d5c65159SKalle Valo 1615d5c65159SKalle Valo static void ath11k_htt_pktlog(struct ath11k_base *ab, struct sk_buff *skb) 1616d5c65159SKalle Valo { 1617d5c65159SKalle Valo struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; 1618443d2ee7SAnilkumar Kolli struct ath_pktlog_hdr *hdr = (struct ath_pktlog_hdr *)data; 1619d5c65159SKalle Valo struct ath11k *ar; 1620d5c65159SKalle Valo u8 pdev_id; 1621d5c65159SKalle Valo 1622d5c65159SKalle Valo pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); 1623d0f390eaSAnilkumar Kolli ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); 1624d0f390eaSAnilkumar Kolli if (!ar) { 1625d0f390eaSAnilkumar Kolli ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); 1626d0f390eaSAnilkumar Kolli return; 1627d0f390eaSAnilkumar Kolli } 1628d5c65159SKalle Valo 162921c1b063SMaharaja Kennadyrajan trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, 163021c1b063SMaharaja Kennadyrajan ar->ab->pktlog_defs_checksum); 1631d5c65159SKalle Valo } 1632d5c65159SKalle Valo 1633678e8414SSriram R static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, 1634678e8414SSriram R struct sk_buff *skb) 1635678e8414SSriram R { 1636678e8414SSriram R u32 *data = (u32 *)skb->data; 163771fbc847SSriram R u8 pdev_id, ring_type, ring_id, pdev_idx; 1638678e8414SSriram R u16 hp, tp; 1639678e8414SSriram R u32 backpressure_time; 164071fbc847SSriram R struct ath11k_bp_stats *bp_stats; 1641678e8414SSriram R 1642678e8414SSriram R pdev_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_PDEV_ID_M, *data); 1643678e8414SSriram R ring_type = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_TYPE_M, *data); 1644678e8414SSriram R ring_id = FIELD_GET(HTT_BACKPRESSURE_EVENT_RING_ID_M, *data); 1645678e8414SSriram R ++data; 1646678e8414SSriram R 1647678e8414SSriram R hp = FIELD_GET(HTT_BACKPRESSURE_EVENT_HP_M, *data); 1648678e8414SSriram R tp = FIELD_GET(HTT_BACKPRESSURE_EVENT_TP_M, *data); 1649678e8414SSriram R ++data; 1650678e8414SSriram R 1651678e8414SSriram R backpressure_time = *data; 1652678e8414SSriram R 1653678e8414SSriram R ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", 1654678e8414SSriram R pdev_id, ring_type, ring_id, hp, tp, backpressure_time); 165571fbc847SSriram R 165671fbc847SSriram R if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { 165771fbc847SSriram R if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) 165871fbc847SSriram R return; 165971fbc847SSriram R 166071fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; 166171fbc847SSriram R } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { 166271fbc847SSriram R pdev_idx = DP_HW2SW_MACID(pdev_id); 166371fbc847SSriram R 166471fbc847SSriram R if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) 166571fbc847SSriram R return; 166671fbc847SSriram R 166771fbc847SSriram R bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; 166871fbc847SSriram R } else { 166971fbc847SSriram R ath11k_warn(ab, "unknown ring type received in htt bp event %d\n", 167071fbc847SSriram R ring_type); 167171fbc847SSriram R return; 167271fbc847SSriram R } 167371fbc847SSriram R 167471fbc847SSriram R spin_lock_bh(&ab->base_lock); 167571fbc847SSriram R bp_stats->hp = hp; 167671fbc847SSriram R bp_stats->tp = tp; 167771fbc847SSriram R bp_stats->count++; 167871fbc847SSriram R bp_stats->jiffies = jiffies; 167971fbc847SSriram R spin_unlock_bh(&ab->base_lock); 1680678e8414SSriram R } 1681678e8414SSriram R 1682d5c65159SKalle Valo void ath11k_dp_htt_htc_t2h_msg_handler(struct ath11k_base *ab, 1683d5c65159SKalle Valo struct sk_buff *skb) 1684d5c65159SKalle Valo { 1685d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 1686d5c65159SKalle Valo struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1687d5c65159SKalle Valo enum htt_t2h_msg_type type = FIELD_GET(HTT_T2H_MSG_TYPE, *(u32 *)resp); 1688d5c65159SKalle Valo u16 peer_id; 1689d5c65159SKalle Valo u8 vdev_id; 1690d5c65159SKalle Valo u8 mac_addr[ETH_ALEN]; 1691d5c65159SKalle Valo u16 peer_mac_h16; 1692d5c65159SKalle Valo u16 ast_hash; 16934b965be5SKarthikeyan Periyasamy u16 hw_peer_id; 1694d5c65159SKalle Valo 1695d5c65159SKalle Valo ath11k_dbg(ab, ATH11K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1696d5c65159SKalle Valo 1697d5c65159SKalle Valo switch (type) { 1698d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_VERSION_CONF: 1699d5c65159SKalle Valo dp->htt_tgt_ver_major = FIELD_GET(HTT_T2H_VERSION_CONF_MAJOR, 1700d5c65159SKalle Valo resp->version_msg.version); 1701d5c65159SKalle Valo dp->htt_tgt_ver_minor = FIELD_GET(HTT_T2H_VERSION_CONF_MINOR, 1702d5c65159SKalle Valo resp->version_msg.version); 1703d5c65159SKalle Valo complete(&dp->htt_tgt_version_received); 1704d5c65159SKalle Valo break; 1705d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_MAP: 1706a6275302SCarl Huang vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1707a6275302SCarl Huang resp->peer_map_ev.info); 1708a6275302SCarl Huang peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1709a6275302SCarl Huang resp->peer_map_ev.info); 1710a6275302SCarl Huang peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1711a6275302SCarl Huang resp->peer_map_ev.info1); 1712a6275302SCarl Huang ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1713a6275302SCarl Huang peer_mac_h16, mac_addr); 17144b965be5SKarthikeyan Periyasamy ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1715a6275302SCarl Huang break; 171613ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_MAP2: 1717d5c65159SKalle Valo vdev_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_VDEV_ID, 1718d5c65159SKalle Valo resp->peer_map_ev.info); 1719d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO_PEER_ID, 1720d5c65159SKalle Valo resp->peer_map_ev.info); 1721d5c65159SKalle Valo peer_mac_h16 = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16, 1722d5c65159SKalle Valo resp->peer_map_ev.info1); 1723d5c65159SKalle Valo ath11k_dp_get_mac_addr(resp->peer_map_ev.mac_addr_l32, 1724d5c65159SKalle Valo peer_mac_h16, mac_addr); 1725d5c65159SKalle Valo ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, 17260f37fbf4SAnilkumar Kolli resp->peer_map_ev.info2); 17274b965be5SKarthikeyan Periyasamy hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID, 17284b965be5SKarthikeyan Periyasamy resp->peer_map_ev.info1); 17294b965be5SKarthikeyan Periyasamy ath11k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 17304b965be5SKarthikeyan Periyasamy hw_peer_id); 1731d5c65159SKalle Valo break; 1732d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PEER_UNMAP: 173313ecd81fSCarl Huang case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1734d5c65159SKalle Valo peer_id = FIELD_GET(HTT_T2H_PEER_UNMAP_INFO_PEER_ID, 1735d5c65159SKalle Valo resp->peer_unmap_ev.info); 1736d5c65159SKalle Valo ath11k_peer_unmap_event(ab, peer_id); 1737d5c65159SKalle Valo break; 1738d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1739d5c65159SKalle Valo ath11k_htt_pull_ppdu_stats(ab, skb); 1740d5c65159SKalle Valo break; 1741d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1742568f0603SKalle Valo ath11k_debugfs_htt_ext_stats_handler(ab, skb); 1743d5c65159SKalle Valo break; 1744d5c65159SKalle Valo case HTT_T2H_MSG_TYPE_PKTLOG: 1745d5c65159SKalle Valo ath11k_htt_pktlog(ab, skb); 1746d5c65159SKalle Valo break; 1747678e8414SSriram R case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: 1748678e8414SSriram R ath11k_htt_backpressure_event_handler(ab, skb); 1749678e8414SSriram R break; 1750d5c65159SKalle Valo default: 1751d5c65159SKalle Valo ath11k_warn(ab, "htt event %d not handled\n", type); 1752d5c65159SKalle Valo break; 1753d5c65159SKalle Valo } 1754d5c65159SKalle Valo 1755d5c65159SKalle Valo dev_kfree_skb_any(skb); 1756d5c65159SKalle Valo } 1757d5c65159SKalle Valo 1758d5c65159SKalle Valo static int ath11k_dp_rx_msdu_coalesce(struct ath11k *ar, 1759d5c65159SKalle Valo struct sk_buff_head *msdu_list, 1760d5c65159SKalle Valo struct sk_buff *first, struct sk_buff *last, 1761d5c65159SKalle Valo u8 l3pad_bytes, int msdu_len) 1762d5c65159SKalle Valo { 1763e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 1764d5c65159SKalle Valo struct sk_buff *skb; 1765d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1766d2f510faSSriram R int buf_first_hdr_len, buf_first_len; 1767d5c65159SKalle Valo struct hal_rx_desc *ldesc; 1768e678fbd4SKarthikeyan Periyasamy int space_extra, rem_len, buf_len; 1769e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 1770d5c65159SKalle Valo 1771d2f510faSSriram R /* As the msdu is spread across multiple rx buffers, 1772d2f510faSSriram R * find the offset to the start of msdu for computing 1773d2f510faSSriram R * the length of the msdu in the first buffer. 1774d2f510faSSriram R */ 1775e678fbd4SKarthikeyan Periyasamy buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1776d2f510faSSriram R buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1777d2f510faSSriram R 1778d2f510faSSriram R if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1779d2f510faSSriram R skb_put(first, buf_first_hdr_len + msdu_len); 1780d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1781d5c65159SKalle Valo return 0; 1782d5c65159SKalle Valo } 1783d5c65159SKalle Valo 1784d5c65159SKalle Valo ldesc = (struct hal_rx_desc *)last->data; 1785e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ab, ldesc); 1786e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ab, ldesc); 1787d5c65159SKalle Valo 1788d5c65159SKalle Valo /* MSDU spans over multiple buffers because the length of the MSDU 1789d5c65159SKalle Valo * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1790d5c65159SKalle Valo * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1791d5c65159SKalle Valo */ 1792d5c65159SKalle Valo skb_put(first, DP_RX_BUFFER_SIZE); 1793d2f510faSSriram R skb_pull(first, buf_first_hdr_len); 1794d5c65159SKalle Valo 179530679ec4SKarthikeyan Periyasamy /* When an MSDU spread over multiple buffers attention, MSDU_END and 179630679ec4SKarthikeyan Periyasamy * MPDU_END tlvs are valid only in the last buffer. Copy those tlvs. 179730679ec4SKarthikeyan Periyasamy */ 1798e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 179930679ec4SKarthikeyan Periyasamy 1800d2f510faSSriram R space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1801d5c65159SKalle Valo if (space_extra > 0 && 1802d5c65159SKalle Valo (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1803d5c65159SKalle Valo /* Free up all buffers of the MSDU */ 1804d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1805d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1806d5c65159SKalle Valo if (!rxcb->is_continuation) { 1807d5c65159SKalle Valo dev_kfree_skb_any(skb); 1808d5c65159SKalle Valo break; 1809d5c65159SKalle Valo } 1810d5c65159SKalle Valo dev_kfree_skb_any(skb); 1811d5c65159SKalle Valo } 1812d5c65159SKalle Valo return -ENOMEM; 1813d5c65159SKalle Valo } 1814d5c65159SKalle Valo 1815d2f510faSSriram R rem_len = msdu_len - buf_first_len; 1816d5c65159SKalle Valo while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1817d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1818d5c65159SKalle Valo if (rxcb->is_continuation) 1819e678fbd4SKarthikeyan Periyasamy buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1820d5c65159SKalle Valo else 1821d5c65159SKalle Valo buf_len = rem_len; 1822d5c65159SKalle Valo 1823e678fbd4SKarthikeyan Periyasamy if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1824d5c65159SKalle Valo WARN_ON_ONCE(1); 1825d5c65159SKalle Valo dev_kfree_skb_any(skb); 1826d5c65159SKalle Valo return -EINVAL; 1827d5c65159SKalle Valo } 1828d5c65159SKalle Valo 1829e678fbd4SKarthikeyan Periyasamy skb_put(skb, buf_len + hal_rx_desc_sz); 1830e678fbd4SKarthikeyan Periyasamy skb_pull(skb, hal_rx_desc_sz); 1831d5c65159SKalle Valo skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1832d5c65159SKalle Valo buf_len); 1833d5c65159SKalle Valo dev_kfree_skb_any(skb); 1834d5c65159SKalle Valo 1835d5c65159SKalle Valo rem_len -= buf_len; 1836d5c65159SKalle Valo if (!rxcb->is_continuation) 1837d5c65159SKalle Valo break; 1838d5c65159SKalle Valo } 1839d5c65159SKalle Valo 1840d5c65159SKalle Valo return 0; 1841d5c65159SKalle Valo } 1842d5c65159SKalle Valo 1843d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1844d5c65159SKalle Valo struct sk_buff *first) 1845d5c65159SKalle Valo { 1846d5c65159SKalle Valo struct sk_buff *skb; 1847d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(first); 1848d5c65159SKalle Valo 1849d5c65159SKalle Valo if (!rxcb->is_continuation) 1850d5c65159SKalle Valo return first; 1851d5c65159SKalle Valo 1852d5c65159SKalle Valo skb_queue_walk(msdu_list, skb) { 1853d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 1854d5c65159SKalle Valo if (!rxcb->is_continuation) 1855d5c65159SKalle Valo return skb; 1856d5c65159SKalle Valo } 1857d5c65159SKalle Valo 1858d5c65159SKalle Valo return NULL; 1859d5c65159SKalle Valo } 1860d5c65159SKalle Valo 1861e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_h_csum_offload(struct ath11k *ar, struct sk_buff *msdu) 1862d5c65159SKalle Valo { 1863d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1864e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 1865d5c65159SKalle Valo bool ip_csum_fail, l4_csum_fail; 1866d5c65159SKalle Valo 1867e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rxcb->rx_desc); 1868e678fbd4SKarthikeyan Periyasamy ip_csum_fail = ath11k_dp_rx_h_attn_ip_cksum_fail(rx_attention); 1869e678fbd4SKarthikeyan Periyasamy l4_csum_fail = ath11k_dp_rx_h_attn_l4_cksum_fail(rx_attention); 1870d5c65159SKalle Valo 1871d5c65159SKalle Valo msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1872d5c65159SKalle Valo CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1873d5c65159SKalle Valo } 1874d5c65159SKalle Valo 1875d5c65159SKalle Valo static int ath11k_dp_rx_crypto_mic_len(struct ath11k *ar, 1876d5c65159SKalle Valo enum hal_encrypt_type enctype) 1877d5c65159SKalle Valo { 1878d5c65159SKalle Valo switch (enctype) { 1879d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1880d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1881d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1882d5c65159SKalle Valo return 0; 1883d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1884d5c65159SKalle Valo return IEEE80211_CCMP_MIC_LEN; 1885d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1886d5c65159SKalle Valo return IEEE80211_CCMP_256_MIC_LEN; 1887d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1888d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1889d5c65159SKalle Valo return IEEE80211_GCMP_MIC_LEN; 1890d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1891d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1892d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1893d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1894d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1895d5c65159SKalle Valo break; 1896d5c65159SKalle Valo } 1897d5c65159SKalle Valo 1898d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1899d5c65159SKalle Valo return 0; 1900d5c65159SKalle Valo } 1901d5c65159SKalle Valo 1902d5c65159SKalle Valo static int ath11k_dp_rx_crypto_param_len(struct ath11k *ar, 1903d5c65159SKalle Valo enum hal_encrypt_type enctype) 1904d5c65159SKalle Valo { 1905d5c65159SKalle Valo switch (enctype) { 1906d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1907d5c65159SKalle Valo return 0; 1908d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1909d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1910d5c65159SKalle Valo return IEEE80211_TKIP_IV_LEN; 1911d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1912d5c65159SKalle Valo return IEEE80211_CCMP_HDR_LEN; 1913d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1914d5c65159SKalle Valo return IEEE80211_CCMP_256_HDR_LEN; 1915d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1916d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1917d5c65159SKalle Valo return IEEE80211_GCMP_HDR_LEN; 1918d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1919d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1920d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1921d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1922d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1923d5c65159SKalle Valo break; 1924d5c65159SKalle Valo } 1925d5c65159SKalle Valo 1926d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1927d5c65159SKalle Valo return 0; 1928d5c65159SKalle Valo } 1929d5c65159SKalle Valo 1930d5c65159SKalle Valo static int ath11k_dp_rx_crypto_icv_len(struct ath11k *ar, 1931d5c65159SKalle Valo enum hal_encrypt_type enctype) 1932d5c65159SKalle Valo { 1933d5c65159SKalle Valo switch (enctype) { 1934d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_OPEN: 1935d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_128: 1936d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_CCMP_256: 1937d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_GCMP_128: 1938d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1939d5c65159SKalle Valo return 0; 1940d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1941d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_TKIP_MIC: 1942d5c65159SKalle Valo return IEEE80211_TKIP_ICV_LEN; 1943d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_40: 1944d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_104: 1945d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WEP_128: 1946d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1947d5c65159SKalle Valo case HAL_ENCRYPT_TYPE_WAPI: 1948d5c65159SKalle Valo break; 1949d5c65159SKalle Valo } 1950d5c65159SKalle Valo 1951d5c65159SKalle Valo ath11k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1952d5c65159SKalle Valo return 0; 1953d5c65159SKalle Valo } 1954d5c65159SKalle Valo 1955d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_nwifi(struct ath11k *ar, 1956d5c65159SKalle Valo struct sk_buff *msdu, 1957d5c65159SKalle Valo u8 *first_hdr, 1958d5c65159SKalle Valo enum hal_encrypt_type enctype, 1959d5c65159SKalle Valo struct ieee80211_rx_status *status) 1960d5c65159SKalle Valo { 1961acc79d98SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 1962acc79d98SSriram R u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1963d5c65159SKalle Valo struct ieee80211_hdr *hdr; 1964d5c65159SKalle Valo size_t hdr_len; 1965d5c65159SKalle Valo u8 da[ETH_ALEN]; 1966d5c65159SKalle Valo u8 sa[ETH_ALEN]; 1967acc79d98SSriram R u16 qos_ctl = 0; 1968acc79d98SSriram R u8 *qos; 1969d5c65159SKalle Valo 1970acc79d98SSriram R /* copy SA & DA and pull decapped header */ 1971d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 1972acc79d98SSriram R hdr_len = ieee80211_hdrlen(hdr->frame_control); 1973d5c65159SKalle Valo ether_addr_copy(da, ieee80211_get_DA(hdr)); 1974d5c65159SKalle Valo ether_addr_copy(sa, ieee80211_get_SA(hdr)); 1975d5c65159SKalle Valo skb_pull(msdu, ieee80211_hdrlen(hdr->frame_control)); 1976d5c65159SKalle Valo 1977acc79d98SSriram R if (rxcb->is_first_msdu) { 1978acc79d98SSriram R /* original 802.11 header is valid for the first msdu 1979acc79d98SSriram R * hence we can reuse the same header 1980acc79d98SSriram R */ 1981d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 1982d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 1983d5c65159SKalle Valo 1984acc79d98SSriram R /* Each A-MSDU subframe will be reported as a separate MSDU, 1985acc79d98SSriram R * so strip the A-MSDU bit from QoS Ctl. 1986acc79d98SSriram R */ 1987acc79d98SSriram R if (ieee80211_is_data_qos(hdr->frame_control)) { 1988acc79d98SSriram R qos = ieee80211_get_qos_ctl(hdr); 1989acc79d98SSriram R qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT; 1990acc79d98SSriram R } 1991acc79d98SSriram R } else { 1992acc79d98SSriram R /* Rebuild qos header if this is a middle/last msdu */ 1993acc79d98SSriram R hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1994acc79d98SSriram R 1995acc79d98SSriram R /* Reset the order bit as the HT_Control header is stripped */ 1996acc79d98SSriram R hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1997acc79d98SSriram R 1998acc79d98SSriram R qos_ctl = rxcb->tid; 1999acc79d98SSriram R 2000e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rx_h_msdu_start_mesh_ctl_present(ar->ab, rxcb->rx_desc)) 2001acc79d98SSriram R qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2002acc79d98SSriram R 2003acc79d98SSriram R /* TODO Add other QoS ctl fields when required */ 2004acc79d98SSriram R 2005acc79d98SSriram R /* copy decap header before overwriting for reuse below */ 2006acc79d98SSriram R memcpy(decap_hdr, (uint8_t *)hdr, hdr_len); 2007acc79d98SSriram R } 2008acc79d98SSriram R 2009d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2010d5c65159SKalle Valo memcpy(skb_push(msdu, 2011d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 2012d5c65159SKalle Valo (void *)hdr + hdr_len, 2013d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 2014d5c65159SKalle Valo } 2015d5c65159SKalle Valo 2016acc79d98SSriram R if (!rxcb->is_first_msdu) { 2017acc79d98SSriram R memcpy(skb_push(msdu, 2018acc79d98SSriram R IEEE80211_QOS_CTL_LEN), &qos_ctl, 2019acc79d98SSriram R IEEE80211_QOS_CTL_LEN); 2020acc79d98SSriram R memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2021acc79d98SSriram R return; 2022acc79d98SSriram R } 2023acc79d98SSriram R 2024d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2025d5c65159SKalle Valo 2026d5c65159SKalle Valo /* original 802.11 header has a different DA and in 2027d5c65159SKalle Valo * case of 4addr it may also have different SA 2028d5c65159SKalle Valo */ 2029d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 2030d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 2031d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 2032d5c65159SKalle Valo } 2033d5c65159SKalle Valo 2034d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_raw(struct ath11k *ar, struct sk_buff *msdu, 2035d5c65159SKalle Valo enum hal_encrypt_type enctype, 2036d5c65159SKalle Valo struct ieee80211_rx_status *status, 2037d5c65159SKalle Valo bool decrypted) 2038d5c65159SKalle Valo { 2039d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2040d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2041d5c65159SKalle Valo size_t hdr_len; 2042d5c65159SKalle Valo size_t crypto_len; 2043d5c65159SKalle Valo 2044d5c65159SKalle Valo if (!rxcb->is_first_msdu || 2045d5c65159SKalle Valo !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2046d5c65159SKalle Valo WARN_ON_ONCE(1); 2047d5c65159SKalle Valo return; 2048d5c65159SKalle Valo } 2049d5c65159SKalle Valo 2050d5c65159SKalle Valo skb_trim(msdu, msdu->len - FCS_LEN); 2051d5c65159SKalle Valo 2052d5c65159SKalle Valo if (!decrypted) 2053d5c65159SKalle Valo return; 2054d5c65159SKalle Valo 2055d5c65159SKalle Valo hdr = (void *)msdu->data; 2056d5c65159SKalle Valo 2057d5c65159SKalle Valo /* Tail */ 2058d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 2059d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2060d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2061d5c65159SKalle Valo 2062d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2063d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2064d5c65159SKalle Valo } else { 2065d5c65159SKalle Valo /* MIC */ 2066d5c65159SKalle Valo if (status->flag & RX_FLAG_MIC_STRIPPED) 2067d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2068d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 2069d5c65159SKalle Valo 2070d5c65159SKalle Valo /* ICV */ 2071d5c65159SKalle Valo if (status->flag & RX_FLAG_ICV_STRIPPED) 2072d5c65159SKalle Valo skb_trim(msdu, msdu->len - 2073d5c65159SKalle Valo ath11k_dp_rx_crypto_icv_len(ar, enctype)); 2074d5c65159SKalle Valo } 2075d5c65159SKalle Valo 2076d5c65159SKalle Valo /* MMIC */ 2077d5c65159SKalle Valo if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2078d5c65159SKalle Valo !ieee80211_has_morefrags(hdr->frame_control) && 2079d5c65159SKalle Valo enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2080d5c65159SKalle Valo skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2081d5c65159SKalle Valo 2082d5c65159SKalle Valo /* Head */ 2083d5c65159SKalle Valo if (status->flag & RX_FLAG_IV_STRIPPED) { 2084d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2085d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2086d5c65159SKalle Valo 2087d5c65159SKalle Valo memmove((void *)msdu->data + crypto_len, 2088d5c65159SKalle Valo (void *)msdu->data, hdr_len); 2089d5c65159SKalle Valo skb_pull(msdu, crypto_len); 2090d5c65159SKalle Valo } 2091d5c65159SKalle Valo } 2092d5c65159SKalle Valo 2093d5c65159SKalle Valo static void *ath11k_dp_rx_h_find_rfc1042(struct ath11k *ar, 2094d5c65159SKalle Valo struct sk_buff *msdu, 2095d5c65159SKalle Valo enum hal_encrypt_type enctype) 2096d5c65159SKalle Valo { 2097d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 2098d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2099d5c65159SKalle Valo size_t hdr_len, crypto_len; 2100d5c65159SKalle Valo void *rfc1042; 2101d5c65159SKalle Valo bool is_amsdu; 2102d5c65159SKalle Valo 2103d5c65159SKalle Valo is_amsdu = !(rxcb->is_first_msdu && rxcb->is_last_msdu); 2104e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)ath11k_dp_rx_h_80211_hdr(ar->ab, rxcb->rx_desc); 2105d5c65159SKalle Valo rfc1042 = hdr; 2106d5c65159SKalle Valo 2107d5c65159SKalle Valo if (rxcb->is_first_msdu) { 2108d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2109d5c65159SKalle Valo crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 2110d5c65159SKalle Valo 2111d5c65159SKalle Valo rfc1042 += hdr_len + crypto_len; 2112d5c65159SKalle Valo } 2113d5c65159SKalle Valo 2114d5c65159SKalle Valo if (is_amsdu) 2115d5c65159SKalle Valo rfc1042 += sizeof(struct ath11k_dp_amsdu_subframe_hdr); 2116d5c65159SKalle Valo 2117d5c65159SKalle Valo return rfc1042; 2118d5c65159SKalle Valo } 2119d5c65159SKalle Valo 2120d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap_eth(struct ath11k *ar, 2121d5c65159SKalle Valo struct sk_buff *msdu, 2122d5c65159SKalle Valo u8 *first_hdr, 2123d5c65159SKalle Valo enum hal_encrypt_type enctype, 2124d5c65159SKalle Valo struct ieee80211_rx_status *status) 2125d5c65159SKalle Valo { 2126d5c65159SKalle Valo struct ieee80211_hdr *hdr; 2127d5c65159SKalle Valo struct ethhdr *eth; 2128d5c65159SKalle Valo size_t hdr_len; 2129d5c65159SKalle Valo u8 da[ETH_ALEN]; 2130d5c65159SKalle Valo u8 sa[ETH_ALEN]; 2131d5c65159SKalle Valo void *rfc1042; 2132d5c65159SKalle Valo 2133d5c65159SKalle Valo rfc1042 = ath11k_dp_rx_h_find_rfc1042(ar, msdu, enctype); 2134d5c65159SKalle Valo if (WARN_ON_ONCE(!rfc1042)) 2135d5c65159SKalle Valo return; 2136d5c65159SKalle Valo 2137d5c65159SKalle Valo /* pull decapped header and copy SA & DA */ 2138d5c65159SKalle Valo eth = (struct ethhdr *)msdu->data; 2139d5c65159SKalle Valo ether_addr_copy(da, eth->h_dest); 2140d5c65159SKalle Valo ether_addr_copy(sa, eth->h_source); 2141d5c65159SKalle Valo skb_pull(msdu, sizeof(struct ethhdr)); 2142d5c65159SKalle Valo 2143d5c65159SKalle Valo /* push rfc1042/llc/snap */ 2144d5c65159SKalle Valo memcpy(skb_push(msdu, sizeof(struct ath11k_dp_rfc1042_hdr)), rfc1042, 2145d5c65159SKalle Valo sizeof(struct ath11k_dp_rfc1042_hdr)); 2146d5c65159SKalle Valo 2147d5c65159SKalle Valo /* push original 802.11 header */ 2148d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)first_hdr; 2149d5c65159SKalle Valo hdr_len = ieee80211_hdrlen(hdr->frame_control); 2150d5c65159SKalle Valo 2151d5c65159SKalle Valo if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2152d5c65159SKalle Valo memcpy(skb_push(msdu, 2153d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)), 2154d5c65159SKalle Valo (void *)hdr + hdr_len, 2155d5c65159SKalle Valo ath11k_dp_rx_crypto_param_len(ar, enctype)); 2156d5c65159SKalle Valo } 2157d5c65159SKalle Valo 2158d5c65159SKalle Valo memcpy(skb_push(msdu, hdr_len), hdr, hdr_len); 2159d5c65159SKalle Valo 2160d5c65159SKalle Valo /* original 802.11 header has a different DA and in 2161d5c65159SKalle Valo * case of 4addr it may also have different SA 2162d5c65159SKalle Valo */ 2163d5c65159SKalle Valo hdr = (struct ieee80211_hdr *)msdu->data; 2164d5c65159SKalle Valo ether_addr_copy(ieee80211_get_DA(hdr), da); 2165d5c65159SKalle Valo ether_addr_copy(ieee80211_get_SA(hdr), sa); 2166d5c65159SKalle Valo } 2167d5c65159SKalle Valo 2168d5c65159SKalle Valo static void ath11k_dp_rx_h_undecap(struct ath11k *ar, struct sk_buff *msdu, 2169d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2170d5c65159SKalle Valo enum hal_encrypt_type enctype, 2171d5c65159SKalle Valo struct ieee80211_rx_status *status, 2172d5c65159SKalle Valo bool decrypted) 2173d5c65159SKalle Valo { 2174d5c65159SKalle Valo u8 *first_hdr; 2175d5c65159SKalle Valo u8 decap; 21762167fa60SSriram R struct ethhdr *ehdr; 2177d5c65159SKalle Valo 2178e678fbd4SKarthikeyan Periyasamy first_hdr = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 2179e678fbd4SKarthikeyan Periyasamy decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc); 2180d5c65159SKalle Valo 2181d5c65159SKalle Valo switch (decap) { 2182d5c65159SKalle Valo case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2183d5c65159SKalle Valo ath11k_dp_rx_h_undecap_nwifi(ar, msdu, first_hdr, 2184d5c65159SKalle Valo enctype, status); 2185d5c65159SKalle Valo break; 2186d5c65159SKalle Valo case DP_RX_DECAP_TYPE_RAW: 2187d5c65159SKalle Valo ath11k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2188d5c65159SKalle Valo decrypted); 2189d5c65159SKalle Valo break; 2190d5c65159SKalle Valo case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 21912167fa60SSriram R ehdr = (struct ethhdr *)msdu->data; 21922167fa60SSriram R 21932167fa60SSriram R /* mac80211 allows fast path only for authorized STA */ 21942167fa60SSriram R if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 21952167fa60SSriram R ATH11K_SKB_RXCB(msdu)->is_eapol = true; 21962167fa60SSriram R ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 21972167fa60SSriram R enctype, status); 21982167fa60SSriram R break; 21992167fa60SSriram R } 22002167fa60SSriram R 22012167fa60SSriram R /* PN for mcast packets will be validated in mac80211; 22022167fa60SSriram R * remove eth header and add 802.11 header. 22032167fa60SSriram R */ 22042167fa60SSriram R if (ATH11K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2205d5c65159SKalle Valo ath11k_dp_rx_h_undecap_eth(ar, msdu, first_hdr, 2206d5c65159SKalle Valo enctype, status); 2207d5c65159SKalle Valo break; 2208d5c65159SKalle Valo case DP_RX_DECAP_TYPE_8023: 2209d5c65159SKalle Valo /* TODO: Handle undecap for these formats */ 2210d5c65159SKalle Valo break; 2211d5c65159SKalle Valo } 2212d5c65159SKalle Valo } 2213d5c65159SKalle Valo 22142167fa60SSriram R static struct ath11k_peer * 22152167fa60SSriram R ath11k_dp_rx_h_find_peer(struct ath11k_base *ab, struct sk_buff *msdu) 22162167fa60SSriram R { 22172167fa60SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 22182167fa60SSriram R struct hal_rx_desc *rx_desc = rxcb->rx_desc; 22192167fa60SSriram R struct ath11k_peer *peer = NULL; 22202167fa60SSriram R 22212167fa60SSriram R lockdep_assert_held(&ab->base_lock); 22222167fa60SSriram R 22232167fa60SSriram R if (rxcb->peer_id) 22242167fa60SSriram R peer = ath11k_peer_find_by_id(ab, rxcb->peer_id); 22252167fa60SSriram R 22262167fa60SSriram R if (peer) 22272167fa60SSriram R return peer; 22282167fa60SSriram R 22292167fa60SSriram R if (!rx_desc || !(ath11k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 22302167fa60SSriram R return NULL; 22312167fa60SSriram R 22322167fa60SSriram R peer = ath11k_peer_find_by_addr(ab, 22332167fa60SSriram R ath11k_dp_rxdesc_mpdu_start_addr2(ab, rx_desc)); 22342167fa60SSriram R return peer; 22352167fa60SSriram R } 22362167fa60SSriram R 2237d5c65159SKalle Valo static void ath11k_dp_rx_h_mpdu(struct ath11k *ar, 2238acc79d98SSriram R struct sk_buff *msdu, 2239d5c65159SKalle Valo struct hal_rx_desc *rx_desc, 2240d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2241d5c65159SKalle Valo { 22422167fa60SSriram R bool fill_crypto_hdr; 2243d5c65159SKalle Valo enum hal_encrypt_type enctype; 2244acc79d98SSriram R bool is_decrypted = false; 22452167fa60SSriram R struct ath11k_skb_rxcb *rxcb; 2246acc79d98SSriram R struct ieee80211_hdr *hdr; 2247acc79d98SSriram R struct ath11k_peer *peer; 2248e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 2249d5c65159SKalle Valo u32 err_bitmap; 2250d5c65159SKalle Valo 22511441b2f2SManikanta Pubbisetty /* PN for multicast packets will be checked in mac80211 */ 22522167fa60SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 22532167fa60SSriram R fill_crypto_hdr = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 22542167fa60SSriram R rxcb->is_mcbc = fill_crypto_hdr; 2255acc79d98SSriram R 22562167fa60SSriram R if (rxcb->is_mcbc) { 22572167fa60SSriram R rxcb->peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 22582167fa60SSriram R rxcb->seq_no = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 22592167fa60SSriram R } 22601441b2f2SManikanta Pubbisetty 2261acc79d98SSriram R spin_lock_bh(&ar->ab->base_lock); 22622167fa60SSriram R peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 2263acc79d98SSriram R if (peer) { 22642167fa60SSriram R if (rxcb->is_mcbc) 2265acc79d98SSriram R enctype = peer->sec_type_grp; 2266acc79d98SSriram R else 2267acc79d98SSriram R enctype = peer->sec_type; 2268acc79d98SSriram R } else { 22692167fa60SSriram R enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 2270acc79d98SSriram R } 2271acc79d98SSriram R spin_unlock_bh(&ar->ab->base_lock); 2272d5c65159SKalle Valo 2273e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 2274e678fbd4SKarthikeyan Periyasamy err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 2275aa2092a9SVenkateswara Naralasetty if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2276e678fbd4SKarthikeyan Periyasamy is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 2277d5c65159SKalle Valo 2278acc79d98SSriram R /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2279d5c65159SKalle Valo rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2280d5c65159SKalle Valo RX_FLAG_MMIC_ERROR | 2281d5c65159SKalle Valo RX_FLAG_DECRYPTED | 2282d5c65159SKalle Valo RX_FLAG_IV_STRIPPED | 2283d5c65159SKalle Valo RX_FLAG_MMIC_STRIPPED); 2284d5c65159SKalle Valo 2285d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_FCS) 2286d5c65159SKalle Valo rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2287d5c65159SKalle Valo if (err_bitmap & DP_RX_MPDU_ERR_TKIP_MIC) 2288d5c65159SKalle Valo rx_status->flag |= RX_FLAG_MMIC_ERROR; 2289d5c65159SKalle Valo 22901441b2f2SManikanta Pubbisetty if (is_decrypted) { 22911441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 22921441b2f2SManikanta Pubbisetty 22931441b2f2SManikanta Pubbisetty if (fill_crypto_hdr) 22941441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_MIC_STRIPPED | 22951441b2f2SManikanta Pubbisetty RX_FLAG_ICV_STRIPPED; 22961441b2f2SManikanta Pubbisetty else 22971441b2f2SManikanta Pubbisetty rx_status->flag |= RX_FLAG_IV_STRIPPED | 22981441b2f2SManikanta Pubbisetty RX_FLAG_PN_VALIDATED; 22991441b2f2SManikanta Pubbisetty } 2300d5c65159SKalle Valo 2301e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_h_csum_offload(ar, msdu); 2302d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 2303d5c65159SKalle Valo enctype, rx_status, is_decrypted); 23041441b2f2SManikanta Pubbisetty 23051441b2f2SManikanta Pubbisetty if (!is_decrypted || fill_crypto_hdr) 2306acc79d98SSriram R return; 23071441b2f2SManikanta Pubbisetty 23082167fa60SSriram R if (ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rx_desc) != 23092167fa60SSriram R DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 23101441b2f2SManikanta Pubbisetty hdr = (void *)msdu->data; 23111441b2f2SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2312d5c65159SKalle Valo } 23132167fa60SSriram R } 2314d5c65159SKalle Valo 2315d5c65159SKalle Valo static void ath11k_dp_rx_h_rate(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2316d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2317d5c65159SKalle Valo { 2318d5c65159SKalle Valo struct ieee80211_supported_band *sband; 2319d5c65159SKalle Valo enum rx_msdu_start_pkt_type pkt_type; 2320d5c65159SKalle Valo u8 bw; 2321d5c65159SKalle Valo u8 rate_mcs, nss; 2322d5c65159SKalle Valo u8 sgi; 2323b3febdccSP Praneesh bool is_cck, is_ldpc; 2324d5c65159SKalle Valo 2325e678fbd4SKarthikeyan Periyasamy pkt_type = ath11k_dp_rx_h_msdu_start_pkt_type(ar->ab, rx_desc); 2326e678fbd4SKarthikeyan Periyasamy bw = ath11k_dp_rx_h_msdu_start_rx_bw(ar->ab, rx_desc); 2327e678fbd4SKarthikeyan Periyasamy rate_mcs = ath11k_dp_rx_h_msdu_start_rate_mcs(ar->ab, rx_desc); 2328e678fbd4SKarthikeyan Periyasamy nss = ath11k_dp_rx_h_msdu_start_nss(ar->ab, rx_desc); 2329e678fbd4SKarthikeyan Periyasamy sgi = ath11k_dp_rx_h_msdu_start_sgi(ar->ab, rx_desc); 2330d5c65159SKalle Valo 2331d5c65159SKalle Valo switch (pkt_type) { 2332d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11A: 2333d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11B: 2334d5c65159SKalle Valo is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2335d5c65159SKalle Valo sband = &ar->mac.sbands[rx_status->band]; 2336d5c65159SKalle Valo rx_status->rate_idx = ath11k_mac_hw_rate_to_idx(sband, rate_mcs, 2337d5c65159SKalle Valo is_cck); 2338d5c65159SKalle Valo break; 2339d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11N: 2340d5c65159SKalle Valo rx_status->encoding = RX_ENC_HT; 2341d5c65159SKalle Valo if (rate_mcs > ATH11K_HT_MCS_MAX) { 2342d5c65159SKalle Valo ath11k_warn(ar->ab, 2343d5c65159SKalle Valo "Received with invalid mcs in HT mode %d\n", 2344d5c65159SKalle Valo rate_mcs); 2345d5c65159SKalle Valo break; 2346d5c65159SKalle Valo } 2347d5c65159SKalle Valo rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2348d5c65159SKalle Valo if (sgi) 2349d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 235039e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2351d5c65159SKalle Valo break; 2352d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AC: 2353d5c65159SKalle Valo rx_status->encoding = RX_ENC_VHT; 2354d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2355d5c65159SKalle Valo if (rate_mcs > ATH11K_VHT_MCS_MAX) { 2356d5c65159SKalle Valo ath11k_warn(ar->ab, 2357d5c65159SKalle Valo "Received with invalid mcs in VHT mode %d\n", 2358d5c65159SKalle Valo rate_mcs); 2359d5c65159SKalle Valo break; 2360d5c65159SKalle Valo } 2361d5c65159SKalle Valo rx_status->nss = nss; 2362d5c65159SKalle Valo if (sgi) 2363d5c65159SKalle Valo rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 236439e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2365b3febdccSP Praneesh is_ldpc = ath11k_dp_rx_h_msdu_start_ldpc_support(ar->ab, rx_desc); 2366b3febdccSP Praneesh if (is_ldpc) 2367b3febdccSP Praneesh rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2368d5c65159SKalle Valo break; 2369d5c65159SKalle Valo case RX_MSDU_START_PKT_TYPE_11AX: 2370d5c65159SKalle Valo rx_status->rate_idx = rate_mcs; 2371d5c65159SKalle Valo if (rate_mcs > ATH11K_HE_MCS_MAX) { 2372d5c65159SKalle Valo ath11k_warn(ar->ab, 2373d5c65159SKalle Valo "Received with invalid mcs in HE mode %d\n", 2374d5c65159SKalle Valo rate_mcs); 2375d5c65159SKalle Valo break; 2376d5c65159SKalle Valo } 2377d5c65159SKalle Valo rx_status->encoding = RX_ENC_HE; 2378d5c65159SKalle Valo rx_status->nss = nss; 23791b8bb94cSWen Gong rx_status->he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi); 238039e81c6aSTamizh chelvam rx_status->bw = ath11k_mac_bw_to_mac80211_bw(bw); 2381d5c65159SKalle Valo break; 2382d5c65159SKalle Valo } 2383d5c65159SKalle Valo } 2384d5c65159SKalle Valo 2385d5c65159SKalle Valo static void ath11k_dp_rx_h_ppdu(struct ath11k *ar, struct hal_rx_desc *rx_desc, 2386d5c65159SKalle Valo struct ieee80211_rx_status *rx_status) 2387d5c65159SKalle Valo { 2388d5c65159SKalle Valo u8 channel_num; 2389e678fbd4SKarthikeyan Periyasamy u32 center_freq, meta_data; 239035970106SCarl Huang struct ieee80211_channel *channel; 2391d5c65159SKalle Valo 2392d5c65159SKalle Valo rx_status->freq = 0; 2393d5c65159SKalle Valo rx_status->rate_idx = 0; 2394d5c65159SKalle Valo rx_status->nss = 0; 2395d5c65159SKalle Valo rx_status->encoding = RX_ENC_LEGACY; 2396d5c65159SKalle Valo rx_status->bw = RATE_INFO_BW_20; 2397d5c65159SKalle Valo 2398d5c65159SKalle Valo rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2399d5c65159SKalle Valo 2400e678fbd4SKarthikeyan Periyasamy meta_data = ath11k_dp_rx_h_msdu_start_freq(ar->ab, rx_desc); 2401e678fbd4SKarthikeyan Periyasamy channel_num = meta_data; 2402e678fbd4SKarthikeyan Periyasamy center_freq = meta_data >> 16; 2403d5c65159SKalle Valo 24049d6ae1f5SPradeep Kumar Chitrapu if (center_freq >= ATH11K_MIN_6G_FREQ && 24059d6ae1f5SPradeep Kumar Chitrapu center_freq <= ATH11K_MAX_6G_FREQ) { 24065dcf42f8SPradeep Kumar Chitrapu rx_status->band = NL80211_BAND_6GHZ; 24079d6ae1f5SPradeep Kumar Chitrapu rx_status->freq = center_freq; 24085dcf42f8SPradeep Kumar Chitrapu } else if (channel_num >= 1 && channel_num <= 14) { 2409d5c65159SKalle Valo rx_status->band = NL80211_BAND_2GHZ; 2410d5c65159SKalle Valo } else if (channel_num >= 36 && channel_num <= 173) { 2411d5c65159SKalle Valo rx_status->band = NL80211_BAND_5GHZ; 2412d5c65159SKalle Valo } else { 2413de06b2f7SVenkateswara Naralasetty spin_lock_bh(&ar->data_lock); 241435970106SCarl Huang channel = ar->rx_channel; 241535970106SCarl Huang if (channel) { 241635970106SCarl Huang rx_status->band = channel->band; 2417de06b2f7SVenkateswara Naralasetty channel_num = 241835970106SCarl Huang ieee80211_frequency_to_channel(channel->center_freq); 241935970106SCarl Huang } 2420de06b2f7SVenkateswara Naralasetty spin_unlock_bh(&ar->data_lock); 2421de06b2f7SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ", 2422de06b2f7SVenkateswara Naralasetty rx_desc, sizeof(struct hal_rx_desc)); 2423d5c65159SKalle Valo } 2424d5c65159SKalle Valo 24259d6ae1f5SPradeep Kumar Chitrapu if (rx_status->band != NL80211_BAND_6GHZ) 2426d5c65159SKalle Valo rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2427d5c65159SKalle Valo rx_status->band); 2428d5c65159SKalle Valo 2429d5c65159SKalle Valo ath11k_dp_rx_h_rate(ar, rx_desc, rx_status); 2430d5c65159SKalle Valo } 2431d5c65159SKalle Valo 2432d5c65159SKalle Valo static void ath11k_dp_rx_deliver_msdu(struct ath11k *ar, struct napi_struct *napi, 24332167fa60SSriram R struct sk_buff *msdu, 24342167fa60SSriram R struct ieee80211_rx_status *status) 2435d5c65159SKalle Valo { 2436e4eb7b5cSJohn Crispin static const struct ieee80211_radiotap_he known = { 243793634c61SJohn Crispin .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 243893634c61SJohn Crispin IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2439e4eb7b5cSJohn Crispin .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2440e4eb7b5cSJohn Crispin }; 24412167fa60SSriram R struct ieee80211_rx_status *rx_status; 2442e4eb7b5cSJohn Crispin struct ieee80211_radiotap_he *he = NULL; 24432167fa60SSriram R struct ieee80211_sta *pubsta = NULL; 24442167fa60SSriram R struct ath11k_peer *peer; 24452167fa60SSriram R struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 24462167fa60SSriram R u8 decap = DP_RX_DECAP_TYPE_RAW; 24472167fa60SSriram R bool is_mcbc = rxcb->is_mcbc; 24482167fa60SSriram R bool is_eapol = rxcb->is_eapol; 2449d5c65159SKalle Valo 24502167fa60SSriram R if (status->encoding == RX_ENC_HE && 24512167fa60SSriram R !(status->flag & RX_FLAG_RADIOTAP_HE) && 24522167fa60SSriram R !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2453e4eb7b5cSJohn Crispin he = skb_push(msdu, sizeof(known)); 2454e4eb7b5cSJohn Crispin memcpy(he, &known, sizeof(known)); 2455e4eb7b5cSJohn Crispin status->flag |= RX_FLAG_RADIOTAP_HE; 2456e4eb7b5cSJohn Crispin } 2457d5c65159SKalle Valo 24582167fa60SSriram R if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 24592167fa60SSriram R decap = ath11k_dp_rx_h_msdu_start_decap_type(ar->ab, rxcb->rx_desc); 24602167fa60SSriram R 24612167fa60SSriram R spin_lock_bh(&ar->ab->base_lock); 24622167fa60SSriram R peer = ath11k_dp_rx_h_find_peer(ar->ab, msdu); 24632167fa60SSriram R if (peer && peer->sta) 24642167fa60SSriram R pubsta = peer->sta; 24652167fa60SSriram R spin_unlock_bh(&ar->ab->base_lock); 24662167fa60SSriram R 2467d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 24682167fa60SSriram R "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2469d5c65159SKalle Valo msdu, 2470d5c65159SKalle Valo msdu->len, 24712167fa60SSriram R peer ? peer->addr : NULL, 24722167fa60SSriram R rxcb->tid, 24732167fa60SSriram R is_mcbc ? "mcast" : "ucast", 24742167fa60SSriram R rxcb->seq_no, 2475d5c65159SKalle Valo (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2476d5c65159SKalle Valo (status->encoding == RX_ENC_HT) ? "ht" : "", 2477d5c65159SKalle Valo (status->encoding == RX_ENC_VHT) ? "vht" : "", 2478d5c65159SKalle Valo (status->encoding == RX_ENC_HE) ? "he" : "", 2479d5c65159SKalle Valo (status->bw == RATE_INFO_BW_40) ? "40" : "", 2480d5c65159SKalle Valo (status->bw == RATE_INFO_BW_80) ? "80" : "", 2481d5c65159SKalle Valo (status->bw == RATE_INFO_BW_160) ? "160" : "", 2482d5c65159SKalle Valo status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2483d5c65159SKalle Valo status->rate_idx, 2484d5c65159SKalle Valo status->nss, 2485d5c65159SKalle Valo status->freq, 2486d5c65159SKalle Valo status->band, status->flag, 2487d5c65159SKalle Valo !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2488d5c65159SKalle Valo !!(status->flag & RX_FLAG_MMIC_ERROR), 2489d5c65159SKalle Valo !!(status->flag & RX_FLAG_AMSDU_MORE)); 2490d5c65159SKalle Valo 2491aa2092a9SVenkateswara Naralasetty ath11k_dbg_dump(ar->ab, ATH11K_DBG_DP_RX, NULL, "dp rx msdu: ", 2492aa2092a9SVenkateswara Naralasetty msdu->data, msdu->len); 2493aa2092a9SVenkateswara Naralasetty 24942167fa60SSriram R rx_status = IEEE80211_SKB_RXCB(msdu); 24952167fa60SSriram R *rx_status = *status; 24962167fa60SSriram R 2497d5c65159SKalle Valo /* TODO: trace rx packet */ 2498d5c65159SKalle Valo 24992167fa60SSriram R /* PN for multicast packets are not validate in HW, 25002167fa60SSriram R * so skip 802.3 rx path 25012167fa60SSriram R * Also, fast_rx expectes the STA to be authorized, hence 25022167fa60SSriram R * eapol packets are sent in slow path. 25032167fa60SSriram R */ 25042167fa60SSriram R if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 25052167fa60SSriram R !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 25062167fa60SSriram R rx_status->flag |= RX_FLAG_8023; 25072167fa60SSriram R 25082167fa60SSriram R ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 2509d5c65159SKalle Valo } 2510d5c65159SKalle Valo 2511acc79d98SSriram R static int ath11k_dp_rx_process_msdu(struct ath11k *ar, 2512acc79d98SSriram R struct sk_buff *msdu, 25132167fa60SSriram R struct sk_buff_head *msdu_list, 25142167fa60SSriram R struct ieee80211_rx_status *rx_status) 2515d5c65159SKalle Valo { 2516e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 2517acc79d98SSriram R struct hal_rx_desc *rx_desc, *lrx_desc; 2518e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 2519acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2520acc79d98SSriram R struct sk_buff *last_buf; 2521acc79d98SSriram R u8 l3_pad_bytes; 2522d7d43782STamizh Chelvam u8 *hdr_status; 2523acc79d98SSriram R u16 msdu_len; 2524acc79d98SSriram R int ret; 2525e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 2526d5c65159SKalle Valo 2527acc79d98SSriram R last_buf = ath11k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2528acc79d98SSriram R if (!last_buf) { 2529e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, 2530acc79d98SSriram R "No valid Rx buffer to access Atten/MSDU_END/MPDU_END tlvs\n"); 2531acc79d98SSriram R ret = -EIO; 2532acc79d98SSriram R goto free_out; 2533d5c65159SKalle Valo } 2534acc79d98SSriram R 2535acc79d98SSriram R rx_desc = (struct hal_rx_desc *)msdu->data; 2536cd18ed4cSBaochen Qiang if (ath11k_dp_rx_h_attn_msdu_len_err(ab, rx_desc)) { 2537cd18ed4cSBaochen Qiang ath11k_warn(ar->ab, "msdu len not valid\n"); 2538cd18ed4cSBaochen Qiang ret = -EIO; 2539cd18ed4cSBaochen Qiang goto free_out; 2540cd18ed4cSBaochen Qiang } 2541cd18ed4cSBaochen Qiang 2542acc79d98SSriram R lrx_desc = (struct hal_rx_desc *)last_buf->data; 2543e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ab, lrx_desc); 2544e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 2545e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, "msdu_done bit in attention is not set\n"); 2546acc79d98SSriram R ret = -EIO; 2547acc79d98SSriram R goto free_out; 2548acc79d98SSriram R } 2549acc79d98SSriram R 2550acc79d98SSriram R rxcb = ATH11K_SKB_RXCB(msdu); 2551acc79d98SSriram R rxcb->rx_desc = rx_desc; 2552e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ab, rx_desc); 2553e678fbd4SKarthikeyan Periyasamy l3_pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ab, lrx_desc); 2554acc79d98SSriram R 2555acc79d98SSriram R if (rxcb->is_frag) { 2556e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 2557acc79d98SSriram R } else if (!rxcb->is_continuation) { 2558e678fbd4SKarthikeyan Periyasamy if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2559e678fbd4SKarthikeyan Periyasamy hdr_status = ath11k_dp_rx_h_80211_hdr(ab, rx_desc); 2560acc79d98SSriram R ret = -EINVAL; 2561e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, "invalid msdu len %u\n", msdu_len); 2562e678fbd4SKarthikeyan Periyasamy ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 2563d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 2564e678fbd4SKarthikeyan Periyasamy ath11k_dbg_dump(ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 2565d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 2566acc79d98SSriram R goto free_out; 2567acc79d98SSriram R } 2568e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2569e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2570acc79d98SSriram R } else { 2571acc79d98SSriram R ret = ath11k_dp_rx_msdu_coalesce(ar, msdu_list, 2572acc79d98SSriram R msdu, last_buf, 2573acc79d98SSriram R l3_pad_bytes, msdu_len); 2574acc79d98SSriram R if (ret) { 2575e678fbd4SKarthikeyan Periyasamy ath11k_warn(ab, 2576acc79d98SSriram R "failed to coalesce msdu rx buffer%d\n", ret); 2577acc79d98SSriram R goto free_out; 2578acc79d98SSriram R } 2579acc79d98SSriram R } 2580acc79d98SSriram R 25812167fa60SSriram R ath11k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 25822167fa60SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2583acc79d98SSriram R 25842167fa60SSriram R rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2585acc79d98SSriram R 2586acc79d98SSriram R return 0; 2587acc79d98SSriram R 2588acc79d98SSriram R free_out: 2589acc79d98SSriram R return ret; 2590d5c65159SKalle Valo } 2591d5c65159SKalle Valo 2592acc79d98SSriram R static void ath11k_dp_rx_process_received_packets(struct ath11k_base *ab, 2593d5c65159SKalle Valo struct napi_struct *napi, 2594acc79d98SSriram R struct sk_buff_head *msdu_list, 2595db2ecf9fSP Praneesh int mac_id) 2596d5c65159SKalle Valo { 2597d5c65159SKalle Valo struct sk_buff *msdu; 2598acc79d98SSriram R struct ath11k *ar; 25992167fa60SSriram R struct ieee80211_rx_status rx_status = {0}; 2600acc79d98SSriram R int ret; 2601d5c65159SKalle Valo 2602acc79d98SSriram R if (skb_queue_empty(msdu_list)) 2603d5c65159SKalle Valo return; 2604d5c65159SKalle Valo 260540058803SP Praneesh if (unlikely(!rcu_access_pointer(ab->pdevs_active[mac_id]))) { 2606c4d12cb3SP Praneesh __skb_queue_purge(msdu_list); 2607c4d12cb3SP Praneesh return; 2608acc79d98SSriram R } 2609acc79d98SSriram R 261040058803SP Praneesh ar = ab->pdevs[mac_id].ar; 261140058803SP Praneesh if (unlikely(test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags))) { 2612c4d12cb3SP Praneesh __skb_queue_purge(msdu_list); 2613c4d12cb3SP Praneesh return; 2614acc79d98SSriram R } 2615acc79d98SSriram R 2616c4d12cb3SP Praneesh while ((msdu = __skb_dequeue(msdu_list))) { 26172167fa60SSriram R ret = ath11k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 261840058803SP Praneesh if (unlikely(ret)) { 2619acc79d98SSriram R ath11k_dbg(ab, ATH11K_DBG_DATA, 2620acc79d98SSriram R "Unable to process msdu %d", ret); 2621d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2622d5c65159SKalle Valo continue; 2623d5c65159SKalle Valo } 2624d5c65159SKalle Valo 26252167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2626d5c65159SKalle Valo } 2627d5c65159SKalle Valo } 2628d5c65159SKalle Valo 2629acc79d98SSriram R int ath11k_dp_process_rx(struct ath11k_base *ab, int ring_id, 2630acc79d98SSriram R struct napi_struct *napi, int budget) 2631d5c65159SKalle Valo { 2632acc79d98SSriram R struct ath11k_dp *dp = &ab->dp; 2633acc79d98SSriram R struct dp_rxdma_ring *rx_ring; 2634acc79d98SSriram R int num_buffs_reaped[MAX_RADIOS] = {0}; 2635c4d12cb3SP Praneesh struct sk_buff_head msdu_list[MAX_RADIOS]; 2636acc79d98SSriram R struct ath11k_skb_rxcb *rxcb; 2637acc79d98SSriram R int total_msdu_reaped = 0; 2638d5c65159SKalle Valo struct hal_srng *srng; 2639d5c65159SKalle Valo struct sk_buff *msdu; 2640d5c65159SKalle Valo bool done = false; 2641acc79d98SSriram R int buf_id, mac_id; 2642acc79d98SSriram R struct ath11k *ar; 2643c4d12cb3SP Praneesh struct hal_reo_dest_ring *desc; 2644c4d12cb3SP Praneesh enum hal_reo_dest_ring_push_reason push_reason; 2645c4d12cb3SP Praneesh u32 cookie; 2646acc79d98SSriram R int i; 2647d5c65159SKalle Valo 2648c4d12cb3SP Praneesh for (i = 0; i < MAX_RADIOS; i++) 2649c4d12cb3SP Praneesh __skb_queue_head_init(&msdu_list[i]); 2650d5c65159SKalle Valo 2651acc79d98SSriram R srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2652d5c65159SKalle Valo 2653d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2654d5c65159SKalle Valo 2655f2180ccbSRameshkumar Sundaram try_again: 2656d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2657d5c65159SKalle Valo 2658c4d12cb3SP Praneesh while (likely(desc = 2659c4d12cb3SP Praneesh (struct hal_reo_dest_ring *)ath11k_hal_srng_dst_get_next_entry(ab, 2660c4d12cb3SP Praneesh srng))) { 2661293cb583SJohn Crispin cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 2662c4d12cb3SP Praneesh desc->buf_addr_info.info1); 2663d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 2664293cb583SJohn Crispin cookie); 2665acc79d98SSriram R mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, cookie); 2666acc79d98SSriram R 2667acc79d98SSriram R ar = ab->pdevs[mac_id].ar; 2668acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2669d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2670d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 267140058803SP Praneesh if (unlikely(!msdu)) { 2672d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d\n", 2673d5c65159SKalle Valo buf_id); 2674d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2675d5c65159SKalle Valo continue; 2676d5c65159SKalle Valo } 2677d5c65159SKalle Valo 2678d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2679d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2680d5c65159SKalle Valo 2681d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 2682d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 2683d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 2684d5c65159SKalle Valo DMA_FROM_DEVICE); 2685d5c65159SKalle Valo 2686acc79d98SSriram R num_buffs_reaped[mac_id]++; 2687d5c65159SKalle Valo 2688293cb583SJohn Crispin push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 2689c4d12cb3SP Praneesh desc->info0); 269040058803SP Praneesh if (unlikely(push_reason != 269140058803SP Praneesh HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) { 2692d5c65159SKalle Valo dev_kfree_skb_any(msdu); 2693acc79d98SSriram R ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2694d5c65159SKalle Valo continue; 2695d5c65159SKalle Valo } 2696d5c65159SKalle Valo 2697c4d12cb3SP Praneesh rxcb->is_first_msdu = !!(desc->rx_msdu_info.info0 & 2698293cb583SJohn Crispin RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2699c4d12cb3SP Praneesh rxcb->is_last_msdu = !!(desc->rx_msdu_info.info0 & 2700293cb583SJohn Crispin RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2701c4d12cb3SP Praneesh rxcb->is_continuation = !!(desc->rx_msdu_info.info0 & 2702293cb583SJohn Crispin RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 27032167fa60SSriram R rxcb->peer_id = FIELD_GET(RX_MPDU_DESC_META_DATA_PEER_ID, 2704c4d12cb3SP Praneesh desc->rx_mpdu_info.meta_data); 27052167fa60SSriram R rxcb->seq_no = FIELD_GET(RX_MPDU_DESC_INFO0_SEQ_NUM, 2706c4d12cb3SP Praneesh desc->rx_mpdu_info.info0); 2707acc79d98SSriram R rxcb->tid = FIELD_GET(HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM, 2708c4d12cb3SP Praneesh desc->info0); 2709acc79d98SSriram R 27102167fa60SSriram R rxcb->mac_id = mac_id; 2711c4d12cb3SP Praneesh __skb_queue_tail(&msdu_list[mac_id], msdu); 2712d5c65159SKalle Valo 2713a1775e73SP Praneesh if (rxcb->is_continuation) { 2714a1775e73SP Praneesh done = false; 2715a1775e73SP Praneesh } else { 2716a1775e73SP Praneesh total_msdu_reaped++; 2717d5c65159SKalle Valo done = true; 2718d5c65159SKalle Valo } 2719a1775e73SP Praneesh 2720a1775e73SP Praneesh if (total_msdu_reaped >= budget) 2721a1775e73SP Praneesh break; 2722d5c65159SKalle Valo } 2723d5c65159SKalle Valo 2724d5c65159SKalle Valo /* Hw might have updated the head pointer after we cached it. 2725d5c65159SKalle Valo * In this case, even though there are entries in the ring we'll 2726d5c65159SKalle Valo * get rx_desc NULL. Give the read another try with updated cached 2727d5c65159SKalle Valo * head pointer so that we can reap complete MPDU in the current 2728d5c65159SKalle Valo * rx processing. 2729d5c65159SKalle Valo */ 273040058803SP Praneesh if (unlikely(!done && ath11k_hal_srng_dst_num_free(ab, srng, true))) { 2731d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2732d5c65159SKalle Valo goto try_again; 2733d5c65159SKalle Valo } 2734d5c65159SKalle Valo 2735d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2736d5c65159SKalle Valo 2737d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2738d5c65159SKalle Valo 273940058803SP Praneesh if (unlikely(!total_msdu_reaped)) 2740d5c65159SKalle Valo goto exit; 2741d5c65159SKalle Valo 2742acc79d98SSriram R for (i = 0; i < ab->num_radios; i++) { 2743acc79d98SSriram R if (!num_buffs_reaped[i]) 2744d5c65159SKalle Valo continue; 2745acc79d98SSriram R 2746db2ecf9fSP Praneesh ath11k_dp_rx_process_received_packets(ab, napi, &msdu_list[i], i); 2747c4d12cb3SP Praneesh 2748acc79d98SSriram R ar = ab->pdevs[i].ar; 2749acc79d98SSriram R rx_ring = &ar->dp.rx_refill_buf_ring; 2750acc79d98SSriram R 2751acc79d98SSriram R ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 2752734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 2753d5c65159SKalle Valo } 2754d5c65159SKalle Valo exit: 2755db2ecf9fSP Praneesh return total_msdu_reaped; 2756d5c65159SKalle Valo } 2757d5c65159SKalle Valo 2758d5c65159SKalle Valo static void ath11k_dp_rx_update_peer_stats(struct ath11k_sta *arsta, 2759d5c65159SKalle Valo struct hal_rx_mon_ppdu_info *ppdu_info) 2760d5c65159SKalle Valo { 2761d5c65159SKalle Valo struct ath11k_rx_peer_stats *rx_stats = arsta->rx_stats; 2762d5c65159SKalle Valo u32 num_msdu; 2763b488c766SWen Gong int i; 2764d5c65159SKalle Valo 2765d5c65159SKalle Valo if (!rx_stats) 2766d5c65159SKalle Valo return; 2767d5c65159SKalle Valo 2768d5c65159SKalle Valo num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2769d5c65159SKalle Valo ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2770d5c65159SKalle Valo 2771d5c65159SKalle Valo rx_stats->num_msdu += num_msdu; 2772d5c65159SKalle Valo rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2773d5c65159SKalle Valo ppdu_info->tcp_ack_msdu_count; 2774d5c65159SKalle Valo rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2775d5c65159SKalle Valo rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2776d5c65159SKalle Valo 2777d5c65159SKalle Valo if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2778d5c65159SKalle Valo ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2779d5c65159SKalle Valo ppdu_info->nss = 1; 2780d5c65159SKalle Valo ppdu_info->mcs = HAL_RX_MAX_MCS; 2781d5c65159SKalle Valo ppdu_info->tid = IEEE80211_NUM_TIDS; 2782d5c65159SKalle Valo } 2783d5c65159SKalle Valo 2784d5c65159SKalle Valo if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) 2785d5c65159SKalle Valo rx_stats->nss_count[ppdu_info->nss - 1] += num_msdu; 2786d5c65159SKalle Valo 2787d5c65159SKalle Valo if (ppdu_info->mcs <= HAL_RX_MAX_MCS) 2788d5c65159SKalle Valo rx_stats->mcs_count[ppdu_info->mcs] += num_msdu; 2789d5c65159SKalle Valo 2790d5c65159SKalle Valo if (ppdu_info->gi < HAL_RX_GI_MAX) 2791d5c65159SKalle Valo rx_stats->gi_count[ppdu_info->gi] += num_msdu; 2792d5c65159SKalle Valo 2793d5c65159SKalle Valo if (ppdu_info->bw < HAL_RX_BW_MAX) 2794d5c65159SKalle Valo rx_stats->bw_count[ppdu_info->bw] += num_msdu; 2795d5c65159SKalle Valo 2796d5c65159SKalle Valo if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2797d5c65159SKalle Valo rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2798d5c65159SKalle Valo 2799d5c65159SKalle Valo if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2800d5c65159SKalle Valo rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2801d5c65159SKalle Valo 2802d5c65159SKalle Valo if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2803d5c65159SKalle Valo rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2804d5c65159SKalle Valo 2805d5c65159SKalle Valo if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2806d5c65159SKalle Valo rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2807d5c65159SKalle Valo 2808d5c65159SKalle Valo if (ppdu_info->is_stbc) 2809d5c65159SKalle Valo rx_stats->stbc_count += num_msdu; 2810d5c65159SKalle Valo 2811d5c65159SKalle Valo if (ppdu_info->beamformed) 2812d5c65159SKalle Valo rx_stats->beamformed_count += num_msdu; 2813d5c65159SKalle Valo 2814d5c65159SKalle Valo if (ppdu_info->num_mpdu_fcs_ok > 1) 2815d5c65159SKalle Valo rx_stats->ampdu_msdu_count += num_msdu; 2816d5c65159SKalle Valo else 2817d5c65159SKalle Valo rx_stats->non_ampdu_msdu_count += num_msdu; 2818d5c65159SKalle Valo 2819d5c65159SKalle Valo rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2820d5c65159SKalle Valo rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 28216a0c3702SJohn Crispin rx_stats->dcm_count += ppdu_info->dcm; 28226a0c3702SJohn Crispin rx_stats->ru_alloc_cnt[ppdu_info->ru_alloc] += num_msdu; 2823d5c65159SKalle Valo 2824d5c65159SKalle Valo arsta->rssi_comb = ppdu_info->rssi_comb; 2825b488c766SWen Gong 2826b488c766SWen Gong BUILD_BUG_ON(ARRAY_SIZE(arsta->chain_signal) > 2827b488c766SWen Gong ARRAY_SIZE(ppdu_info->rssi_chain_pri20)); 2828b488c766SWen Gong 2829b488c766SWen Gong for (i = 0; i < ARRAY_SIZE(arsta->chain_signal); i++) 2830b488c766SWen Gong arsta->chain_signal[i] = ppdu_info->rssi_chain_pri20[i]; 2831b488c766SWen Gong 2832d5c65159SKalle Valo rx_stats->rx_duration += ppdu_info->rx_duration; 2833d5c65159SKalle Valo arsta->rx_duration = rx_stats->rx_duration; 2834d5c65159SKalle Valo } 2835d5c65159SKalle Valo 2836d5c65159SKalle Valo static struct sk_buff *ath11k_dp_rx_alloc_mon_status_buf(struct ath11k_base *ab, 2837d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 283887e8497aSGovind Singh int *buf_id) 2839d5c65159SKalle Valo { 2840d5c65159SKalle Valo struct sk_buff *skb; 2841d5c65159SKalle Valo dma_addr_t paddr; 2842d5c65159SKalle Valo 2843d5c65159SKalle Valo skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 2844d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE); 2845d5c65159SKalle Valo 2846d5c65159SKalle Valo if (!skb) 2847d5c65159SKalle Valo goto fail_alloc_skb; 2848d5c65159SKalle Valo 2849d5c65159SKalle Valo if (!IS_ALIGNED((unsigned long)skb->data, 2850d5c65159SKalle Valo DP_RX_BUFFER_ALIGN_SIZE)) { 2851d5c65159SKalle Valo skb_pull(skb, PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 2852d5c65159SKalle Valo skb->data); 2853d5c65159SKalle Valo } 2854d5c65159SKalle Valo 2855d5c65159SKalle Valo paddr = dma_map_single(ab->dev, skb->data, 2856d5c65159SKalle Valo skb->len + skb_tailroom(skb), 2857cd6181ffSKalle Valo DMA_FROM_DEVICE); 2858d5c65159SKalle Valo if (unlikely(dma_mapping_error(ab->dev, paddr))) 2859d5c65159SKalle Valo goto fail_free_skb; 2860d5c65159SKalle Valo 2861d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2862d5c65159SKalle Valo *buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 286387e8497aSGovind Singh rx_ring->bufs_max, GFP_ATOMIC); 2864d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2865d5c65159SKalle Valo if (*buf_id < 0) 2866d5c65159SKalle Valo goto fail_dma_unmap; 2867d5c65159SKalle Valo 2868d5c65159SKalle Valo ATH11K_SKB_RXCB(skb)->paddr = paddr; 2869d5c65159SKalle Valo return skb; 2870d5c65159SKalle Valo 2871d5c65159SKalle Valo fail_dma_unmap: 2872d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2873cd6181ffSKalle Valo DMA_FROM_DEVICE); 2874d5c65159SKalle Valo fail_free_skb: 2875d5c65159SKalle Valo dev_kfree_skb_any(skb); 2876d5c65159SKalle Valo fail_alloc_skb: 2877d5c65159SKalle Valo return NULL; 2878d5c65159SKalle Valo } 2879d5c65159SKalle Valo 2880d5c65159SKalle Valo int ath11k_dp_rx_mon_status_bufs_replenish(struct ath11k_base *ab, int mac_id, 2881d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring, 2882d5c65159SKalle Valo int req_entries, 288387e8497aSGovind Singh enum hal_rx_buf_return_buf_manager mgr) 2884d5c65159SKalle Valo { 2885d5c65159SKalle Valo struct hal_srng *srng; 2886d5c65159SKalle Valo u32 *desc; 2887d5c65159SKalle Valo struct sk_buff *skb; 2888d5c65159SKalle Valo int num_free; 2889d5c65159SKalle Valo int num_remain; 2890d5c65159SKalle Valo int buf_id; 2891d5c65159SKalle Valo u32 cookie; 2892d5c65159SKalle Valo dma_addr_t paddr; 2893d5c65159SKalle Valo 2894d5c65159SKalle Valo req_entries = min(req_entries, rx_ring->bufs_max); 2895d5c65159SKalle Valo 2896d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 2897d5c65159SKalle Valo 2898d5c65159SKalle Valo spin_lock_bh(&srng->lock); 2899d5c65159SKalle Valo 2900d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 2901d5c65159SKalle Valo 2902d5c65159SKalle Valo num_free = ath11k_hal_srng_src_num_free(ab, srng, true); 2903d5c65159SKalle Valo 2904d5c65159SKalle Valo req_entries = min(num_free, req_entries); 2905d5c65159SKalle Valo num_remain = req_entries; 2906d5c65159SKalle Valo 2907d5c65159SKalle Valo while (num_remain > 0) { 2908d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 290987e8497aSGovind Singh &buf_id); 2910d5c65159SKalle Valo if (!skb) 2911d5c65159SKalle Valo break; 2912d5c65159SKalle Valo paddr = ATH11K_SKB_RXCB(skb)->paddr; 2913d5c65159SKalle Valo 2914d5c65159SKalle Valo desc = ath11k_hal_srng_src_get_next_entry(ab, srng); 2915d5c65159SKalle Valo if (!desc) 2916d5c65159SKalle Valo goto fail_desc_get; 2917d5c65159SKalle Valo 2918d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 2919d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 2920d5c65159SKalle Valo 2921d5c65159SKalle Valo num_remain--; 2922d5c65159SKalle Valo 2923d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 2924d5c65159SKalle Valo } 2925d5c65159SKalle Valo 2926d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2927d5c65159SKalle Valo 2928d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2929d5c65159SKalle Valo 2930d5c65159SKalle Valo return req_entries - num_remain; 2931d5c65159SKalle Valo 2932d5c65159SKalle Valo fail_desc_get: 2933d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 2934d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 2935d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 2936d5c65159SKalle Valo dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 2937cd6181ffSKalle Valo DMA_FROM_DEVICE); 2938d5c65159SKalle Valo dev_kfree_skb_any(skb); 2939d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 2940d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 2941d5c65159SKalle Valo 2942d5c65159SKalle Valo return req_entries - num_remain; 2943d5c65159SKalle Valo } 2944d5c65159SKalle Valo 29457e2ea2e9SAnilkumar Kolli #define ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP 32535 29467e2ea2e9SAnilkumar Kolli 29477e2ea2e9SAnilkumar Kolli static void 29487e2ea2e9SAnilkumar Kolli ath11k_dp_rx_mon_update_status_buf_state(struct ath11k_mon_data *pmon, 29497e2ea2e9SAnilkumar Kolli struct hal_tlv_hdr *tlv) 29507e2ea2e9SAnilkumar Kolli { 29517e2ea2e9SAnilkumar Kolli struct hal_rx_ppdu_start *ppdu_start; 29527e2ea2e9SAnilkumar Kolli u16 ppdu_id_diff, ppdu_id, tlv_len; 29537e2ea2e9SAnilkumar Kolli u8 *ptr; 29547e2ea2e9SAnilkumar Kolli 29557e2ea2e9SAnilkumar Kolli /* PPDU id is part of second tlv, move ptr to second tlv */ 29567e2ea2e9SAnilkumar Kolli tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 29577e2ea2e9SAnilkumar Kolli ptr = (u8 *)tlv; 29587e2ea2e9SAnilkumar Kolli ptr += sizeof(*tlv) + tlv_len; 29597e2ea2e9SAnilkumar Kolli tlv = (struct hal_tlv_hdr *)ptr; 29607e2ea2e9SAnilkumar Kolli 29617e2ea2e9SAnilkumar Kolli if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != HAL_RX_PPDU_START) 29627e2ea2e9SAnilkumar Kolli return; 29637e2ea2e9SAnilkumar Kolli 29647e2ea2e9SAnilkumar Kolli ptr += sizeof(*tlv); 29657e2ea2e9SAnilkumar Kolli ppdu_start = (struct hal_rx_ppdu_start *)ptr; 29667e2ea2e9SAnilkumar Kolli ppdu_id = FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 29677e2ea2e9SAnilkumar Kolli __le32_to_cpu(ppdu_start->info0)); 29687e2ea2e9SAnilkumar Kolli 29697e2ea2e9SAnilkumar Kolli if (pmon->sw_mon_entries.ppdu_id < ppdu_id) { 29707e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_LEAD; 29717e2ea2e9SAnilkumar Kolli ppdu_id_diff = ppdu_id - pmon->sw_mon_entries.ppdu_id; 29727e2ea2e9SAnilkumar Kolli if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 29737e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_LAG; 29747e2ea2e9SAnilkumar Kolli } else if (pmon->sw_mon_entries.ppdu_id > ppdu_id) { 29757e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_LAG; 29767e2ea2e9SAnilkumar Kolli ppdu_id_diff = pmon->sw_mon_entries.ppdu_id - ppdu_id; 29777e2ea2e9SAnilkumar Kolli if (ppdu_id_diff > ATH11K_DP_RX_FULL_MON_PPDU_ID_WRAP) 29787e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_LEAD; 29797e2ea2e9SAnilkumar Kolli } 29807e2ea2e9SAnilkumar Kolli } 29817e2ea2e9SAnilkumar Kolli 2982d5c65159SKalle Valo static int ath11k_dp_rx_reap_mon_status_ring(struct ath11k_base *ab, int mac_id, 2983d5c65159SKalle Valo int *budget, struct sk_buff_head *skb_list) 2984d5c65159SKalle Valo { 29854152e420SCarl Huang struct ath11k *ar; 2986734223d7SBaochen Qiang const struct ath11k_hw_hal_params *hal_params; 29874152e420SCarl Huang struct ath11k_pdev_dp *dp; 29884152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 29897e2ea2e9SAnilkumar Kolli struct ath11k_mon_data *pmon; 2990d5c65159SKalle Valo struct hal_srng *srng; 2991d5c65159SKalle Valo void *rx_mon_status_desc; 2992d5c65159SKalle Valo struct sk_buff *skb; 2993d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 2994d5c65159SKalle Valo struct hal_tlv_hdr *tlv; 2995d5c65159SKalle Valo u32 cookie; 29964152e420SCarl Huang int buf_id, srng_id; 2997d5c65159SKalle Valo dma_addr_t paddr; 2998d5c65159SKalle Valo u8 rbm; 2999d5c65159SKalle Valo int num_buffs_reaped = 0; 3000d5c65159SKalle Valo 30014152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 30024152e420SCarl Huang dp = &ar->dp; 30037e2ea2e9SAnilkumar Kolli pmon = &dp->mon_data; 30044152e420SCarl Huang srng_id = ath11k_hw_mac_id_to_srng_id(&ab->hw_params, mac_id); 30054152e420SCarl Huang rx_ring = &dp->rx_mon_status_refill_ring[srng_id]; 30064152e420SCarl Huang 3007d5c65159SKalle Valo srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 3008d5c65159SKalle Valo 3009d5c65159SKalle Valo spin_lock_bh(&srng->lock); 3010d5c65159SKalle Valo 3011d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 3012d5c65159SKalle Valo while (*budget) { 3013d5c65159SKalle Valo *budget -= 1; 3014d5c65159SKalle Valo rx_mon_status_desc = 3015d5c65159SKalle Valo ath11k_hal_srng_src_peek(ab, srng); 30167e2ea2e9SAnilkumar Kolli if (!rx_mon_status_desc) { 30177e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_REPLINISH; 3018d5c65159SKalle Valo break; 30197e2ea2e9SAnilkumar Kolli } 3020d5c65159SKalle Valo 3021d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_get(rx_mon_status_desc, &paddr, 3022d5c65159SKalle Valo &cookie, &rbm); 3023d5c65159SKalle Valo if (paddr) { 3024d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, cookie); 3025d5c65159SKalle Valo 3026d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 3027d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 3028d5c65159SKalle Valo if (!skb) { 3029d5c65159SKalle Valo ath11k_warn(ab, "rx monitor status with invalid buf_id %d\n", 3030d5c65159SKalle Valo buf_id); 3031d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 30327e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_REPLINISH; 303332a2be49SMiles Hu goto move_next; 3034d5c65159SKalle Valo } 3035d5c65159SKalle Valo 3036d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 3037d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3038d5c65159SKalle Valo 3039d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3040d5c65159SKalle Valo 3041d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 3042d5c65159SKalle Valo skb->len + skb_tailroom(skb), 3043cd6181ffSKalle Valo DMA_FROM_DEVICE); 3044d5c65159SKalle Valo 3045d5c65159SKalle Valo tlv = (struct hal_tlv_hdr *)skb->data; 3046d5c65159SKalle Valo if (FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl) != 3047d5c65159SKalle Valo HAL_RX_STATUS_BUFFER_DONE) { 304832a2be49SMiles Hu ath11k_warn(ab, "mon status DONE not set %lx\n", 304932a2be49SMiles Hu FIELD_GET(HAL_TLV_HDR_TAG, 305032a2be49SMiles Hu tlv->tl)); 305132a2be49SMiles Hu dev_kfree_skb_any(skb); 30527e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_NO_DMA; 305332a2be49SMiles Hu goto move_next; 3054d5c65159SKalle Valo } 3055d5c65159SKalle Valo 30567e2ea2e9SAnilkumar Kolli if (ab->hw_params.full_monitor_mode) { 30577e2ea2e9SAnilkumar Kolli ath11k_dp_rx_mon_update_status_buf_state(pmon, tlv); 30587e2ea2e9SAnilkumar Kolli if (paddr == pmon->mon_status_paddr) 30597e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_MATCH; 30607e2ea2e9SAnilkumar Kolli } 3061d5c65159SKalle Valo __skb_queue_tail(skb_list, skb); 30627e2ea2e9SAnilkumar Kolli } else { 30637e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_REPLINISH; 3064d5c65159SKalle Valo } 306532a2be49SMiles Hu move_next: 3066d5c65159SKalle Valo skb = ath11k_dp_rx_alloc_mon_status_buf(ab, rx_ring, 306787e8497aSGovind Singh &buf_id); 3068d5c65159SKalle Valo 3069d5c65159SKalle Valo if (!skb) { 3070734223d7SBaochen Qiang hal_params = ab->hw_params.hal_params; 3071d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, 0, 0, 3072734223d7SBaochen Qiang hal_params->rx_buf_rbm); 3073d5c65159SKalle Valo num_buffs_reaped++; 3074d5c65159SKalle Valo break; 3075d5c65159SKalle Valo } 3076d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3077d5c65159SKalle Valo 3078d5c65159SKalle Valo cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, mac_id) | 3079d5c65159SKalle Valo FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3080d5c65159SKalle Valo 3081d5c65159SKalle Valo ath11k_hal_rx_buf_addr_info_set(rx_mon_status_desc, rxcb->paddr, 3082734223d7SBaochen Qiang cookie, 3083734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3084d5c65159SKalle Valo ath11k_hal_srng_src_get_next_entry(ab, srng); 3085d5c65159SKalle Valo num_buffs_reaped++; 3086d5c65159SKalle Valo } 3087d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3088d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3089d5c65159SKalle Valo 3090d5c65159SKalle Valo return num_buffs_reaped; 3091d5c65159SKalle Valo } 3092d5c65159SKalle Valo 3093243874c6SManikanta Pubbisetty static void ath11k_dp_rx_frag_timer(struct timer_list *timer) 3094d5c65159SKalle Valo { 3095243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 3096d5c65159SKalle Valo 3097243874c6SManikanta Pubbisetty spin_lock_bh(&rx_tid->ab->base_lock); 3098243874c6SManikanta Pubbisetty if (rx_tid->last_frag_no && 3099243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 3100243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 3101243874c6SManikanta Pubbisetty return; 3102243874c6SManikanta Pubbisetty } 3103243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3104243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_tid->ab->base_lock); 3105d5c65159SKalle Valo } 3106d5c65159SKalle Valo 3107243874c6SManikanta Pubbisetty int ath11k_peer_rx_frag_setup(struct ath11k *ar, const u8 *peer_mac, int vdev_id) 3108243874c6SManikanta Pubbisetty { 3109243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3110243874c6SManikanta Pubbisetty struct crypto_shash *tfm; 3111243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 3112243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 3113243874c6SManikanta Pubbisetty int i; 3114d5c65159SKalle Valo 3115243874c6SManikanta Pubbisetty tfm = crypto_alloc_shash("michael_mic", 0, 0); 3116243874c6SManikanta Pubbisetty if (IS_ERR(tfm)) 3117243874c6SManikanta Pubbisetty return PTR_ERR(tfm); 3118d5c65159SKalle Valo 3119243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3120d5c65159SKalle Valo 3121243874c6SManikanta Pubbisetty peer = ath11k_peer_find(ab, vdev_id, peer_mac); 3122243874c6SManikanta Pubbisetty if (!peer) { 3123243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to set up fragment info\n"); 3124243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3125243874c6SManikanta Pubbisetty return -ENOENT; 3126243874c6SManikanta Pubbisetty } 3127243874c6SManikanta Pubbisetty 3128243874c6SManikanta Pubbisetty for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 3129243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[i]; 3130243874c6SManikanta Pubbisetty rx_tid->ab = ab; 3131243874c6SManikanta Pubbisetty timer_setup(&rx_tid->frag_timer, ath11k_dp_rx_frag_timer, 0); 3132243874c6SManikanta Pubbisetty skb_queue_head_init(&rx_tid->rx_frags); 3133243874c6SManikanta Pubbisetty } 3134243874c6SManikanta Pubbisetty 3135243874c6SManikanta Pubbisetty peer->tfm_mmic = tfm; 3136243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3137243874c6SManikanta Pubbisetty 3138243874c6SManikanta Pubbisetty return 0; 3139243874c6SManikanta Pubbisetty } 3140243874c6SManikanta Pubbisetty 3141243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 3142243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr, u8 *data, 3143243874c6SManikanta Pubbisetty size_t data_len, u8 *mic) 3144243874c6SManikanta Pubbisetty { 3145243874c6SManikanta Pubbisetty SHASH_DESC_ON_STACK(desc, tfm); 3146243874c6SManikanta Pubbisetty u8 mic_hdr[16] = {0}; 3147243874c6SManikanta Pubbisetty u8 tid = 0; 3148243874c6SManikanta Pubbisetty int ret; 3149243874c6SManikanta Pubbisetty 3150243874c6SManikanta Pubbisetty if (!tfm) 3151243874c6SManikanta Pubbisetty return -EINVAL; 3152243874c6SManikanta Pubbisetty 3153243874c6SManikanta Pubbisetty desc->tfm = tfm; 3154243874c6SManikanta Pubbisetty 3155243874c6SManikanta Pubbisetty ret = crypto_shash_setkey(tfm, key, 8); 3156243874c6SManikanta Pubbisetty if (ret) 3157243874c6SManikanta Pubbisetty goto out; 3158243874c6SManikanta Pubbisetty 3159243874c6SManikanta Pubbisetty ret = crypto_shash_init(desc); 3160243874c6SManikanta Pubbisetty if (ret) 3161243874c6SManikanta Pubbisetty goto out; 3162243874c6SManikanta Pubbisetty 3163243874c6SManikanta Pubbisetty /* TKIP MIC header */ 3164243874c6SManikanta Pubbisetty memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 3165243874c6SManikanta Pubbisetty memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 3166243874c6SManikanta Pubbisetty if (ieee80211_is_data_qos(hdr->frame_control)) 3167243874c6SManikanta Pubbisetty tid = ieee80211_get_tid(hdr); 3168243874c6SManikanta Pubbisetty mic_hdr[12] = tid; 3169243874c6SManikanta Pubbisetty 3170243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, mic_hdr, 16); 3171243874c6SManikanta Pubbisetty if (ret) 3172243874c6SManikanta Pubbisetty goto out; 3173243874c6SManikanta Pubbisetty ret = crypto_shash_update(desc, data, data_len); 3174243874c6SManikanta Pubbisetty if (ret) 3175243874c6SManikanta Pubbisetty goto out; 3176243874c6SManikanta Pubbisetty ret = crypto_shash_final(desc, mic); 3177243874c6SManikanta Pubbisetty out: 3178243874c6SManikanta Pubbisetty shash_desc_zero(desc); 3179d5c65159SKalle Valo return ret; 3180d5c65159SKalle Valo } 3181d5c65159SKalle Valo 3182243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_verify_tkip_mic(struct ath11k *ar, struct ath11k_peer *peer, 3183243874c6SManikanta Pubbisetty struct sk_buff *msdu) 3184d5c65159SKalle Valo { 3185243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3186243874c6SManikanta Pubbisetty struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 3187243874c6SManikanta Pubbisetty struct ieee80211_key_conf *key_conf; 3188243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3189243874c6SManikanta Pubbisetty u8 mic[IEEE80211_CCMP_MIC_LEN]; 3190243874c6SManikanta Pubbisetty int head_len, tail_len, ret; 3191243874c6SManikanta Pubbisetty size_t data_len; 3192e678fbd4SKarthikeyan Periyasamy u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3193243874c6SManikanta Pubbisetty u8 *key, *data; 3194243874c6SManikanta Pubbisetty u8 key_idx; 3195d5c65159SKalle Valo 3196e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc) != 3197e678fbd4SKarthikeyan Periyasamy HAL_ENCRYPT_TYPE_TKIP_MIC) 3198243874c6SManikanta Pubbisetty return 0; 3199d5c65159SKalle Valo 3200e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3201243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3202e678fbd4SKarthikeyan Periyasamy head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 3203243874c6SManikanta Pubbisetty tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 3204d5c65159SKalle Valo 3205243874c6SManikanta Pubbisetty if (!is_multicast_ether_addr(hdr->addr1)) 3206243874c6SManikanta Pubbisetty key_idx = peer->ucast_keyidx; 3207243874c6SManikanta Pubbisetty else 3208243874c6SManikanta Pubbisetty key_idx = peer->mcast_keyidx; 3209d5c65159SKalle Valo 3210243874c6SManikanta Pubbisetty key_conf = peer->keys[key_idx]; 3211d5c65159SKalle Valo 3212243874c6SManikanta Pubbisetty data = msdu->data + head_len; 3213243874c6SManikanta Pubbisetty data_len = msdu->len - head_len - tail_len; 3214243874c6SManikanta Pubbisetty key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 3215d5c65159SKalle Valo 3216243874c6SManikanta Pubbisetty ret = ath11k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 3217243874c6SManikanta Pubbisetty if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 3218243874c6SManikanta Pubbisetty goto mic_fail; 3219d5c65159SKalle Valo 3220243874c6SManikanta Pubbisetty return 0; 3221243874c6SManikanta Pubbisetty 3222243874c6SManikanta Pubbisetty mic_fail: 3223b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_first_msdu = true; 3224b7b527b9SJason Yan (ATH11K_SKB_RXCB(msdu))->is_last_msdu = true; 3225243874c6SManikanta Pubbisetty 3226243874c6SManikanta Pubbisetty rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 3227243874c6SManikanta Pubbisetty RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 3228e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 3229243874c6SManikanta Pubbisetty 3230243874c6SManikanta Pubbisetty ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 3231243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap(ar, msdu, rx_desc, 3232243874c6SManikanta Pubbisetty HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 3233243874c6SManikanta Pubbisetty ieee80211_rx(ar->hw, msdu); 3234243874c6SManikanta Pubbisetty return -EINVAL; 3235d5c65159SKalle Valo } 3236d5c65159SKalle Valo 3237243874c6SManikanta Pubbisetty static void ath11k_dp_rx_h_undecap_frag(struct ath11k *ar, struct sk_buff *msdu, 3238243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype, u32 flags) 3239243874c6SManikanta Pubbisetty { 3240243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3241243874c6SManikanta Pubbisetty size_t hdr_len; 3242243874c6SManikanta Pubbisetty size_t crypto_len; 3243e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3244d5c65159SKalle Valo 3245243874c6SManikanta Pubbisetty if (!flags) 3246243874c6SManikanta Pubbisetty return; 3247d5c65159SKalle Valo 3248e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 3249243874c6SManikanta Pubbisetty 3250243874c6SManikanta Pubbisetty if (flags & RX_FLAG_MIC_STRIPPED) 3251d5c65159SKalle Valo skb_trim(msdu, msdu->len - 3252d5c65159SKalle Valo ath11k_dp_rx_crypto_mic_len(ar, enctype)); 3253243874c6SManikanta Pubbisetty 3254243874c6SManikanta Pubbisetty if (flags & RX_FLAG_ICV_STRIPPED) 3255243874c6SManikanta Pubbisetty skb_trim(msdu, msdu->len - 3256243874c6SManikanta Pubbisetty ath11k_dp_rx_crypto_icv_len(ar, enctype)); 3257243874c6SManikanta Pubbisetty 3258243874c6SManikanta Pubbisetty if (flags & RX_FLAG_IV_STRIPPED) { 3259243874c6SManikanta Pubbisetty hdr_len = ieee80211_hdrlen(hdr->frame_control); 3260243874c6SManikanta Pubbisetty crypto_len = ath11k_dp_rx_crypto_param_len(ar, enctype); 3261243874c6SManikanta Pubbisetty 3262e678fbd4SKarthikeyan Periyasamy memmove((void *)msdu->data + hal_rx_desc_sz + crypto_len, 3263e678fbd4SKarthikeyan Periyasamy (void *)msdu->data + hal_rx_desc_sz, hdr_len); 3264243874c6SManikanta Pubbisetty skb_pull(msdu, crypto_len); 3265d5c65159SKalle Valo } 3266d5c65159SKalle Valo } 3267d5c65159SKalle Valo 3268243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag(struct ath11k *ar, 3269243874c6SManikanta Pubbisetty struct ath11k_peer *peer, 3270243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid, 3271243874c6SManikanta Pubbisetty struct sk_buff **defrag_skb) 3272243874c6SManikanta Pubbisetty { 3273243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3274243874c6SManikanta Pubbisetty struct sk_buff *skb, *first_frag, *last_frag; 3275243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3276e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 3277243874c6SManikanta Pubbisetty enum hal_encrypt_type enctype; 3278243874c6SManikanta Pubbisetty bool is_decrypted = false; 3279243874c6SManikanta Pubbisetty int msdu_len = 0; 3280243874c6SManikanta Pubbisetty int extra_space; 3281e678fbd4SKarthikeyan Periyasamy u32 flags, hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3282243874c6SManikanta Pubbisetty 3283243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3284243874c6SManikanta Pubbisetty last_frag = skb_peek_tail(&rx_tid->rx_frags); 3285243874c6SManikanta Pubbisetty 3286243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3287243874c6SManikanta Pubbisetty flags = 0; 3288243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)skb->data; 3289e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3290243874c6SManikanta Pubbisetty 3291e678fbd4SKarthikeyan Periyasamy enctype = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, rx_desc); 3292e678fbd4SKarthikeyan Periyasamy if (enctype != HAL_ENCRYPT_TYPE_OPEN) { 3293e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, rx_desc); 3294e678fbd4SKarthikeyan Periyasamy is_decrypted = ath11k_dp_rx_h_attn_is_decrypted(rx_attention); 3295e678fbd4SKarthikeyan Periyasamy } 3296243874c6SManikanta Pubbisetty 3297243874c6SManikanta Pubbisetty if (is_decrypted) { 3298243874c6SManikanta Pubbisetty if (skb != first_frag) 3299243874c6SManikanta Pubbisetty flags |= RX_FLAG_IV_STRIPPED; 3300243874c6SManikanta Pubbisetty if (skb != last_frag) 3301243874c6SManikanta Pubbisetty flags |= RX_FLAG_ICV_STRIPPED | 3302243874c6SManikanta Pubbisetty RX_FLAG_MIC_STRIPPED; 3303243874c6SManikanta Pubbisetty } 3304243874c6SManikanta Pubbisetty 3305243874c6SManikanta Pubbisetty /* RX fragments are always raw packets */ 3306243874c6SManikanta Pubbisetty if (skb != last_frag) 3307243874c6SManikanta Pubbisetty skb_trim(skb, skb->len - FCS_LEN); 3308243874c6SManikanta Pubbisetty ath11k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 3309243874c6SManikanta Pubbisetty 3310243874c6SManikanta Pubbisetty if (skb != first_frag) 3311e678fbd4SKarthikeyan Periyasamy skb_pull(skb, hal_rx_desc_sz + 3312243874c6SManikanta Pubbisetty ieee80211_hdrlen(hdr->frame_control)); 3313243874c6SManikanta Pubbisetty msdu_len += skb->len; 3314243874c6SManikanta Pubbisetty } 3315243874c6SManikanta Pubbisetty 3316243874c6SManikanta Pubbisetty extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 3317243874c6SManikanta Pubbisetty if (extra_space > 0 && 3318243874c6SManikanta Pubbisetty (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 3319243874c6SManikanta Pubbisetty return -ENOMEM; 3320243874c6SManikanta Pubbisetty 3321243874c6SManikanta Pubbisetty __skb_unlink(first_frag, &rx_tid->rx_frags); 3322243874c6SManikanta Pubbisetty while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 3323243874c6SManikanta Pubbisetty skb_put_data(first_frag, skb->data, skb->len); 3324243874c6SManikanta Pubbisetty dev_kfree_skb_any(skb); 3325243874c6SManikanta Pubbisetty } 3326243874c6SManikanta Pubbisetty 3327e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 3328243874c6SManikanta Pubbisetty hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 3329243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(first_frag)->is_frag = 1; 3330243874c6SManikanta Pubbisetty 3331243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 3332243874c6SManikanta Pubbisetty first_frag = NULL; 3333243874c6SManikanta Pubbisetty 3334243874c6SManikanta Pubbisetty *defrag_skb = first_frag; 3335243874c6SManikanta Pubbisetty return 0; 3336243874c6SManikanta Pubbisetty } 3337243874c6SManikanta Pubbisetty 3338243874c6SManikanta Pubbisetty static int ath11k_dp_rx_h_defrag_reo_reinject(struct ath11k *ar, struct dp_rx_tid *rx_tid, 3339243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb) 3340243874c6SManikanta Pubbisetty { 3341243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3342243874c6SManikanta Pubbisetty struct ath11k_pdev_dp *dp = &ar->dp; 3343243874c6SManikanta Pubbisetty struct dp_rxdma_ring *rx_refill_ring = &dp->rx_refill_buf_ring; 3344243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 3345243874c6SManikanta Pubbisetty struct hal_reo_entrance_ring *reo_ent_ring; 3346243874c6SManikanta Pubbisetty struct hal_reo_dest_ring *reo_dest_ring; 3347243874c6SManikanta Pubbisetty struct dp_link_desc_bank *link_desc_banks; 3348243874c6SManikanta Pubbisetty struct hal_rx_msdu_link *msdu_link; 3349243874c6SManikanta Pubbisetty struct hal_rx_msdu_details *msdu0; 3350243874c6SManikanta Pubbisetty struct hal_srng *srng; 3351243874c6SManikanta Pubbisetty dma_addr_t paddr; 3352243874c6SManikanta Pubbisetty u32 desc_bank, msdu_info, mpdu_info; 3353e678fbd4SKarthikeyan Periyasamy u32 dst_idx, cookie, hal_rx_desc_sz; 3354243874c6SManikanta Pubbisetty int ret, buf_id; 3355243874c6SManikanta Pubbisetty 3356e678fbd4SKarthikeyan Periyasamy hal_rx_desc_sz = ab->hw_params.hal_desc_sz; 3357243874c6SManikanta Pubbisetty link_desc_banks = ab->dp.link_desc_banks; 3358243874c6SManikanta Pubbisetty reo_dest_ring = rx_tid->dst_ring_desc; 3359243874c6SManikanta Pubbisetty 3360243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3361243874c6SManikanta Pubbisetty msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 3362243874c6SManikanta Pubbisetty (paddr - link_desc_banks[desc_bank].paddr)); 3363243874c6SManikanta Pubbisetty msdu0 = &msdu_link->msdu_link[0]; 3364243874c6SManikanta Pubbisetty dst_idx = FIELD_GET(RX_MSDU_DESC_INFO0_REO_DEST_IND, msdu0->rx_msdu_info.info0); 3365243874c6SManikanta Pubbisetty memset(msdu0, 0, sizeof(*msdu0)); 3366243874c6SManikanta Pubbisetty 3367243874c6SManikanta Pubbisetty msdu_info = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1) | 3368243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1) | 3369243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_CONTINUATION, 0) | 3370243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_MSDU_LENGTH, 3371e678fbd4SKarthikeyan Periyasamy defrag_skb->len - hal_rx_desc_sz) | 3372243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_REO_DEST_IND, dst_idx) | 3373243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_SA, 1) | 3374243874c6SManikanta Pubbisetty FIELD_PREP(RX_MSDU_DESC_INFO0_VALID_DA, 1); 3375243874c6SManikanta Pubbisetty msdu0->rx_msdu_info.info0 = msdu_info; 3376243874c6SManikanta Pubbisetty 3377243874c6SManikanta Pubbisetty /* change msdu len in hal rx desc */ 3378e678fbd4SKarthikeyan Periyasamy ath11k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3379243874c6SManikanta Pubbisetty 3380243874c6SManikanta Pubbisetty paddr = dma_map_single(ab->dev, defrag_skb->data, 3381243874c6SManikanta Pubbisetty defrag_skb->len + skb_tailroom(defrag_skb), 338286a03dadSBaochen Qiang DMA_TO_DEVICE); 3383243874c6SManikanta Pubbisetty if (dma_mapping_error(ab->dev, paddr)) 3384243874c6SManikanta Pubbisetty return -ENOMEM; 3385243874c6SManikanta Pubbisetty 3386243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3387243874c6SManikanta Pubbisetty buf_id = idr_alloc(&rx_refill_ring->bufs_idr, defrag_skb, 0, 3388243874c6SManikanta Pubbisetty rx_refill_ring->bufs_max * 3, GFP_ATOMIC); 3389243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3390243874c6SManikanta Pubbisetty if (buf_id < 0) { 3391243874c6SManikanta Pubbisetty ret = -ENOMEM; 3392243874c6SManikanta Pubbisetty goto err_unmap_dma; 3393243874c6SManikanta Pubbisetty } 3394243874c6SManikanta Pubbisetty 3395243874c6SManikanta Pubbisetty ATH11K_SKB_RXCB(defrag_skb)->paddr = paddr; 3396243874c6SManikanta Pubbisetty cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, dp->mac_id) | 3397243874c6SManikanta Pubbisetty FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); 3398243874c6SManikanta Pubbisetty 3399734223d7SBaochen Qiang ath11k_hal_rx_buf_addr_info_set(msdu0, paddr, cookie, 3400734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3401243874c6SManikanta Pubbisetty 3402243874c6SManikanta Pubbisetty /* Fill mpdu details into reo entrace ring */ 3403243874c6SManikanta Pubbisetty srng = &ab->hal.srng_list[ab->dp.reo_reinject_ring.ring_id]; 3404243874c6SManikanta Pubbisetty 3405243874c6SManikanta Pubbisetty spin_lock_bh(&srng->lock); 3406243874c6SManikanta Pubbisetty ath11k_hal_srng_access_begin(ab, srng); 3407243874c6SManikanta Pubbisetty 3408243874c6SManikanta Pubbisetty reo_ent_ring = (struct hal_reo_entrance_ring *) 3409243874c6SManikanta Pubbisetty ath11k_hal_srng_src_get_next_entry(ab, srng); 3410243874c6SManikanta Pubbisetty if (!reo_ent_ring) { 3411243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3412243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3413243874c6SManikanta Pubbisetty ret = -ENOSPC; 3414243874c6SManikanta Pubbisetty goto err_free_idr; 3415243874c6SManikanta Pubbisetty } 3416243874c6SManikanta Pubbisetty memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3417243874c6SManikanta Pubbisetty 3418243874c6SManikanta Pubbisetty ath11k_hal_rx_reo_ent_paddr_get(ab, reo_dest_ring, &paddr, &desc_bank); 3419243874c6SManikanta Pubbisetty ath11k_hal_rx_buf_addr_info_set(reo_ent_ring, paddr, desc_bank, 3420243874c6SManikanta Pubbisetty HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST); 3421243874c6SManikanta Pubbisetty 3422243874c6SManikanta Pubbisetty mpdu_info = FIELD_PREP(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1) | 3423243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_SEQ_NUM, rx_tid->cur_sn) | 3424243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_FRAG_FLAG, 0) | 3425243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_SA, 1) | 3426243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_DA, 1) | 3427243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_RAW_MPDU, 1) | 3428243874c6SManikanta Pubbisetty FIELD_PREP(RX_MPDU_DESC_INFO0_VALID_PN, 1); 3429243874c6SManikanta Pubbisetty 3430243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.info0 = mpdu_info; 3431243874c6SManikanta Pubbisetty reo_ent_ring->rx_mpdu_info.meta_data = reo_dest_ring->rx_mpdu_info.meta_data; 3432243874c6SManikanta Pubbisetty reo_ent_ring->queue_addr_lo = reo_dest_ring->queue_addr_lo; 3433243874c6SManikanta Pubbisetty reo_ent_ring->info0 = FIELD_PREP(HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI, 3434243874c6SManikanta Pubbisetty FIELD_GET(HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI, 3435243874c6SManikanta Pubbisetty reo_dest_ring->info0)) | 3436243874c6SManikanta Pubbisetty FIELD_PREP(HAL_REO_ENTR_RING_INFO0_DEST_IND, dst_idx); 3437243874c6SManikanta Pubbisetty ath11k_hal_srng_access_end(ab, srng); 3438243874c6SManikanta Pubbisetty spin_unlock_bh(&srng->lock); 3439243874c6SManikanta Pubbisetty 3440243874c6SManikanta Pubbisetty return 0; 3441243874c6SManikanta Pubbisetty 3442243874c6SManikanta Pubbisetty err_free_idr: 3443243874c6SManikanta Pubbisetty spin_lock_bh(&rx_refill_ring->idr_lock); 3444243874c6SManikanta Pubbisetty idr_remove(&rx_refill_ring->bufs_idr, buf_id); 3445243874c6SManikanta Pubbisetty spin_unlock_bh(&rx_refill_ring->idr_lock); 3446243874c6SManikanta Pubbisetty err_unmap_dma: 3447243874c6SManikanta Pubbisetty dma_unmap_single(ab->dev, paddr, defrag_skb->len + skb_tailroom(defrag_skb), 344886a03dadSBaochen Qiang DMA_TO_DEVICE); 3449243874c6SManikanta Pubbisetty return ret; 3450243874c6SManikanta Pubbisetty } 3451243874c6SManikanta Pubbisetty 3452e678fbd4SKarthikeyan Periyasamy static int ath11k_dp_rx_h_cmp_frags(struct ath11k *ar, 3453e678fbd4SKarthikeyan Periyasamy struct sk_buff *a, struct sk_buff *b) 3454243874c6SManikanta Pubbisetty { 3455243874c6SManikanta Pubbisetty int frag1, frag2; 3456243874c6SManikanta Pubbisetty 3457e678fbd4SKarthikeyan Periyasamy frag1 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, a); 3458e678fbd4SKarthikeyan Periyasamy frag2 = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, b); 3459243874c6SManikanta Pubbisetty 3460243874c6SManikanta Pubbisetty return frag1 - frag2; 3461243874c6SManikanta Pubbisetty } 3462243874c6SManikanta Pubbisetty 3463e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_h_sort_frags(struct ath11k *ar, 3464e678fbd4SKarthikeyan Periyasamy struct sk_buff_head *frag_list, 3465243874c6SManikanta Pubbisetty struct sk_buff *cur_frag) 3466243874c6SManikanta Pubbisetty { 3467243874c6SManikanta Pubbisetty struct sk_buff *skb; 3468243874c6SManikanta Pubbisetty int cmp; 3469243874c6SManikanta Pubbisetty 3470243874c6SManikanta Pubbisetty skb_queue_walk(frag_list, skb) { 3471e678fbd4SKarthikeyan Periyasamy cmp = ath11k_dp_rx_h_cmp_frags(ar, skb, cur_frag); 3472243874c6SManikanta Pubbisetty if (cmp < 0) 3473243874c6SManikanta Pubbisetty continue; 3474243874c6SManikanta Pubbisetty __skb_queue_before(frag_list, skb, cur_frag); 3475243874c6SManikanta Pubbisetty return; 3476243874c6SManikanta Pubbisetty } 3477243874c6SManikanta Pubbisetty __skb_queue_tail(frag_list, cur_frag); 3478243874c6SManikanta Pubbisetty } 3479243874c6SManikanta Pubbisetty 3480e678fbd4SKarthikeyan Periyasamy static u64 ath11k_dp_rx_h_get_pn(struct ath11k *ar, struct sk_buff *skb) 3481243874c6SManikanta Pubbisetty { 3482243874c6SManikanta Pubbisetty struct ieee80211_hdr *hdr; 3483243874c6SManikanta Pubbisetty u64 pn = 0; 3484243874c6SManikanta Pubbisetty u8 *ehdr; 3485e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3486243874c6SManikanta Pubbisetty 3487e678fbd4SKarthikeyan Periyasamy hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3488e678fbd4SKarthikeyan Periyasamy ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3489243874c6SManikanta Pubbisetty 3490243874c6SManikanta Pubbisetty pn = ehdr[0]; 3491243874c6SManikanta Pubbisetty pn |= (u64)ehdr[1] << 8; 3492243874c6SManikanta Pubbisetty pn |= (u64)ehdr[4] << 16; 3493243874c6SManikanta Pubbisetty pn |= (u64)ehdr[5] << 24; 3494243874c6SManikanta Pubbisetty pn |= (u64)ehdr[6] << 32; 3495243874c6SManikanta Pubbisetty pn |= (u64)ehdr[7] << 40; 3496243874c6SManikanta Pubbisetty 3497243874c6SManikanta Pubbisetty return pn; 3498243874c6SManikanta Pubbisetty } 3499243874c6SManikanta Pubbisetty 3500243874c6SManikanta Pubbisetty static bool 3501243874c6SManikanta Pubbisetty ath11k_dp_rx_h_defrag_validate_incr_pn(struct ath11k *ar, struct dp_rx_tid *rx_tid) 3502243874c6SManikanta Pubbisetty { 3503243874c6SManikanta Pubbisetty enum hal_encrypt_type encrypt_type; 3504243874c6SManikanta Pubbisetty struct sk_buff *first_frag, *skb; 3505243874c6SManikanta Pubbisetty struct hal_rx_desc *desc; 3506243874c6SManikanta Pubbisetty u64 last_pn; 3507243874c6SManikanta Pubbisetty u64 cur_pn; 3508243874c6SManikanta Pubbisetty 3509243874c6SManikanta Pubbisetty first_frag = skb_peek(&rx_tid->rx_frags); 3510243874c6SManikanta Pubbisetty desc = (struct hal_rx_desc *)first_frag->data; 3511243874c6SManikanta Pubbisetty 3512e678fbd4SKarthikeyan Periyasamy encrypt_type = ath11k_dp_rx_h_mpdu_start_enctype(ar->ab, desc); 3513243874c6SManikanta Pubbisetty if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3514243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3515243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3516243874c6SManikanta Pubbisetty encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3517243874c6SManikanta Pubbisetty return true; 3518243874c6SManikanta Pubbisetty 3519e678fbd4SKarthikeyan Periyasamy last_pn = ath11k_dp_rx_h_get_pn(ar, first_frag); 3520243874c6SManikanta Pubbisetty skb_queue_walk(&rx_tid->rx_frags, skb) { 3521243874c6SManikanta Pubbisetty if (skb == first_frag) 3522243874c6SManikanta Pubbisetty continue; 3523243874c6SManikanta Pubbisetty 3524e678fbd4SKarthikeyan Periyasamy cur_pn = ath11k_dp_rx_h_get_pn(ar, skb); 3525243874c6SManikanta Pubbisetty if (cur_pn != last_pn + 1) 3526243874c6SManikanta Pubbisetty return false; 3527243874c6SManikanta Pubbisetty last_pn = cur_pn; 3528243874c6SManikanta Pubbisetty } 3529243874c6SManikanta Pubbisetty return true; 3530243874c6SManikanta Pubbisetty } 3531243874c6SManikanta Pubbisetty 3532243874c6SManikanta Pubbisetty static int ath11k_dp_rx_frag_h_mpdu(struct ath11k *ar, 3533243874c6SManikanta Pubbisetty struct sk_buff *msdu, 3534243874c6SManikanta Pubbisetty u32 *ring_desc) 3535243874c6SManikanta Pubbisetty { 3536243874c6SManikanta Pubbisetty struct ath11k_base *ab = ar->ab; 3537243874c6SManikanta Pubbisetty struct hal_rx_desc *rx_desc; 3538243874c6SManikanta Pubbisetty struct ath11k_peer *peer; 3539243874c6SManikanta Pubbisetty struct dp_rx_tid *rx_tid; 3540243874c6SManikanta Pubbisetty struct sk_buff *defrag_skb = NULL; 3541243874c6SManikanta Pubbisetty u32 peer_id; 3542243874c6SManikanta Pubbisetty u16 seqno, frag_no; 3543243874c6SManikanta Pubbisetty u8 tid; 3544243874c6SManikanta Pubbisetty int ret = 0; 3545243874c6SManikanta Pubbisetty bool more_frags; 3546210f563bSSriram R bool is_mcbc; 3547243874c6SManikanta Pubbisetty 3548243874c6SManikanta Pubbisetty rx_desc = (struct hal_rx_desc *)msdu->data; 3549e678fbd4SKarthikeyan Periyasamy peer_id = ath11k_dp_rx_h_mpdu_start_peer_id(ar->ab, rx_desc); 3550e678fbd4SKarthikeyan Periyasamy tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, rx_desc); 3551e678fbd4SKarthikeyan Periyasamy seqno = ath11k_dp_rx_h_mpdu_start_seq_no(ar->ab, rx_desc); 3552e678fbd4SKarthikeyan Periyasamy frag_no = ath11k_dp_rx_h_mpdu_start_frag_no(ar->ab, msdu); 3553e678fbd4SKarthikeyan Periyasamy more_frags = ath11k_dp_rx_h_mpdu_start_more_frags(ar->ab, msdu); 3554210f563bSSriram R is_mcbc = ath11k_dp_rx_h_attn_is_mcbc(ar->ab, rx_desc); 3555210f563bSSriram R 3556210f563bSSriram R /* Multicast/Broadcast fragments are not expected */ 3557210f563bSSriram R if (is_mcbc) 3558210f563bSSriram R return -EINVAL; 3559243874c6SManikanta Pubbisetty 3560e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_mpdu_start_seq_ctrl_valid(ar->ab, rx_desc) || 3561e678fbd4SKarthikeyan Periyasamy !ath11k_dp_rx_h_mpdu_start_fc_valid(ar->ab, rx_desc) || 3562243874c6SManikanta Pubbisetty tid > IEEE80211_NUM_TIDS) 3563243874c6SManikanta Pubbisetty return -EINVAL; 3564243874c6SManikanta Pubbisetty 3565243874c6SManikanta Pubbisetty /* received unfragmented packet in reo 3566243874c6SManikanta Pubbisetty * exception ring, this shouldn't happen 3567243874c6SManikanta Pubbisetty * as these packets typically come from 3568243874c6SManikanta Pubbisetty * reo2sw srngs. 3569243874c6SManikanta Pubbisetty */ 3570243874c6SManikanta Pubbisetty if (WARN_ON_ONCE(!frag_no && !more_frags)) 3571243874c6SManikanta Pubbisetty return -EINVAL; 3572243874c6SManikanta Pubbisetty 3573243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3574243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3575243874c6SManikanta Pubbisetty if (!peer) { 3576243874c6SManikanta Pubbisetty ath11k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3577243874c6SManikanta Pubbisetty peer_id); 3578243874c6SManikanta Pubbisetty ret = -ENOENT; 3579243874c6SManikanta Pubbisetty goto out_unlock; 3580243874c6SManikanta Pubbisetty } 3581243874c6SManikanta Pubbisetty rx_tid = &peer->rx_tid[tid]; 3582243874c6SManikanta Pubbisetty 3583243874c6SManikanta Pubbisetty if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3584243874c6SManikanta Pubbisetty skb_queue_empty(&rx_tid->rx_frags)) { 3585243874c6SManikanta Pubbisetty /* Flush stored fragments and start a new sequence */ 3586243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3587243874c6SManikanta Pubbisetty rx_tid->cur_sn = seqno; 3588243874c6SManikanta Pubbisetty } 3589243874c6SManikanta Pubbisetty 3590243874c6SManikanta Pubbisetty if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3591243874c6SManikanta Pubbisetty /* Fragment already present */ 3592243874c6SManikanta Pubbisetty ret = -EINVAL; 3593243874c6SManikanta Pubbisetty goto out_unlock; 3594243874c6SManikanta Pubbisetty } 3595243874c6SManikanta Pubbisetty 3596243874c6SManikanta Pubbisetty if (frag_no > __fls(rx_tid->rx_frag_bitmap)) 3597243874c6SManikanta Pubbisetty __skb_queue_tail(&rx_tid->rx_frags, msdu); 3598243874c6SManikanta Pubbisetty else 3599e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_h_sort_frags(ar, &rx_tid->rx_frags, msdu); 3600243874c6SManikanta Pubbisetty 3601243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap |= BIT(frag_no); 3602243874c6SManikanta Pubbisetty if (!more_frags) 3603243874c6SManikanta Pubbisetty rx_tid->last_frag_no = frag_no; 3604243874c6SManikanta Pubbisetty 3605243874c6SManikanta Pubbisetty if (frag_no == 0) { 3606243874c6SManikanta Pubbisetty rx_tid->dst_ring_desc = kmemdup(ring_desc, 3607243874c6SManikanta Pubbisetty sizeof(*rx_tid->dst_ring_desc), 3608243874c6SManikanta Pubbisetty GFP_ATOMIC); 3609243874c6SManikanta Pubbisetty if (!rx_tid->dst_ring_desc) { 3610243874c6SManikanta Pubbisetty ret = -ENOMEM; 3611243874c6SManikanta Pubbisetty goto out_unlock; 3612243874c6SManikanta Pubbisetty } 3613243874c6SManikanta Pubbisetty } else { 3614243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ab, ring_desc, 3615243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3616243874c6SManikanta Pubbisetty } 3617243874c6SManikanta Pubbisetty 3618243874c6SManikanta Pubbisetty if (!rx_tid->last_frag_no || 3619243874c6SManikanta Pubbisetty rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3620243874c6SManikanta Pubbisetty mod_timer(&rx_tid->frag_timer, jiffies + 3621243874c6SManikanta Pubbisetty ATH11K_DP_RX_FRAGMENT_TIMEOUT_MS); 3622243874c6SManikanta Pubbisetty goto out_unlock; 3623243874c6SManikanta Pubbisetty } 3624243874c6SManikanta Pubbisetty 3625243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3626243874c6SManikanta Pubbisetty del_timer_sync(&rx_tid->frag_timer); 3627243874c6SManikanta Pubbisetty spin_lock_bh(&ab->base_lock); 3628243874c6SManikanta Pubbisetty 3629243874c6SManikanta Pubbisetty peer = ath11k_peer_find_by_id(ab, peer_id); 3630243874c6SManikanta Pubbisetty if (!peer) 3631243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3632243874c6SManikanta Pubbisetty 3633243874c6SManikanta Pubbisetty if (!ath11k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3634243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3635243874c6SManikanta Pubbisetty 3636243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3637243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3638243874c6SManikanta Pubbisetty 3639243874c6SManikanta Pubbisetty if (!defrag_skb) 3640243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3641243874c6SManikanta Pubbisetty 3642243874c6SManikanta Pubbisetty if (ath11k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3643243874c6SManikanta Pubbisetty goto err_frags_cleanup; 3644243874c6SManikanta Pubbisetty 3645243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, false); 3646243874c6SManikanta Pubbisetty goto out_unlock; 3647243874c6SManikanta Pubbisetty 3648243874c6SManikanta Pubbisetty err_frags_cleanup: 3649243874c6SManikanta Pubbisetty dev_kfree_skb_any(defrag_skb); 3650243874c6SManikanta Pubbisetty ath11k_dp_rx_frags_cleanup(rx_tid, true); 3651243874c6SManikanta Pubbisetty out_unlock: 3652243874c6SManikanta Pubbisetty spin_unlock_bh(&ab->base_lock); 3653243874c6SManikanta Pubbisetty return ret; 3654243874c6SManikanta Pubbisetty } 3655243874c6SManikanta Pubbisetty 3656d5c65159SKalle Valo static int 3657243874c6SManikanta Pubbisetty ath11k_dp_process_rx_err_buf(struct ath11k *ar, u32 *ring_desc, int buf_id, bool drop) 3658d5c65159SKalle Valo { 3659d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 3660d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 3661d5c65159SKalle Valo struct sk_buff *msdu; 3662d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3663d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 3664d7d43782STamizh Chelvam u8 *hdr_status; 3665d5c65159SKalle Valo u16 msdu_len; 3666e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3667d5c65159SKalle Valo 3668d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 3669d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 3670d5c65159SKalle Valo if (!msdu) { 3671d5c65159SKalle Valo ath11k_warn(ar->ab, "rx err buf with invalid buf_id %d\n", 3672d5c65159SKalle Valo buf_id); 3673d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3674d5c65159SKalle Valo return -EINVAL; 3675d5c65159SKalle Valo } 3676d5c65159SKalle Valo 3677d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 3678d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 3679d5c65159SKalle Valo 3680d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 3681d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 3682d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 3683d5c65159SKalle Valo DMA_FROM_DEVICE); 3684d5c65159SKalle Valo 3685243874c6SManikanta Pubbisetty if (drop) { 3686d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3687d5c65159SKalle Valo return 0; 3688d5c65159SKalle Valo } 3689d5c65159SKalle Valo 3690d5c65159SKalle Valo rcu_read_lock(); 3691d5c65159SKalle Valo if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3692d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3693d5c65159SKalle Valo goto exit; 3694d5c65159SKalle Valo } 3695d5c65159SKalle Valo 3696d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 3697d5c65159SKalle Valo dev_kfree_skb_any(msdu); 3698d5c65159SKalle Valo goto exit; 3699d5c65159SKalle Valo } 3700d5c65159SKalle Valo 3701d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 3702e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, rx_desc); 3703e678fbd4SKarthikeyan Periyasamy if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3704e678fbd4SKarthikeyan Periyasamy hdr_status = ath11k_dp_rx_h_80211_hdr(ar->ab, rx_desc); 3705d7d43782STamizh Chelvam ath11k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3706d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", hdr_status, 3707d7d43782STamizh Chelvam sizeof(struct ieee80211_hdr)); 3708d7d43782STamizh Chelvam ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "", rx_desc, 3709d7d43782STamizh Chelvam sizeof(struct hal_rx_desc)); 3710d7d43782STamizh Chelvam dev_kfree_skb_any(msdu); 3711d7d43782STamizh Chelvam goto exit; 3712d7d43782STamizh Chelvam } 3713d7d43782STamizh Chelvam 3714e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + msdu_len); 3715d5c65159SKalle Valo 3716243874c6SManikanta Pubbisetty if (ath11k_dp_rx_frag_h_mpdu(ar, msdu, ring_desc)) { 3717243874c6SManikanta Pubbisetty dev_kfree_skb_any(msdu); 3718243874c6SManikanta Pubbisetty ath11k_dp_rx_link_desc_return(ar->ab, ring_desc, 3719243874c6SManikanta Pubbisetty HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3720243874c6SManikanta Pubbisetty } 3721d5c65159SKalle Valo exit: 3722d5c65159SKalle Valo rcu_read_unlock(); 3723d5c65159SKalle Valo return 0; 3724d5c65159SKalle Valo } 3725d5c65159SKalle Valo 3726d5c65159SKalle Valo int ath11k_dp_process_rx_err(struct ath11k_base *ab, struct napi_struct *napi, 3727d5c65159SKalle Valo int budget) 3728d5c65159SKalle Valo { 3729293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3730d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks; 3731d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 3732d5c65159SKalle Valo int tot_n_bufs_reaped, quota, ret, i; 3733d5c65159SKalle Valo int n_bufs_reaped[MAX_RADIOS] = {0}; 3734d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 3735d5c65159SKalle Valo struct dp_srng *reo_except; 3736d5c65159SKalle Valo u32 desc_bank, num_msdus; 3737d5c65159SKalle Valo struct hal_srng *srng; 3738d5c65159SKalle Valo struct ath11k_dp *dp; 3739d5c65159SKalle Valo void *link_desc_va; 3740d5c65159SKalle Valo int buf_id, mac_id; 3741d5c65159SKalle Valo struct ath11k *ar; 3742d5c65159SKalle Valo dma_addr_t paddr; 3743d5c65159SKalle Valo u32 *desc; 3744d5c65159SKalle Valo bool is_frag; 3745243874c6SManikanta Pubbisetty u8 drop = 0; 3746d5c65159SKalle Valo 3747d5c65159SKalle Valo tot_n_bufs_reaped = 0; 3748d5c65159SKalle Valo quota = budget; 3749d5c65159SKalle Valo 3750d5c65159SKalle Valo dp = &ab->dp; 3751d5c65159SKalle Valo reo_except = &dp->reo_except_ring; 3752d5c65159SKalle Valo link_desc_banks = dp->link_desc_banks; 3753d5c65159SKalle Valo 3754d5c65159SKalle Valo srng = &ab->hal.srng_list[reo_except->ring_id]; 3755d5c65159SKalle Valo 3756d5c65159SKalle Valo spin_lock_bh(&srng->lock); 3757d5c65159SKalle Valo 3758d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 3759d5c65159SKalle Valo 3760d5c65159SKalle Valo while (budget && 3761d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 3762293cb583SJohn Crispin struct hal_reo_dest_ring *reo_desc = (struct hal_reo_dest_ring *)desc; 3763293cb583SJohn Crispin 3764d5c65159SKalle Valo ab->soc_stats.err_ring_pkts++; 3765d5c65159SKalle Valo ret = ath11k_hal_desc_reo_parse_err(ab, desc, &paddr, 3766d5c65159SKalle Valo &desc_bank); 3767d5c65159SKalle Valo if (ret) { 3768d5c65159SKalle Valo ath11k_warn(ab, "failed to parse error reo desc %d\n", 3769d5c65159SKalle Valo ret); 3770d5c65159SKalle Valo continue; 3771d5c65159SKalle Valo } 3772d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 3773d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 3774293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3775d5c65159SKalle Valo &rbm); 3776d5c65159SKalle Valo if (rbm != HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST && 377771c748b5SBaochen Qiang rbm != HAL_RX_BUF_RBM_SW3_BM) { 3778d5c65159SKalle Valo ab->soc_stats.invalid_rbm++; 3779d5c65159SKalle Valo ath11k_warn(ab, "invalid return buffer manager %d\n", rbm); 3780d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3781d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_REL_MSDU); 3782d5c65159SKalle Valo continue; 3783d5c65159SKalle Valo } 3784d5c65159SKalle Valo 3785293cb583SJohn Crispin is_frag = !!(reo_desc->rx_mpdu_info.info0 & RX_MPDU_DESC_INFO0_FRAG_FLAG); 3786d5c65159SKalle Valo 3787243874c6SManikanta Pubbisetty /* Process only rx fragments with one msdu per link desc below, and drop 3788243874c6SManikanta Pubbisetty * msdu's indicated due to error reasons. 3789243874c6SManikanta Pubbisetty */ 3790243874c6SManikanta Pubbisetty if (!is_frag || num_msdus > 1) { 3791243874c6SManikanta Pubbisetty drop = 1; 3792d5c65159SKalle Valo /* Return the link desc back to wbm idle list */ 3793d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 3794d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3795243874c6SManikanta Pubbisetty } 3796d5c65159SKalle Valo 3797d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 3798d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 3799293cb583SJohn Crispin msdu_cookies[i]); 3800d5c65159SKalle Valo 3801d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, 3802293cb583SJohn Crispin msdu_cookies[i]); 3803d5c65159SKalle Valo 3804d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 3805d5c65159SKalle Valo 3806243874c6SManikanta Pubbisetty if (!ath11k_dp_process_rx_err_buf(ar, desc, buf_id, drop)) { 3807d5c65159SKalle Valo n_bufs_reaped[mac_id]++; 3808d5c65159SKalle Valo tot_n_bufs_reaped++; 3809d5c65159SKalle Valo } 3810d5c65159SKalle Valo } 3811d5c65159SKalle Valo 3812d5c65159SKalle Valo if (tot_n_bufs_reaped >= quota) { 3813d5c65159SKalle Valo tot_n_bufs_reaped = quota; 3814d5c65159SKalle Valo goto exit; 3815d5c65159SKalle Valo } 3816d5c65159SKalle Valo 3817d5c65159SKalle Valo budget = quota - tot_n_bufs_reaped; 3818d5c65159SKalle Valo } 3819d5c65159SKalle Valo 3820d5c65159SKalle Valo exit: 3821d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 3822d5c65159SKalle Valo 3823d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 3824d5c65159SKalle Valo 3825d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 3826d5c65159SKalle Valo if (!n_bufs_reaped[i]) 3827d5c65159SKalle Valo continue; 3828d5c65159SKalle Valo 3829d5c65159SKalle Valo ar = ab->pdevs[i].ar; 3830d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 3831d5c65159SKalle Valo 3832d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, n_bufs_reaped[i], 3833734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 3834d5c65159SKalle Valo } 3835d5c65159SKalle Valo 3836d5c65159SKalle Valo return tot_n_bufs_reaped; 3837d5c65159SKalle Valo } 3838d5c65159SKalle Valo 3839d5c65159SKalle Valo static void ath11k_dp_rx_null_q_desc_sg_drop(struct ath11k *ar, 3840d5c65159SKalle Valo int msdu_len, 3841d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3842d5c65159SKalle Valo { 3843d5c65159SKalle Valo struct sk_buff *skb, *tmp; 3844d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 3845d5c65159SKalle Valo int n_buffs; 3846d5c65159SKalle Valo 3847d5c65159SKalle Valo n_buffs = DIV_ROUND_UP(msdu_len, 3848e678fbd4SKarthikeyan Periyasamy (DP_RX_BUFFER_SIZE - ar->ab->hw_params.hal_desc_sz)); 3849d5c65159SKalle Valo 3850d5c65159SKalle Valo skb_queue_walk_safe(msdu_list, skb, tmp) { 3851d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 3852d5c65159SKalle Valo if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3853d5c65159SKalle Valo rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3854d5c65159SKalle Valo if (!n_buffs) 3855d5c65159SKalle Valo break; 3856d5c65159SKalle Valo __skb_unlink(skb, msdu_list); 3857d5c65159SKalle Valo dev_kfree_skb_any(skb); 3858d5c65159SKalle Valo n_buffs--; 3859d5c65159SKalle Valo } 3860d5c65159SKalle Valo } 3861d5c65159SKalle Valo } 3862d5c65159SKalle Valo 3863d5c65159SKalle Valo static int ath11k_dp_rx_h_null_q_desc(struct ath11k *ar, struct sk_buff *msdu, 3864d5c65159SKalle Valo struct ieee80211_rx_status *status, 3865d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3866d5c65159SKalle Valo { 3867d5c65159SKalle Valo u16 msdu_len; 3868d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3869e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 3870d5c65159SKalle Valo u8 l3pad_bytes; 3871d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3872e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3873d5c65159SKalle Valo 3874e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3875d5c65159SKalle Valo 3876e678fbd4SKarthikeyan Periyasamy if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3877d5c65159SKalle Valo /* First buffer will be freed by the caller, so deduct it's length */ 3878e678fbd4SKarthikeyan Periyasamy msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3879d5c65159SKalle Valo ath11k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3880d5c65159SKalle Valo return -EINVAL; 3881d5c65159SKalle Valo } 3882d5c65159SKalle Valo 3883e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ar->ab, desc); 3884e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rx_h_attn_msdu_done(rx_attention)) { 3885d5c65159SKalle Valo ath11k_warn(ar->ab, 3886d5c65159SKalle Valo "msdu_done bit not set in null_q_des processing\n"); 3887d5c65159SKalle Valo __skb_queue_purge(msdu_list); 3888d5c65159SKalle Valo return -EIO; 3889d5c65159SKalle Valo } 3890d5c65159SKalle Valo 3891d5c65159SKalle Valo /* Handle NULL queue descriptor violations arising out a missing 3892d5c65159SKalle Valo * REO queue for a given peer or a given TID. This typically 3893d5c65159SKalle Valo * may happen if a packet is received on a QOS enabled TID before the 3894d5c65159SKalle Valo * ADDBA negotiation for that TID, when the TID queue is setup. Or 3895d5c65159SKalle Valo * it may also happen for MC/BC frames if they are not routed to the 3896d5c65159SKalle Valo * non-QOS TID queue, in the absence of any other default TID queue. 3897d5c65159SKalle Valo * This error can show up both in a REO destination or WBM release ring. 3898d5c65159SKalle Valo */ 3899d5c65159SKalle Valo 3900e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3901e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3902d5c65159SKalle Valo 3903243874c6SManikanta Pubbisetty if (rxcb->is_frag) { 3904e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz); 3905243874c6SManikanta Pubbisetty } else { 3906e678fbd4SKarthikeyan Periyasamy l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3907d5c65159SKalle Valo 3908e678fbd4SKarthikeyan Periyasamy if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3909d5c65159SKalle Valo return -EINVAL; 3910d5c65159SKalle Valo 3911e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3912e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3913243874c6SManikanta Pubbisetty } 3914d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3915d5c65159SKalle Valo 3916acc79d98SSriram R ath11k_dp_rx_h_mpdu(ar, msdu, desc, status); 3917d5c65159SKalle Valo 3918e678fbd4SKarthikeyan Periyasamy rxcb->tid = ath11k_dp_rx_h_mpdu_start_tid(ar->ab, desc); 3919d5c65159SKalle Valo 3920d5c65159SKalle Valo /* Please note that caller will having the access to msdu and completing 3921d5c65159SKalle Valo * rx with mac80211. Need not worry about cleaning up amsdu_list. 3922d5c65159SKalle Valo */ 3923d5c65159SKalle Valo 3924d5c65159SKalle Valo return 0; 3925d5c65159SKalle Valo } 3926d5c65159SKalle Valo 3927d5c65159SKalle Valo static bool ath11k_dp_rx_h_reo_err(struct ath11k *ar, struct sk_buff *msdu, 3928d5c65159SKalle Valo struct ieee80211_rx_status *status, 3929d5c65159SKalle Valo struct sk_buff_head *msdu_list) 3930d5c65159SKalle Valo { 3931d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3932d5c65159SKalle Valo bool drop = false; 3933d5c65159SKalle Valo 3934d5c65159SKalle Valo ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3935d5c65159SKalle Valo 3936d5c65159SKalle Valo switch (rxcb->err_code) { 3937d5c65159SKalle Valo case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3938d5c65159SKalle Valo if (ath11k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3939d5c65159SKalle Valo drop = true; 3940d5c65159SKalle Valo break; 39411441b2f2SManikanta Pubbisetty case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 39421441b2f2SManikanta Pubbisetty /* TODO: Do not drop PN failed packets in the driver; 39431441b2f2SManikanta Pubbisetty * instead, it is good to drop such packets in mac80211 39441441b2f2SManikanta Pubbisetty * after incrementing the replay counters. 39451441b2f2SManikanta Pubbisetty */ 39460b294aebSGustavo A. R. Silva fallthrough; 3947d5c65159SKalle Valo default: 3948d5c65159SKalle Valo /* TODO: Review other errors and process them to mac80211 3949d5c65159SKalle Valo * as appropriate. 3950d5c65159SKalle Valo */ 3951d5c65159SKalle Valo drop = true; 3952d5c65159SKalle Valo break; 3953d5c65159SKalle Valo } 3954d5c65159SKalle Valo 3955d5c65159SKalle Valo return drop; 3956d5c65159SKalle Valo } 3957d5c65159SKalle Valo 3958d5c65159SKalle Valo static void ath11k_dp_rx_h_tkip_mic_err(struct ath11k *ar, struct sk_buff *msdu, 3959d5c65159SKalle Valo struct ieee80211_rx_status *status) 3960d5c65159SKalle Valo { 3961d5c65159SKalle Valo u16 msdu_len; 3962d5c65159SKalle Valo struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3963d5c65159SKalle Valo u8 l3pad_bytes; 3964d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3965e678fbd4SKarthikeyan Periyasamy u32 hal_rx_desc_sz = ar->ab->hw_params.hal_desc_sz; 3966d5c65159SKalle Valo 3967e678fbd4SKarthikeyan Periyasamy rxcb->is_first_msdu = ath11k_dp_rx_h_msdu_end_first_msdu(ar->ab, desc); 3968e678fbd4SKarthikeyan Periyasamy rxcb->is_last_msdu = ath11k_dp_rx_h_msdu_end_last_msdu(ar->ab, desc); 3969d5c65159SKalle Valo 3970e678fbd4SKarthikeyan Periyasamy l3pad_bytes = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, desc); 3971e678fbd4SKarthikeyan Periyasamy msdu_len = ath11k_dp_rx_h_msdu_start_msdu_len(ar->ab, desc); 3972e678fbd4SKarthikeyan Periyasamy skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3973e678fbd4SKarthikeyan Periyasamy skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3974d5c65159SKalle Valo 3975d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, desc, status); 3976d5c65159SKalle Valo 3977d5c65159SKalle Valo status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3978d5c65159SKalle Valo RX_FLAG_DECRYPTED); 3979d5c65159SKalle Valo 3980d5c65159SKalle Valo ath11k_dp_rx_h_undecap(ar, msdu, desc, 3981d5c65159SKalle Valo HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3982d5c65159SKalle Valo } 3983d5c65159SKalle Valo 3984d5c65159SKalle Valo static bool ath11k_dp_rx_h_rxdma_err(struct ath11k *ar, struct sk_buff *msdu, 3985d5c65159SKalle Valo struct ieee80211_rx_status *status) 3986d5c65159SKalle Valo { 3987d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 3988d5c65159SKalle Valo bool drop = false; 3989d5c65159SKalle Valo 3990d5c65159SKalle Valo ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3991d5c65159SKalle Valo 3992d5c65159SKalle Valo switch (rxcb->err_code) { 3993d5c65159SKalle Valo case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3994d5c65159SKalle Valo ath11k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3995d5c65159SKalle Valo break; 3996d5c65159SKalle Valo default: 3997d5c65159SKalle Valo /* TODO: Review other rxdma error code to check if anything is 3998d5c65159SKalle Valo * worth reporting to mac80211 3999d5c65159SKalle Valo */ 4000d5c65159SKalle Valo drop = true; 4001d5c65159SKalle Valo break; 4002d5c65159SKalle Valo } 4003d5c65159SKalle Valo 4004d5c65159SKalle Valo return drop; 4005d5c65159SKalle Valo } 4006d5c65159SKalle Valo 4007d5c65159SKalle Valo static void ath11k_dp_rx_wbm_err(struct ath11k *ar, 4008d5c65159SKalle Valo struct napi_struct *napi, 4009d5c65159SKalle Valo struct sk_buff *msdu, 4010d5c65159SKalle Valo struct sk_buff_head *msdu_list) 4011d5c65159SKalle Valo { 4012d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb = ATH11K_SKB_RXCB(msdu); 4013d5c65159SKalle Valo struct ieee80211_rx_status rxs = {0}; 4014d5c65159SKalle Valo bool drop = true; 4015d5c65159SKalle Valo 4016d5c65159SKalle Valo switch (rxcb->err_rel_src) { 4017d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_REO: 4018d5c65159SKalle Valo drop = ath11k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 4019d5c65159SKalle Valo break; 4020d5c65159SKalle Valo case HAL_WBM_REL_SRC_MODULE_RXDMA: 4021d5c65159SKalle Valo drop = ath11k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 4022d5c65159SKalle Valo break; 4023d5c65159SKalle Valo default: 4024d5c65159SKalle Valo /* msdu will get freed */ 4025d5c65159SKalle Valo break; 4026d5c65159SKalle Valo } 4027d5c65159SKalle Valo 4028d5c65159SKalle Valo if (drop) { 4029d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4030d5c65159SKalle Valo return; 4031d5c65159SKalle Valo } 4032d5c65159SKalle Valo 40332167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 4034d5c65159SKalle Valo } 4035d5c65159SKalle Valo 4036d5c65159SKalle Valo int ath11k_dp_rx_process_wbm_err(struct ath11k_base *ab, 4037d5c65159SKalle Valo struct napi_struct *napi, int budget) 4038d5c65159SKalle Valo { 4039d5c65159SKalle Valo struct ath11k *ar; 4040d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 4041d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring; 4042d5c65159SKalle Valo struct hal_rx_wbm_rel_info err_info; 4043d5c65159SKalle Valo struct hal_srng *srng; 4044d5c65159SKalle Valo struct sk_buff *msdu; 4045d5c65159SKalle Valo struct sk_buff_head msdu_list[MAX_RADIOS]; 4046d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4047d5c65159SKalle Valo u32 *rx_desc; 4048d5c65159SKalle Valo int buf_id, mac_id; 4049d5c65159SKalle Valo int num_buffs_reaped[MAX_RADIOS] = {0}; 4050d5c65159SKalle Valo int total_num_buffs_reaped = 0; 4051d5c65159SKalle Valo int ret, i; 4052d5c65159SKalle Valo 4053b1cc29e9SAnilkumar Kolli for (i = 0; i < ab->num_radios; i++) 4054d5c65159SKalle Valo __skb_queue_head_init(&msdu_list[i]); 4055d5c65159SKalle Valo 4056d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 4057d5c65159SKalle Valo 4058d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4059d5c65159SKalle Valo 4060d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4061d5c65159SKalle Valo 4062d5c65159SKalle Valo while (budget) { 4063d5c65159SKalle Valo rx_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng); 4064d5c65159SKalle Valo if (!rx_desc) 4065d5c65159SKalle Valo break; 4066d5c65159SKalle Valo 4067d5c65159SKalle Valo ret = ath11k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 4068d5c65159SKalle Valo if (ret) { 4069d5c65159SKalle Valo ath11k_warn(ab, 4070d5c65159SKalle Valo "failed to parse rx error in wbm_rel ring desc %d\n", 4071d5c65159SKalle Valo ret); 4072d5c65159SKalle Valo continue; 4073d5c65159SKalle Valo } 4074d5c65159SKalle Valo 4075d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, err_info.cookie); 4076d5c65159SKalle Valo mac_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_PDEV_ID, err_info.cookie); 4077d5c65159SKalle Valo 4078d5c65159SKalle Valo ar = ab->pdevs[mac_id].ar; 4079d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 4080d5c65159SKalle Valo 4081d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4082d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4083d5c65159SKalle Valo if (!msdu) { 4084d5c65159SKalle Valo ath11k_warn(ab, "frame rx with invalid buf_id %d pdev %d\n", 4085d5c65159SKalle Valo buf_id, mac_id); 4086d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4087d5c65159SKalle Valo continue; 4088d5c65159SKalle Valo } 4089d5c65159SKalle Valo 4090d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4091d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4092d5c65159SKalle Valo 4093d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 4094d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 4095d5c65159SKalle Valo msdu->len + skb_tailroom(msdu), 4096d5c65159SKalle Valo DMA_FROM_DEVICE); 4097d5c65159SKalle Valo 4098d5c65159SKalle Valo num_buffs_reaped[mac_id]++; 4099d5c65159SKalle Valo total_num_buffs_reaped++; 4100d5c65159SKalle Valo budget--; 4101d5c65159SKalle Valo 4102d5c65159SKalle Valo if (err_info.push_reason != 4103d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4104d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4105d5c65159SKalle Valo continue; 4106d5c65159SKalle Valo } 4107d5c65159SKalle Valo 4108d5c65159SKalle Valo rxcb->err_rel_src = err_info.err_rel_src; 4109d5c65159SKalle Valo rxcb->err_code = err_info.err_code; 4110d5c65159SKalle Valo rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 4111d5c65159SKalle Valo __skb_queue_tail(&msdu_list[mac_id], msdu); 4112d5c65159SKalle Valo } 4113d5c65159SKalle Valo 4114d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4115d5c65159SKalle Valo 4116d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4117d5c65159SKalle Valo 4118d5c65159SKalle Valo if (!total_num_buffs_reaped) 4119d5c65159SKalle Valo goto done; 4120d5c65159SKalle Valo 4121d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 4122d5c65159SKalle Valo if (!num_buffs_reaped[i]) 4123d5c65159SKalle Valo continue; 4124d5c65159SKalle Valo 4125d5c65159SKalle Valo ar = ab->pdevs[i].ar; 4126d5c65159SKalle Valo rx_ring = &ar->dp.rx_refill_buf_ring; 4127d5c65159SKalle Valo 4128d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, i, rx_ring, num_buffs_reaped[i], 4129734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 4130d5c65159SKalle Valo } 4131d5c65159SKalle Valo 4132d5c65159SKalle Valo rcu_read_lock(); 4133d5c65159SKalle Valo for (i = 0; i < ab->num_radios; i++) { 4134d5c65159SKalle Valo if (!rcu_dereference(ab->pdevs_active[i])) { 4135d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 4136d5c65159SKalle Valo continue; 4137d5c65159SKalle Valo } 4138d5c65159SKalle Valo 4139d5c65159SKalle Valo ar = ab->pdevs[i].ar; 4140d5c65159SKalle Valo 4141d5c65159SKalle Valo if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { 4142d5c65159SKalle Valo __skb_queue_purge(&msdu_list[i]); 4143d5c65159SKalle Valo continue; 4144d5c65159SKalle Valo } 4145d5c65159SKalle Valo 4146d5c65159SKalle Valo while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 4147d5c65159SKalle Valo ath11k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 4148d5c65159SKalle Valo } 4149d5c65159SKalle Valo rcu_read_unlock(); 4150d5c65159SKalle Valo done: 4151d5c65159SKalle Valo return total_num_buffs_reaped; 4152d5c65159SKalle Valo } 4153d5c65159SKalle Valo 4154d5c65159SKalle Valo int ath11k_dp_process_rxdma_err(struct ath11k_base *ab, int mac_id, int budget) 4155d5c65159SKalle Valo { 41564152e420SCarl Huang struct ath11k *ar; 41574152e420SCarl Huang struct dp_srng *err_ring; 41584152e420SCarl Huang struct dp_rxdma_ring *rx_ring; 4159d5c65159SKalle Valo struct dp_link_desc_bank *link_desc_banks = ab->dp.link_desc_banks; 4160d5c65159SKalle Valo struct hal_srng *srng; 4161293cb583SJohn Crispin u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 4162d5c65159SKalle Valo enum hal_rx_buf_return_buf_manager rbm; 4163d5c65159SKalle Valo enum hal_reo_entr_rxdma_ecode rxdma_err_code; 4164d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4165d5c65159SKalle Valo struct sk_buff *skb; 4166d5c65159SKalle Valo struct hal_reo_entrance_ring *entr_ring; 4167d5c65159SKalle Valo void *desc; 4168d5c65159SKalle Valo int num_buf_freed = 0; 4169d5c65159SKalle Valo int quota = budget; 4170d5c65159SKalle Valo dma_addr_t paddr; 4171d5c65159SKalle Valo u32 desc_bank; 4172d5c65159SKalle Valo void *link_desc_va; 4173d5c65159SKalle Valo int num_msdus; 4174d5c65159SKalle Valo int i; 4175d5c65159SKalle Valo int buf_id; 4176d5c65159SKalle Valo 41774152e420SCarl Huang ar = ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar; 41784152e420SCarl Huang err_ring = &ar->dp.rxdma_err_dst_ring[ath11k_hw_mac_id_to_srng_id(&ab->hw_params, 41794152e420SCarl Huang mac_id)]; 41804152e420SCarl Huang rx_ring = &ar->dp.rx_refill_buf_ring; 41814152e420SCarl Huang 4182d5c65159SKalle Valo srng = &ab->hal.srng_list[err_ring->ring_id]; 4183d5c65159SKalle Valo 4184d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4185d5c65159SKalle Valo 4186d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4187d5c65159SKalle Valo 4188d5c65159SKalle Valo while (quota-- && 4189d5c65159SKalle Valo (desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4190d5c65159SKalle Valo ath11k_hal_rx_reo_ent_paddr_get(ab, desc, &paddr, &desc_bank); 4191d5c65159SKalle Valo 4192d5c65159SKalle Valo entr_ring = (struct hal_reo_entrance_ring *)desc; 4193d5c65159SKalle Valo rxdma_err_code = 4194d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4195d5c65159SKalle Valo entr_ring->info1); 4196d5c65159SKalle Valo ab->soc_stats.rxdma_error[rxdma_err_code]++; 4197d5c65159SKalle Valo 4198d5c65159SKalle Valo link_desc_va = link_desc_banks[desc_bank].vaddr + 4199d5c65159SKalle Valo (paddr - link_desc_banks[desc_bank].paddr); 4200293cb583SJohn Crispin ath11k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, 4201293cb583SJohn Crispin msdu_cookies, &rbm); 4202d5c65159SKalle Valo 4203d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4204d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4205293cb583SJohn Crispin msdu_cookies[i]); 4206d5c65159SKalle Valo 4207d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4208d5c65159SKalle Valo skb = idr_find(&rx_ring->bufs_idr, buf_id); 4209d5c65159SKalle Valo if (!skb) { 4210d5c65159SKalle Valo ath11k_warn(ab, "rxdma error with invalid buf_id %d\n", 4211d5c65159SKalle Valo buf_id); 4212d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4213d5c65159SKalle Valo continue; 4214d5c65159SKalle Valo } 4215d5c65159SKalle Valo 4216d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4217d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4218d5c65159SKalle Valo 4219d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(skb); 4220d5c65159SKalle Valo dma_unmap_single(ab->dev, rxcb->paddr, 4221d5c65159SKalle Valo skb->len + skb_tailroom(skb), 4222d5c65159SKalle Valo DMA_FROM_DEVICE); 4223d5c65159SKalle Valo dev_kfree_skb_any(skb); 4224d5c65159SKalle Valo 4225d5c65159SKalle Valo num_buf_freed++; 4226d5c65159SKalle Valo } 4227d5c65159SKalle Valo 4228d5c65159SKalle Valo ath11k_dp_rx_link_desc_return(ab, desc, 4229d5c65159SKalle Valo HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4230d5c65159SKalle Valo } 4231d5c65159SKalle Valo 4232d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4233d5c65159SKalle Valo 4234d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4235d5c65159SKalle Valo 4236d5c65159SKalle Valo if (num_buf_freed) 4237d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ab, mac_id, rx_ring, num_buf_freed, 4238734223d7SBaochen Qiang ab->hw_params.hal_params->rx_buf_rbm); 4239d5c65159SKalle Valo 4240d5c65159SKalle Valo return budget - quota; 4241d5c65159SKalle Valo } 4242d5c65159SKalle Valo 4243d5c65159SKalle Valo void ath11k_dp_process_reo_status(struct ath11k_base *ab) 4244d5c65159SKalle Valo { 4245d5c65159SKalle Valo struct ath11k_dp *dp = &ab->dp; 4246d5c65159SKalle Valo struct hal_srng *srng; 4247d5c65159SKalle Valo struct dp_reo_cmd *cmd, *tmp; 4248d5c65159SKalle Valo bool found = false; 4249d5c65159SKalle Valo u32 *reo_desc; 4250d5c65159SKalle Valo u16 tag; 4251d5c65159SKalle Valo struct hal_reo_status reo_status; 4252d5c65159SKalle Valo 4253d5c65159SKalle Valo srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 4254d5c65159SKalle Valo 4255d5c65159SKalle Valo memset(&reo_status, 0, sizeof(reo_status)); 4256d5c65159SKalle Valo 4257d5c65159SKalle Valo spin_lock_bh(&srng->lock); 4258d5c65159SKalle Valo 4259d5c65159SKalle Valo ath11k_hal_srng_access_begin(ab, srng); 4260d5c65159SKalle Valo 4261d5c65159SKalle Valo while ((reo_desc = ath11k_hal_srng_dst_get_next_entry(ab, srng))) { 4262d5c65159SKalle Valo tag = FIELD_GET(HAL_SRNG_TLV_HDR_TAG, *reo_desc); 4263d5c65159SKalle Valo 4264d5c65159SKalle Valo switch (tag) { 4265d5c65159SKalle Valo case HAL_REO_GET_QUEUE_STATS_STATUS: 4266d5c65159SKalle Valo ath11k_hal_reo_status_queue_stats(ab, reo_desc, 4267d5c65159SKalle Valo &reo_status); 4268d5c65159SKalle Valo break; 4269d5c65159SKalle Valo case HAL_REO_FLUSH_QUEUE_STATUS: 4270d5c65159SKalle Valo ath11k_hal_reo_flush_queue_status(ab, reo_desc, 4271d5c65159SKalle Valo &reo_status); 4272d5c65159SKalle Valo break; 4273d5c65159SKalle Valo case HAL_REO_FLUSH_CACHE_STATUS: 4274d5c65159SKalle Valo ath11k_hal_reo_flush_cache_status(ab, reo_desc, 4275d5c65159SKalle Valo &reo_status); 4276d5c65159SKalle Valo break; 4277d5c65159SKalle Valo case HAL_REO_UNBLOCK_CACHE_STATUS: 4278d5c65159SKalle Valo ath11k_hal_reo_unblk_cache_status(ab, reo_desc, 4279d5c65159SKalle Valo &reo_status); 4280d5c65159SKalle Valo break; 4281d5c65159SKalle Valo case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 4282d5c65159SKalle Valo ath11k_hal_reo_flush_timeout_list_status(ab, reo_desc, 4283d5c65159SKalle Valo &reo_status); 4284d5c65159SKalle Valo break; 4285d5c65159SKalle Valo case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 4286d5c65159SKalle Valo ath11k_hal_reo_desc_thresh_reached_status(ab, reo_desc, 4287d5c65159SKalle Valo &reo_status); 4288d5c65159SKalle Valo break; 4289d5c65159SKalle Valo case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 4290d5c65159SKalle Valo ath11k_hal_reo_update_rx_reo_queue_status(ab, reo_desc, 4291d5c65159SKalle Valo &reo_status); 4292d5c65159SKalle Valo break; 4293d5c65159SKalle Valo default: 4294d5c65159SKalle Valo ath11k_warn(ab, "Unknown reo status type %d\n", tag); 4295d5c65159SKalle Valo continue; 4296d5c65159SKalle Valo } 4297d5c65159SKalle Valo 4298d5c65159SKalle Valo spin_lock_bh(&dp->reo_cmd_lock); 4299d5c65159SKalle Valo list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 4300d5c65159SKalle Valo if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 4301d5c65159SKalle Valo found = true; 4302d5c65159SKalle Valo list_del(&cmd->list); 4303d5c65159SKalle Valo break; 4304d5c65159SKalle Valo } 4305d5c65159SKalle Valo } 4306d5c65159SKalle Valo spin_unlock_bh(&dp->reo_cmd_lock); 4307d5c65159SKalle Valo 4308d5c65159SKalle Valo if (found) { 4309d5c65159SKalle Valo cmd->handler(dp, (void *)&cmd->data, 4310d5c65159SKalle Valo reo_status.uniform_hdr.cmd_status); 4311d5c65159SKalle Valo kfree(cmd); 4312d5c65159SKalle Valo } 4313d5c65159SKalle Valo 4314d5c65159SKalle Valo found = false; 4315d5c65159SKalle Valo } 4316d5c65159SKalle Valo 4317d5c65159SKalle Valo ath11k_hal_srng_access_end(ab, srng); 4318d5c65159SKalle Valo 4319d5c65159SKalle Valo spin_unlock_bh(&srng->lock); 4320d5c65159SKalle Valo } 4321d5c65159SKalle Valo 4322d5c65159SKalle Valo void ath11k_dp_rx_pdev_free(struct ath11k_base *ab, int mac_id) 4323d5c65159SKalle Valo { 4324d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4325d5c65159SKalle Valo 4326d5c65159SKalle Valo ath11k_dp_rx_pdev_srng_free(ar); 4327d5c65159SKalle Valo ath11k_dp_rxdma_pdev_buf_free(ar); 4328d5c65159SKalle Valo } 4329d5c65159SKalle Valo 4330d5c65159SKalle Valo int ath11k_dp_rx_pdev_alloc(struct ath11k_base *ab, int mac_id) 4331d5c65159SKalle Valo { 4332d5c65159SKalle Valo struct ath11k *ar = ab->pdevs[mac_id].ar; 4333d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4334d5c65159SKalle Valo u32 ring_id; 43354152e420SCarl Huang int i; 4336d5c65159SKalle Valo int ret; 4337d5c65159SKalle Valo 4338d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_srng_alloc(ar); 4339d5c65159SKalle Valo if (ret) { 4340d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rx srngs\n"); 4341d5c65159SKalle Valo return ret; 4342d5c65159SKalle Valo } 4343d5c65159SKalle Valo 4344d5c65159SKalle Valo ret = ath11k_dp_rxdma_pdev_buf_setup(ar); 4345d5c65159SKalle Valo if (ret) { 4346d5c65159SKalle Valo ath11k_warn(ab, "failed to setup rxdma ring\n"); 4347d5c65159SKalle Valo return ret; 4348d5c65159SKalle Valo } 4349d5c65159SKalle Valo 4350d5c65159SKalle Valo ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4351d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id, HAL_RXDMA_BUF); 4352d5c65159SKalle Valo if (ret) { 4353d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4354d5c65159SKalle Valo ret); 4355d5c65159SKalle Valo return ret; 4356d5c65159SKalle Valo } 4357d5c65159SKalle Valo 43584152e420SCarl Huang if (ab->hw_params.rx_mac_buf_ring) { 43594152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 43604152e420SCarl Huang ring_id = dp->rx_mac_buf_ring[i].ring_id; 43614152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 43624152e420SCarl Huang mac_id + i, HAL_RXDMA_BUF); 4363d5c65159SKalle Valo if (ret) { 43644152e420SCarl Huang ath11k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 43654152e420SCarl Huang i, ret); 4366d5c65159SKalle Valo return ret; 4367d5c65159SKalle Valo } 43684152e420SCarl Huang } 43694152e420SCarl Huang } 43704152e420SCarl Huang 43714152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 43724152e420SCarl Huang ring_id = dp->rxdma_err_dst_ring[i].ring_id; 43734152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 43744152e420SCarl Huang mac_id + i, HAL_RXDMA_DST); 43754152e420SCarl Huang if (ret) { 43764152e420SCarl Huang ath11k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 43774152e420SCarl Huang i, ret); 43784152e420SCarl Huang return ret; 43794152e420SCarl Huang } 43804152e420SCarl Huang } 4381d5c65159SKalle Valo 43827f6fc1ebSCarl Huang if (!ab->hw_params.rxdma1_enable) 43837f6fc1ebSCarl Huang goto config_refill_ring; 43847f6fc1ebSCarl Huang 4385d5c65159SKalle Valo ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4386d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, 4387d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_BUF); 4388d5c65159SKalle Valo if (ret) { 4389d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4390d5c65159SKalle Valo ret); 4391d5c65159SKalle Valo return ret; 4392d5c65159SKalle Valo } 4393d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4394d5c65159SKalle Valo dp->rxdma_mon_dst_ring.ring_id, 4395d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DST); 4396d5c65159SKalle Valo if (ret) { 4397d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4398d5c65159SKalle Valo ret); 4399d5c65159SKalle Valo return ret; 4400d5c65159SKalle Valo } 4401d5c65159SKalle Valo ret = ath11k_dp_tx_htt_srng_setup(ab, 4402d5c65159SKalle Valo dp->rxdma_mon_desc_ring.ring_id, 4403d5c65159SKalle Valo mac_id, HAL_RXDMA_MONITOR_DESC); 4404d5c65159SKalle Valo if (ret) { 4405d5c65159SKalle Valo ath11k_warn(ab, "failed to configure rxdma_mon_dst_ring %d\n", 4406d5c65159SKalle Valo ret); 4407d5c65159SKalle Valo return ret; 4408d5c65159SKalle Valo } 44097f6fc1ebSCarl Huang 44107f6fc1ebSCarl Huang config_refill_ring: 44114152e420SCarl Huang for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) { 44124152e420SCarl Huang ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id; 44134152e420SCarl Huang ret = ath11k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, 4414d5c65159SKalle Valo HAL_RXDMA_MONITOR_STATUS); 4415d5c65159SKalle Valo if (ret) { 4416d5c65159SKalle Valo ath11k_warn(ab, 44174152e420SCarl Huang "failed to configure mon_status_refill_ring%d %d\n", 44184152e420SCarl Huang i, ret); 4419d5c65159SKalle Valo return ret; 4420d5c65159SKalle Valo } 44214152e420SCarl Huang } 44227f6fc1ebSCarl Huang 4423d5c65159SKalle Valo return 0; 4424d5c65159SKalle Valo } 4425d5c65159SKalle Valo 4426d5c65159SKalle Valo static void ath11k_dp_mon_set_frag_len(u32 *total_len, u32 *frag_len) 4427d5c65159SKalle Valo { 4428d5c65159SKalle Valo if (*total_len >= (DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc))) { 4429d5c65159SKalle Valo *frag_len = DP_RX_BUFFER_SIZE - sizeof(struct hal_rx_desc); 4430d5c65159SKalle Valo *total_len -= *frag_len; 4431d5c65159SKalle Valo } else { 4432d5c65159SKalle Valo *frag_len = *total_len; 4433d5c65159SKalle Valo *total_len = 0; 4434d5c65159SKalle Valo } 4435d5c65159SKalle Valo } 4436d5c65159SKalle Valo 4437d5c65159SKalle Valo static 4438d5c65159SKalle Valo int ath11k_dp_rx_monitor_link_desc_return(struct ath11k *ar, 4439d5c65159SKalle Valo void *p_last_buf_addr_info, 4440d5c65159SKalle Valo u8 mac_id) 4441d5c65159SKalle Valo { 4442d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4443d5c65159SKalle Valo struct dp_srng *dp_srng; 4444d5c65159SKalle Valo void *hal_srng; 4445d5c65159SKalle Valo void *src_srng_desc; 4446d5c65159SKalle Valo int ret = 0; 4447d5c65159SKalle Valo 4448701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4449d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 4450d5c65159SKalle Valo hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4451701e48a4SCarl Huang } else { 4452701e48a4SCarl Huang dp_srng = &ar->ab->dp.wbm_desc_rel_ring; 4453701e48a4SCarl Huang hal_srng = &ar->ab->hal.srng_list[dp_srng->ring_id]; 4454701e48a4SCarl Huang } 4455d5c65159SKalle Valo 4456d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, hal_srng); 4457d5c65159SKalle Valo 4458d5c65159SKalle Valo src_srng_desc = ath11k_hal_srng_src_get_next_entry(ar->ab, hal_srng); 4459d5c65159SKalle Valo 4460d5c65159SKalle Valo if (src_srng_desc) { 4461d5c65159SKalle Valo struct ath11k_buffer_addr *src_desc = 4462d5c65159SKalle Valo (struct ath11k_buffer_addr *)src_srng_desc; 4463d5c65159SKalle Valo 4464d5c65159SKalle Valo *src_desc = *((struct ath11k_buffer_addr *)p_last_buf_addr_info); 4465d5c65159SKalle Valo } else { 4466d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4467d5c65159SKalle Valo "Monitor Link Desc Ring %d Full", mac_id); 4468d5c65159SKalle Valo ret = -ENOMEM; 4469d5c65159SKalle Valo } 4470d5c65159SKalle Valo 4471d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, hal_srng); 4472d5c65159SKalle Valo return ret; 4473d5c65159SKalle Valo } 4474d5c65159SKalle Valo 4475d5c65159SKalle Valo static 4476d5c65159SKalle Valo void ath11k_dp_rx_mon_next_link_desc_get(void *rx_msdu_link_desc, 4477d5c65159SKalle Valo dma_addr_t *paddr, u32 *sw_cookie, 4478701e48a4SCarl Huang u8 *rbm, 4479d5c65159SKalle Valo void **pp_buf_addr_info) 4480d5c65159SKalle Valo { 4481d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = 4482d5c65159SKalle Valo (struct hal_rx_msdu_link *)rx_msdu_link_desc; 4483d5c65159SKalle Valo struct ath11k_buffer_addr *buf_addr_info; 4484d5c65159SKalle Valo 4485d5c65159SKalle Valo buf_addr_info = (struct ath11k_buffer_addr *)&msdu_link->buf_addr_info; 4486d5c65159SKalle Valo 4487701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_get(buf_addr_info, paddr, sw_cookie, rbm); 4488d5c65159SKalle Valo 4489d5c65159SKalle Valo *pp_buf_addr_info = (void *)buf_addr_info; 4490d5c65159SKalle Valo } 4491d5c65159SKalle Valo 4492d5c65159SKalle Valo static int ath11k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) 4493d5c65159SKalle Valo { 4494d5c65159SKalle Valo if (skb->len > len) { 4495d5c65159SKalle Valo skb_trim(skb, len); 4496d5c65159SKalle Valo } else { 4497d5c65159SKalle Valo if (skb_tailroom(skb) < len - skb->len) { 4498d5c65159SKalle Valo if ((pskb_expand_head(skb, 0, 4499d5c65159SKalle Valo len - skb->len - skb_tailroom(skb), 4500d5c65159SKalle Valo GFP_ATOMIC))) { 4501d5c65159SKalle Valo dev_kfree_skb_any(skb); 4502d5c65159SKalle Valo return -ENOMEM; 4503d5c65159SKalle Valo } 4504d5c65159SKalle Valo } 4505d5c65159SKalle Valo skb_put(skb, (len - skb->len)); 4506d5c65159SKalle Valo } 4507d5c65159SKalle Valo return 0; 4508d5c65159SKalle Valo } 4509d5c65159SKalle Valo 4510d5c65159SKalle Valo static void ath11k_hal_rx_msdu_list_get(struct ath11k *ar, 4511d5c65159SKalle Valo void *msdu_link_desc, 4512d5c65159SKalle Valo struct hal_rx_msdu_list *msdu_list, 4513d5c65159SKalle Valo u16 *num_msdus) 4514d5c65159SKalle Valo { 4515d5c65159SKalle Valo struct hal_rx_msdu_details *msdu_details = NULL; 4516d5c65159SKalle Valo struct rx_msdu_desc *msdu_desc_info = NULL; 4517d5c65159SKalle Valo struct hal_rx_msdu_link *msdu_link = NULL; 4518d5c65159SKalle Valo int i; 4519d5c65159SKalle Valo u32 last = FIELD_PREP(RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU, 1); 4520d5c65159SKalle Valo u32 first = FIELD_PREP(RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU, 1); 4521d5c65159SKalle Valo u8 tmp = 0; 4522d5c65159SKalle Valo 4523d5c65159SKalle Valo msdu_link = (struct hal_rx_msdu_link *)msdu_link_desc; 4524d5c65159SKalle Valo msdu_details = &msdu_link->msdu_link[0]; 4525d5c65159SKalle Valo 4526d5c65159SKalle Valo for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 4527d5c65159SKalle Valo if (FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 4528d5c65159SKalle Valo msdu_details[i].buf_addr_info.info0) == 0) { 4529d5c65159SKalle Valo msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 4530d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4531d5c65159SKalle Valo ; 4532d5c65159SKalle Valo break; 4533d5c65159SKalle Valo } 4534d5c65159SKalle Valo msdu_desc_info = &msdu_details[i].rx_msdu_info; 4535d5c65159SKalle Valo 4536d5c65159SKalle Valo if (!i) 4537d5c65159SKalle Valo msdu_desc_info->info0 |= first; 4538d5c65159SKalle Valo else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 4539d5c65159SKalle Valo msdu_desc_info->info0 |= last; 4540d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_flags = msdu_desc_info->info0; 4541d5c65159SKalle Valo msdu_list->msdu_info[i].msdu_len = 4542d5c65159SKalle Valo HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 4543d5c65159SKalle Valo msdu_list->sw_cookie[i] = 4544d5c65159SKalle Valo FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 4545d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4546d5c65159SKalle Valo tmp = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 4547d5c65159SKalle Valo msdu_details[i].buf_addr_info.info1); 4548d5c65159SKalle Valo msdu_list->rbm[i] = tmp; 4549d5c65159SKalle Valo } 4550d5c65159SKalle Valo *num_msdus = i; 4551d5c65159SKalle Valo } 4552d5c65159SKalle Valo 4553d5c65159SKalle Valo static u32 ath11k_dp_rx_mon_comp_ppduid(u32 msdu_ppdu_id, u32 *ppdu_id, 4554d5c65159SKalle Valo u32 *rx_bufs_used) 4555d5c65159SKalle Valo { 4556d5c65159SKalle Valo u32 ret = 0; 4557d5c65159SKalle Valo 4558d5c65159SKalle Valo if ((*ppdu_id < msdu_ppdu_id) && 4559d5c65159SKalle Valo ((msdu_ppdu_id - *ppdu_id) < DP_NOT_PPDU_ID_WRAP_AROUND)) { 4560d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4561d5c65159SKalle Valo ret = msdu_ppdu_id; 4562d5c65159SKalle Valo } else if ((*ppdu_id > msdu_ppdu_id) && 4563d5c65159SKalle Valo ((*ppdu_id - msdu_ppdu_id) > DP_NOT_PPDU_ID_WRAP_AROUND)) { 4564d5c65159SKalle Valo /* mon_dst is behind than mon_status 4565d5c65159SKalle Valo * skip dst_ring and free it 4566d5c65159SKalle Valo */ 4567d5c65159SKalle Valo *rx_bufs_used += 1; 4568d5c65159SKalle Valo *ppdu_id = msdu_ppdu_id; 4569d5c65159SKalle Valo ret = msdu_ppdu_id; 4570d5c65159SKalle Valo } 4571d5c65159SKalle Valo return ret; 4572d5c65159SKalle Valo } 4573d5c65159SKalle Valo 4574d5c65159SKalle Valo static void ath11k_dp_mon_get_buf_len(struct hal_rx_msdu_desc_info *info, 4575d5c65159SKalle Valo bool *is_frag, u32 *total_len, 4576d5c65159SKalle Valo u32 *frag_len, u32 *msdu_cnt) 4577d5c65159SKalle Valo { 4578d5c65159SKalle Valo if (info->msdu_flags & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) { 4579d5c65159SKalle Valo if (!*is_frag) { 4580d5c65159SKalle Valo *total_len = info->msdu_len; 4581d5c65159SKalle Valo *is_frag = true; 4582d5c65159SKalle Valo } 4583d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4584d5c65159SKalle Valo frag_len); 4585d5c65159SKalle Valo } else { 4586d5c65159SKalle Valo if (*is_frag) { 4587d5c65159SKalle Valo ath11k_dp_mon_set_frag_len(total_len, 4588d5c65159SKalle Valo frag_len); 4589d5c65159SKalle Valo } else { 4590d5c65159SKalle Valo *frag_len = info->msdu_len; 4591d5c65159SKalle Valo } 4592d5c65159SKalle Valo *is_frag = false; 4593d5c65159SKalle Valo *msdu_cnt -= 1; 4594d5c65159SKalle Valo } 4595d5c65159SKalle Valo } 4596d5c65159SKalle Valo 4597d5c65159SKalle Valo static u32 4598701e48a4SCarl Huang ath11k_dp_rx_mon_mpdu_pop(struct ath11k *ar, int mac_id, 4599d5c65159SKalle Valo void *ring_entry, struct sk_buff **head_msdu, 4600d5c65159SKalle Valo struct sk_buff **tail_msdu, u32 *npackets, 4601d5c65159SKalle Valo u32 *ppdu_id) 4602d5c65159SKalle Valo { 4603d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4604d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 4605d5c65159SKalle Valo struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 4606d5c65159SKalle Valo struct sk_buff *msdu = NULL, *last = NULL; 4607d5c65159SKalle Valo struct hal_rx_msdu_list msdu_list; 4608d5c65159SKalle Valo void *p_buf_addr_info, *p_last_buf_addr_info; 4609d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4610d5c65159SKalle Valo void *rx_msdu_link_desc; 4611d5c65159SKalle Valo dma_addr_t paddr; 4612d5c65159SKalle Valo u16 num_msdus = 0; 4613d5c65159SKalle Valo u32 rx_buf_size, rx_pkt_offset, sw_cookie; 4614d5c65159SKalle Valo u32 rx_bufs_used = 0, i = 0; 4615d5c65159SKalle Valo u32 msdu_ppdu_id = 0, msdu_cnt = 0; 4616d5c65159SKalle Valo u32 total_len = 0, frag_len = 0; 4617d5c65159SKalle Valo bool is_frag, is_first_msdu; 4618d5c65159SKalle Valo bool drop_mpdu = false; 4619d5c65159SKalle Valo struct ath11k_skb_rxcb *rxcb; 4620d5c65159SKalle Valo struct hal_reo_entrance_ring *ent_desc = 4621d5c65159SKalle Valo (struct hal_reo_entrance_ring *)ring_entry; 4622d5c65159SKalle Valo int buf_id; 4623701e48a4SCarl Huang u32 rx_link_buf_info[2]; 4624701e48a4SCarl Huang u8 rbm; 4625701e48a4SCarl Huang 4626701e48a4SCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 4627701e48a4SCarl Huang rx_ring = &dp->rx_refill_buf_ring; 4628d5c65159SKalle Valo 4629d5c65159SKalle Valo ath11k_hal_rx_reo_ent_buf_paddr_get(ring_entry, &paddr, 4630701e48a4SCarl Huang &sw_cookie, 4631701e48a4SCarl Huang &p_last_buf_addr_info, &rbm, 4632d5c65159SKalle Valo &msdu_cnt); 4633d5c65159SKalle Valo 4634d5c65159SKalle Valo if (FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON, 4635d5c65159SKalle Valo ent_desc->info1) == 4636d5c65159SKalle Valo HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 4637d5c65159SKalle Valo u8 rxdma_err = 4638d5c65159SKalle Valo FIELD_GET(HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE, 4639d5c65159SKalle Valo ent_desc->info1); 4640d5c65159SKalle Valo if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 4641d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 4642d5c65159SKalle Valo rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 4643d5c65159SKalle Valo drop_mpdu = true; 4644d5c65159SKalle Valo pmon->rx_mon_stats.dest_mpdu_drop++; 4645d5c65159SKalle Valo } 4646d5c65159SKalle Valo } 4647d5c65159SKalle Valo 4648d5c65159SKalle Valo is_frag = false; 4649d5c65159SKalle Valo is_first_msdu = true; 4650d5c65159SKalle Valo 4651d5c65159SKalle Valo do { 4652d5c65159SKalle Valo if (pmon->mon_last_linkdesc_paddr == paddr) { 4653d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_linkdesc_cnt++; 4654d5c65159SKalle Valo return rx_bufs_used; 4655d5c65159SKalle Valo } 4656d5c65159SKalle Valo 4657701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 4658d5c65159SKalle Valo rx_msdu_link_desc = 4659d5c65159SKalle Valo (void *)pmon->link_desc_banks[sw_cookie].vaddr + 4660d5c65159SKalle Valo (paddr - pmon->link_desc_banks[sw_cookie].paddr); 4661701e48a4SCarl Huang else 4662701e48a4SCarl Huang rx_msdu_link_desc = 4663701e48a4SCarl Huang (void *)ar->ab->dp.link_desc_banks[sw_cookie].vaddr + 4664701e48a4SCarl Huang (paddr - ar->ab->dp.link_desc_banks[sw_cookie].paddr); 4665d5c65159SKalle Valo 4666d5c65159SKalle Valo ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 4667d5c65159SKalle Valo &num_msdus); 4668d5c65159SKalle Valo 4669d5c65159SKalle Valo for (i = 0; i < num_msdus; i++) { 4670d5c65159SKalle Valo u32 l2_hdr_offset; 4671d5c65159SKalle Valo 4672d5c65159SKalle Valo if (pmon->mon_last_buf_cookie == msdu_list.sw_cookie[i]) { 4673d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4674d5c65159SKalle Valo "i %d last_cookie %d is same\n", 4675d5c65159SKalle Valo i, pmon->mon_last_buf_cookie); 4676d5c65159SKalle Valo drop_mpdu = true; 4677d5c65159SKalle Valo pmon->rx_mon_stats.dup_mon_buf_cnt++; 4678d5c65159SKalle Valo continue; 4679d5c65159SKalle Valo } 4680d5c65159SKalle Valo buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 4681d5c65159SKalle Valo msdu_list.sw_cookie[i]); 4682d5c65159SKalle Valo 4683d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4684d5c65159SKalle Valo msdu = idr_find(&rx_ring->bufs_idr, buf_id); 4685d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4686d5c65159SKalle Valo if (!msdu) { 4687d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4688d5c65159SKalle Valo "msdu_pop: invalid buf_id %d\n", buf_id); 4689d5c65159SKalle Valo break; 4690d5c65159SKalle Valo } 4691d5c65159SKalle Valo rxcb = ATH11K_SKB_RXCB(msdu); 4692d5c65159SKalle Valo if (!rxcb->unmapped) { 4693d5c65159SKalle Valo dma_unmap_single(ar->ab->dev, rxcb->paddr, 4694d5c65159SKalle Valo msdu->len + 4695d5c65159SKalle Valo skb_tailroom(msdu), 4696d5c65159SKalle Valo DMA_FROM_DEVICE); 4697d5c65159SKalle Valo rxcb->unmapped = 1; 4698d5c65159SKalle Valo } 4699d5c65159SKalle Valo if (drop_mpdu) { 4700d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4701d5c65159SKalle Valo "i %d drop msdu %p *ppdu_id %x\n", 4702d5c65159SKalle Valo i, msdu, *ppdu_id); 4703d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4704d5c65159SKalle Valo msdu = NULL; 4705d5c65159SKalle Valo goto next_msdu; 4706d5c65159SKalle Valo } 4707d5c65159SKalle Valo 4708d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)msdu->data; 4709d5c65159SKalle Valo 4710d5c65159SKalle Valo rx_pkt_offset = sizeof(struct hal_rx_desc); 4711e678fbd4SKarthikeyan Periyasamy l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 4712d5c65159SKalle Valo 4713d5c65159SKalle Valo if (is_first_msdu) { 4714e678fbd4SKarthikeyan Periyasamy if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 4715d5c65159SKalle Valo drop_mpdu = true; 4716d5c65159SKalle Valo dev_kfree_skb_any(msdu); 4717d5c65159SKalle Valo msdu = NULL; 4718d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4719d5c65159SKalle Valo goto next_msdu; 4720d5c65159SKalle Valo } 4721d5c65159SKalle Valo 4722d5c65159SKalle Valo msdu_ppdu_id = 4723e678fbd4SKarthikeyan Periyasamy ath11k_dp_rxdesc_get_ppduid(ar->ab, rx_desc); 4724d5c65159SKalle Valo 4725d5c65159SKalle Valo if (ath11k_dp_rx_mon_comp_ppduid(msdu_ppdu_id, 4726d5c65159SKalle Valo ppdu_id, 47275e02bc73SMiles Hu &rx_bufs_used)) { 47285e02bc73SMiles Hu if (rx_bufs_used) { 47295e02bc73SMiles Hu drop_mpdu = true; 47305e02bc73SMiles Hu dev_kfree_skb_any(msdu); 47315e02bc73SMiles Hu msdu = NULL; 47325e02bc73SMiles Hu goto next_msdu; 47335e02bc73SMiles Hu } 4734d5c65159SKalle Valo return rx_bufs_used; 47355e02bc73SMiles Hu } 4736d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = paddr; 4737d5c65159SKalle Valo is_first_msdu = false; 4738d5c65159SKalle Valo } 4739d5c65159SKalle Valo ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 4740d5c65159SKalle Valo &is_frag, &total_len, 4741d5c65159SKalle Valo &frag_len, &msdu_cnt); 4742d5c65159SKalle Valo rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 4743d5c65159SKalle Valo 4744d5c65159SKalle Valo ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 4745d5c65159SKalle Valo 4746d5c65159SKalle Valo if (!(*head_msdu)) 4747d5c65159SKalle Valo *head_msdu = msdu; 4748d5c65159SKalle Valo else if (last) 4749d5c65159SKalle Valo last->next = msdu; 4750d5c65159SKalle Valo 4751d5c65159SKalle Valo last = msdu; 4752d5c65159SKalle Valo next_msdu: 4753d5c65159SKalle Valo pmon->mon_last_buf_cookie = msdu_list.sw_cookie[i]; 4754d5c65159SKalle Valo rx_bufs_used++; 4755d5c65159SKalle Valo spin_lock_bh(&rx_ring->idr_lock); 4756d5c65159SKalle Valo idr_remove(&rx_ring->bufs_idr, buf_id); 4757d5c65159SKalle Valo spin_unlock_bh(&rx_ring->idr_lock); 4758d5c65159SKalle Valo } 4759d5c65159SKalle Valo 4760701e48a4SCarl Huang ath11k_hal_rx_buf_addr_info_set(rx_link_buf_info, paddr, sw_cookie, rbm); 4761701e48a4SCarl Huang 4762d5c65159SKalle Valo ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, &paddr, 4763701e48a4SCarl Huang &sw_cookie, &rbm, 4764d5c65159SKalle Valo &p_buf_addr_info); 4765d5c65159SKalle Valo 4766701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) { 4767d5c65159SKalle Valo if (ath11k_dp_rx_monitor_link_desc_return(ar, 4768d5c65159SKalle Valo p_last_buf_addr_info, 4769d5c65159SKalle Valo dp->mac_id)) 4770d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 4771d5c65159SKalle Valo "dp_rx_monitor_link_desc_return failed"); 4772701e48a4SCarl Huang } else { 4773701e48a4SCarl Huang ath11k_dp_rx_link_desc_return(ar->ab, rx_link_buf_info, 4774701e48a4SCarl Huang HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 4775701e48a4SCarl Huang } 4776d5c65159SKalle Valo 4777d5c65159SKalle Valo p_last_buf_addr_info = p_buf_addr_info; 4778d5c65159SKalle Valo 4779d5c65159SKalle Valo } while (paddr && msdu_cnt); 4780d5c65159SKalle Valo 4781d5c65159SKalle Valo if (last) 4782d5c65159SKalle Valo last->next = NULL; 4783d5c65159SKalle Valo 4784d5c65159SKalle Valo *tail_msdu = msdu; 4785d5c65159SKalle Valo 4786d5c65159SKalle Valo if (msdu_cnt == 0) 4787d5c65159SKalle Valo *npackets = 1; 4788d5c65159SKalle Valo 4789d5c65159SKalle Valo return rx_bufs_used; 4790d5c65159SKalle Valo } 4791d5c65159SKalle Valo 4792e678fbd4SKarthikeyan Periyasamy static void ath11k_dp_rx_msdus_set_payload(struct ath11k *ar, struct sk_buff *msdu) 4793d5c65159SKalle Valo { 4794d5c65159SKalle Valo u32 rx_pkt_offset, l2_hdr_offset; 4795d5c65159SKalle Valo 4796e678fbd4SKarthikeyan Periyasamy rx_pkt_offset = ar->ab->hw_params.hal_desc_sz; 4797e678fbd4SKarthikeyan Periyasamy l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, 4798e678fbd4SKarthikeyan Periyasamy (struct hal_rx_desc *)msdu->data); 4799d5c65159SKalle Valo skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 4800d5c65159SKalle Valo } 4801d5c65159SKalle Valo 4802d5c65159SKalle Valo static struct sk_buff * 4803d5c65159SKalle Valo ath11k_dp_rx_mon_merg_msdus(struct ath11k *ar, 4804d5c65159SKalle Valo u32 mac_id, struct sk_buff *head_msdu, 4805d5c65159SKalle Valo struct sk_buff *last_msdu, 480678726489SP Praneesh struct ieee80211_rx_status *rxs, bool *fcs_err) 4807d5c65159SKalle Valo { 4808e678fbd4SKarthikeyan Periyasamy struct ath11k_base *ab = ar->ab; 48097210b4b7STim Gardner struct sk_buff *msdu, *prev_buf; 4810d5c65159SKalle Valo struct hal_rx_desc *rx_desc; 4811d5c65159SKalle Valo char *hdr_desc; 4812e678fbd4SKarthikeyan Periyasamy u8 *dest, decap_format; 4813d5c65159SKalle Valo struct ieee80211_hdr_3addr *wh; 4814e678fbd4SKarthikeyan Periyasamy struct rx_attention *rx_attention; 481578726489SP Praneesh u32 err_bitmap; 4816d5c65159SKalle Valo 4817d5c65159SKalle Valo if (!head_msdu) 4818d5c65159SKalle Valo goto err_merge_fail; 4819d5c65159SKalle Valo 4820d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4821e678fbd4SKarthikeyan Periyasamy rx_attention = ath11k_dp_rx_get_attention(ab, rx_desc); 482278726489SP Praneesh err_bitmap = ath11k_dp_rx_h_attn_mpdu_err(rx_attention); 482378726489SP Praneesh 482478726489SP Praneesh if (err_bitmap & DP_RX_MPDU_ERR_FCS) 482578726489SP Praneesh *fcs_err = true; 4826d5c65159SKalle Valo 4827e678fbd4SKarthikeyan Periyasamy if (ath11k_dp_rxdesc_get_mpdulen_err(rx_attention)) 4828d5c65159SKalle Valo return NULL; 4829d5c65159SKalle Valo 4830e678fbd4SKarthikeyan Periyasamy decap_format = ath11k_dp_rx_h_msdu_start_decap_type(ab, rx_desc); 4831d5c65159SKalle Valo 4832d5c65159SKalle Valo ath11k_dp_rx_h_ppdu(ar, rx_desc, rxs); 4833d5c65159SKalle Valo 4834d5c65159SKalle Valo if (decap_format == DP_RX_DECAP_TYPE_RAW) { 4835e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_msdus_set_payload(ar, head_msdu); 4836d5c65159SKalle Valo 4837d5c65159SKalle Valo prev_buf = head_msdu; 4838d5c65159SKalle Valo msdu = head_msdu->next; 4839d5c65159SKalle Valo 4840d5c65159SKalle Valo while (msdu) { 4841e678fbd4SKarthikeyan Periyasamy ath11k_dp_rx_msdus_set_payload(ar, msdu); 4842d5c65159SKalle Valo 4843d5c65159SKalle Valo prev_buf = msdu; 4844d5c65159SKalle Valo msdu = msdu->next; 4845d5c65159SKalle Valo } 4846d5c65159SKalle Valo 4847d5c65159SKalle Valo prev_buf->next = NULL; 4848d5c65159SKalle Valo 4849d5c65159SKalle Valo skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 4850d5c65159SKalle Valo } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 4851d5c65159SKalle Valo u8 qos_pkt = 0; 4852d5c65159SKalle Valo 4853d5c65159SKalle Valo rx_desc = (struct hal_rx_desc *)head_msdu->data; 4854e678fbd4SKarthikeyan Periyasamy hdr_desc = ath11k_dp_rxdesc_get_80211hdr(ab, rx_desc); 4855d5c65159SKalle Valo 4856d5c65159SKalle Valo /* Base size */ 4857d5c65159SKalle Valo wh = (struct ieee80211_hdr_3addr *)hdr_desc; 4858d5c65159SKalle Valo 4859*01d2f285SPradeep Kumar Chitrapu if (ieee80211_is_data_qos(wh->frame_control)) 4860d5c65159SKalle Valo qos_pkt = 1; 4861*01d2f285SPradeep Kumar Chitrapu 4862d5c65159SKalle Valo msdu = head_msdu; 4863d5c65159SKalle Valo 4864d5c65159SKalle Valo while (msdu) { 4865*01d2f285SPradeep Kumar Chitrapu ath11k_dp_rx_msdus_set_payload(ar, msdu); 4866d5c65159SKalle Valo if (qos_pkt) { 4867d5c65159SKalle Valo dest = skb_push(msdu, sizeof(__le16)); 4868d5c65159SKalle Valo if (!dest) 4869d5c65159SKalle Valo goto err_merge_fail; 4870*01d2f285SPradeep Kumar Chitrapu memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 4871d5c65159SKalle Valo } 4872d5c65159SKalle Valo prev_buf = msdu; 4873d5c65159SKalle Valo msdu = msdu->next; 4874d5c65159SKalle Valo } 4875d5c65159SKalle Valo dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 4876d5c65159SKalle Valo if (!dest) 4877d5c65159SKalle Valo goto err_merge_fail; 4878d5c65159SKalle Valo 4879e678fbd4SKarthikeyan Periyasamy ath11k_dbg(ab, ATH11K_DBG_DATA, 4880d5c65159SKalle Valo "mpdu_buf %pK mpdu_buf->len %u", 4881d5c65159SKalle Valo prev_buf, prev_buf->len); 4882d5c65159SKalle Valo } else { 4883e678fbd4SKarthikeyan Periyasamy ath11k_dbg(ab, ATH11K_DBG_DATA, 4884d5c65159SKalle Valo "decap format %d is not supported!\n", 4885d5c65159SKalle Valo decap_format); 4886d5c65159SKalle Valo goto err_merge_fail; 4887d5c65159SKalle Valo } 4888d5c65159SKalle Valo 4889d5c65159SKalle Valo return head_msdu; 4890d5c65159SKalle Valo 4891d5c65159SKalle Valo err_merge_fail: 4892d5c65159SKalle Valo return NULL; 4893d5c65159SKalle Valo } 4894d5c65159SKalle Valo 4895*01d2f285SPradeep Kumar Chitrapu static void 4896*01d2f285SPradeep Kumar Chitrapu ath11k_dp_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 4897*01d2f285SPradeep Kumar Chitrapu u8 *rtap_buf) 4898*01d2f285SPradeep Kumar Chitrapu { 4899*01d2f285SPradeep Kumar Chitrapu u32 rtap_len = 0; 4900*01d2f285SPradeep Kumar Chitrapu 4901*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 4902*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4903*01d2f285SPradeep Kumar Chitrapu 4904*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 4905*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4906*01d2f285SPradeep Kumar Chitrapu 4907*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 4908*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4909*01d2f285SPradeep Kumar Chitrapu 4910*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 4911*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4912*01d2f285SPradeep Kumar Chitrapu 4913*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 4914*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4915*01d2f285SPradeep Kumar Chitrapu 4916*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 4917*01d2f285SPradeep Kumar Chitrapu } 4918*01d2f285SPradeep Kumar Chitrapu 4919*01d2f285SPradeep Kumar Chitrapu static void 4920*01d2f285SPradeep Kumar Chitrapu ath11k_dp_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 4921*01d2f285SPradeep Kumar Chitrapu u8 *rtap_buf) 4922*01d2f285SPradeep Kumar Chitrapu { 4923*01d2f285SPradeep Kumar Chitrapu u32 rtap_len = 0; 4924*01d2f285SPradeep Kumar Chitrapu 4925*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 4926*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4927*01d2f285SPradeep Kumar Chitrapu 4928*01d2f285SPradeep Kumar Chitrapu put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 4929*01d2f285SPradeep Kumar Chitrapu rtap_len += 2; 4930*01d2f285SPradeep Kumar Chitrapu 4931*01d2f285SPradeep Kumar Chitrapu rtap_buf[rtap_len] = rx_status->he_RU[0]; 4932*01d2f285SPradeep Kumar Chitrapu rtap_len += 1; 4933*01d2f285SPradeep Kumar Chitrapu 4934*01d2f285SPradeep Kumar Chitrapu rtap_buf[rtap_len] = rx_status->he_RU[1]; 4935*01d2f285SPradeep Kumar Chitrapu rtap_len += 1; 4936*01d2f285SPradeep Kumar Chitrapu 4937*01d2f285SPradeep Kumar Chitrapu rtap_buf[rtap_len] = rx_status->he_RU[2]; 4938*01d2f285SPradeep Kumar Chitrapu rtap_len += 1; 4939*01d2f285SPradeep Kumar Chitrapu 4940*01d2f285SPradeep Kumar Chitrapu rtap_buf[rtap_len] = rx_status->he_RU[3]; 4941*01d2f285SPradeep Kumar Chitrapu } 4942*01d2f285SPradeep Kumar Chitrapu 4943*01d2f285SPradeep Kumar Chitrapu static void ath11k_update_radiotap(struct hal_rx_mon_ppdu_info *ppduinfo, 4944*01d2f285SPradeep Kumar Chitrapu struct sk_buff *mon_skb, 4945*01d2f285SPradeep Kumar Chitrapu struct ieee80211_rx_status *rxs) 4946*01d2f285SPradeep Kumar Chitrapu { 4947*01d2f285SPradeep Kumar Chitrapu u8 *ptr = NULL; 4948*01d2f285SPradeep Kumar Chitrapu 4949*01d2f285SPradeep Kumar Chitrapu if (ppduinfo->he_mu_flags) { 4950*01d2f285SPradeep Kumar Chitrapu rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 4951*01d2f285SPradeep Kumar Chitrapu rxs->encoding = RX_ENC_HE; 4952*01d2f285SPradeep Kumar Chitrapu ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 4953*01d2f285SPradeep Kumar Chitrapu ath11k_dp_rx_update_radiotap_he_mu(ppduinfo, ptr); 4954*01d2f285SPradeep Kumar Chitrapu } 4955*01d2f285SPradeep Kumar Chitrapu if (ppduinfo->he_flags) { 4956*01d2f285SPradeep Kumar Chitrapu rxs->flag |= RX_FLAG_RADIOTAP_HE; 4957*01d2f285SPradeep Kumar Chitrapu rxs->encoding = RX_ENC_HE; 4958*01d2f285SPradeep Kumar Chitrapu ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 4959*01d2f285SPradeep Kumar Chitrapu ath11k_dp_rx_update_radiotap_he(ppduinfo, ptr); 4960*01d2f285SPradeep Kumar Chitrapu } 4961*01d2f285SPradeep Kumar Chitrapu 4962*01d2f285SPradeep Kumar Chitrapu rxs->flag |= RX_FLAG_MACTIME_START; 4963*01d2f285SPradeep Kumar Chitrapu rxs->signal = ppduinfo->rssi_comb + ATH11K_DEFAULT_NOISE_FLOOR; 4964*01d2f285SPradeep Kumar Chitrapu rxs->nss = ppduinfo->nss; 4965*01d2f285SPradeep Kumar Chitrapu 4966*01d2f285SPradeep Kumar Chitrapu rxs->mactime = ppduinfo->tsft; 4967*01d2f285SPradeep Kumar Chitrapu } 4968*01d2f285SPradeep Kumar Chitrapu 4969d5c65159SKalle Valo static int ath11k_dp_rx_mon_deliver(struct ath11k *ar, u32 mac_id, 4970d5c65159SKalle Valo struct sk_buff *head_msdu, 4971*01d2f285SPradeep Kumar Chitrapu struct hal_rx_mon_ppdu_info *ppduinfo, 4972d5c65159SKalle Valo struct sk_buff *tail_msdu, 4973d5c65159SKalle Valo struct napi_struct *napi) 4974d5c65159SKalle Valo { 4975d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 4976d5c65159SKalle Valo struct sk_buff *mon_skb, *skb_next, *header; 49772167fa60SSriram R struct ieee80211_rx_status *rxs = &dp->rx_status; 497878726489SP Praneesh bool fcs_err = false; 4979d5c65159SKalle Valo 4980d5c65159SKalle Valo mon_skb = ath11k_dp_rx_mon_merg_msdus(ar, mac_id, head_msdu, 498178726489SP Praneesh tail_msdu, rxs, &fcs_err); 4982d5c65159SKalle Valo 4983d5c65159SKalle Valo if (!mon_skb) 4984d5c65159SKalle Valo goto mon_deliver_fail; 4985d5c65159SKalle Valo 4986d5c65159SKalle Valo header = mon_skb; 4987d5c65159SKalle Valo 4988d5c65159SKalle Valo rxs->flag = 0; 498978726489SP Praneesh 499078726489SP Praneesh if (fcs_err) 499178726489SP Praneesh rxs->flag = RX_FLAG_FAILED_FCS_CRC; 499278726489SP Praneesh 4993d5c65159SKalle Valo do { 4994d5c65159SKalle Valo skb_next = mon_skb->next; 4995d5c65159SKalle Valo if (!skb_next) 4996d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_AMSDU_MORE; 4997d5c65159SKalle Valo else 4998d5c65159SKalle Valo rxs->flag |= RX_FLAG_AMSDU_MORE; 4999d5c65159SKalle Valo 5000d5c65159SKalle Valo if (mon_skb == header) { 5001d5c65159SKalle Valo header = NULL; 5002d5c65159SKalle Valo rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 5003d5c65159SKalle Valo } else { 5004d5c65159SKalle Valo rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 5005d5c65159SKalle Valo } 5006*01d2f285SPradeep Kumar Chitrapu ath11k_update_radiotap(ppduinfo, mon_skb, rxs); 5007d5c65159SKalle Valo 50082167fa60SSriram R ath11k_dp_rx_deliver_msdu(ar, napi, mon_skb, rxs); 5009d5c65159SKalle Valo mon_skb = skb_next; 50105e02bc73SMiles Hu } while (mon_skb); 5011d5c65159SKalle Valo rxs->flag = 0; 5012d5c65159SKalle Valo 5013d5c65159SKalle Valo return 0; 5014d5c65159SKalle Valo 5015d5c65159SKalle Valo mon_deliver_fail: 5016d5c65159SKalle Valo mon_skb = head_msdu; 5017d5c65159SKalle Valo while (mon_skb) { 5018d5c65159SKalle Valo skb_next = mon_skb->next; 5019d5c65159SKalle Valo dev_kfree_skb_any(mon_skb); 5020d5c65159SKalle Valo mon_skb = skb_next; 5021d5c65159SKalle Valo } 5022d5c65159SKalle Valo return -EINVAL; 5023d5c65159SKalle Valo } 5024d5c65159SKalle Valo 50251e15aacdSKarthikeyan Kathirvel /* The destination ring processing is stuck if the destination is not 50261e15aacdSKarthikeyan Kathirvel * moving while status ring moves 16 PPDU. The destination ring processing 50271e15aacdSKarthikeyan Kathirvel * skips this destination ring PPDU as a workaround. 50281e15aacdSKarthikeyan Kathirvel */ 50291e15aacdSKarthikeyan Kathirvel #define MON_DEST_RING_STUCK_MAX_CNT 16 50301e15aacdSKarthikeyan Kathirvel 5031701e48a4SCarl Huang static void ath11k_dp_rx_mon_dest_process(struct ath11k *ar, int mac_id, 5032701e48a4SCarl Huang u32 quota, struct napi_struct *napi) 5033d5c65159SKalle Valo { 5034d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5035d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5036734223d7SBaochen Qiang const struct ath11k_hw_hal_params *hal_params; 5037d5c65159SKalle Valo void *ring_entry; 5038d5c65159SKalle Valo void *mon_dst_srng; 5039d5c65159SKalle Valo u32 ppdu_id; 5040d5c65159SKalle Valo u32 rx_bufs_used; 5041701e48a4SCarl Huang u32 ring_id; 5042d5c65159SKalle Valo struct ath11k_pdev_mon_stats *rx_mon_stats; 5043d5c65159SKalle Valo u32 npackets = 0; 50441e15aacdSKarthikeyan Kathirvel u32 mpdu_rx_bufs_used; 5045d5c65159SKalle Valo 5046701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 5047701e48a4SCarl Huang ring_id = dp->rxdma_mon_dst_ring.ring_id; 5048701e48a4SCarl Huang else 5049701e48a4SCarl Huang ring_id = dp->rxdma_err_dst_ring[mac_id].ring_id; 5050701e48a4SCarl Huang 5051701e48a4SCarl Huang mon_dst_srng = &ar->ab->hal.srng_list[ring_id]; 5052d5c65159SKalle Valo 5053d5c65159SKalle Valo if (!mon_dst_srng) { 5054d5c65159SKalle Valo ath11k_warn(ar->ab, 5055d5c65159SKalle Valo "HAL Monitor Destination Ring Init Failed -- %pK", 5056d5c65159SKalle Valo mon_dst_srng); 5057d5c65159SKalle Valo return; 5058d5c65159SKalle Valo } 5059d5c65159SKalle Valo 5060d5c65159SKalle Valo spin_lock_bh(&pmon->mon_lock); 5061d5c65159SKalle Valo 5062d5c65159SKalle Valo ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 5063d5c65159SKalle Valo 5064d5c65159SKalle Valo ppdu_id = pmon->mon_ppdu_info.ppdu_id; 5065d5c65159SKalle Valo rx_bufs_used = 0; 5066d5c65159SKalle Valo rx_mon_stats = &pmon->rx_mon_stats; 5067d5c65159SKalle Valo 5068d5c65159SKalle Valo while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 5069d5c65159SKalle Valo struct sk_buff *head_msdu, *tail_msdu; 5070d5c65159SKalle Valo 5071d5c65159SKalle Valo head_msdu = NULL; 5072d5c65159SKalle Valo tail_msdu = NULL; 5073d5c65159SKalle Valo 50741e15aacdSKarthikeyan Kathirvel mpdu_rx_bufs_used = ath11k_dp_rx_mon_mpdu_pop(ar, mac_id, ring_entry, 5075d5c65159SKalle Valo &head_msdu, 5076d5c65159SKalle Valo &tail_msdu, 5077d5c65159SKalle Valo &npackets, &ppdu_id); 5078d5c65159SKalle Valo 50791e15aacdSKarthikeyan Kathirvel rx_bufs_used += mpdu_rx_bufs_used; 50801e15aacdSKarthikeyan Kathirvel 50811e15aacdSKarthikeyan Kathirvel if (mpdu_rx_bufs_used) { 50821e15aacdSKarthikeyan Kathirvel dp->mon_dest_ring_stuck_cnt = 0; 50831e15aacdSKarthikeyan Kathirvel } else { 50841e15aacdSKarthikeyan Kathirvel dp->mon_dest_ring_stuck_cnt++; 50851e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_not_reaped++; 50861e15aacdSKarthikeyan Kathirvel } 50871e15aacdSKarthikeyan Kathirvel 50881e15aacdSKarthikeyan Kathirvel if (dp->mon_dest_ring_stuck_cnt > MON_DEST_RING_STUCK_MAX_CNT) { 50891e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_stuck++; 50901e15aacdSKarthikeyan Kathirvel ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 50911e15aacdSKarthikeyan Kathirvel "status ring ppdu_id=%d dest ring ppdu_id=%d mon_dest_ring_stuck_cnt=%d dest_mon_not_reaped=%u dest_mon_stuck=%u\n", 50921e15aacdSKarthikeyan Kathirvel pmon->mon_ppdu_info.ppdu_id, ppdu_id, 50931e15aacdSKarthikeyan Kathirvel dp->mon_dest_ring_stuck_cnt, 50941e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_not_reaped, 50951e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_stuck); 50961e15aacdSKarthikeyan Kathirvel pmon->mon_ppdu_info.ppdu_id = ppdu_id; 50971e15aacdSKarthikeyan Kathirvel continue; 50981e15aacdSKarthikeyan Kathirvel } 50991e15aacdSKarthikeyan Kathirvel 5100d5c65159SKalle Valo if (ppdu_id != pmon->mon_ppdu_info.ppdu_id) { 5101d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5102d5c65159SKalle Valo ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 51031e15aacdSKarthikeyan Kathirvel "dest_rx: new ppdu_id %x != status ppdu_id %x dest_mon_not_reaped = %u dest_mon_stuck = %u\n", 51041e15aacdSKarthikeyan Kathirvel ppdu_id, pmon->mon_ppdu_info.ppdu_id, 51051e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_not_reaped, 51061e15aacdSKarthikeyan Kathirvel rx_mon_stats->dest_mon_stuck); 5107d5c65159SKalle Valo break; 5108d5c65159SKalle Valo } 5109d5c65159SKalle Valo if (head_msdu && tail_msdu) { 5110d5c65159SKalle Valo ath11k_dp_rx_mon_deliver(ar, dp->mac_id, head_msdu, 5111*01d2f285SPradeep Kumar Chitrapu &pmon->mon_ppdu_info, 5112d5c65159SKalle Valo tail_msdu, napi); 5113d5c65159SKalle Valo rx_mon_stats->dest_mpdu_done++; 5114d5c65159SKalle Valo } 5115d5c65159SKalle Valo 5116d5c65159SKalle Valo ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 5117d5c65159SKalle Valo mon_dst_srng); 5118d5c65159SKalle Valo } 5119d5c65159SKalle Valo ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 5120d5c65159SKalle Valo 5121d5c65159SKalle Valo spin_unlock_bh(&pmon->mon_lock); 5122d5c65159SKalle Valo 5123d5c65159SKalle Valo if (rx_bufs_used) { 5124d5c65159SKalle Valo rx_mon_stats->dest_ppdu_done++; 5125734223d7SBaochen Qiang hal_params = ar->ab->hw_params.hal_params; 5126734223d7SBaochen Qiang 5127701e48a4SCarl Huang if (ar->ab->hw_params.rxdma1_enable) 5128d5c65159SKalle Valo ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5129d5c65159SKalle Valo &dp->rxdma_mon_buf_ring, 5130d5c65159SKalle Valo rx_bufs_used, 5131734223d7SBaochen Qiang hal_params->rx_buf_rbm); 5132701e48a4SCarl Huang else 5133701e48a4SCarl Huang ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 5134701e48a4SCarl Huang &dp->rx_refill_buf_ring, 5135701e48a4SCarl Huang rx_bufs_used, 5136734223d7SBaochen Qiang hal_params->rx_buf_rbm); 5137d5c65159SKalle Valo } 5138d5c65159SKalle Valo } 5139d5c65159SKalle Valo 51403cd04a43SAloka Dixit int ath11k_dp_rx_process_mon_status(struct ath11k_base *ab, int mac_id, 51413cd04a43SAloka Dixit struct napi_struct *napi, int budget) 51423cd04a43SAloka Dixit { 51433cd04a43SAloka Dixit struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 51443cd04a43SAloka Dixit enum hal_rx_mon_status hal_status; 51453cd04a43SAloka Dixit struct sk_buff *skb; 51463cd04a43SAloka Dixit struct sk_buff_head skb_list; 51473cd04a43SAloka Dixit struct ath11k_peer *peer; 51483cd04a43SAloka Dixit struct ath11k_sta *arsta; 51493cd04a43SAloka Dixit int num_buffs_reaped = 0; 51503cd04a43SAloka Dixit u32 rx_buf_sz; 5151dca857f0SAnilkumar Kolli u16 log_type; 51523cd04a43SAloka Dixit struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&ar->dp.mon_data; 51533cd04a43SAloka Dixit struct ath11k_pdev_mon_stats *rx_mon_stats = &pmon->rx_mon_stats; 51543cd04a43SAloka Dixit struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 51553cd04a43SAloka Dixit 51563cd04a43SAloka Dixit __skb_queue_head_init(&skb_list); 51573cd04a43SAloka Dixit 51583cd04a43SAloka Dixit num_buffs_reaped = ath11k_dp_rx_reap_mon_status_ring(ab, mac_id, &budget, 51593cd04a43SAloka Dixit &skb_list); 51603cd04a43SAloka Dixit if (!num_buffs_reaped) 51613cd04a43SAloka Dixit goto exit; 51623cd04a43SAloka Dixit 51633cd04a43SAloka Dixit memset(ppdu_info, 0, sizeof(*ppdu_info)); 51643cd04a43SAloka Dixit ppdu_info->peer_id = HAL_INVALID_PEERID; 51653cd04a43SAloka Dixit 51663cd04a43SAloka Dixit while ((skb = __skb_dequeue(&skb_list))) { 51673cd04a43SAloka Dixit if (ath11k_debugfs_is_pktlog_lite_mode_enabled(ar)) { 51683cd04a43SAloka Dixit log_type = ATH11K_PKTLOG_TYPE_LITE_RX; 51693cd04a43SAloka Dixit rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; 51703cd04a43SAloka Dixit } else if (ath11k_debugfs_is_pktlog_rx_stats_enabled(ar)) { 51713cd04a43SAloka Dixit log_type = ATH11K_PKTLOG_TYPE_RX_STATBUF; 51723cd04a43SAloka Dixit rx_buf_sz = DP_RX_BUFFER_SIZE; 5173dca857f0SAnilkumar Kolli } else { 5174dca857f0SAnilkumar Kolli log_type = ATH11K_PKTLOG_TYPE_INVALID; 5175dca857f0SAnilkumar Kolli rx_buf_sz = 0; 51763cd04a43SAloka Dixit } 51773cd04a43SAloka Dixit 5178dca857f0SAnilkumar Kolli if (log_type != ATH11K_PKTLOG_TYPE_INVALID) 51793cd04a43SAloka Dixit trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 51803cd04a43SAloka Dixit 5181*01d2f285SPradeep Kumar Chitrapu memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); 51823cd04a43SAloka Dixit hal_status = ath11k_hal_rx_parse_mon_status(ab, ppdu_info, skb); 51833cd04a43SAloka Dixit 51843cd04a43SAloka Dixit if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 51853cd04a43SAloka Dixit pmon->mon_ppdu_status == DP_PPDU_STATUS_START && 51863cd04a43SAloka Dixit hal_status == HAL_TLV_STATUS_PPDU_DONE) { 51873cd04a43SAloka Dixit rx_mon_stats->status_ppdu_done++; 51883cd04a43SAloka Dixit pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; 51893cd04a43SAloka Dixit ath11k_dp_rx_mon_dest_process(ar, mac_id, budget, napi); 51903cd04a43SAloka Dixit pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 51913cd04a43SAloka Dixit } 51923cd04a43SAloka Dixit 51933cd04a43SAloka Dixit if (ppdu_info->peer_id == HAL_INVALID_PEERID || 51943cd04a43SAloka Dixit hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 51953cd04a43SAloka Dixit dev_kfree_skb_any(skb); 51963cd04a43SAloka Dixit continue; 51973cd04a43SAloka Dixit } 51983cd04a43SAloka Dixit 51993cd04a43SAloka Dixit rcu_read_lock(); 52003cd04a43SAloka Dixit spin_lock_bh(&ab->base_lock); 52013cd04a43SAloka Dixit peer = ath11k_peer_find_by_id(ab, ppdu_info->peer_id); 52023cd04a43SAloka Dixit 52033cd04a43SAloka Dixit if (!peer || !peer->sta) { 52043cd04a43SAloka Dixit ath11k_dbg(ab, ATH11K_DBG_DATA, 52053cd04a43SAloka Dixit "failed to find the peer with peer_id %d\n", 52063cd04a43SAloka Dixit ppdu_info->peer_id); 52073cd04a43SAloka Dixit goto next_skb; 52083cd04a43SAloka Dixit } 52093cd04a43SAloka Dixit 52103cd04a43SAloka Dixit arsta = (struct ath11k_sta *)peer->sta->drv_priv; 52113cd04a43SAloka Dixit ath11k_dp_rx_update_peer_stats(arsta, ppdu_info); 52123cd04a43SAloka Dixit 52133cd04a43SAloka Dixit if (ath11k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) 52143cd04a43SAloka Dixit trace_ath11k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); 52153cd04a43SAloka Dixit 52163cd04a43SAloka Dixit next_skb: 52173cd04a43SAloka Dixit spin_unlock_bh(&ab->base_lock); 52183cd04a43SAloka Dixit rcu_read_unlock(); 52193cd04a43SAloka Dixit 52203cd04a43SAloka Dixit dev_kfree_skb_any(skb); 52213cd04a43SAloka Dixit memset(ppdu_info, 0, sizeof(*ppdu_info)); 52223cd04a43SAloka Dixit ppdu_info->peer_id = HAL_INVALID_PEERID; 52233cd04a43SAloka Dixit } 52243cd04a43SAloka Dixit exit: 52253cd04a43SAloka Dixit return num_buffs_reaped; 52263cd04a43SAloka Dixit } 52273cd04a43SAloka Dixit 52287e2ea2e9SAnilkumar Kolli static u32 52297e2ea2e9SAnilkumar Kolli ath11k_dp_rx_full_mon_mpdu_pop(struct ath11k *ar, 52307e2ea2e9SAnilkumar Kolli void *ring_entry, struct sk_buff **head_msdu, 52317e2ea2e9SAnilkumar Kolli struct sk_buff **tail_msdu, 52327e2ea2e9SAnilkumar Kolli struct hal_sw_mon_ring_entries *sw_mon_entries) 52337e2ea2e9SAnilkumar Kolli { 52347e2ea2e9SAnilkumar Kolli struct ath11k_pdev_dp *dp = &ar->dp; 52357e2ea2e9SAnilkumar Kolli struct ath11k_mon_data *pmon = &dp->mon_data; 52367e2ea2e9SAnilkumar Kolli struct dp_rxdma_ring *rx_ring = &dp->rxdma_mon_buf_ring; 52377e2ea2e9SAnilkumar Kolli struct sk_buff *msdu = NULL, *last = NULL; 52387e2ea2e9SAnilkumar Kolli struct hal_sw_monitor_ring *sw_desc = ring_entry; 52397e2ea2e9SAnilkumar Kolli struct hal_rx_msdu_list msdu_list; 52407e2ea2e9SAnilkumar Kolli struct hal_rx_desc *rx_desc; 52417e2ea2e9SAnilkumar Kolli struct ath11k_skb_rxcb *rxcb; 52427e2ea2e9SAnilkumar Kolli void *rx_msdu_link_desc; 52437e2ea2e9SAnilkumar Kolli void *p_buf_addr_info, *p_last_buf_addr_info; 52447e2ea2e9SAnilkumar Kolli int buf_id, i = 0; 52457e2ea2e9SAnilkumar Kolli u32 rx_buf_size, rx_pkt_offset, l2_hdr_offset; 52467e2ea2e9SAnilkumar Kolli u32 rx_bufs_used = 0, msdu_cnt = 0; 52477e2ea2e9SAnilkumar Kolli u32 total_len = 0, frag_len = 0, sw_cookie; 52487e2ea2e9SAnilkumar Kolli u16 num_msdus = 0; 52497e2ea2e9SAnilkumar Kolli u8 rxdma_err, rbm; 52507e2ea2e9SAnilkumar Kolli bool is_frag, is_first_msdu; 52517e2ea2e9SAnilkumar Kolli bool drop_mpdu = false; 52527e2ea2e9SAnilkumar Kolli 52537e2ea2e9SAnilkumar Kolli ath11k_hal_rx_sw_mon_ring_buf_paddr_get(ring_entry, sw_mon_entries); 52547e2ea2e9SAnilkumar Kolli 52557e2ea2e9SAnilkumar Kolli sw_cookie = sw_mon_entries->mon_dst_sw_cookie; 52567e2ea2e9SAnilkumar Kolli sw_mon_entries->end_of_ppdu = false; 52577e2ea2e9SAnilkumar Kolli sw_mon_entries->drop_ppdu = false; 52587e2ea2e9SAnilkumar Kolli p_last_buf_addr_info = sw_mon_entries->dst_buf_addr_info; 52597e2ea2e9SAnilkumar Kolli msdu_cnt = sw_mon_entries->msdu_cnt; 52607e2ea2e9SAnilkumar Kolli 52617e2ea2e9SAnilkumar Kolli sw_mon_entries->end_of_ppdu = 52627e2ea2e9SAnilkumar Kolli FIELD_GET(HAL_SW_MON_RING_INFO0_END_OF_PPDU, sw_desc->info0); 52637e2ea2e9SAnilkumar Kolli if (sw_mon_entries->end_of_ppdu) 52647e2ea2e9SAnilkumar Kolli return rx_bufs_used; 52657e2ea2e9SAnilkumar Kolli 52667e2ea2e9SAnilkumar Kolli if (FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON, 52677e2ea2e9SAnilkumar Kolli sw_desc->info0) == 52687e2ea2e9SAnilkumar Kolli HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 52697e2ea2e9SAnilkumar Kolli rxdma_err = 52707e2ea2e9SAnilkumar Kolli FIELD_GET(HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE, 52717e2ea2e9SAnilkumar Kolli sw_desc->info0); 52727e2ea2e9SAnilkumar Kolli if (rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR || 52737e2ea2e9SAnilkumar Kolli rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR || 52747e2ea2e9SAnilkumar Kolli rxdma_err == HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR) { 52757e2ea2e9SAnilkumar Kolli pmon->rx_mon_stats.dest_mpdu_drop++; 52767e2ea2e9SAnilkumar Kolli drop_mpdu = true; 52777e2ea2e9SAnilkumar Kolli } 52787e2ea2e9SAnilkumar Kolli } 52797e2ea2e9SAnilkumar Kolli 52807e2ea2e9SAnilkumar Kolli is_frag = false; 52817e2ea2e9SAnilkumar Kolli is_first_msdu = true; 52827e2ea2e9SAnilkumar Kolli 52837e2ea2e9SAnilkumar Kolli do { 52847e2ea2e9SAnilkumar Kolli rx_msdu_link_desc = 52857e2ea2e9SAnilkumar Kolli (u8 *)pmon->link_desc_banks[sw_cookie].vaddr + 52867e2ea2e9SAnilkumar Kolli (sw_mon_entries->mon_dst_paddr - 52877e2ea2e9SAnilkumar Kolli pmon->link_desc_banks[sw_cookie].paddr); 52887e2ea2e9SAnilkumar Kolli 52897e2ea2e9SAnilkumar Kolli ath11k_hal_rx_msdu_list_get(ar, rx_msdu_link_desc, &msdu_list, 52907e2ea2e9SAnilkumar Kolli &num_msdus); 52917e2ea2e9SAnilkumar Kolli 52927e2ea2e9SAnilkumar Kolli for (i = 0; i < num_msdus; i++) { 52937e2ea2e9SAnilkumar Kolli buf_id = FIELD_GET(DP_RXDMA_BUF_COOKIE_BUF_ID, 52947e2ea2e9SAnilkumar Kolli msdu_list.sw_cookie[i]); 52957e2ea2e9SAnilkumar Kolli 52967e2ea2e9SAnilkumar Kolli spin_lock_bh(&rx_ring->idr_lock); 52977e2ea2e9SAnilkumar Kolli msdu = idr_find(&rx_ring->bufs_idr, buf_id); 52987e2ea2e9SAnilkumar Kolli if (!msdu) { 52997e2ea2e9SAnilkumar Kolli ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 53007e2ea2e9SAnilkumar Kolli "full mon msdu_pop: invalid buf_id %d\n", 53017e2ea2e9SAnilkumar Kolli buf_id); 53027e2ea2e9SAnilkumar Kolli spin_unlock_bh(&rx_ring->idr_lock); 53037e2ea2e9SAnilkumar Kolli break; 53047e2ea2e9SAnilkumar Kolli } 53057e2ea2e9SAnilkumar Kolli idr_remove(&rx_ring->bufs_idr, buf_id); 53067e2ea2e9SAnilkumar Kolli spin_unlock_bh(&rx_ring->idr_lock); 53077e2ea2e9SAnilkumar Kolli 53087e2ea2e9SAnilkumar Kolli rxcb = ATH11K_SKB_RXCB(msdu); 53097e2ea2e9SAnilkumar Kolli if (!rxcb->unmapped) { 53107e2ea2e9SAnilkumar Kolli dma_unmap_single(ar->ab->dev, rxcb->paddr, 53117e2ea2e9SAnilkumar Kolli msdu->len + 53127e2ea2e9SAnilkumar Kolli skb_tailroom(msdu), 53137e2ea2e9SAnilkumar Kolli DMA_FROM_DEVICE); 53147e2ea2e9SAnilkumar Kolli rxcb->unmapped = 1; 53157e2ea2e9SAnilkumar Kolli } 53167e2ea2e9SAnilkumar Kolli if (drop_mpdu) { 53177e2ea2e9SAnilkumar Kolli ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 53187e2ea2e9SAnilkumar Kolli "full mon: i %d drop msdu %p *ppdu_id %x\n", 53197e2ea2e9SAnilkumar Kolli i, msdu, sw_mon_entries->ppdu_id); 53207e2ea2e9SAnilkumar Kolli dev_kfree_skb_any(msdu); 53217e2ea2e9SAnilkumar Kolli msdu_cnt--; 53227e2ea2e9SAnilkumar Kolli goto next_msdu; 53237e2ea2e9SAnilkumar Kolli } 53247e2ea2e9SAnilkumar Kolli 53257e2ea2e9SAnilkumar Kolli rx_desc = (struct hal_rx_desc *)msdu->data; 53267e2ea2e9SAnilkumar Kolli 53277e2ea2e9SAnilkumar Kolli rx_pkt_offset = sizeof(struct hal_rx_desc); 53287e2ea2e9SAnilkumar Kolli l2_hdr_offset = ath11k_dp_rx_h_msdu_end_l3pad(ar->ab, rx_desc); 53297e2ea2e9SAnilkumar Kolli 53307e2ea2e9SAnilkumar Kolli if (is_first_msdu) { 53317e2ea2e9SAnilkumar Kolli if (!ath11k_dp_rxdesc_mpdu_valid(ar->ab, rx_desc)) { 53327e2ea2e9SAnilkumar Kolli drop_mpdu = true; 53337e2ea2e9SAnilkumar Kolli dev_kfree_skb_any(msdu); 53347e2ea2e9SAnilkumar Kolli msdu = NULL; 53357e2ea2e9SAnilkumar Kolli goto next_msdu; 53367e2ea2e9SAnilkumar Kolli } 53377e2ea2e9SAnilkumar Kolli is_first_msdu = false; 53387e2ea2e9SAnilkumar Kolli } 53397e2ea2e9SAnilkumar Kolli 53407e2ea2e9SAnilkumar Kolli ath11k_dp_mon_get_buf_len(&msdu_list.msdu_info[i], 53417e2ea2e9SAnilkumar Kolli &is_frag, &total_len, 53427e2ea2e9SAnilkumar Kolli &frag_len, &msdu_cnt); 53437e2ea2e9SAnilkumar Kolli 53447e2ea2e9SAnilkumar Kolli rx_buf_size = rx_pkt_offset + l2_hdr_offset + frag_len; 53457e2ea2e9SAnilkumar Kolli 53467e2ea2e9SAnilkumar Kolli ath11k_dp_pkt_set_pktlen(msdu, rx_buf_size); 53477e2ea2e9SAnilkumar Kolli 53487e2ea2e9SAnilkumar Kolli if (!(*head_msdu)) 53497e2ea2e9SAnilkumar Kolli *head_msdu = msdu; 53507e2ea2e9SAnilkumar Kolli else if (last) 53517e2ea2e9SAnilkumar Kolli last->next = msdu; 53527e2ea2e9SAnilkumar Kolli 53537e2ea2e9SAnilkumar Kolli last = msdu; 53547e2ea2e9SAnilkumar Kolli next_msdu: 53557e2ea2e9SAnilkumar Kolli rx_bufs_used++; 53567e2ea2e9SAnilkumar Kolli } 53577e2ea2e9SAnilkumar Kolli 53587e2ea2e9SAnilkumar Kolli ath11k_dp_rx_mon_next_link_desc_get(rx_msdu_link_desc, 53597e2ea2e9SAnilkumar Kolli &sw_mon_entries->mon_dst_paddr, 53607e2ea2e9SAnilkumar Kolli &sw_mon_entries->mon_dst_sw_cookie, 53617e2ea2e9SAnilkumar Kolli &rbm, 53627e2ea2e9SAnilkumar Kolli &p_buf_addr_info); 53637e2ea2e9SAnilkumar Kolli 53647e2ea2e9SAnilkumar Kolli if (ath11k_dp_rx_monitor_link_desc_return(ar, 53657e2ea2e9SAnilkumar Kolli p_last_buf_addr_info, 53667e2ea2e9SAnilkumar Kolli dp->mac_id)) 53677e2ea2e9SAnilkumar Kolli ath11k_dbg(ar->ab, ATH11K_DBG_DATA, 53687e2ea2e9SAnilkumar Kolli "full mon: dp_rx_monitor_link_desc_return failed\n"); 53697e2ea2e9SAnilkumar Kolli 53707e2ea2e9SAnilkumar Kolli p_last_buf_addr_info = p_buf_addr_info; 53717e2ea2e9SAnilkumar Kolli 53727e2ea2e9SAnilkumar Kolli } while (sw_mon_entries->mon_dst_paddr && msdu_cnt); 53737e2ea2e9SAnilkumar Kolli 53747e2ea2e9SAnilkumar Kolli if (last) 53757e2ea2e9SAnilkumar Kolli last->next = NULL; 53767e2ea2e9SAnilkumar Kolli 53777e2ea2e9SAnilkumar Kolli *tail_msdu = msdu; 53787e2ea2e9SAnilkumar Kolli 53797e2ea2e9SAnilkumar Kolli return rx_bufs_used; 53807e2ea2e9SAnilkumar Kolli } 53817e2ea2e9SAnilkumar Kolli 53827e2ea2e9SAnilkumar Kolli static int ath11k_dp_rx_full_mon_prepare_mpdu(struct ath11k_dp *dp, 53837e2ea2e9SAnilkumar Kolli struct dp_full_mon_mpdu *mon_mpdu, 53847e2ea2e9SAnilkumar Kolli struct sk_buff *head, 53857e2ea2e9SAnilkumar Kolli struct sk_buff *tail) 53867e2ea2e9SAnilkumar Kolli { 53877e2ea2e9SAnilkumar Kolli mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 53887e2ea2e9SAnilkumar Kolli if (!mon_mpdu) 53897e2ea2e9SAnilkumar Kolli return -ENOMEM; 53907e2ea2e9SAnilkumar Kolli 53917e2ea2e9SAnilkumar Kolli list_add_tail(&mon_mpdu->list, &dp->dp_full_mon_mpdu_list); 53927e2ea2e9SAnilkumar Kolli mon_mpdu->head = head; 53937e2ea2e9SAnilkumar Kolli mon_mpdu->tail = tail; 53947e2ea2e9SAnilkumar Kolli 53957e2ea2e9SAnilkumar Kolli return 0; 53967e2ea2e9SAnilkumar Kolli } 53977e2ea2e9SAnilkumar Kolli 53987e2ea2e9SAnilkumar Kolli static void ath11k_dp_rx_full_mon_drop_ppdu(struct ath11k_dp *dp, 53997e2ea2e9SAnilkumar Kolli struct dp_full_mon_mpdu *mon_mpdu) 54007e2ea2e9SAnilkumar Kolli { 54017e2ea2e9SAnilkumar Kolli struct dp_full_mon_mpdu *tmp; 54027e2ea2e9SAnilkumar Kolli struct sk_buff *tmp_msdu, *skb_next; 54037e2ea2e9SAnilkumar Kolli 54047e2ea2e9SAnilkumar Kolli if (list_empty(&dp->dp_full_mon_mpdu_list)) 54057e2ea2e9SAnilkumar Kolli return; 54067e2ea2e9SAnilkumar Kolli 54077e2ea2e9SAnilkumar Kolli list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 54087e2ea2e9SAnilkumar Kolli list_del(&mon_mpdu->list); 54097e2ea2e9SAnilkumar Kolli 54107e2ea2e9SAnilkumar Kolli tmp_msdu = mon_mpdu->head; 54117e2ea2e9SAnilkumar Kolli while (tmp_msdu) { 54127e2ea2e9SAnilkumar Kolli skb_next = tmp_msdu->next; 54137e2ea2e9SAnilkumar Kolli dev_kfree_skb_any(tmp_msdu); 54147e2ea2e9SAnilkumar Kolli tmp_msdu = skb_next; 54157e2ea2e9SAnilkumar Kolli } 54167e2ea2e9SAnilkumar Kolli 54177e2ea2e9SAnilkumar Kolli kfree(mon_mpdu); 54187e2ea2e9SAnilkumar Kolli } 54197e2ea2e9SAnilkumar Kolli } 54207e2ea2e9SAnilkumar Kolli 54217e2ea2e9SAnilkumar Kolli static int ath11k_dp_rx_full_mon_deliver_ppdu(struct ath11k *ar, 54227e2ea2e9SAnilkumar Kolli int mac_id, 54237e2ea2e9SAnilkumar Kolli struct ath11k_mon_data *pmon, 54247e2ea2e9SAnilkumar Kolli struct napi_struct *napi) 54257e2ea2e9SAnilkumar Kolli { 54267e2ea2e9SAnilkumar Kolli struct ath11k_pdev_mon_stats *rx_mon_stats; 54277e2ea2e9SAnilkumar Kolli struct dp_full_mon_mpdu *tmp; 54287e2ea2e9SAnilkumar Kolli struct dp_full_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 54297e2ea2e9SAnilkumar Kolli struct sk_buff *head_msdu, *tail_msdu; 54307e2ea2e9SAnilkumar Kolli struct ath11k_base *ab = ar->ab; 54317e2ea2e9SAnilkumar Kolli struct ath11k_dp *dp = &ab->dp; 54327e2ea2e9SAnilkumar Kolli int ret; 54337e2ea2e9SAnilkumar Kolli 54347e2ea2e9SAnilkumar Kolli rx_mon_stats = &pmon->rx_mon_stats; 54357e2ea2e9SAnilkumar Kolli 54367e2ea2e9SAnilkumar Kolli list_for_each_entry_safe(mon_mpdu, tmp, &dp->dp_full_mon_mpdu_list, list) { 54377e2ea2e9SAnilkumar Kolli list_del(&mon_mpdu->list); 54387e2ea2e9SAnilkumar Kolli head_msdu = mon_mpdu->head; 54397e2ea2e9SAnilkumar Kolli tail_msdu = mon_mpdu->tail; 54407e2ea2e9SAnilkumar Kolli if (head_msdu && tail_msdu) { 54417e2ea2e9SAnilkumar Kolli ret = ath11k_dp_rx_mon_deliver(ar, mac_id, head_msdu, 5442*01d2f285SPradeep Kumar Chitrapu &pmon->mon_ppdu_info, 54437e2ea2e9SAnilkumar Kolli tail_msdu, napi); 54447e2ea2e9SAnilkumar Kolli rx_mon_stats->dest_mpdu_done++; 54457e2ea2e9SAnilkumar Kolli ath11k_dbg(ar->ab, ATH11K_DBG_DATA, "full mon: deliver ppdu\n"); 54467e2ea2e9SAnilkumar Kolli } 54477e2ea2e9SAnilkumar Kolli kfree(mon_mpdu); 54487e2ea2e9SAnilkumar Kolli } 54497e2ea2e9SAnilkumar Kolli 54507e2ea2e9SAnilkumar Kolli return ret; 54517e2ea2e9SAnilkumar Kolli } 54527e2ea2e9SAnilkumar Kolli 54537e2ea2e9SAnilkumar Kolli static int 54547e2ea2e9SAnilkumar Kolli ath11k_dp_rx_process_full_mon_status_ring(struct ath11k_base *ab, int mac_id, 54557e2ea2e9SAnilkumar Kolli struct napi_struct *napi, int budget) 54567e2ea2e9SAnilkumar Kolli { 54577e2ea2e9SAnilkumar Kolli struct ath11k *ar = ab->pdevs[mac_id].ar; 54587e2ea2e9SAnilkumar Kolli struct ath11k_pdev_dp *dp = &ar->dp; 54597e2ea2e9SAnilkumar Kolli struct ath11k_mon_data *pmon = &dp->mon_data; 54607e2ea2e9SAnilkumar Kolli struct hal_sw_mon_ring_entries *sw_mon_entries; 54617e2ea2e9SAnilkumar Kolli int quota = 0, work = 0, count; 54627e2ea2e9SAnilkumar Kolli 54637e2ea2e9SAnilkumar Kolli sw_mon_entries = &pmon->sw_mon_entries; 54647e2ea2e9SAnilkumar Kolli 54657e2ea2e9SAnilkumar Kolli while (pmon->hold_mon_dst_ring) { 54667e2ea2e9SAnilkumar Kolli quota = ath11k_dp_rx_process_mon_status(ab, mac_id, 54677e2ea2e9SAnilkumar Kolli napi, 1); 54687e2ea2e9SAnilkumar Kolli if (pmon->buf_state == DP_MON_STATUS_MATCH) { 54697e2ea2e9SAnilkumar Kolli count = sw_mon_entries->status_buf_count; 54707e2ea2e9SAnilkumar Kolli if (count > 1) { 54717e2ea2e9SAnilkumar Kolli quota += ath11k_dp_rx_process_mon_status(ab, mac_id, 54727e2ea2e9SAnilkumar Kolli napi, count); 54737e2ea2e9SAnilkumar Kolli } 54747e2ea2e9SAnilkumar Kolli 54757e2ea2e9SAnilkumar Kolli ath11k_dp_rx_full_mon_deliver_ppdu(ar, dp->mac_id, 54767e2ea2e9SAnilkumar Kolli pmon, napi); 54777e2ea2e9SAnilkumar Kolli pmon->hold_mon_dst_ring = false; 54787e2ea2e9SAnilkumar Kolli } else if (!pmon->mon_status_paddr || 54797e2ea2e9SAnilkumar Kolli pmon->buf_state == DP_MON_STATUS_LEAD) { 54807e2ea2e9SAnilkumar Kolli sw_mon_entries->drop_ppdu = true; 54817e2ea2e9SAnilkumar Kolli pmon->hold_mon_dst_ring = false; 54827e2ea2e9SAnilkumar Kolli } 54837e2ea2e9SAnilkumar Kolli 54847e2ea2e9SAnilkumar Kolli if (!quota) 54857e2ea2e9SAnilkumar Kolli break; 54867e2ea2e9SAnilkumar Kolli 54877e2ea2e9SAnilkumar Kolli work += quota; 54887e2ea2e9SAnilkumar Kolli } 54897e2ea2e9SAnilkumar Kolli 54907e2ea2e9SAnilkumar Kolli if (sw_mon_entries->drop_ppdu) 54917e2ea2e9SAnilkumar Kolli ath11k_dp_rx_full_mon_drop_ppdu(&ab->dp, pmon->mon_mpdu); 54927e2ea2e9SAnilkumar Kolli 54937e2ea2e9SAnilkumar Kolli return work; 54947e2ea2e9SAnilkumar Kolli } 54957e2ea2e9SAnilkumar Kolli 54967e2ea2e9SAnilkumar Kolli static int ath11k_dp_full_mon_process_rx(struct ath11k_base *ab, int mac_id, 54977e2ea2e9SAnilkumar Kolli struct napi_struct *napi, int budget) 54987e2ea2e9SAnilkumar Kolli { 54997e2ea2e9SAnilkumar Kolli struct ath11k *ar = ab->pdevs[mac_id].ar; 55007e2ea2e9SAnilkumar Kolli struct ath11k_pdev_dp *dp = &ar->dp; 55017e2ea2e9SAnilkumar Kolli struct ath11k_mon_data *pmon = &dp->mon_data; 55027e2ea2e9SAnilkumar Kolli struct hal_sw_mon_ring_entries *sw_mon_entries; 55037e2ea2e9SAnilkumar Kolli struct ath11k_pdev_mon_stats *rx_mon_stats; 55047e2ea2e9SAnilkumar Kolli struct sk_buff *head_msdu, *tail_msdu; 55057e2ea2e9SAnilkumar Kolli void *mon_dst_srng = &ar->ab->hal.srng_list[dp->rxdma_mon_dst_ring.ring_id]; 55067e2ea2e9SAnilkumar Kolli void *ring_entry; 55077e2ea2e9SAnilkumar Kolli u32 rx_bufs_used = 0, mpdu_rx_bufs_used; 55087e2ea2e9SAnilkumar Kolli int quota = 0, ret; 55097e2ea2e9SAnilkumar Kolli bool break_dst_ring = false; 55107e2ea2e9SAnilkumar Kolli 55117e2ea2e9SAnilkumar Kolli spin_lock_bh(&pmon->mon_lock); 55127e2ea2e9SAnilkumar Kolli 55137e2ea2e9SAnilkumar Kolli sw_mon_entries = &pmon->sw_mon_entries; 55147e2ea2e9SAnilkumar Kolli rx_mon_stats = &pmon->rx_mon_stats; 55157e2ea2e9SAnilkumar Kolli 55167e2ea2e9SAnilkumar Kolli if (pmon->hold_mon_dst_ring) { 55177e2ea2e9SAnilkumar Kolli spin_unlock_bh(&pmon->mon_lock); 55187e2ea2e9SAnilkumar Kolli goto reap_status_ring; 55197e2ea2e9SAnilkumar Kolli } 55207e2ea2e9SAnilkumar Kolli 55217e2ea2e9SAnilkumar Kolli ath11k_hal_srng_access_begin(ar->ab, mon_dst_srng); 55227e2ea2e9SAnilkumar Kolli while ((ring_entry = ath11k_hal_srng_dst_peek(ar->ab, mon_dst_srng))) { 55237e2ea2e9SAnilkumar Kolli head_msdu = NULL; 55247e2ea2e9SAnilkumar Kolli tail_msdu = NULL; 55257e2ea2e9SAnilkumar Kolli 55267e2ea2e9SAnilkumar Kolli mpdu_rx_bufs_used = ath11k_dp_rx_full_mon_mpdu_pop(ar, ring_entry, 55277e2ea2e9SAnilkumar Kolli &head_msdu, 55287e2ea2e9SAnilkumar Kolli &tail_msdu, 55297e2ea2e9SAnilkumar Kolli sw_mon_entries); 55307e2ea2e9SAnilkumar Kolli rx_bufs_used += mpdu_rx_bufs_used; 55317e2ea2e9SAnilkumar Kolli 55327e2ea2e9SAnilkumar Kolli if (!sw_mon_entries->end_of_ppdu) { 55337e2ea2e9SAnilkumar Kolli if (head_msdu) { 55347e2ea2e9SAnilkumar Kolli ret = ath11k_dp_rx_full_mon_prepare_mpdu(&ab->dp, 55357e2ea2e9SAnilkumar Kolli pmon->mon_mpdu, 55367e2ea2e9SAnilkumar Kolli head_msdu, 55377e2ea2e9SAnilkumar Kolli tail_msdu); 55387e2ea2e9SAnilkumar Kolli if (ret) 55397e2ea2e9SAnilkumar Kolli break_dst_ring = true; 55407e2ea2e9SAnilkumar Kolli } 55417e2ea2e9SAnilkumar Kolli 55427e2ea2e9SAnilkumar Kolli goto next_entry; 55437e2ea2e9SAnilkumar Kolli } else { 55447e2ea2e9SAnilkumar Kolli if (!sw_mon_entries->ppdu_id && 55457e2ea2e9SAnilkumar Kolli !sw_mon_entries->mon_status_paddr) { 55467e2ea2e9SAnilkumar Kolli break_dst_ring = true; 55477e2ea2e9SAnilkumar Kolli goto next_entry; 55487e2ea2e9SAnilkumar Kolli } 55497e2ea2e9SAnilkumar Kolli } 55507e2ea2e9SAnilkumar Kolli 55517e2ea2e9SAnilkumar Kolli rx_mon_stats->dest_ppdu_done++; 55527e2ea2e9SAnilkumar Kolli pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 55537e2ea2e9SAnilkumar Kolli pmon->buf_state = DP_MON_STATUS_LAG; 55547e2ea2e9SAnilkumar Kolli pmon->mon_status_paddr = sw_mon_entries->mon_status_paddr; 55557e2ea2e9SAnilkumar Kolli pmon->hold_mon_dst_ring = true; 55567e2ea2e9SAnilkumar Kolli next_entry: 55577e2ea2e9SAnilkumar Kolli ring_entry = ath11k_hal_srng_dst_get_next_entry(ar->ab, 55587e2ea2e9SAnilkumar Kolli mon_dst_srng); 55597e2ea2e9SAnilkumar Kolli if (break_dst_ring) 55607e2ea2e9SAnilkumar Kolli break; 55617e2ea2e9SAnilkumar Kolli } 55627e2ea2e9SAnilkumar Kolli 55637e2ea2e9SAnilkumar Kolli ath11k_hal_srng_access_end(ar->ab, mon_dst_srng); 55647e2ea2e9SAnilkumar Kolli spin_unlock_bh(&pmon->mon_lock); 55657e2ea2e9SAnilkumar Kolli 55667e2ea2e9SAnilkumar Kolli if (rx_bufs_used) { 55677e2ea2e9SAnilkumar Kolli ath11k_dp_rxbufs_replenish(ar->ab, dp->mac_id, 55687e2ea2e9SAnilkumar Kolli &dp->rxdma_mon_buf_ring, 55697e2ea2e9SAnilkumar Kolli rx_bufs_used, 55707e2ea2e9SAnilkumar Kolli HAL_RX_BUF_RBM_SW3_BM); 55717e2ea2e9SAnilkumar Kolli } 55727e2ea2e9SAnilkumar Kolli 55737e2ea2e9SAnilkumar Kolli reap_status_ring: 55747e2ea2e9SAnilkumar Kolli quota = ath11k_dp_rx_process_full_mon_status_ring(ab, mac_id, 55757e2ea2e9SAnilkumar Kolli napi, budget); 55767e2ea2e9SAnilkumar Kolli 55777e2ea2e9SAnilkumar Kolli return quota; 55787e2ea2e9SAnilkumar Kolli } 55797e2ea2e9SAnilkumar Kolli 5580d5c65159SKalle Valo int ath11k_dp_rx_process_mon_rings(struct ath11k_base *ab, int mac_id, 5581d5c65159SKalle Valo struct napi_struct *napi, int budget) 5582d5c65159SKalle Valo { 55834152e420SCarl Huang struct ath11k *ar = ath11k_ab_to_ar(ab, mac_id); 5584d5c65159SKalle Valo int ret = 0; 5585d5c65159SKalle Valo 55867e2ea2e9SAnilkumar Kolli if (test_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags) && 55877e2ea2e9SAnilkumar Kolli ab->hw_params.full_monitor_mode) 55887e2ea2e9SAnilkumar Kolli ret = ath11k_dp_full_mon_process_rx(ab, mac_id, napi, budget); 5589d5c65159SKalle Valo else 5590d5c65159SKalle Valo ret = ath11k_dp_rx_process_mon_status(ab, mac_id, napi, budget); 55917e2ea2e9SAnilkumar Kolli 5592d5c65159SKalle Valo return ret; 5593d5c65159SKalle Valo } 5594d5c65159SKalle Valo 5595d5c65159SKalle Valo static int ath11k_dp_rx_pdev_mon_status_attach(struct ath11k *ar) 5596d5c65159SKalle Valo { 5597d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5598d5c65159SKalle Valo struct ath11k_mon_data *pmon = (struct ath11k_mon_data *)&dp->mon_data; 5599d5c65159SKalle Valo 5600d5c65159SKalle Valo skb_queue_head_init(&pmon->rx_status_q); 5601d5c65159SKalle Valo 5602d5c65159SKalle Valo pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 5603d5c65159SKalle Valo 5604d5c65159SKalle Valo memset(&pmon->rx_mon_stats, 0, 5605d5c65159SKalle Valo sizeof(pmon->rx_mon_stats)); 5606d5c65159SKalle Valo return 0; 5607d5c65159SKalle Valo } 5608d5c65159SKalle Valo 5609d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_attach(struct ath11k *ar) 5610d5c65159SKalle Valo { 5611d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5612d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 5613d5c65159SKalle Valo struct hal_srng *mon_desc_srng = NULL; 5614d5c65159SKalle Valo struct dp_srng *dp_srng; 5615d5c65159SKalle Valo int ret = 0; 5616d5c65159SKalle Valo u32 n_link_desc = 0; 5617d5c65159SKalle Valo 5618d5c65159SKalle Valo ret = ath11k_dp_rx_pdev_mon_status_attach(ar); 5619d5c65159SKalle Valo if (ret) { 5620d5c65159SKalle Valo ath11k_warn(ar->ab, "pdev_mon_status_attach() failed"); 5621d5c65159SKalle Valo return ret; 5622d5c65159SKalle Valo } 5623d5c65159SKalle Valo 56247f6fc1ebSCarl Huang /* if rxdma1_enable is false, no need to setup 56257f6fc1ebSCarl Huang * rxdma_mon_desc_ring. 56267f6fc1ebSCarl Huang */ 56277f6fc1ebSCarl Huang if (!ar->ab->hw_params.rxdma1_enable) 56287f6fc1ebSCarl Huang return 0; 56297f6fc1ebSCarl Huang 5630d5c65159SKalle Valo dp_srng = &dp->rxdma_mon_desc_ring; 5631d5c65159SKalle Valo n_link_desc = dp_srng->size / 5632f7eb4b04SKalle Valo ath11k_hal_srng_get_entrysize(ar->ab, HAL_RXDMA_MONITOR_DESC); 5633d5c65159SKalle Valo mon_desc_srng = 5634d5c65159SKalle Valo &ar->ab->hal.srng_list[dp->rxdma_mon_desc_ring.ring_id]; 5635d5c65159SKalle Valo 5636d5c65159SKalle Valo ret = ath11k_dp_link_desc_setup(ar->ab, pmon->link_desc_banks, 5637d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, mon_desc_srng, 5638d5c65159SKalle Valo n_link_desc); 5639d5c65159SKalle Valo if (ret) { 5640d5c65159SKalle Valo ath11k_warn(ar->ab, "mon_link_desc_pool_setup() failed"); 5641d5c65159SKalle Valo return ret; 5642d5c65159SKalle Valo } 5643d5c65159SKalle Valo pmon->mon_last_linkdesc_paddr = 0; 5644d5c65159SKalle Valo pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 5645d5c65159SKalle Valo spin_lock_init(&pmon->mon_lock); 56467f6fc1ebSCarl Huang 5647d5c65159SKalle Valo return 0; 5648d5c65159SKalle Valo } 5649d5c65159SKalle Valo 5650d5c65159SKalle Valo static int ath11k_dp_mon_link_free(struct ath11k *ar) 5651d5c65159SKalle Valo { 5652d5c65159SKalle Valo struct ath11k_pdev_dp *dp = &ar->dp; 5653d5c65159SKalle Valo struct ath11k_mon_data *pmon = &dp->mon_data; 5654d5c65159SKalle Valo 5655d5c65159SKalle Valo ath11k_dp_link_desc_cleanup(ar->ab, pmon->link_desc_banks, 5656d5c65159SKalle Valo HAL_RXDMA_MONITOR_DESC, 5657d5c65159SKalle Valo &dp->rxdma_mon_desc_ring); 5658d5c65159SKalle Valo return 0; 5659d5c65159SKalle Valo } 5660d5c65159SKalle Valo 5661d5c65159SKalle Valo int ath11k_dp_rx_pdev_mon_detach(struct ath11k *ar) 5662d5c65159SKalle Valo { 5663d5c65159SKalle Valo ath11k_dp_mon_link_free(ar); 5664d5c65159SKalle Valo return 0; 5665d5c65159SKalle Valo } 5666840c36faSCarl Huang 5667840c36faSCarl Huang int ath11k_dp_rx_pktlog_start(struct ath11k_base *ab) 5668840c36faSCarl Huang { 5669840c36faSCarl Huang /* start reap timer */ 5670840c36faSCarl Huang mod_timer(&ab->mon_reap_timer, 5671840c36faSCarl Huang jiffies + msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL)); 5672840c36faSCarl Huang 5673840c36faSCarl Huang return 0; 5674840c36faSCarl Huang } 5675840c36faSCarl Huang 5676840c36faSCarl Huang int ath11k_dp_rx_pktlog_stop(struct ath11k_base *ab, bool stop_timer) 5677840c36faSCarl Huang { 5678840c36faSCarl Huang int ret; 5679840c36faSCarl Huang 5680840c36faSCarl Huang if (stop_timer) 5681840c36faSCarl Huang del_timer_sync(&ab->mon_reap_timer); 5682840c36faSCarl Huang 5683840c36faSCarl Huang /* reap all the monitor related rings */ 5684840c36faSCarl Huang ret = ath11k_dp_purge_mon_ring(ab); 5685840c36faSCarl Huang if (ret) { 5686840c36faSCarl Huang ath11k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 5687840c36faSCarl Huang return ret; 5688840c36faSCarl Huang } 5689840c36faSCarl Huang 5690840c36faSCarl Huang return 0; 5691840c36faSCarl Huang } 5692