1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 #define MAX_RXDMA_PER_PDEV 2 12 13 struct ath11k_base; 14 struct ath11k_peer; 15 struct ath11k_dp; 16 struct ath11k_vif; 17 struct hal_tcl_status_ring; 18 struct ath11k_ext_irq_grp; 19 20 struct dp_rx_tid { 21 u8 tid; 22 u32 *vaddr; 23 dma_addr_t paddr; 24 u32 size; 25 u32 ba_win_sz; 26 bool active; 27 28 /* Info related to rx fragments */ 29 u32 cur_sn; 30 u16 last_frag_no; 31 u16 rx_frag_bitmap; 32 33 struct sk_buff_head rx_frags; 34 struct hal_reo_dest_ring *dst_ring_desc; 35 36 /* Timer info related to fragments */ 37 struct timer_list frag_timer; 38 struct ath11k_base *ab; 39 }; 40 41 #define DP_REO_DESC_FREE_THRESHOLD 64 42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 43 #define DP_MON_PURGE_TIMEOUT_MS 100 44 #define DP_MON_SERVICE_BUDGET 128 45 46 struct dp_reo_cache_flush_elem { 47 struct list_head list; 48 struct dp_rx_tid data; 49 unsigned long ts; 50 }; 51 52 struct dp_reo_cmd { 53 struct list_head list; 54 struct dp_rx_tid data; 55 int cmd_num; 56 void (*handler)(struct ath11k_dp *, void *, 57 enum hal_reo_cmd_status status); 58 }; 59 60 struct dp_srng { 61 u32 *vaddr_unaligned; 62 u32 *vaddr; 63 dma_addr_t paddr_unaligned; 64 dma_addr_t paddr; 65 int size; 66 u32 ring_id; 67 }; 68 69 struct dp_rxdma_ring { 70 struct dp_srng refill_buf_ring; 71 struct idr bufs_idr; 72 /* Protects bufs_idr */ 73 spinlock_t idr_lock; 74 int bufs_max; 75 }; 76 77 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 78 79 struct dp_tx_ring { 80 u8 tcl_data_ring_id; 81 struct dp_srng tcl_data_ring; 82 struct dp_srng tcl_comp_ring; 83 struct idr txbuf_idr; 84 /* Protects txbuf_idr and num_pending */ 85 spinlock_t tx_idr_lock; 86 struct hal_wbm_release_ring *tx_status; 87 int tx_status_head; 88 int tx_status_tail; 89 }; 90 91 struct ath11k_pdev_mon_stats { 92 u32 status_ppdu_state; 93 u32 status_ppdu_start; 94 u32 status_ppdu_end; 95 u32 status_ppdu_compl; 96 u32 status_ppdu_start_mis; 97 u32 status_ppdu_end_mis; 98 u32 status_ppdu_done; 99 u32 dest_ppdu_done; 100 u32 dest_mpdu_done; 101 u32 dest_mpdu_drop; 102 u32 dup_mon_linkdesc_cnt; 103 u32 dup_mon_buf_cnt; 104 }; 105 106 struct dp_link_desc_bank { 107 void *vaddr_unaligned; 108 void *vaddr; 109 dma_addr_t paddr_unaligned; 110 dma_addr_t paddr; 111 u32 size; 112 }; 113 114 /* Size to enforce scatter idle list mode */ 115 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 116 #define DP_LINK_DESC_BANKS_MAX 8 117 118 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 119 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 120 #define DP_RX_DESC_COOKIE_MAX \ 121 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 122 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 123 124 enum ath11k_dp_ppdu_state { 125 DP_PPDU_STATUS_START, 126 DP_PPDU_STATUS_DONE, 127 }; 128 129 struct ath11k_mon_data { 130 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 131 struct hal_rx_mon_ppdu_info mon_ppdu_info; 132 133 u32 mon_ppdu_status; 134 u32 mon_last_buf_cookie; 135 u64 mon_last_linkdesc_paddr; 136 u16 chan_noise_floor; 137 138 struct ath11k_pdev_mon_stats rx_mon_stats; 139 /* lock for monitor data */ 140 spinlock_t mon_lock; 141 struct sk_buff_head rx_status_q; 142 }; 143 144 struct ath11k_pdev_dp { 145 u32 mac_id; 146 atomic_t num_tx_pending; 147 wait_queue_head_t tx_empty_waitq; 148 struct dp_rxdma_ring rx_refill_buf_ring; 149 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 150 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 151 struct dp_srng rxdma_mon_dst_ring; 152 struct dp_srng rxdma_mon_desc_ring; 153 154 struct dp_rxdma_ring rxdma_mon_buf_ring; 155 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 156 struct ieee80211_rx_status rx_status; 157 struct ath11k_mon_data mon_data; 158 }; 159 160 #define DP_NUM_CLIENTS_MAX 64 161 #define DP_AVG_TIDS_PER_CLIENT 2 162 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 163 #define DP_AVG_MSDUS_PER_FLOW 128 164 #define DP_AVG_FLOWS_PER_TID 2 165 #define DP_AVG_MPDUS_PER_TID_MAX 128 166 #define DP_AVG_MSDUS_PER_MPDU 4 167 168 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 169 170 #define DP_BA_WIN_SZ_MAX 256 171 172 #define DP_TCL_NUM_RING_MAX 3 173 #define DP_TCL_NUM_RING_MAX_QCA6390 1 174 175 #define DP_IDLE_SCATTER_BUFS_MAX 16 176 177 #define DP_WBM_RELEASE_RING_SIZE 64 178 #define DP_TCL_DATA_RING_SIZE 512 179 #define DP_TX_COMP_RING_SIZE 32768 180 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 181 #define DP_TCL_CMD_RING_SIZE 32 182 #define DP_TCL_STATUS_RING_SIZE 32 183 #define DP_REO_DST_RING_MAX 4 184 #define DP_REO_DST_RING_SIZE 2048 185 #define DP_REO_REINJECT_RING_SIZE 32 186 #define DP_RX_RELEASE_RING_SIZE 1024 187 #define DP_REO_EXCEPTION_RING_SIZE 128 188 #define DP_REO_CMD_RING_SIZE 128 189 #define DP_REO_STATUS_RING_SIZE 2048 190 #define DP_RXDMA_BUF_RING_SIZE 4096 191 #define DP_RXDMA_REFILL_RING_SIZE 2048 192 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 193 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 194 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 195 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 196 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 197 198 #define DP_RX_BUFFER_SIZE 2048 199 #define DP_RX_BUFFER_SIZE_LITE 1024 200 #define DP_RX_BUFFER_ALIGN_SIZE 128 201 202 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 203 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 204 205 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 206 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 207 208 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 209 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 210 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 211 212 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 213 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 214 215 struct ath11k_hp_update_timer { 216 struct timer_list timer; 217 bool started; 218 bool init; 219 u32 tx_num; 220 u32 timer_tx_num; 221 u32 ring_id; 222 u32 interval; 223 struct ath11k_base *ab; 224 }; 225 226 struct ath11k_dp { 227 struct ath11k_base *ab; 228 enum ath11k_htc_ep_id eid; 229 struct completion htt_tgt_version_received; 230 u8 htt_tgt_ver_major; 231 u8 htt_tgt_ver_minor; 232 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 233 struct dp_srng wbm_idle_ring; 234 struct dp_srng wbm_desc_rel_ring; 235 struct dp_srng tcl_cmd_ring; 236 struct dp_srng tcl_status_ring; 237 struct dp_srng reo_reinject_ring; 238 struct dp_srng rx_rel_ring; 239 struct dp_srng reo_except_ring; 240 struct dp_srng reo_cmd_ring; 241 struct dp_srng reo_status_ring; 242 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 243 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 244 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 245 struct list_head reo_cmd_list; 246 struct list_head reo_cmd_cache_flush_list; 247 u32 reo_cmd_cache_flush_count; 248 /** 249 * protects access to below fields, 250 * - reo_cmd_list 251 * - reo_cmd_cache_flush_list 252 * - reo_cmd_cache_flush_count 253 */ 254 spinlock_t reo_cmd_lock; 255 struct ath11k_hp_update_timer reo_cmd_timer; 256 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 257 }; 258 259 /* HTT definitions */ 260 261 #define HTT_TCL_META_DATA_TYPE BIT(0) 262 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 263 264 /* vdev meta data */ 265 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 266 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 267 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 268 269 /* peer meta data */ 270 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 271 272 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 273 274 /* HTT tx completion is overlayed in wbm_release_ring */ 275 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 276 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 277 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 278 279 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 280 281 struct htt_tx_wbm_completion { 282 u32 info0; 283 u32 info1; 284 u32 info2; 285 u32 info3; 286 } __packed; 287 288 enum htt_h2t_msg_type { 289 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 290 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 291 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 292 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 293 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 294 }; 295 296 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 297 298 struct htt_ver_req_cmd { 299 u32 ver_reg_info; 300 } __packed; 301 302 enum htt_srng_ring_type { 303 HTT_HW_TO_SW_RING, 304 HTT_SW_TO_HW_RING, 305 HTT_SW_TO_SW_RING, 306 }; 307 308 enum htt_srng_ring_id { 309 HTT_RXDMA_HOST_BUF_RING, 310 HTT_RXDMA_MONITOR_STATUS_RING, 311 HTT_RXDMA_MONITOR_BUF_RING, 312 HTT_RXDMA_MONITOR_DESC_RING, 313 HTT_RXDMA_MONITOR_DEST_RING, 314 HTT_HOST1_TO_FW_RXBUF_RING, 315 HTT_HOST2_TO_FW_RXBUF_RING, 316 HTT_RXDMA_NON_MONITOR_DEST_RING, 317 }; 318 319 /* host -> target HTT_SRING_SETUP message 320 * 321 * After target is booted up, Host can send SRING setup message for 322 * each host facing LMAC SRING. Target setups up HW registers based 323 * on setup message and confirms back to Host if response_required is set. 324 * Host should wait for confirmation message before sending new SRING 325 * setup message 326 * 327 * The message would appear as follows: 328 * 329 * |31 24|23 20|19|18 16|15|14 8|7 0| 330 * |--------------- +-----------------+----------------+------------------| 331 * | ring_type | ring_id | pdev_id | msg_type | 332 * |----------------------------------------------------------------------| 333 * | ring_base_addr_lo | 334 * |----------------------------------------------------------------------| 335 * | ring_base_addr_hi | 336 * |----------------------------------------------------------------------| 337 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 338 * |----------------------------------------------------------------------| 339 * | ring_head_offset32_remote_addr_lo | 340 * |----------------------------------------------------------------------| 341 * | ring_head_offset32_remote_addr_hi | 342 * |----------------------------------------------------------------------| 343 * | ring_tail_offset32_remote_addr_lo | 344 * |----------------------------------------------------------------------| 345 * | ring_tail_offset32_remote_addr_hi | 346 * |----------------------------------------------------------------------| 347 * | ring_msi_addr_lo | 348 * |----------------------------------------------------------------------| 349 * | ring_msi_addr_hi | 350 * |----------------------------------------------------------------------| 351 * | ring_msi_data | 352 * |----------------------------------------------------------------------| 353 * | intr_timer_th |IM| intr_batch_counter_th | 354 * |----------------------------------------------------------------------| 355 * | reserved |RR|PTCF| intr_low_threshold | 356 * |----------------------------------------------------------------------| 357 * Where 358 * IM = sw_intr_mode 359 * RR = response_required 360 * PTCF = prefetch_timer_cfg 361 * 362 * The message is interpreted as follows: 363 * dword0 - b'0:7 - msg_type: This will be set to 364 * HTT_H2T_MSG_TYPE_SRING_SETUP 365 * b'8:15 - pdev_id: 366 * 0 (for rings at SOC/UMAC level), 367 * 1/2/3 mac id (for rings at LMAC level) 368 * b'16:23 - ring_id: identify which ring is to setup, 369 * more details can be got from enum htt_srng_ring_id 370 * b'24:31 - ring_type: identify type of host rings, 371 * more details can be got from enum htt_srng_ring_type 372 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 373 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 374 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 375 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 376 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 377 * SW_TO_HW_RING. 378 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 379 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 380 * Lower 32 bits of memory address of the remote variable 381 * storing the 4-byte word offset that identifies the head 382 * element within the ring. 383 * (The head offset variable has type u32.) 384 * Valid for HW_TO_SW and SW_TO_SW rings. 385 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 386 * Upper 32 bits of memory address of the remote variable 387 * storing the 4-byte word offset that identifies the head 388 * element within the ring. 389 * (The head offset variable has type u32.) 390 * Valid for HW_TO_SW and SW_TO_SW rings. 391 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 392 * Lower 32 bits of memory address of the remote variable 393 * storing the 4-byte word offset that identifies the tail 394 * element within the ring. 395 * (The tail offset variable has type u32.) 396 * Valid for HW_TO_SW and SW_TO_SW rings. 397 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 398 * Upper 32 bits of memory address of the remote variable 399 * storing the 4-byte word offset that identifies the tail 400 * element within the ring. 401 * (The tail offset variable has type u32.) 402 * Valid for HW_TO_SW and SW_TO_SW rings. 403 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 404 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 405 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 406 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 407 * dword10 - b'0:31 - ring_msi_data: MSI data 408 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 409 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 410 * dword11 - b'0:14 - intr_batch_counter_th: 411 * batch counter threshold is in units of 4-byte words. 412 * HW internally maintains and increments batch count. 413 * (see SRING spec for detail description). 414 * When batch count reaches threshold value, an interrupt 415 * is generated by HW. 416 * b'15 - sw_intr_mode: 417 * This configuration shall be static. 418 * Only programmed at power up. 419 * 0: generate pulse style sw interrupts 420 * 1: generate level style sw interrupts 421 * b'16:31 - intr_timer_th: 422 * The timer init value when timer is idle or is 423 * initialized to start downcounting. 424 * In 8us units (to cover a range of 0 to 524 ms) 425 * dword12 - b'0:15 - intr_low_threshold: 426 * Used only by Consumer ring to generate ring_sw_int_p. 427 * Ring entries low threshold water mark, that is used 428 * in combination with the interrupt timer as well as 429 * the clearing of the level interrupt. 430 * b'16:18 - prefetch_timer_cfg: 431 * Used only by Consumer ring to set timer mode to 432 * support Application prefetch handling. 433 * The external tail offset/pointer will be updated 434 * at following intervals: 435 * 3'b000: (Prefetch feature disabled; used only for debug) 436 * 3'b001: 1 usec 437 * 3'b010: 4 usec 438 * 3'b011: 8 usec (default) 439 * 3'b100: 16 usec 440 * Others: Reserverd 441 * b'19 - response_required: 442 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 443 * b'20:31 - reserved: reserved for future use 444 */ 445 446 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 447 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 448 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 449 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 450 451 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 452 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 453 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 454 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 455 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 456 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 457 458 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 459 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 460 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 461 462 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 463 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 464 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 465 466 struct htt_srng_setup_cmd { 467 u32 info0; 468 u32 ring_base_addr_lo; 469 u32 ring_base_addr_hi; 470 u32 info1; 471 u32 ring_head_off32_remote_addr_lo; 472 u32 ring_head_off32_remote_addr_hi; 473 u32 ring_tail_off32_remote_addr_lo; 474 u32 ring_tail_off32_remote_addr_hi; 475 u32 ring_msi_addr_lo; 476 u32 ring_msi_addr_hi; 477 u32 msi_data; 478 u32 intr_info; 479 u32 info2; 480 } __packed; 481 482 /* host -> target FW PPDU_STATS config message 483 * 484 * @details 485 * The following field definitions describe the format of the HTT host 486 * to target FW for PPDU_STATS_CFG msg. 487 * The message allows the host to configure the PPDU_STATS_IND messages 488 * produced by the target. 489 * 490 * |31 24|23 16|15 8|7 0| 491 * |-----------------------------------------------------------| 492 * | REQ bit mask | pdev_mask | msg type | 493 * |-----------------------------------------------------------| 494 * Header fields: 495 * - MSG_TYPE 496 * Bits 7:0 497 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 498 * Value: 0x11 499 * - PDEV_MASK 500 * Bits 8:15 501 * Purpose: identifies which pdevs this PPDU stats configuration applies to 502 * Value: This is a overloaded field, refer to usage and interpretation of 503 * PDEV in interface document. 504 * Bit 8 : Reserved for SOC stats 505 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 506 * Indicates MACID_MASK in DBS 507 * - REQ_TLV_BIT_MASK 508 * Bits 16:31 509 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 510 * needs to be included in the target's PPDU_STATS_IND messages. 511 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 512 * 513 */ 514 515 struct htt_ppdu_stats_cfg_cmd { 516 u32 msg; 517 } __packed; 518 519 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 520 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 521 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 522 523 enum htt_ppdu_stats_tag_type { 524 HTT_PPDU_STATS_TAG_COMMON, 525 HTT_PPDU_STATS_TAG_USR_COMMON, 526 HTT_PPDU_STATS_TAG_USR_RATE, 527 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 528 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 529 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 530 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 531 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 532 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 533 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 534 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 535 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 536 HTT_PPDU_STATS_TAG_INFO, 537 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 538 539 /* New TLV's are added above to this line */ 540 HTT_PPDU_STATS_TAG_MAX, 541 }; 542 543 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 544 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 545 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 546 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 547 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 548 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 549 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 550 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 551 552 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 553 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 554 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 555 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 556 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 557 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 558 HTT_PPDU_STATS_TAG_DEFAULT) 559 560 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 561 * 562 * details: 563 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 564 * configure RXDMA rings. 565 * The configuration is per ring based and includes both packet subtypes 566 * and PPDU/MPDU TLVs. 567 * 568 * The message would appear as follows: 569 * 570 * |31 26|25|24|23 16|15 8|7 0| 571 * |-----------------+----------------+----------------+---------------| 572 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 573 * |-------------------------------------------------------------------| 574 * | rsvd2 | ring_buffer_size | 575 * |-------------------------------------------------------------------| 576 * | packet_type_enable_flags_0 | 577 * |-------------------------------------------------------------------| 578 * | packet_type_enable_flags_1 | 579 * |-------------------------------------------------------------------| 580 * | packet_type_enable_flags_2 | 581 * |-------------------------------------------------------------------| 582 * | packet_type_enable_flags_3 | 583 * |-------------------------------------------------------------------| 584 * | tlv_filter_in_flags | 585 * |-------------------------------------------------------------------| 586 * Where: 587 * PS = pkt_swap 588 * SS = status_swap 589 * The message is interpreted as follows: 590 * dword0 - b'0:7 - msg_type: This will be set to 591 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 592 * b'8:15 - pdev_id: 593 * 0 (for rings at SOC/UMAC level), 594 * 1/2/3 mac id (for rings at LMAC level) 595 * b'16:23 - ring_id : Identify the ring to configure. 596 * More details can be got from enum htt_srng_ring_id 597 * b'24 - status_swap: 1 is to swap status TLV 598 * b'25 - pkt_swap: 1 is to swap packet TLV 599 * b'26:31 - rsvd1: reserved for future use 600 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 601 * in byte units. 602 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 603 * - b'16:31 - rsvd2: Reserved for future use 604 * dword2 - b'0:31 - packet_type_enable_flags_0: 605 * Enable MGMT packet from 0b0000 to 0b1001 606 * bits from low to high: FP, MD, MO - 3 bits 607 * FP: Filter_Pass 608 * MD: Monitor_Direct 609 * MO: Monitor_Other 610 * 10 mgmt subtypes * 3 bits -> 30 bits 611 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 612 * dword3 - b'0:31 - packet_type_enable_flags_1: 613 * Enable MGMT packet from 0b1010 to 0b1111 614 * bits from low to high: FP, MD, MO - 3 bits 615 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 616 * dword4 - b'0:31 - packet_type_enable_flags_2: 617 * Enable CTRL packet from 0b0000 to 0b1001 618 * bits from low to high: FP, MD, MO - 3 bits 619 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 620 * dword5 - b'0:31 - packet_type_enable_flags_3: 621 * Enable CTRL packet from 0b1010 to 0b1111, 622 * MCAST_DATA, UCAST_DATA, NULL_DATA 623 * bits from low to high: FP, MD, MO - 3 bits 624 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 625 * dword6 - b'0:31 - tlv_filter_in_flags: 626 * Filter in Attention/MPDU/PPDU/Header/User tlvs 627 * Refer to CFG_TLV_FILTER_IN_FLAG defs 628 */ 629 630 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 631 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 632 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 633 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 634 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 635 636 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 637 638 enum htt_rx_filter_tlv_flags { 639 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 640 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 641 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 642 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 643 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 644 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 645 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 646 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 647 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 648 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 649 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 650 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 651 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 652 }; 653 654 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 655 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 656 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 657 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 658 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 659 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 660 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 661 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 662 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 663 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 664 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 665 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 666 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 667 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 668 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 669 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 670 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 671 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 672 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 673 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 674 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 675 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 676 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 677 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 678 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 679 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 680 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 681 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 682 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 683 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 684 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 685 }; 686 687 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 688 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 689 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 690 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 691 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 692 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 693 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 694 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 695 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 696 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 697 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 698 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 699 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 700 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 701 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 702 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 703 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 704 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 705 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 706 }; 707 708 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 709 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 710 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 711 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 712 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 713 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 714 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 715 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 716 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 717 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 718 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 719 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 720 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 721 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 722 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 723 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 724 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 725 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 726 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 727 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 728 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 729 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 730 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 731 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 732 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 733 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 734 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 735 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 736 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 737 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 738 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 739 }; 740 741 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 742 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 743 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 744 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 745 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 746 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 747 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 748 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 749 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 750 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 751 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 752 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 753 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 754 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 755 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 756 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 757 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 758 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 759 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 760 }; 761 762 enum htt_rx_data_pkt_filter_tlv_flasg3 { 763 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 764 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 765 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 766 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 767 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 768 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 769 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 770 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 771 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 772 }; 773 774 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 775 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 776 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 777 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 781 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 782 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 783 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 784 785 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 786 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 787 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 788 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 789 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 790 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 791 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 792 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 793 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 794 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 795 796 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 797 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 798 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 799 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 800 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 801 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 802 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 803 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 804 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 805 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 806 807 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 808 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 809 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 810 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 811 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 812 813 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 814 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 815 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 816 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 817 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 818 819 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 820 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 821 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 822 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 823 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 824 825 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 826 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 827 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 828 829 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 830 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 831 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 832 833 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 834 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 835 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 836 837 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 838 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 839 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 840 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 841 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 842 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 843 844 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 845 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 846 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 847 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 848 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 849 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 850 851 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 852 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 853 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 854 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 855 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 856 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 857 858 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 859 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 860 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 861 862 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 863 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 864 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 865 866 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 867 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 868 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 869 870 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 871 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 872 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 873 874 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 875 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 876 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 877 878 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 879 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 880 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 881 882 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 883 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 884 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 885 886 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 887 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 889 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 892 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 893 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 894 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 895 896 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 897 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 899 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 900 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 902 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 903 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 904 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 905 906 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 907 908 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 909 910 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 911 912 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 913 914 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 915 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 916 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 917 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 918 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 919 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 920 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 921 922 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 923 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 924 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 925 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 926 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 927 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 928 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 929 930 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 931 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 932 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 933 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 934 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 935 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 936 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 937 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 938 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 939 940 struct htt_rx_ring_selection_cfg_cmd { 941 u32 info0; 942 u32 info1; 943 u32 pkt_type_en_flags0; 944 u32 pkt_type_en_flags1; 945 u32 pkt_type_en_flags2; 946 u32 pkt_type_en_flags3; 947 u32 rx_filter_tlv; 948 } __packed; 949 950 struct htt_rx_ring_tlv_filter { 951 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 952 u32 pkt_filter_flags0; /* MGMT */ 953 u32 pkt_filter_flags1; /* MGMT */ 954 u32 pkt_filter_flags2; /* CTRL */ 955 u32 pkt_filter_flags3; /* DATA */ 956 }; 957 958 /* HTT message target->host */ 959 960 enum htt_t2h_msg_type { 961 HTT_T2H_MSG_TYPE_VERSION_CONF, 962 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 963 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 964 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 965 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 966 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 967 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 968 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 969 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 970 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 971 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 972 }; 973 974 #define HTT_TARGET_VERSION_MAJOR 3 975 976 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 977 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 978 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 979 980 struct htt_t2h_version_conf_msg { 981 u32 version; 982 } __packed; 983 984 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 985 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 986 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 987 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 988 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 989 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 990 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 991 992 struct htt_t2h_peer_map_event { 993 u32 info; 994 u32 mac_addr_l32; 995 u32 info1; 996 u32 info2; 997 } __packed; 998 999 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1000 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1001 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1002 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1003 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1004 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1005 1006 struct htt_t2h_peer_unmap_event { 1007 u32 info; 1008 u32 mac_addr_l32; 1009 u32 info1; 1010 } __packed; 1011 1012 struct htt_resp_msg { 1013 union { 1014 struct htt_t2h_version_conf_msg version_msg; 1015 struct htt_t2h_peer_map_event peer_map_ev; 1016 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1017 }; 1018 } __packed; 1019 1020 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1021 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1022 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1023 1024 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1025 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1026 1027 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1028 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1029 1030 enum htt_backpressure_umac_ringid { 1031 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1032 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1033 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1034 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1035 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1036 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1037 HTT_SW_RING_IDX_REO_REO2FW_RING, 1038 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1039 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1040 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1041 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1042 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1043 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1044 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1045 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1046 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1047 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1048 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1049 HTT_SW_UMAC_RING_IDX_MAX, 1050 }; 1051 1052 enum htt_backpressure_lmac_ringid { 1053 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1054 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1055 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1056 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1057 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1058 HTT_SW_RING_IDX_RXDMA2FW_RING, 1059 HTT_SW_RING_IDX_RXDMA2SW_RING, 1060 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1061 HTT_SW_RING_IDX_RXDMA2REO_RING, 1062 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1063 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1064 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1065 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1066 HTT_SW_LMAC_RING_IDX_MAX, 1067 }; 1068 1069 /* ppdu stats 1070 * 1071 * @details 1072 * The following field definitions describe the format of the HTT target 1073 * to host ppdu stats indication message. 1074 * 1075 * 1076 * |31 16|15 12|11 10|9 8|7 0 | 1077 * |----------------------------------------------------------------------| 1078 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1079 * |----------------------------------------------------------------------| 1080 * | ppdu_id | 1081 * |----------------------------------------------------------------------| 1082 * | Timestamp in us | 1083 * |----------------------------------------------------------------------| 1084 * | reserved | 1085 * |----------------------------------------------------------------------| 1086 * | type-specific stats info | 1087 * | (see htt_ppdu_stats.h) | 1088 * |----------------------------------------------------------------------| 1089 * Header fields: 1090 * - MSG_TYPE 1091 * Bits 7:0 1092 * Purpose: Identifies this is a PPDU STATS indication 1093 * message. 1094 * Value: 0x1d 1095 * - mac_id 1096 * Bits 9:8 1097 * Purpose: mac_id of this ppdu_id 1098 * Value: 0-3 1099 * - pdev_id 1100 * Bits 11:10 1101 * Purpose: pdev_id of this ppdu_id 1102 * Value: 0-3 1103 * 0 (for rings at SOC level), 1104 * 1/2/3 PDEV -> 0/1/2 1105 * - payload_size 1106 * Bits 31:16 1107 * Purpose: total tlv size 1108 * Value: payload_size in bytes 1109 */ 1110 1111 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1112 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1113 1114 struct ath11k_htt_ppdu_stats_msg { 1115 u32 info; 1116 u32 ppdu_id; 1117 u32 timestamp; 1118 u32 rsvd; 1119 u8 data[0]; 1120 } __packed; 1121 1122 struct htt_tlv { 1123 u32 header; 1124 u8 value[0]; 1125 } __packed; 1126 1127 #define HTT_TLV_TAG GENMASK(11, 0) 1128 #define HTT_TLV_LEN GENMASK(23, 12) 1129 1130 enum HTT_PPDU_STATS_BW { 1131 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1132 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1133 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1134 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1135 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1136 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1137 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1138 }; 1139 1140 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1141 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1142 /* bw - HTT_PPDU_STATS_BW */ 1143 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1144 1145 struct htt_ppdu_stats_common { 1146 u32 ppdu_id; 1147 u16 sched_cmdid; 1148 u8 ring_id; 1149 u8 num_users; 1150 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1151 u32 chain_mask; 1152 u32 fes_duration_us; /* frame exchange sequence */ 1153 u32 ppdu_sch_eval_start_tstmp_us; 1154 u32 ppdu_sch_end_tstmp_us; 1155 u32 ppdu_start_tstmp_us; 1156 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1157 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1158 */ 1159 u16 phy_mode; 1160 u16 bw_mhz; 1161 } __packed; 1162 1163 enum htt_ppdu_stats_gi { 1164 HTT_PPDU_STATS_SGI_0_8_US, 1165 HTT_PPDU_STATS_SGI_0_4_US, 1166 HTT_PPDU_STATS_SGI_1_6_US, 1167 HTT_PPDU_STATS_SGI_3_2_US, 1168 }; 1169 1170 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1171 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1172 1173 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1174 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1175 1176 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1177 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1178 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1179 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1180 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1181 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1182 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1183 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1184 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1185 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1186 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1187 1188 #define HTT_USR_RATE_PREAMBLE(_val) \ 1189 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1190 #define HTT_USR_RATE_BW(_val) \ 1191 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1192 #define HTT_USR_RATE_NSS(_val) \ 1193 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1194 #define HTT_USR_RATE_MCS(_val) \ 1195 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1196 #define HTT_USR_RATE_GI(_val) \ 1197 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1198 #define HTT_USR_RATE_DCM(_val) \ 1199 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1200 1201 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1202 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1203 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1204 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1205 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1206 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1207 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1208 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1209 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1210 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1211 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1212 1213 struct htt_ppdu_stats_user_rate { 1214 u8 tid_num; 1215 u8 reserved0; 1216 u16 sw_peer_id; 1217 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1218 u16 ru_end; 1219 u16 ru_start; 1220 u16 resp_ru_end; 1221 u16 resp_ru_start; 1222 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1223 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1224 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1225 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1226 } __packed; 1227 1228 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1229 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1230 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1231 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1232 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1233 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1234 1235 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1236 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1237 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1238 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1239 #define HTT_TX_INFO_RATECODE(_flags) \ 1240 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1241 #define HTT_TX_INFO_PEERID(_flags) \ 1242 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1243 1244 struct htt_tx_ppdu_stats_info { 1245 struct htt_tlv tlv_hdr; 1246 u32 tx_success_bytes; 1247 u32 tx_retry_bytes; 1248 u32 tx_failed_bytes; 1249 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1250 u16 tx_success_msdus; 1251 u16 tx_retry_msdus; 1252 u16 tx_failed_msdus; 1253 u16 tx_duration; /* united in us */ 1254 } __packed; 1255 1256 enum htt_ppdu_stats_usr_compln_status { 1257 HTT_PPDU_STATS_USER_STATUS_OK, 1258 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1259 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1260 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1261 HTT_PPDU_STATS_USER_STATUS_ABORT, 1262 }; 1263 1264 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1265 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1266 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1267 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1268 1269 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1270 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1271 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1272 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1273 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1274 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1275 1276 struct htt_ppdu_stats_usr_cmpltn_cmn { 1277 u8 status; 1278 u8 tid_num; 1279 u16 sw_peer_id; 1280 /* RSSI value of last ack packet (units = dB above noise floor) */ 1281 u32 ack_rssi; 1282 u16 mpdu_tried; 1283 u16 mpdu_success; 1284 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1285 } __packed; 1286 1287 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1288 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1289 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1290 1291 #define HTT_PPDU_STATS_NON_QOS_TID 16 1292 1293 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1294 u32 ppdu_id; 1295 u16 sw_peer_id; 1296 u16 reserved0; 1297 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1298 u16 current_seq; 1299 u16 start_seq; 1300 u32 success_bytes; 1301 } __packed; 1302 1303 struct htt_ppdu_stats_usr_cmn_array { 1304 struct htt_tlv tlv_hdr; 1305 u32 num_ppdu_stats; 1306 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1307 * elements. 1308 * tx_ppdu_stats_info is variable length, with length = 1309 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1310 */ 1311 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1312 } __packed; 1313 1314 struct htt_ppdu_user_stats { 1315 u16 peer_id; 1316 u32 tlv_flags; 1317 bool is_valid_peer_id; 1318 struct htt_ppdu_stats_user_rate rate; 1319 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1320 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1321 }; 1322 1323 #define HTT_PPDU_STATS_MAX_USERS 8 1324 #define HTT_PPDU_DESC_MAX_DEPTH 16 1325 1326 struct htt_ppdu_stats { 1327 struct htt_ppdu_stats_common common; 1328 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1329 }; 1330 1331 struct htt_ppdu_stats_info { 1332 u32 ppdu_id; 1333 struct htt_ppdu_stats ppdu_stats; 1334 struct list_head list; 1335 }; 1336 1337 /** 1338 * @brief target -> host packet log message 1339 * 1340 * @details 1341 * The following field definitions describe the format of the packet log 1342 * message sent from the target to the host. 1343 * The message consists of a 4-octet header,followed by a variable number 1344 * of 32-bit character values. 1345 * 1346 * |31 16|15 12|11 10|9 8|7 0| 1347 * |------------------------------------------------------------------| 1348 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1349 * |------------------------------------------------------------------| 1350 * | payload | 1351 * |------------------------------------------------------------------| 1352 * - MSG_TYPE 1353 * Bits 7:0 1354 * Purpose: identifies this as a pktlog message 1355 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1356 * - mac_id 1357 * Bits 9:8 1358 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1359 * Value: 0-3 1360 * - pdev_id 1361 * Bits 11:10 1362 * Purpose: pdev_id 1363 * Value: 0-3 1364 * 0 (for rings at SOC level), 1365 * 1/2/3 PDEV -> 0/1/2 1366 * - payload_size 1367 * Bits 31:16 1368 * Purpose: explicitly specify the payload size 1369 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1370 */ 1371 struct htt_pktlog_msg { 1372 u32 hdr; 1373 u8 payload[0]; 1374 }; 1375 1376 /** 1377 * @brief host -> target FW extended statistics retrieve 1378 * 1379 * @details 1380 * The following field definitions describe the format of the HTT host 1381 * to target FW extended stats retrieve message. 1382 * The message specifies the type of stats the host wants to retrieve. 1383 * 1384 * |31 24|23 16|15 8|7 0| 1385 * |-----------------------------------------------------------| 1386 * | reserved | stats type | pdev_mask | msg type | 1387 * |-----------------------------------------------------------| 1388 * | config param [0] | 1389 * |-----------------------------------------------------------| 1390 * | config param [1] | 1391 * |-----------------------------------------------------------| 1392 * | config param [2] | 1393 * |-----------------------------------------------------------| 1394 * | config param [3] | 1395 * |-----------------------------------------------------------| 1396 * | reserved | 1397 * |-----------------------------------------------------------| 1398 * | cookie LSBs | 1399 * |-----------------------------------------------------------| 1400 * | cookie MSBs | 1401 * |-----------------------------------------------------------| 1402 * Header fields: 1403 * - MSG_TYPE 1404 * Bits 7:0 1405 * Purpose: identifies this is a extended stats upload request message 1406 * Value: 0x10 1407 * - PDEV_MASK 1408 * Bits 8:15 1409 * Purpose: identifies the mask of PDEVs to retrieve stats from 1410 * Value: This is a overloaded field, refer to usage and interpretation of 1411 * PDEV in interface document. 1412 * Bit 8 : Reserved for SOC stats 1413 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1414 * Indicates MACID_MASK in DBS 1415 * - STATS_TYPE 1416 * Bits 23:16 1417 * Purpose: identifies which FW statistics to upload 1418 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1419 * - Reserved 1420 * Bits 31:24 1421 * - CONFIG_PARAM [0] 1422 * Bits 31:0 1423 * Purpose: give an opaque configuration value to the specified stats type 1424 * Value: stats-type specific configuration value 1425 * Refer to htt_stats.h for interpretation for each stats sub_type 1426 * - CONFIG_PARAM [1] 1427 * Bits 31:0 1428 * Purpose: give an opaque configuration value to the specified stats type 1429 * Value: stats-type specific configuration value 1430 * Refer to htt_stats.h for interpretation for each stats sub_type 1431 * - CONFIG_PARAM [2] 1432 * Bits 31:0 1433 * Purpose: give an opaque configuration value to the specified stats type 1434 * Value: stats-type specific configuration value 1435 * Refer to htt_stats.h for interpretation for each stats sub_type 1436 * - CONFIG_PARAM [3] 1437 * Bits 31:0 1438 * Purpose: give an opaque configuration value to the specified stats type 1439 * Value: stats-type specific configuration value 1440 * Refer to htt_stats.h for interpretation for each stats sub_type 1441 * - Reserved [31:0] for future use. 1442 * - COOKIE_LSBS 1443 * Bits 31:0 1444 * Purpose: Provide a mechanism to match a target->host stats confirmation 1445 * message with its preceding host->target stats request message. 1446 * Value: LSBs of the opaque cookie specified by the host-side requestor 1447 * - COOKIE_MSBS 1448 * Bits 31:0 1449 * Purpose: Provide a mechanism to match a target->host stats confirmation 1450 * message with its preceding host->target stats request message. 1451 * Value: MSBs of the opaque cookie specified by the host-side requestor 1452 */ 1453 1454 struct htt_ext_stats_cfg_hdr { 1455 u8 msg_type; 1456 u8 pdev_mask; 1457 u8 stats_type; 1458 u8 reserved; 1459 } __packed; 1460 1461 struct htt_ext_stats_cfg_cmd { 1462 struct htt_ext_stats_cfg_hdr hdr; 1463 u32 cfg_param0; 1464 u32 cfg_param1; 1465 u32 cfg_param2; 1466 u32 cfg_param3; 1467 u32 reserved; 1468 u32 cookie_lsb; 1469 u32 cookie_msb; 1470 } __packed; 1471 1472 /* htt stats config default params */ 1473 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1474 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1475 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1476 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1477 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1478 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1479 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1480 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1481 1482 /* HTT_DBG_EXT_STATS_PEER_INFO 1483 * PARAMS: 1484 * @config_param0: 1485 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1486 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1487 * [Bit31 : Bit16] sw_peer_id 1488 * @config_param1: 1489 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1490 * 0 bit htt_peer_stats_cmn_tlv 1491 * 1 bit htt_peer_details_tlv 1492 * 2 bit htt_tx_peer_rate_stats_tlv 1493 * 3 bit htt_rx_peer_rate_stats_tlv 1494 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1495 * 5 bit htt_rx_tid_stats_tlv 1496 * 6 bit htt_msdu_flow_stats_tlv 1497 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1498 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1499 * [Bit31 : Bit16] reserved 1500 */ 1501 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1502 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1503 1504 /* Used to set different configs to the specified stats type.*/ 1505 struct htt_ext_stats_cfg_params { 1506 u32 cfg0; 1507 u32 cfg1; 1508 u32 cfg2; 1509 u32 cfg3; 1510 }; 1511 1512 /** 1513 * @brief target -> host extended statistics upload 1514 * 1515 * @details 1516 * The following field definitions describe the format of the HTT target 1517 * to host stats upload confirmation message. 1518 * The message contains a cookie echoed from the HTT host->target stats 1519 * upload request, which identifies which request the confirmation is 1520 * for, and a single stats can span over multiple HTT stats indication 1521 * due to the HTT message size limitation so every HTT ext stats indication 1522 * will have tag-length-value stats information elements. 1523 * The tag-length header for each HTT stats IND message also includes a 1524 * status field, to indicate whether the request for the stat type in 1525 * question was fully met, partially met, unable to be met, or invalid 1526 * (if the stat type in question is disabled in the target). 1527 * A Done bit 1's indicate the end of the of stats info elements. 1528 * 1529 * 1530 * |31 16|15 12|11|10 8|7 5|4 0| 1531 * |--------------------------------------------------------------| 1532 * | reserved | msg type | 1533 * |--------------------------------------------------------------| 1534 * | cookie LSBs | 1535 * |--------------------------------------------------------------| 1536 * | cookie MSBs | 1537 * |--------------------------------------------------------------| 1538 * | stats entry length | rsvd | D| S | stat type | 1539 * |--------------------------------------------------------------| 1540 * | type-specific stats info | 1541 * | (see htt_stats.h) | 1542 * |--------------------------------------------------------------| 1543 * Header fields: 1544 * - MSG_TYPE 1545 * Bits 7:0 1546 * Purpose: Identifies this is a extended statistics upload confirmation 1547 * message. 1548 * Value: 0x1c 1549 * - COOKIE_LSBS 1550 * Bits 31:0 1551 * Purpose: Provide a mechanism to match a target->host stats confirmation 1552 * message with its preceding host->target stats request message. 1553 * Value: LSBs of the opaque cookie specified by the host-side requestor 1554 * - COOKIE_MSBS 1555 * Bits 31:0 1556 * Purpose: Provide a mechanism to match a target->host stats confirmation 1557 * message with its preceding host->target stats request message. 1558 * Value: MSBs of the opaque cookie specified by the host-side requestor 1559 * 1560 * Stats Information Element tag-length header fields: 1561 * - STAT_TYPE 1562 * Bits 7:0 1563 * Purpose: identifies the type of statistics info held in the 1564 * following information element 1565 * Value: htt_dbg_ext_stats_type 1566 * - STATUS 1567 * Bits 10:8 1568 * Purpose: indicate whether the requested stats are present 1569 * Value: htt_dbg_ext_stats_status 1570 * - DONE 1571 * Bits 11 1572 * Purpose: 1573 * Indicates the completion of the stats entry, this will be the last 1574 * stats conf HTT segment for the requested stats type. 1575 * Value: 1576 * 0 -> the stats retrieval is ongoing 1577 * 1 -> the stats retrieval is complete 1578 * - LENGTH 1579 * Bits 31:16 1580 * Purpose: indicate the stats information size 1581 * Value: This field specifies the number of bytes of stats information 1582 * that follows the element tag-length header. 1583 * It is expected but not required that this length is a multiple of 1584 * 4 bytes. 1585 */ 1586 1587 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1588 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1589 1590 struct ath11k_htt_extd_stats_msg { 1591 u32 info0; 1592 u64 cookie; 1593 u32 info1; 1594 u8 data[0]; 1595 } __packed; 1596 1597 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1598 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1599 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1600 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1601 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1602 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1603 1604 struct htt_mac_addr { 1605 u32 mac_addr_l32; 1606 u32 mac_addr_h16; 1607 }; 1608 1609 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1610 { 1611 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1612 addr_l32 = swab32(addr_l32); 1613 addr_h16 = swab16(addr_h16); 1614 } 1615 1616 memcpy(addr, &addr_l32, 4); 1617 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1618 } 1619 1620 int ath11k_dp_service_srng(struct ath11k_base *ab, 1621 struct ath11k_ext_irq_grp *irq_grp, 1622 int budget); 1623 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1624 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1625 void ath11k_dp_free(struct ath11k_base *ab); 1626 int ath11k_dp_alloc(struct ath11k_base *ab); 1627 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1628 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1629 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1630 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1631 int mac_id, enum hal_ring_type ring_type); 1632 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1633 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1634 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1635 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1636 enum hal_ring_type type, int ring_num, 1637 int mac_id, int num_entries); 1638 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1639 struct dp_link_desc_bank *desc_bank, 1640 u32 ring_type, struct dp_srng *ring); 1641 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1642 struct dp_link_desc_bank *link_desc_banks, 1643 u32 ring_type, struct hal_srng *srng, 1644 u32 n_link_desc); 1645 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1646 struct hal_srng *srng, 1647 struct ath11k_hp_update_timer *update_timer); 1648 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1649 struct ath11k_hp_update_timer *update_timer); 1650 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1651 struct ath11k_hp_update_timer *update_timer, 1652 u32 interval, u32 ring_id); 1653 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1654 1655 #endif 1656