1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 #define MAX_RXDMA_PER_PDEV 2 12 13 struct ath11k_base; 14 struct ath11k_peer; 15 struct ath11k_dp; 16 struct ath11k_vif; 17 struct hal_tcl_status_ring; 18 struct ath11k_ext_irq_grp; 19 20 struct dp_rx_tid { 21 u8 tid; 22 u32 *vaddr; 23 dma_addr_t paddr; 24 u32 size; 25 u32 ba_win_sz; 26 bool active; 27 28 /* Info related to rx fragments */ 29 u32 cur_sn; 30 u16 last_frag_no; 31 u16 rx_frag_bitmap; 32 33 struct sk_buff_head rx_frags; 34 struct hal_reo_dest_ring *dst_ring_desc; 35 36 /* Timer info related to fragments */ 37 struct timer_list frag_timer; 38 struct ath11k_base *ab; 39 }; 40 41 #define DP_REO_DESC_FREE_THRESHOLD 64 42 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 43 #define DP_MON_PURGE_TIMEOUT_MS 100 44 #define DP_MON_SERVICE_BUDGET 128 45 46 struct dp_reo_cache_flush_elem { 47 struct list_head list; 48 struct dp_rx_tid data; 49 unsigned long ts; 50 }; 51 52 struct dp_reo_cmd { 53 struct list_head list; 54 struct dp_rx_tid data; 55 int cmd_num; 56 void (*handler)(struct ath11k_dp *, void *, 57 enum hal_reo_cmd_status status); 58 }; 59 60 struct dp_srng { 61 u32 *vaddr_unaligned; 62 u32 *vaddr; 63 dma_addr_t paddr_unaligned; 64 dma_addr_t paddr; 65 int size; 66 u32 ring_id; 67 }; 68 69 struct dp_rxdma_ring { 70 struct dp_srng refill_buf_ring; 71 struct idr bufs_idr; 72 /* Protects bufs_idr */ 73 spinlock_t idr_lock; 74 int bufs_max; 75 }; 76 77 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 78 79 struct dp_tx_ring { 80 u8 tcl_data_ring_id; 81 struct dp_srng tcl_data_ring; 82 struct dp_srng tcl_comp_ring; 83 struct idr txbuf_idr; 84 /* Protects txbuf_idr and num_pending */ 85 spinlock_t tx_idr_lock; 86 struct hal_wbm_release_ring *tx_status; 87 int tx_status_head; 88 int tx_status_tail; 89 }; 90 91 struct ath11k_pdev_mon_stats { 92 u32 status_ppdu_state; 93 u32 status_ppdu_start; 94 u32 status_ppdu_end; 95 u32 status_ppdu_compl; 96 u32 status_ppdu_start_mis; 97 u32 status_ppdu_end_mis; 98 u32 status_ppdu_done; 99 u32 dest_ppdu_done; 100 u32 dest_mpdu_done; 101 u32 dest_mpdu_drop; 102 u32 dup_mon_linkdesc_cnt; 103 u32 dup_mon_buf_cnt; 104 }; 105 106 struct dp_link_desc_bank { 107 void *vaddr_unaligned; 108 void *vaddr; 109 dma_addr_t paddr_unaligned; 110 dma_addr_t paddr; 111 u32 size; 112 }; 113 114 /* Size to enforce scatter idle list mode */ 115 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 116 #define DP_LINK_DESC_BANKS_MAX 8 117 118 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 119 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 120 #define DP_RX_DESC_COOKIE_MAX \ 121 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 122 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 123 124 enum ath11k_dp_ppdu_state { 125 DP_PPDU_STATUS_START, 126 DP_PPDU_STATUS_DONE, 127 }; 128 129 struct ath11k_mon_data { 130 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 131 struct hal_rx_mon_ppdu_info mon_ppdu_info; 132 133 u32 mon_ppdu_status; 134 u32 mon_last_buf_cookie; 135 u64 mon_last_linkdesc_paddr; 136 u16 chan_noise_floor; 137 138 struct ath11k_pdev_mon_stats rx_mon_stats; 139 /* lock for monitor data */ 140 spinlock_t mon_lock; 141 struct sk_buff_head rx_status_q; 142 }; 143 144 struct ath11k_pdev_dp { 145 u32 mac_id; 146 atomic_t num_tx_pending; 147 wait_queue_head_t tx_empty_waitq; 148 struct dp_rxdma_ring rx_refill_buf_ring; 149 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 150 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 151 struct dp_srng rxdma_mon_dst_ring; 152 struct dp_srng rxdma_mon_desc_ring; 153 154 struct dp_rxdma_ring rxdma_mon_buf_ring; 155 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 156 struct ieee80211_rx_status rx_status; 157 struct ath11k_mon_data mon_data; 158 }; 159 160 #define DP_NUM_CLIENTS_MAX 64 161 #define DP_AVG_TIDS_PER_CLIENT 2 162 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 163 #define DP_AVG_MSDUS_PER_FLOW 128 164 #define DP_AVG_FLOWS_PER_TID 2 165 #define DP_AVG_MPDUS_PER_TID_MAX 128 166 #define DP_AVG_MSDUS_PER_MPDU 4 167 168 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 169 170 #define DP_BA_WIN_SZ_MAX 256 171 172 #define DP_TCL_NUM_RING_MAX 3 173 174 #define DP_IDLE_SCATTER_BUFS_MAX 16 175 176 #define DP_WBM_RELEASE_RING_SIZE 64 177 #define DP_TCL_DATA_RING_SIZE 512 178 #define DP_TX_COMP_RING_SIZE 32768 179 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 180 #define DP_TCL_CMD_RING_SIZE 32 181 #define DP_TCL_STATUS_RING_SIZE 32 182 #define DP_REO_DST_RING_MAX 4 183 #define DP_REO_DST_RING_SIZE 2048 184 #define DP_REO_REINJECT_RING_SIZE 32 185 #define DP_RX_RELEASE_RING_SIZE 1024 186 #define DP_REO_EXCEPTION_RING_SIZE 128 187 #define DP_REO_CMD_RING_SIZE 128 188 #define DP_REO_STATUS_RING_SIZE 2048 189 #define DP_RXDMA_BUF_RING_SIZE 4096 190 #define DP_RXDMA_REFILL_RING_SIZE 2048 191 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 192 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 193 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 194 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 195 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 196 197 #define DP_RX_BUFFER_SIZE 2048 198 #define DP_RX_BUFFER_ALIGN_SIZE 128 199 200 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 201 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 202 203 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 204 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 205 206 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 207 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 208 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 209 210 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 211 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 212 213 struct ath11k_hp_update_timer { 214 struct timer_list timer; 215 bool started; 216 bool init; 217 u32 tx_num; 218 u32 timer_tx_num; 219 u32 ring_id; 220 u32 interval; 221 struct ath11k_base *ab; 222 }; 223 224 struct ath11k_dp { 225 struct ath11k_base *ab; 226 enum ath11k_htc_ep_id eid; 227 struct completion htt_tgt_version_received; 228 u8 htt_tgt_ver_major; 229 u8 htt_tgt_ver_minor; 230 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 231 struct dp_srng wbm_idle_ring; 232 struct dp_srng wbm_desc_rel_ring; 233 struct dp_srng tcl_cmd_ring; 234 struct dp_srng tcl_status_ring; 235 struct dp_srng reo_reinject_ring; 236 struct dp_srng rx_rel_ring; 237 struct dp_srng reo_except_ring; 238 struct dp_srng reo_cmd_ring; 239 struct dp_srng reo_status_ring; 240 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 241 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 242 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 243 struct list_head reo_cmd_list; 244 struct list_head reo_cmd_cache_flush_list; 245 u32 reo_cmd_cache_flush_count; 246 /** 247 * protects access to below fields, 248 * - reo_cmd_list 249 * - reo_cmd_cache_flush_list 250 * - reo_cmd_cache_flush_count 251 */ 252 spinlock_t reo_cmd_lock; 253 struct ath11k_hp_update_timer reo_cmd_timer; 254 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 255 }; 256 257 /* HTT definitions */ 258 259 #define HTT_TCL_META_DATA_TYPE BIT(0) 260 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 261 262 /* vdev meta data */ 263 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 264 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 265 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 266 267 /* peer meta data */ 268 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 269 270 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 271 272 /* HTT tx completion is overlayed in wbm_release_ring */ 273 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 274 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 275 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 276 277 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 278 279 struct htt_tx_wbm_completion { 280 u32 info0; 281 u32 info1; 282 u32 info2; 283 u32 info3; 284 } __packed; 285 286 enum htt_h2t_msg_type { 287 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 288 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 289 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 290 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 291 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 292 }; 293 294 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 295 296 struct htt_ver_req_cmd { 297 u32 ver_reg_info; 298 } __packed; 299 300 enum htt_srng_ring_type { 301 HTT_HW_TO_SW_RING, 302 HTT_SW_TO_HW_RING, 303 HTT_SW_TO_SW_RING, 304 }; 305 306 enum htt_srng_ring_id { 307 HTT_RXDMA_HOST_BUF_RING, 308 HTT_RXDMA_MONITOR_STATUS_RING, 309 HTT_RXDMA_MONITOR_BUF_RING, 310 HTT_RXDMA_MONITOR_DESC_RING, 311 HTT_RXDMA_MONITOR_DEST_RING, 312 HTT_HOST1_TO_FW_RXBUF_RING, 313 HTT_HOST2_TO_FW_RXBUF_RING, 314 HTT_RXDMA_NON_MONITOR_DEST_RING, 315 }; 316 317 /* host -> target HTT_SRING_SETUP message 318 * 319 * After target is booted up, Host can send SRING setup message for 320 * each host facing LMAC SRING. Target setups up HW registers based 321 * on setup message and confirms back to Host if response_required is set. 322 * Host should wait for confirmation message before sending new SRING 323 * setup message 324 * 325 * The message would appear as follows: 326 * 327 * |31 24|23 20|19|18 16|15|14 8|7 0| 328 * |--------------- +-----------------+----------------+------------------| 329 * | ring_type | ring_id | pdev_id | msg_type | 330 * |----------------------------------------------------------------------| 331 * | ring_base_addr_lo | 332 * |----------------------------------------------------------------------| 333 * | ring_base_addr_hi | 334 * |----------------------------------------------------------------------| 335 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 336 * |----------------------------------------------------------------------| 337 * | ring_head_offset32_remote_addr_lo | 338 * |----------------------------------------------------------------------| 339 * | ring_head_offset32_remote_addr_hi | 340 * |----------------------------------------------------------------------| 341 * | ring_tail_offset32_remote_addr_lo | 342 * |----------------------------------------------------------------------| 343 * | ring_tail_offset32_remote_addr_hi | 344 * |----------------------------------------------------------------------| 345 * | ring_msi_addr_lo | 346 * |----------------------------------------------------------------------| 347 * | ring_msi_addr_hi | 348 * |----------------------------------------------------------------------| 349 * | ring_msi_data | 350 * |----------------------------------------------------------------------| 351 * | intr_timer_th |IM| intr_batch_counter_th | 352 * |----------------------------------------------------------------------| 353 * | reserved |RR|PTCF| intr_low_threshold | 354 * |----------------------------------------------------------------------| 355 * Where 356 * IM = sw_intr_mode 357 * RR = response_required 358 * PTCF = prefetch_timer_cfg 359 * 360 * The message is interpreted as follows: 361 * dword0 - b'0:7 - msg_type: This will be set to 362 * HTT_H2T_MSG_TYPE_SRING_SETUP 363 * b'8:15 - pdev_id: 364 * 0 (for rings at SOC/UMAC level), 365 * 1/2/3 mac id (for rings at LMAC level) 366 * b'16:23 - ring_id: identify which ring is to setup, 367 * more details can be got from enum htt_srng_ring_id 368 * b'24:31 - ring_type: identify type of host rings, 369 * more details can be got from enum htt_srng_ring_type 370 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 371 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 372 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 373 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 374 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 375 * SW_TO_HW_RING. 376 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 377 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 378 * Lower 32 bits of memory address of the remote variable 379 * storing the 4-byte word offset that identifies the head 380 * element within the ring. 381 * (The head offset variable has type u32.) 382 * Valid for HW_TO_SW and SW_TO_SW rings. 383 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 384 * Upper 32 bits of memory address of the remote variable 385 * storing the 4-byte word offset that identifies the head 386 * element within the ring. 387 * (The head offset variable has type u32.) 388 * Valid for HW_TO_SW and SW_TO_SW rings. 389 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 390 * Lower 32 bits of memory address of the remote variable 391 * storing the 4-byte word offset that identifies the tail 392 * element within the ring. 393 * (The tail offset variable has type u32.) 394 * Valid for HW_TO_SW and SW_TO_SW rings. 395 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 396 * Upper 32 bits of memory address of the remote variable 397 * storing the 4-byte word offset that identifies the tail 398 * element within the ring. 399 * (The tail offset variable has type u32.) 400 * Valid for HW_TO_SW and SW_TO_SW rings. 401 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 402 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 403 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 404 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 405 * dword10 - b'0:31 - ring_msi_data: MSI data 406 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 407 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 408 * dword11 - b'0:14 - intr_batch_counter_th: 409 * batch counter threshold is in units of 4-byte words. 410 * HW internally maintains and increments batch count. 411 * (see SRING spec for detail description). 412 * When batch count reaches threshold value, an interrupt 413 * is generated by HW. 414 * b'15 - sw_intr_mode: 415 * This configuration shall be static. 416 * Only programmed at power up. 417 * 0: generate pulse style sw interrupts 418 * 1: generate level style sw interrupts 419 * b'16:31 - intr_timer_th: 420 * The timer init value when timer is idle or is 421 * initialized to start downcounting. 422 * In 8us units (to cover a range of 0 to 524 ms) 423 * dword12 - b'0:15 - intr_low_threshold: 424 * Used only by Consumer ring to generate ring_sw_int_p. 425 * Ring entries low threshold water mark, that is used 426 * in combination with the interrupt timer as well as 427 * the clearing of the level interrupt. 428 * b'16:18 - prefetch_timer_cfg: 429 * Used only by Consumer ring to set timer mode to 430 * support Application prefetch handling. 431 * The external tail offset/pointer will be updated 432 * at following intervals: 433 * 3'b000: (Prefetch feature disabled; used only for debug) 434 * 3'b001: 1 usec 435 * 3'b010: 4 usec 436 * 3'b011: 8 usec (default) 437 * 3'b100: 16 usec 438 * Others: Reserverd 439 * b'19 - response_required: 440 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 441 * b'20:31 - reserved: reserved for future use 442 */ 443 444 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 445 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 446 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 447 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 448 449 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 450 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 451 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 452 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 453 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 454 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 455 456 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 457 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 458 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 459 460 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 461 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 462 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 463 464 struct htt_srng_setup_cmd { 465 u32 info0; 466 u32 ring_base_addr_lo; 467 u32 ring_base_addr_hi; 468 u32 info1; 469 u32 ring_head_off32_remote_addr_lo; 470 u32 ring_head_off32_remote_addr_hi; 471 u32 ring_tail_off32_remote_addr_lo; 472 u32 ring_tail_off32_remote_addr_hi; 473 u32 ring_msi_addr_lo; 474 u32 ring_msi_addr_hi; 475 u32 msi_data; 476 u32 intr_info; 477 u32 info2; 478 } __packed; 479 480 /* host -> target FW PPDU_STATS config message 481 * 482 * @details 483 * The following field definitions describe the format of the HTT host 484 * to target FW for PPDU_STATS_CFG msg. 485 * The message allows the host to configure the PPDU_STATS_IND messages 486 * produced by the target. 487 * 488 * |31 24|23 16|15 8|7 0| 489 * |-----------------------------------------------------------| 490 * | REQ bit mask | pdev_mask | msg type | 491 * |-----------------------------------------------------------| 492 * Header fields: 493 * - MSG_TYPE 494 * Bits 7:0 495 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 496 * Value: 0x11 497 * - PDEV_MASK 498 * Bits 8:15 499 * Purpose: identifies which pdevs this PPDU stats configuration applies to 500 * Value: This is a overloaded field, refer to usage and interpretation of 501 * PDEV in interface document. 502 * Bit 8 : Reserved for SOC stats 503 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 504 * Indicates MACID_MASK in DBS 505 * - REQ_TLV_BIT_MASK 506 * Bits 16:31 507 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 508 * needs to be included in the target's PPDU_STATS_IND messages. 509 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 510 * 511 */ 512 513 struct htt_ppdu_stats_cfg_cmd { 514 u32 msg; 515 } __packed; 516 517 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 518 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 8) 519 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 520 521 enum htt_ppdu_stats_tag_type { 522 HTT_PPDU_STATS_TAG_COMMON, 523 HTT_PPDU_STATS_TAG_USR_COMMON, 524 HTT_PPDU_STATS_TAG_USR_RATE, 525 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 526 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 527 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 528 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 529 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 530 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 531 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 532 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 533 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 534 HTT_PPDU_STATS_TAG_INFO, 535 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 536 537 /* New TLV's are added above to this line */ 538 HTT_PPDU_STATS_TAG_MAX, 539 }; 540 541 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 542 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 543 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 544 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 545 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 546 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 547 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 548 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 549 550 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 551 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 552 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 553 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 554 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 555 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 556 HTT_PPDU_STATS_TAG_DEFAULT) 557 558 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 559 * 560 * details: 561 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 562 * configure RXDMA rings. 563 * The configuration is per ring based and includes both packet subtypes 564 * and PPDU/MPDU TLVs. 565 * 566 * The message would appear as follows: 567 * 568 * |31 26|25|24|23 16|15 8|7 0| 569 * |-----------------+----------------+----------------+---------------| 570 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 571 * |-------------------------------------------------------------------| 572 * | rsvd2 | ring_buffer_size | 573 * |-------------------------------------------------------------------| 574 * | packet_type_enable_flags_0 | 575 * |-------------------------------------------------------------------| 576 * | packet_type_enable_flags_1 | 577 * |-------------------------------------------------------------------| 578 * | packet_type_enable_flags_2 | 579 * |-------------------------------------------------------------------| 580 * | packet_type_enable_flags_3 | 581 * |-------------------------------------------------------------------| 582 * | tlv_filter_in_flags | 583 * |-------------------------------------------------------------------| 584 * Where: 585 * PS = pkt_swap 586 * SS = status_swap 587 * The message is interpreted as follows: 588 * dword0 - b'0:7 - msg_type: This will be set to 589 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 590 * b'8:15 - pdev_id: 591 * 0 (for rings at SOC/UMAC level), 592 * 1/2/3 mac id (for rings at LMAC level) 593 * b'16:23 - ring_id : Identify the ring to configure. 594 * More details can be got from enum htt_srng_ring_id 595 * b'24 - status_swap: 1 is to swap status TLV 596 * b'25 - pkt_swap: 1 is to swap packet TLV 597 * b'26:31 - rsvd1: reserved for future use 598 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 599 * in byte units. 600 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 601 * - b'16:31 - rsvd2: Reserved for future use 602 * dword2 - b'0:31 - packet_type_enable_flags_0: 603 * Enable MGMT packet from 0b0000 to 0b1001 604 * bits from low to high: FP, MD, MO - 3 bits 605 * FP: Filter_Pass 606 * MD: Monitor_Direct 607 * MO: Monitor_Other 608 * 10 mgmt subtypes * 3 bits -> 30 bits 609 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 610 * dword3 - b'0:31 - packet_type_enable_flags_1: 611 * Enable MGMT packet from 0b1010 to 0b1111 612 * bits from low to high: FP, MD, MO - 3 bits 613 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 614 * dword4 - b'0:31 - packet_type_enable_flags_2: 615 * Enable CTRL packet from 0b0000 to 0b1001 616 * bits from low to high: FP, MD, MO - 3 bits 617 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 618 * dword5 - b'0:31 - packet_type_enable_flags_3: 619 * Enable CTRL packet from 0b1010 to 0b1111, 620 * MCAST_DATA, UCAST_DATA, NULL_DATA 621 * bits from low to high: FP, MD, MO - 3 bits 622 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 623 * dword6 - b'0:31 - tlv_filter_in_flags: 624 * Filter in Attention/MPDU/PPDU/Header/User tlvs 625 * Refer to CFG_TLV_FILTER_IN_FLAG defs 626 */ 627 628 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 629 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 630 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 631 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 632 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 633 634 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 635 636 enum htt_rx_filter_tlv_flags { 637 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 638 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 639 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 640 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 641 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 642 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 643 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 644 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 645 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 646 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 647 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 648 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 649 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 650 }; 651 652 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 653 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 654 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 655 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 656 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 657 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 658 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 659 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 660 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 661 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 662 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 663 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 664 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 665 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 666 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 667 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 668 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 669 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 670 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 671 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 672 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 673 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 674 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 675 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 676 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 677 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 678 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 679 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 680 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 681 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 682 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 683 }; 684 685 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 686 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 687 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 688 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 689 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 690 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 691 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 692 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 693 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 694 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 695 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 696 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 697 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 698 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 699 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 700 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 701 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 702 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 703 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 704 }; 705 706 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 707 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 708 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 709 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 710 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 711 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 712 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 713 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 714 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 715 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 716 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 717 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 718 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 719 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 720 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 721 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 722 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 723 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 724 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 725 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 726 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 727 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 728 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 729 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 730 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 731 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 732 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 733 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 734 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 735 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 736 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 737 }; 738 739 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 740 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 741 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 742 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 743 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 744 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 745 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 746 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 747 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 748 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 749 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 750 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 751 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 752 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 753 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 754 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 755 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 756 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 757 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 758 }; 759 760 enum htt_rx_data_pkt_filter_tlv_flasg3 { 761 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 762 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 763 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 764 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 765 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 766 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 767 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 768 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 769 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 770 }; 771 772 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 773 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 774 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 775 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 776 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 777 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 781 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 782 783 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 784 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 785 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 786 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 787 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 788 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 789 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 790 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 791 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 792 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 793 794 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 795 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 796 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 797 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 798 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 799 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 800 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 801 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 802 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 803 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 804 805 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 806 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 807 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 808 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 809 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 810 811 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 812 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 813 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 814 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 815 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 816 817 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 818 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 819 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 820 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 821 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 822 823 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 824 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 825 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 826 827 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 828 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 829 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 830 831 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 832 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 833 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 834 835 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 836 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 837 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 838 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 839 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 840 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 841 842 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 843 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 844 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 845 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 846 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 847 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 848 849 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 850 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 851 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 852 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 853 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 854 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 855 856 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 857 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 858 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 859 860 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 861 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 862 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 863 864 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 865 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 866 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 867 868 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 869 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 870 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 871 872 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 873 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 874 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 875 876 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 877 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 878 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 879 880 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 881 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 882 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 883 884 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 885 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 886 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 887 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 888 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 889 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 890 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 891 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 892 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 893 894 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 895 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 896 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 897 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 898 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 899 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 900 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 901 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 902 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 903 904 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 905 906 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 907 908 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 909 910 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 911 912 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 913 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 914 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 915 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 916 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 917 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 918 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 919 920 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 921 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 922 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 923 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 924 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 925 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 926 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 927 928 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 929 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 930 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 931 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 932 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 933 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 934 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 935 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 936 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 937 938 struct htt_rx_ring_selection_cfg_cmd { 939 u32 info0; 940 u32 info1; 941 u32 pkt_type_en_flags0; 942 u32 pkt_type_en_flags1; 943 u32 pkt_type_en_flags2; 944 u32 pkt_type_en_flags3; 945 u32 rx_filter_tlv; 946 } __packed; 947 948 struct htt_rx_ring_tlv_filter { 949 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 950 u32 pkt_filter_flags0; /* MGMT */ 951 u32 pkt_filter_flags1; /* MGMT */ 952 u32 pkt_filter_flags2; /* CTRL */ 953 u32 pkt_filter_flags3; /* DATA */ 954 }; 955 956 /* HTT message target->host */ 957 958 enum htt_t2h_msg_type { 959 HTT_T2H_MSG_TYPE_VERSION_CONF, 960 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 961 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 962 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 963 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 964 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 965 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 966 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 967 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 968 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 969 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 970 }; 971 972 #define HTT_TARGET_VERSION_MAJOR 3 973 974 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 975 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 976 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 977 978 struct htt_t2h_version_conf_msg { 979 u32 version; 980 } __packed; 981 982 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 983 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 984 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 985 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 986 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 987 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 988 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 989 990 struct htt_t2h_peer_map_event { 991 u32 info; 992 u32 mac_addr_l32; 993 u32 info1; 994 u32 info2; 995 } __packed; 996 997 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 998 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 999 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1000 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1001 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1002 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1003 1004 struct htt_t2h_peer_unmap_event { 1005 u32 info; 1006 u32 mac_addr_l32; 1007 u32 info1; 1008 } __packed; 1009 1010 struct htt_resp_msg { 1011 union { 1012 struct htt_t2h_version_conf_msg version_msg; 1013 struct htt_t2h_peer_map_event peer_map_ev; 1014 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1015 }; 1016 } __packed; 1017 1018 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1019 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1020 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1021 1022 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1023 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1024 1025 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1026 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1027 1028 enum htt_backpressure_umac_ringid { 1029 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1030 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1031 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1032 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1033 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1034 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1035 HTT_SW_RING_IDX_REO_REO2FW_RING, 1036 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1037 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1038 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1039 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1040 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1041 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1042 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1043 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1044 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1045 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1046 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1047 HTT_SW_UMAC_RING_IDX_MAX, 1048 }; 1049 1050 enum htt_backpressure_lmac_ringid { 1051 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1052 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1053 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1054 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1055 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1056 HTT_SW_RING_IDX_RXDMA2FW_RING, 1057 HTT_SW_RING_IDX_RXDMA2SW_RING, 1058 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1059 HTT_SW_RING_IDX_RXDMA2REO_RING, 1060 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1061 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1062 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1063 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1064 HTT_SW_LMAC_RING_IDX_MAX, 1065 }; 1066 1067 /* ppdu stats 1068 * 1069 * @details 1070 * The following field definitions describe the format of the HTT target 1071 * to host ppdu stats indication message. 1072 * 1073 * 1074 * |31 16|15 12|11 10|9 8|7 0 | 1075 * |----------------------------------------------------------------------| 1076 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1077 * |----------------------------------------------------------------------| 1078 * | ppdu_id | 1079 * |----------------------------------------------------------------------| 1080 * | Timestamp in us | 1081 * |----------------------------------------------------------------------| 1082 * | reserved | 1083 * |----------------------------------------------------------------------| 1084 * | type-specific stats info | 1085 * | (see htt_ppdu_stats.h) | 1086 * |----------------------------------------------------------------------| 1087 * Header fields: 1088 * - MSG_TYPE 1089 * Bits 7:0 1090 * Purpose: Identifies this is a PPDU STATS indication 1091 * message. 1092 * Value: 0x1d 1093 * - mac_id 1094 * Bits 9:8 1095 * Purpose: mac_id of this ppdu_id 1096 * Value: 0-3 1097 * - pdev_id 1098 * Bits 11:10 1099 * Purpose: pdev_id of this ppdu_id 1100 * Value: 0-3 1101 * 0 (for rings at SOC level), 1102 * 1/2/3 PDEV -> 0/1/2 1103 * - payload_size 1104 * Bits 31:16 1105 * Purpose: total tlv size 1106 * Value: payload_size in bytes 1107 */ 1108 1109 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1110 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1111 1112 struct ath11k_htt_ppdu_stats_msg { 1113 u32 info; 1114 u32 ppdu_id; 1115 u32 timestamp; 1116 u32 rsvd; 1117 u8 data[0]; 1118 } __packed; 1119 1120 struct htt_tlv { 1121 u32 header; 1122 u8 value[0]; 1123 } __packed; 1124 1125 #define HTT_TLV_TAG GENMASK(11, 0) 1126 #define HTT_TLV_LEN GENMASK(23, 12) 1127 1128 enum HTT_PPDU_STATS_BW { 1129 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1130 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1131 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1132 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1133 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1134 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1135 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1136 }; 1137 1138 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1139 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1140 /* bw - HTT_PPDU_STATS_BW */ 1141 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1142 1143 struct htt_ppdu_stats_common { 1144 u32 ppdu_id; 1145 u16 sched_cmdid; 1146 u8 ring_id; 1147 u8 num_users; 1148 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1149 u32 chain_mask; 1150 u32 fes_duration_us; /* frame exchange sequence */ 1151 u32 ppdu_sch_eval_start_tstmp_us; 1152 u32 ppdu_sch_end_tstmp_us; 1153 u32 ppdu_start_tstmp_us; 1154 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1155 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1156 */ 1157 u16 phy_mode; 1158 u16 bw_mhz; 1159 } __packed; 1160 1161 enum htt_ppdu_stats_gi { 1162 HTT_PPDU_STATS_SGI_0_8_US, 1163 HTT_PPDU_STATS_SGI_0_4_US, 1164 HTT_PPDU_STATS_SGI_1_6_US, 1165 HTT_PPDU_STATS_SGI_3_2_US, 1166 }; 1167 1168 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1169 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1170 1171 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1172 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1173 1174 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1175 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1176 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1177 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1178 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1179 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1180 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1181 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1182 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1183 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1184 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1185 1186 #define HTT_USR_RATE_PREAMBLE(_val) \ 1187 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1188 #define HTT_USR_RATE_BW(_val) \ 1189 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1190 #define HTT_USR_RATE_NSS(_val) \ 1191 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1192 #define HTT_USR_RATE_MCS(_val) \ 1193 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1194 #define HTT_USR_RATE_GI(_val) \ 1195 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1196 #define HTT_USR_RATE_DCM(_val) \ 1197 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1198 1199 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1200 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1201 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1202 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1203 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1204 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1205 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1206 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1207 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1208 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1209 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1210 1211 struct htt_ppdu_stats_user_rate { 1212 u8 tid_num; 1213 u8 reserved0; 1214 u16 sw_peer_id; 1215 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1216 u16 ru_end; 1217 u16 ru_start; 1218 u16 resp_ru_end; 1219 u16 resp_ru_start; 1220 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1221 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1222 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1223 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1224 } __packed; 1225 1226 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1227 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1228 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1229 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1230 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1231 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1232 1233 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1234 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1235 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1236 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1237 #define HTT_TX_INFO_RATECODE(_flags) \ 1238 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1239 #define HTT_TX_INFO_PEERID(_flags) \ 1240 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1241 1242 struct htt_tx_ppdu_stats_info { 1243 struct htt_tlv tlv_hdr; 1244 u32 tx_success_bytes; 1245 u32 tx_retry_bytes; 1246 u32 tx_failed_bytes; 1247 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1248 u16 tx_success_msdus; 1249 u16 tx_retry_msdus; 1250 u16 tx_failed_msdus; 1251 u16 tx_duration; /* united in us */ 1252 } __packed; 1253 1254 enum htt_ppdu_stats_usr_compln_status { 1255 HTT_PPDU_STATS_USER_STATUS_OK, 1256 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1257 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1258 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1259 HTT_PPDU_STATS_USER_STATUS_ABORT, 1260 }; 1261 1262 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1263 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1264 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1265 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1266 1267 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1268 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1269 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1270 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1271 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1272 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1273 1274 struct htt_ppdu_stats_usr_cmpltn_cmn { 1275 u8 status; 1276 u8 tid_num; 1277 u16 sw_peer_id; 1278 /* RSSI value of last ack packet (units = dB above noise floor) */ 1279 u32 ack_rssi; 1280 u16 mpdu_tried; 1281 u16 mpdu_success; 1282 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1283 } __packed; 1284 1285 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1286 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1287 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1288 1289 #define HTT_PPDU_STATS_NON_QOS_TID 16 1290 1291 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1292 u32 ppdu_id; 1293 u16 sw_peer_id; 1294 u16 reserved0; 1295 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1296 u16 current_seq; 1297 u16 start_seq; 1298 u32 success_bytes; 1299 } __packed; 1300 1301 struct htt_ppdu_stats_usr_cmn_array { 1302 struct htt_tlv tlv_hdr; 1303 u32 num_ppdu_stats; 1304 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1305 * elements. 1306 * tx_ppdu_stats_info is variable length, with length = 1307 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1308 */ 1309 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1310 } __packed; 1311 1312 struct htt_ppdu_user_stats { 1313 u16 peer_id; 1314 u32 tlv_flags; 1315 bool is_valid_peer_id; 1316 struct htt_ppdu_stats_user_rate rate; 1317 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1318 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1319 }; 1320 1321 #define HTT_PPDU_STATS_MAX_USERS 8 1322 #define HTT_PPDU_DESC_MAX_DEPTH 16 1323 1324 struct htt_ppdu_stats { 1325 struct htt_ppdu_stats_common common; 1326 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1327 }; 1328 1329 struct htt_ppdu_stats_info { 1330 u32 ppdu_id; 1331 struct htt_ppdu_stats ppdu_stats; 1332 struct list_head list; 1333 }; 1334 1335 /** 1336 * @brief target -> host packet log message 1337 * 1338 * @details 1339 * The following field definitions describe the format of the packet log 1340 * message sent from the target to the host. 1341 * The message consists of a 4-octet header,followed by a variable number 1342 * of 32-bit character values. 1343 * 1344 * |31 16|15 12|11 10|9 8|7 0| 1345 * |------------------------------------------------------------------| 1346 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1347 * |------------------------------------------------------------------| 1348 * | payload | 1349 * |------------------------------------------------------------------| 1350 * - MSG_TYPE 1351 * Bits 7:0 1352 * Purpose: identifies this as a pktlog message 1353 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1354 * - mac_id 1355 * Bits 9:8 1356 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1357 * Value: 0-3 1358 * - pdev_id 1359 * Bits 11:10 1360 * Purpose: pdev_id 1361 * Value: 0-3 1362 * 0 (for rings at SOC level), 1363 * 1/2/3 PDEV -> 0/1/2 1364 * - payload_size 1365 * Bits 31:16 1366 * Purpose: explicitly specify the payload size 1367 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1368 */ 1369 struct htt_pktlog_msg { 1370 u32 hdr; 1371 u8 payload[0]; 1372 }; 1373 1374 /** 1375 * @brief host -> target FW extended statistics retrieve 1376 * 1377 * @details 1378 * The following field definitions describe the format of the HTT host 1379 * to target FW extended stats retrieve message. 1380 * The message specifies the type of stats the host wants to retrieve. 1381 * 1382 * |31 24|23 16|15 8|7 0| 1383 * |-----------------------------------------------------------| 1384 * | reserved | stats type | pdev_mask | msg type | 1385 * |-----------------------------------------------------------| 1386 * | config param [0] | 1387 * |-----------------------------------------------------------| 1388 * | config param [1] | 1389 * |-----------------------------------------------------------| 1390 * | config param [2] | 1391 * |-----------------------------------------------------------| 1392 * | config param [3] | 1393 * |-----------------------------------------------------------| 1394 * | reserved | 1395 * |-----------------------------------------------------------| 1396 * | cookie LSBs | 1397 * |-----------------------------------------------------------| 1398 * | cookie MSBs | 1399 * |-----------------------------------------------------------| 1400 * Header fields: 1401 * - MSG_TYPE 1402 * Bits 7:0 1403 * Purpose: identifies this is a extended stats upload request message 1404 * Value: 0x10 1405 * - PDEV_MASK 1406 * Bits 8:15 1407 * Purpose: identifies the mask of PDEVs to retrieve stats from 1408 * Value: This is a overloaded field, refer to usage and interpretation of 1409 * PDEV in interface document. 1410 * Bit 8 : Reserved for SOC stats 1411 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1412 * Indicates MACID_MASK in DBS 1413 * - STATS_TYPE 1414 * Bits 23:16 1415 * Purpose: identifies which FW statistics to upload 1416 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1417 * - Reserved 1418 * Bits 31:24 1419 * - CONFIG_PARAM [0] 1420 * Bits 31:0 1421 * Purpose: give an opaque configuration value to the specified stats type 1422 * Value: stats-type specific configuration value 1423 * Refer to htt_stats.h for interpretation for each stats sub_type 1424 * - CONFIG_PARAM [1] 1425 * Bits 31:0 1426 * Purpose: give an opaque configuration value to the specified stats type 1427 * Value: stats-type specific configuration value 1428 * Refer to htt_stats.h for interpretation for each stats sub_type 1429 * - CONFIG_PARAM [2] 1430 * Bits 31:0 1431 * Purpose: give an opaque configuration value to the specified stats type 1432 * Value: stats-type specific configuration value 1433 * Refer to htt_stats.h for interpretation for each stats sub_type 1434 * - CONFIG_PARAM [3] 1435 * Bits 31:0 1436 * Purpose: give an opaque configuration value to the specified stats type 1437 * Value: stats-type specific configuration value 1438 * Refer to htt_stats.h for interpretation for each stats sub_type 1439 * - Reserved [31:0] for future use. 1440 * - COOKIE_LSBS 1441 * Bits 31:0 1442 * Purpose: Provide a mechanism to match a target->host stats confirmation 1443 * message with its preceding host->target stats request message. 1444 * Value: LSBs of the opaque cookie specified by the host-side requestor 1445 * - COOKIE_MSBS 1446 * Bits 31:0 1447 * Purpose: Provide a mechanism to match a target->host stats confirmation 1448 * message with its preceding host->target stats request message. 1449 * Value: MSBs of the opaque cookie specified by the host-side requestor 1450 */ 1451 1452 struct htt_ext_stats_cfg_hdr { 1453 u8 msg_type; 1454 u8 pdev_mask; 1455 u8 stats_type; 1456 u8 reserved; 1457 } __packed; 1458 1459 struct htt_ext_stats_cfg_cmd { 1460 struct htt_ext_stats_cfg_hdr hdr; 1461 u32 cfg_param0; 1462 u32 cfg_param1; 1463 u32 cfg_param2; 1464 u32 cfg_param3; 1465 u32 reserved; 1466 u32 cookie_lsb; 1467 u32 cookie_msb; 1468 } __packed; 1469 1470 /* htt stats config default params */ 1471 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1472 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1473 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1474 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1475 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1476 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1477 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1478 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1479 1480 /* HTT_DBG_EXT_STATS_PEER_INFO 1481 * PARAMS: 1482 * @config_param0: 1483 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1484 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1485 * [Bit31 : Bit16] sw_peer_id 1486 * @config_param1: 1487 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1488 * 0 bit htt_peer_stats_cmn_tlv 1489 * 1 bit htt_peer_details_tlv 1490 * 2 bit htt_tx_peer_rate_stats_tlv 1491 * 3 bit htt_rx_peer_rate_stats_tlv 1492 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1493 * 5 bit htt_rx_tid_stats_tlv 1494 * 6 bit htt_msdu_flow_stats_tlv 1495 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1496 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1497 * [Bit31 : Bit16] reserved 1498 */ 1499 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1500 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1501 1502 /* Used to set different configs to the specified stats type.*/ 1503 struct htt_ext_stats_cfg_params { 1504 u32 cfg0; 1505 u32 cfg1; 1506 u32 cfg2; 1507 u32 cfg3; 1508 }; 1509 1510 /** 1511 * @brief target -> host extended statistics upload 1512 * 1513 * @details 1514 * The following field definitions describe the format of the HTT target 1515 * to host stats upload confirmation message. 1516 * The message contains a cookie echoed from the HTT host->target stats 1517 * upload request, which identifies which request the confirmation is 1518 * for, and a single stats can span over multiple HTT stats indication 1519 * due to the HTT message size limitation so every HTT ext stats indication 1520 * will have tag-length-value stats information elements. 1521 * The tag-length header for each HTT stats IND message also includes a 1522 * status field, to indicate whether the request for the stat type in 1523 * question was fully met, partially met, unable to be met, or invalid 1524 * (if the stat type in question is disabled in the target). 1525 * A Done bit 1's indicate the end of the of stats info elements. 1526 * 1527 * 1528 * |31 16|15 12|11|10 8|7 5|4 0| 1529 * |--------------------------------------------------------------| 1530 * | reserved | msg type | 1531 * |--------------------------------------------------------------| 1532 * | cookie LSBs | 1533 * |--------------------------------------------------------------| 1534 * | cookie MSBs | 1535 * |--------------------------------------------------------------| 1536 * | stats entry length | rsvd | D| S | stat type | 1537 * |--------------------------------------------------------------| 1538 * | type-specific stats info | 1539 * | (see htt_stats.h) | 1540 * |--------------------------------------------------------------| 1541 * Header fields: 1542 * - MSG_TYPE 1543 * Bits 7:0 1544 * Purpose: Identifies this is a extended statistics upload confirmation 1545 * message. 1546 * Value: 0x1c 1547 * - COOKIE_LSBS 1548 * Bits 31:0 1549 * Purpose: Provide a mechanism to match a target->host stats confirmation 1550 * message with its preceding host->target stats request message. 1551 * Value: LSBs of the opaque cookie specified by the host-side requestor 1552 * - COOKIE_MSBS 1553 * Bits 31:0 1554 * Purpose: Provide a mechanism to match a target->host stats confirmation 1555 * message with its preceding host->target stats request message. 1556 * Value: MSBs of the opaque cookie specified by the host-side requestor 1557 * 1558 * Stats Information Element tag-length header fields: 1559 * - STAT_TYPE 1560 * Bits 7:0 1561 * Purpose: identifies the type of statistics info held in the 1562 * following information element 1563 * Value: htt_dbg_ext_stats_type 1564 * - STATUS 1565 * Bits 10:8 1566 * Purpose: indicate whether the requested stats are present 1567 * Value: htt_dbg_ext_stats_status 1568 * - DONE 1569 * Bits 11 1570 * Purpose: 1571 * Indicates the completion of the stats entry, this will be the last 1572 * stats conf HTT segment for the requested stats type. 1573 * Value: 1574 * 0 -> the stats retrieval is ongoing 1575 * 1 -> the stats retrieval is complete 1576 * - LENGTH 1577 * Bits 31:16 1578 * Purpose: indicate the stats information size 1579 * Value: This field specifies the number of bytes of stats information 1580 * that follows the element tag-length header. 1581 * It is expected but not required that this length is a multiple of 1582 * 4 bytes. 1583 */ 1584 1585 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1586 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1587 1588 struct ath11k_htt_extd_stats_msg { 1589 u32 info0; 1590 u64 cookie; 1591 u32 info1; 1592 u8 data[0]; 1593 } __packed; 1594 1595 struct htt_mac_addr { 1596 u32 mac_addr_l32; 1597 u32 mac_addr_h16; 1598 }; 1599 1600 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1601 { 1602 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1603 addr_l32 = swab32(addr_l32); 1604 addr_h16 = swab16(addr_h16); 1605 } 1606 1607 memcpy(addr, &addr_l32, 4); 1608 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1609 } 1610 1611 int ath11k_dp_service_srng(struct ath11k_base *ab, 1612 struct ath11k_ext_irq_grp *irq_grp, 1613 int budget); 1614 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1615 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1616 void ath11k_dp_free(struct ath11k_base *ab); 1617 int ath11k_dp_alloc(struct ath11k_base *ab); 1618 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1619 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1620 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1621 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1622 int mac_id, enum hal_ring_type ring_type); 1623 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1624 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1625 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1626 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1627 enum hal_ring_type type, int ring_num, 1628 int mac_id, int num_entries); 1629 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1630 struct dp_link_desc_bank *desc_bank, 1631 u32 ring_type, struct dp_srng *ring); 1632 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1633 struct dp_link_desc_bank *link_desc_banks, 1634 u32 ring_type, struct hal_srng *srng, 1635 u32 n_link_desc); 1636 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1637 struct hal_srng *srng, 1638 struct ath11k_hp_update_timer *update_timer); 1639 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1640 struct ath11k_hp_update_timer *update_timer); 1641 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1642 struct ath11k_hp_update_timer *update_timer, 1643 u32 interval, u32 ring_id); 1644 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1645 1646 #endif 1647