1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_DP_H 7 #define ATH11K_DP_H 8 9 #include "hal_rx.h" 10 11 struct ath11k_base; 12 struct ath11k_peer; 13 struct ath11k_dp; 14 struct ath11k_vif; 15 struct hal_tcl_status_ring; 16 struct ath11k_ext_irq_grp; 17 18 struct dp_rx_tid { 19 u8 tid; 20 u32 *vaddr; 21 dma_addr_t paddr; 22 u32 size; 23 u32 ba_win_sz; 24 bool active; 25 26 /* Info related to rx fragments */ 27 u32 cur_sn; 28 u16 last_frag_no; 29 u16 rx_frag_bitmap; 30 31 struct sk_buff_head rx_frags; 32 struct hal_reo_dest_ring *dst_ring_desc; 33 34 /* Timer info related to fragments */ 35 struct timer_list frag_timer; 36 struct ath11k_base *ab; 37 }; 38 39 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 40 41 struct dp_reo_cache_flush_elem { 42 struct list_head list; 43 struct dp_rx_tid data; 44 unsigned long ts; 45 }; 46 47 struct dp_reo_cmd { 48 struct list_head list; 49 struct dp_rx_tid data; 50 int cmd_num; 51 void (*handler)(struct ath11k_dp *, void *, 52 enum hal_reo_cmd_status status); 53 }; 54 55 struct dp_srng { 56 u32 *vaddr_unaligned; 57 u32 *vaddr; 58 dma_addr_t paddr_unaligned; 59 dma_addr_t paddr; 60 int size; 61 u32 ring_id; 62 }; 63 64 struct dp_rxdma_ring { 65 struct dp_srng refill_buf_ring; 66 struct idr bufs_idr; 67 /* Protects bufs_idr */ 68 spinlock_t idr_lock; 69 int bufs_max; 70 }; 71 72 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 73 74 struct dp_tx_ring { 75 u8 tcl_data_ring_id; 76 struct dp_srng tcl_data_ring; 77 struct dp_srng tcl_comp_ring; 78 struct idr txbuf_idr; 79 /* Protects txbuf_idr and num_pending */ 80 spinlock_t tx_idr_lock; 81 struct hal_wbm_release_ring *tx_status; 82 int tx_status_head; 83 int tx_status_tail; 84 }; 85 86 struct ath11k_pdev_mon_stats { 87 u32 status_ppdu_state; 88 u32 status_ppdu_start; 89 u32 status_ppdu_end; 90 u32 status_ppdu_compl; 91 u32 status_ppdu_start_mis; 92 u32 status_ppdu_end_mis; 93 u32 status_ppdu_done; 94 u32 dest_ppdu_done; 95 u32 dest_mpdu_done; 96 u32 dest_mpdu_drop; 97 u32 dup_mon_linkdesc_cnt; 98 u32 dup_mon_buf_cnt; 99 }; 100 101 struct dp_link_desc_bank { 102 void *vaddr_unaligned; 103 void *vaddr; 104 dma_addr_t paddr_unaligned; 105 dma_addr_t paddr; 106 u32 size; 107 }; 108 109 /* Size to enforce scatter idle list mode */ 110 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 111 #define DP_LINK_DESC_BANKS_MAX 8 112 113 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 114 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 115 #define DP_RX_DESC_COOKIE_MAX \ 116 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 117 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 118 119 enum ath11k_dp_ppdu_state { 120 DP_PPDU_STATUS_START, 121 DP_PPDU_STATUS_DONE, 122 }; 123 124 struct ath11k_mon_data { 125 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 126 struct hal_rx_mon_ppdu_info mon_ppdu_info; 127 128 u32 mon_ppdu_status; 129 u32 mon_last_buf_cookie; 130 u64 mon_last_linkdesc_paddr; 131 u16 chan_noise_floor; 132 133 struct ath11k_pdev_mon_stats rx_mon_stats; 134 /* lock for monitor data */ 135 spinlock_t mon_lock; 136 struct sk_buff_head rx_status_q; 137 }; 138 139 struct ath11k_pdev_dp { 140 u32 mac_id; 141 atomic_t num_tx_pending; 142 wait_queue_head_t tx_empty_waitq; 143 struct dp_rxdma_ring rx_refill_buf_ring; 144 struct dp_srng rxdma_err_dst_ring; 145 struct dp_srng rxdma_mon_dst_ring; 146 struct dp_srng rxdma_mon_desc_ring; 147 148 struct dp_rxdma_ring rxdma_mon_buf_ring; 149 struct dp_rxdma_ring rx_mon_status_refill_ring; 150 struct ieee80211_rx_status rx_status; 151 struct ath11k_mon_data mon_data; 152 }; 153 154 #define DP_NUM_CLIENTS_MAX 64 155 #define DP_AVG_TIDS_PER_CLIENT 2 156 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 157 #define DP_AVG_MSDUS_PER_FLOW 128 158 #define DP_AVG_FLOWS_PER_TID 2 159 #define DP_AVG_MPDUS_PER_TID_MAX 128 160 #define DP_AVG_MSDUS_PER_MPDU 4 161 162 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 163 164 #define DP_BA_WIN_SZ_MAX 256 165 166 #define DP_TCL_NUM_RING_MAX 3 167 168 #define DP_IDLE_SCATTER_BUFS_MAX 16 169 170 #define DP_WBM_RELEASE_RING_SIZE 64 171 #define DP_TCL_DATA_RING_SIZE 512 172 #define DP_TX_COMP_RING_SIZE 8192 173 #define DP_TX_IDR_SIZE (DP_TX_COMP_RING_SIZE << 1) 174 #define DP_TCL_CMD_RING_SIZE 32 175 #define DP_TCL_STATUS_RING_SIZE 32 176 #define DP_REO_DST_RING_MAX 4 177 #define DP_REO_DST_RING_SIZE 2048 178 #define DP_REO_REINJECT_RING_SIZE 32 179 #define DP_RX_RELEASE_RING_SIZE 1024 180 #define DP_REO_EXCEPTION_RING_SIZE 128 181 #define DP_REO_CMD_RING_SIZE 128 182 #define DP_REO_STATUS_RING_SIZE 2048 183 #define DP_RXDMA_BUF_RING_SIZE 4096 184 #define DP_RXDMA_REFILL_RING_SIZE 2048 185 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 186 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 187 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 188 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 189 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 190 191 #define DP_RX_BUFFER_SIZE 2048 192 #define DP_RX_BUFFER_ALIGN_SIZE 128 193 194 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 195 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 196 197 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 198 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 199 200 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 201 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 202 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 203 204 struct ath11k_dp { 205 struct ath11k_base *ab; 206 enum ath11k_htc_ep_id eid; 207 struct completion htt_tgt_version_received; 208 u8 htt_tgt_ver_major; 209 u8 htt_tgt_ver_minor; 210 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 211 struct dp_srng wbm_idle_ring; 212 struct dp_srng wbm_desc_rel_ring; 213 struct dp_srng tcl_cmd_ring; 214 struct dp_srng tcl_status_ring; 215 struct dp_srng reo_reinject_ring; 216 struct dp_srng rx_rel_ring; 217 struct dp_srng reo_except_ring; 218 struct dp_srng reo_cmd_ring; 219 struct dp_srng reo_status_ring; 220 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 221 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 222 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 223 struct list_head reo_cmd_list; 224 struct list_head reo_cmd_cache_flush_list; 225 /* protects access to reo_cmd_list and reo_cmd_cache_flush_list */ 226 spinlock_t reo_cmd_lock; 227 }; 228 229 /* HTT definitions */ 230 231 #define HTT_TCL_META_DATA_TYPE BIT(0) 232 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 233 234 /* vdev meta data */ 235 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 236 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 237 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 238 239 /* peer meta data */ 240 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 241 242 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 243 244 /* HTT tx completion is overlayed in wbm_release_ring */ 245 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 246 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 247 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 248 249 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 250 251 struct htt_tx_wbm_completion { 252 u32 info0; 253 u32 info1; 254 u32 info2; 255 u32 info3; 256 } __packed; 257 258 enum htt_h2t_msg_type { 259 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 260 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 261 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 262 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 263 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 264 }; 265 266 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 267 268 struct htt_ver_req_cmd { 269 u32 ver_reg_info; 270 } __packed; 271 272 enum htt_srng_ring_type { 273 HTT_HW_TO_SW_RING, 274 HTT_SW_TO_HW_RING, 275 HTT_SW_TO_SW_RING, 276 }; 277 278 enum htt_srng_ring_id { 279 HTT_RXDMA_HOST_BUF_RING, 280 HTT_RXDMA_MONITOR_STATUS_RING, 281 HTT_RXDMA_MONITOR_BUF_RING, 282 HTT_RXDMA_MONITOR_DESC_RING, 283 HTT_RXDMA_MONITOR_DEST_RING, 284 HTT_HOST1_TO_FW_RXBUF_RING, 285 HTT_HOST2_TO_FW_RXBUF_RING, 286 HTT_RXDMA_NON_MONITOR_DEST_RING, 287 }; 288 289 /* host -> target HTT_SRING_SETUP message 290 * 291 * After target is booted up, Host can send SRING setup message for 292 * each host facing LMAC SRING. Target setups up HW registers based 293 * on setup message and confirms back to Host if response_required is set. 294 * Host should wait for confirmation message before sending new SRING 295 * setup message 296 * 297 * The message would appear as follows: 298 * 299 * |31 24|23 20|19|18 16|15|14 8|7 0| 300 * |--------------- +-----------------+----------------+------------------| 301 * | ring_type | ring_id | pdev_id | msg_type | 302 * |----------------------------------------------------------------------| 303 * | ring_base_addr_lo | 304 * |----------------------------------------------------------------------| 305 * | ring_base_addr_hi | 306 * |----------------------------------------------------------------------| 307 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 308 * |----------------------------------------------------------------------| 309 * | ring_head_offset32_remote_addr_lo | 310 * |----------------------------------------------------------------------| 311 * | ring_head_offset32_remote_addr_hi | 312 * |----------------------------------------------------------------------| 313 * | ring_tail_offset32_remote_addr_lo | 314 * |----------------------------------------------------------------------| 315 * | ring_tail_offset32_remote_addr_hi | 316 * |----------------------------------------------------------------------| 317 * | ring_msi_addr_lo | 318 * |----------------------------------------------------------------------| 319 * | ring_msi_addr_hi | 320 * |----------------------------------------------------------------------| 321 * | ring_msi_data | 322 * |----------------------------------------------------------------------| 323 * | intr_timer_th |IM| intr_batch_counter_th | 324 * |----------------------------------------------------------------------| 325 * | reserved |RR|PTCF| intr_low_threshold | 326 * |----------------------------------------------------------------------| 327 * Where 328 * IM = sw_intr_mode 329 * RR = response_required 330 * PTCF = prefetch_timer_cfg 331 * 332 * The message is interpreted as follows: 333 * dword0 - b'0:7 - msg_type: This will be set to 334 * HTT_H2T_MSG_TYPE_SRING_SETUP 335 * b'8:15 - pdev_id: 336 * 0 (for rings at SOC/UMAC level), 337 * 1/2/3 mac id (for rings at LMAC level) 338 * b'16:23 - ring_id: identify which ring is to setup, 339 * more details can be got from enum htt_srng_ring_id 340 * b'24:31 - ring_type: identify type of host rings, 341 * more details can be got from enum htt_srng_ring_type 342 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 343 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 344 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 345 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 346 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 347 * SW_TO_HW_RING. 348 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 349 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 350 * Lower 32 bits of memory address of the remote variable 351 * storing the 4-byte word offset that identifies the head 352 * element within the ring. 353 * (The head offset variable has type u32.) 354 * Valid for HW_TO_SW and SW_TO_SW rings. 355 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 356 * Upper 32 bits of memory address of the remote variable 357 * storing the 4-byte word offset that identifies the head 358 * element within the ring. 359 * (The head offset variable has type u32.) 360 * Valid for HW_TO_SW and SW_TO_SW rings. 361 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 362 * Lower 32 bits of memory address of the remote variable 363 * storing the 4-byte word offset that identifies the tail 364 * element within the ring. 365 * (The tail offset variable has type u32.) 366 * Valid for HW_TO_SW and SW_TO_SW rings. 367 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 368 * Upper 32 bits of memory address of the remote variable 369 * storing the 4-byte word offset that identifies the tail 370 * element within the ring. 371 * (The tail offset variable has type u32.) 372 * Valid for HW_TO_SW and SW_TO_SW rings. 373 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 374 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 375 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 376 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 377 * dword10 - b'0:31 - ring_msi_data: MSI data 378 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 379 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 380 * dword11 - b'0:14 - intr_batch_counter_th: 381 * batch counter threshold is in units of 4-byte words. 382 * HW internally maintains and increments batch count. 383 * (see SRING spec for detail description). 384 * When batch count reaches threshold value, an interrupt 385 * is generated by HW. 386 * b'15 - sw_intr_mode: 387 * This configuration shall be static. 388 * Only programmed at power up. 389 * 0: generate pulse style sw interrupts 390 * 1: generate level style sw interrupts 391 * b'16:31 - intr_timer_th: 392 * The timer init value when timer is idle or is 393 * initialized to start downcounting. 394 * In 8us units (to cover a range of 0 to 524 ms) 395 * dword12 - b'0:15 - intr_low_threshold: 396 * Used only by Consumer ring to generate ring_sw_int_p. 397 * Ring entries low threshold water mark, that is used 398 * in combination with the interrupt timer as well as 399 * the the clearing of the level interrupt. 400 * b'16:18 - prefetch_timer_cfg: 401 * Used only by Consumer ring to set timer mode to 402 * support Application prefetch handling. 403 * The external tail offset/pointer will be updated 404 * at following intervals: 405 * 3'b000: (Prefetch feature disabled; used only for debug) 406 * 3'b001: 1 usec 407 * 3'b010: 4 usec 408 * 3'b011: 8 usec (default) 409 * 3'b100: 16 usec 410 * Others: Reserverd 411 * b'19 - response_required: 412 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 413 * b'20:31 - reserved: reserved for future use 414 */ 415 416 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 417 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 418 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 419 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 420 421 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 422 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 423 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 424 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 425 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 426 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 427 428 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 429 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 430 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 431 432 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 433 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 434 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 435 436 struct htt_srng_setup_cmd { 437 u32 info0; 438 u32 ring_base_addr_lo; 439 u32 ring_base_addr_hi; 440 u32 info1; 441 u32 ring_head_off32_remote_addr_lo; 442 u32 ring_head_off32_remote_addr_hi; 443 u32 ring_tail_off32_remote_addr_lo; 444 u32 ring_tail_off32_remote_addr_hi; 445 u32 ring_msi_addr_lo; 446 u32 ring_msi_addr_hi; 447 u32 msi_data; 448 u32 intr_info; 449 u32 info2; 450 } __packed; 451 452 /* host -> target FW PPDU_STATS config message 453 * 454 * @details 455 * The following field definitions describe the format of the HTT host 456 * to target FW for PPDU_STATS_CFG msg. 457 * The message allows the host to configure the PPDU_STATS_IND messages 458 * produced by the target. 459 * 460 * |31 24|23 16|15 8|7 0| 461 * |-----------------------------------------------------------| 462 * | REQ bit mask | pdev_mask | msg type | 463 * |-----------------------------------------------------------| 464 * Header fields: 465 * - MSG_TYPE 466 * Bits 7:0 467 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 468 * Value: 0x11 469 * - PDEV_MASK 470 * Bits 8:15 471 * Purpose: identifies which pdevs this PPDU stats configuration applies to 472 * Value: This is a overloaded field, refer to usage and interpretation of 473 * PDEV in interface document. 474 * Bit 8 : Reserved for SOC stats 475 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 476 * Indicates MACID_MASK in DBS 477 * - REQ_TLV_BIT_MASK 478 * Bits 16:31 479 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 480 * needs to be included in the target's PPDU_STATS_IND messages. 481 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 482 * 483 */ 484 485 struct htt_ppdu_stats_cfg_cmd { 486 u32 msg; 487 } __packed; 488 489 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 490 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(16, 9) 491 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 492 493 enum htt_ppdu_stats_tag_type { 494 HTT_PPDU_STATS_TAG_COMMON, 495 HTT_PPDU_STATS_TAG_USR_COMMON, 496 HTT_PPDU_STATS_TAG_USR_RATE, 497 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 498 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 499 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 500 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 501 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 502 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 503 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 504 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 505 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 506 HTT_PPDU_STATS_TAG_INFO, 507 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 508 509 /* New TLV's are added above to this line */ 510 HTT_PPDU_STATS_TAG_MAX, 511 }; 512 513 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 514 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 515 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 516 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 517 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 518 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 519 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 520 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 521 522 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 523 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 524 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 525 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 526 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 527 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 528 HTT_PPDU_STATS_TAG_DEFAULT) 529 530 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 531 * 532 * details: 533 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 534 * configure RXDMA rings. 535 * The configuration is per ring based and includes both packet subtypes 536 * and PPDU/MPDU TLVs. 537 * 538 * The message would appear as follows: 539 * 540 * |31 26|25|24|23 16|15 8|7 0| 541 * |-----------------+----------------+----------------+---------------| 542 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 543 * |-------------------------------------------------------------------| 544 * | rsvd2 | ring_buffer_size | 545 * |-------------------------------------------------------------------| 546 * | packet_type_enable_flags_0 | 547 * |-------------------------------------------------------------------| 548 * | packet_type_enable_flags_1 | 549 * |-------------------------------------------------------------------| 550 * | packet_type_enable_flags_2 | 551 * |-------------------------------------------------------------------| 552 * | packet_type_enable_flags_3 | 553 * |-------------------------------------------------------------------| 554 * | tlv_filter_in_flags | 555 * |-------------------------------------------------------------------| 556 * Where: 557 * PS = pkt_swap 558 * SS = status_swap 559 * The message is interpreted as follows: 560 * dword0 - b'0:7 - msg_type: This will be set to 561 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 562 * b'8:15 - pdev_id: 563 * 0 (for rings at SOC/UMAC level), 564 * 1/2/3 mac id (for rings at LMAC level) 565 * b'16:23 - ring_id : Identify the ring to configure. 566 * More details can be got from enum htt_srng_ring_id 567 * b'24 - status_swap: 1 is to swap status TLV 568 * b'25 - pkt_swap: 1 is to swap packet TLV 569 * b'26:31 - rsvd1: reserved for future use 570 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 571 * in byte units. 572 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 573 * - b'16:31 - rsvd2: Reserved for future use 574 * dword2 - b'0:31 - packet_type_enable_flags_0: 575 * Enable MGMT packet from 0b0000 to 0b1001 576 * bits from low to high: FP, MD, MO - 3 bits 577 * FP: Filter_Pass 578 * MD: Monitor_Direct 579 * MO: Monitor_Other 580 * 10 mgmt subtypes * 3 bits -> 30 bits 581 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 582 * dword3 - b'0:31 - packet_type_enable_flags_1: 583 * Enable MGMT packet from 0b1010 to 0b1111 584 * bits from low to high: FP, MD, MO - 3 bits 585 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 586 * dword4 - b'0:31 - packet_type_enable_flags_2: 587 * Enable CTRL packet from 0b0000 to 0b1001 588 * bits from low to high: FP, MD, MO - 3 bits 589 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 590 * dword5 - b'0:31 - packet_type_enable_flags_3: 591 * Enable CTRL packet from 0b1010 to 0b1111, 592 * MCAST_DATA, UCAST_DATA, NULL_DATA 593 * bits from low to high: FP, MD, MO - 3 bits 594 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 595 * dword6 - b'0:31 - tlv_filter_in_flags: 596 * Filter in Attention/MPDU/PPDU/Header/User tlvs 597 * Refer to CFG_TLV_FILTER_IN_FLAG defs 598 */ 599 600 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 601 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 602 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 603 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 604 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 605 606 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 607 608 enum htt_rx_filter_tlv_flags { 609 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 610 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 611 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 612 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 613 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 614 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 615 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 616 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 617 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 618 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 619 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 620 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 621 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 622 }; 623 624 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 625 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 626 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 627 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 628 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 629 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 630 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 631 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 632 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 633 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 634 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 635 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 636 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 637 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 638 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 639 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 640 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 641 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 642 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 643 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 644 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 645 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 646 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 647 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 648 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 649 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 650 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 651 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 652 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 653 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 654 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 655 }; 656 657 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 658 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 659 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 660 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 661 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 662 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 663 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 664 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 665 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 666 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 667 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 668 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 669 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 670 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 671 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 672 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 673 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 674 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 675 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 676 }; 677 678 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 679 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 680 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 681 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 682 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 683 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 684 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 685 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 686 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 687 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 688 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 689 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 690 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 691 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 692 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 693 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 694 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 695 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 696 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 697 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 698 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 699 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 700 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 701 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 702 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 703 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 704 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 705 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 706 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 707 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 708 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 709 }; 710 711 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 712 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 713 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 714 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 715 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 716 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 717 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 718 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 719 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 720 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 721 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 722 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 723 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 724 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 725 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 726 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 727 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 728 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 729 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 730 }; 731 732 enum htt_rx_data_pkt_filter_tlv_flasg3 { 733 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 734 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 735 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 736 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 737 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 738 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 739 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 740 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 741 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 742 }; 743 744 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 745 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 746 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 747 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 748 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 749 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 750 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 751 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 752 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 753 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 754 755 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 756 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 757 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 758 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 759 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 760 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 761 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 762 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 763 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 764 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 765 766 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 767 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 768 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 769 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 770 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 771 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 772 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 773 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 774 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 775 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 776 777 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 778 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 779 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 780 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 781 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 782 783 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 784 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 785 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 786 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 787 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 788 789 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 790 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 791 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 792 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 793 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 794 795 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 796 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 797 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 798 799 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 800 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 801 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 802 803 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 804 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 805 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 806 807 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 808 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 809 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 810 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 811 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 812 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 813 814 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 815 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 816 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 817 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 818 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 819 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 820 821 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 822 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 823 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 824 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 825 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 826 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 827 828 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 829 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 830 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 831 832 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 833 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 834 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 835 836 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 837 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 838 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 839 840 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 841 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 842 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 843 844 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 845 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 846 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 847 848 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 849 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 850 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 851 852 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 853 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 854 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 855 856 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 857 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 858 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 859 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 860 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 861 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 862 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 863 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 864 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 865 866 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 867 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 868 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 869 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 870 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 871 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 872 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 873 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 874 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 875 876 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 877 878 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 879 880 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 881 882 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 883 884 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 885 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 886 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 887 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 888 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 889 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 890 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 891 892 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 893 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 894 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 895 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 896 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 897 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 898 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 899 900 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 901 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 902 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 903 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 904 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 905 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 906 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 907 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 908 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 909 910 struct htt_rx_ring_selection_cfg_cmd { 911 u32 info0; 912 u32 info1; 913 u32 pkt_type_en_flags0; 914 u32 pkt_type_en_flags1; 915 u32 pkt_type_en_flags2; 916 u32 pkt_type_en_flags3; 917 u32 rx_filter_tlv; 918 } __packed; 919 920 struct htt_rx_ring_tlv_filter { 921 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 922 u32 pkt_filter_flags0; /* MGMT */ 923 u32 pkt_filter_flags1; /* MGMT */ 924 u32 pkt_filter_flags2; /* CTRL */ 925 u32 pkt_filter_flags3; /* DATA */ 926 }; 927 928 /* HTT message target->host */ 929 930 enum htt_t2h_msg_type { 931 HTT_T2H_MSG_TYPE_VERSION_CONF, 932 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 933 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 934 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 935 HTT_T2H_MSG_TYPE_PEER_MAP = 0x1e, 936 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x1f, 937 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 938 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 939 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 940 }; 941 942 #define HTT_TARGET_VERSION_MAJOR 3 943 944 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 945 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 946 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 947 948 struct htt_t2h_version_conf_msg { 949 u32 version; 950 } __packed; 951 952 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 953 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 954 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 955 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 956 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 957 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 958 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 959 960 struct htt_t2h_peer_map_event { 961 u32 info; 962 u32 mac_addr_l32; 963 u32 info1; 964 u32 info2; 965 } __packed; 966 967 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 968 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 969 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 970 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 971 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 972 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 973 974 struct htt_t2h_peer_unmap_event { 975 u32 info; 976 u32 mac_addr_l32; 977 u32 info1; 978 } __packed; 979 980 struct htt_resp_msg { 981 union { 982 struct htt_t2h_version_conf_msg version_msg; 983 struct htt_t2h_peer_map_event peer_map_ev; 984 struct htt_t2h_peer_unmap_event peer_unmap_ev; 985 }; 986 } __packed; 987 988 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 989 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 990 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 991 992 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 993 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 994 995 /* ppdu stats 996 * 997 * @details 998 * The following field definitions describe the format of the HTT target 999 * to host ppdu stats indication message. 1000 * 1001 * 1002 * |31 16|15 12|11 10|9 8|7 0 | 1003 * |----------------------------------------------------------------------| 1004 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1005 * |----------------------------------------------------------------------| 1006 * | ppdu_id | 1007 * |----------------------------------------------------------------------| 1008 * | Timestamp in us | 1009 * |----------------------------------------------------------------------| 1010 * | reserved | 1011 * |----------------------------------------------------------------------| 1012 * | type-specific stats info | 1013 * | (see htt_ppdu_stats.h) | 1014 * |----------------------------------------------------------------------| 1015 * Header fields: 1016 * - MSG_TYPE 1017 * Bits 7:0 1018 * Purpose: Identifies this is a PPDU STATS indication 1019 * message. 1020 * Value: 0x1d 1021 * - mac_id 1022 * Bits 9:8 1023 * Purpose: mac_id of this ppdu_id 1024 * Value: 0-3 1025 * - pdev_id 1026 * Bits 11:10 1027 * Purpose: pdev_id of this ppdu_id 1028 * Value: 0-3 1029 * 0 (for rings at SOC level), 1030 * 1/2/3 PDEV -> 0/1/2 1031 * - payload_size 1032 * Bits 31:16 1033 * Purpose: total tlv size 1034 * Value: payload_size in bytes 1035 */ 1036 1037 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1038 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1039 1040 struct ath11k_htt_ppdu_stats_msg { 1041 u32 info; 1042 u32 ppdu_id; 1043 u32 timestamp; 1044 u32 rsvd; 1045 u8 data[0]; 1046 } __packed; 1047 1048 struct htt_tlv { 1049 u32 header; 1050 u8 value[0]; 1051 } __packed; 1052 1053 #define HTT_TLV_TAG GENMASK(11, 0) 1054 #define HTT_TLV_LEN GENMASK(23, 12) 1055 1056 enum HTT_PPDU_STATS_BW { 1057 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1058 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1059 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1060 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1061 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1062 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1063 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1064 }; 1065 1066 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1067 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1068 /* bw - HTT_PPDU_STATS_BW */ 1069 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1070 1071 struct htt_ppdu_stats_common { 1072 u32 ppdu_id; 1073 u16 sched_cmdid; 1074 u8 ring_id; 1075 u8 num_users; 1076 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1077 u32 chain_mask; 1078 u32 fes_duration_us; /* frame exchange sequence */ 1079 u32 ppdu_sch_eval_start_tstmp_us; 1080 u32 ppdu_sch_end_tstmp_us; 1081 u32 ppdu_start_tstmp_us; 1082 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1083 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1084 */ 1085 u16 phy_mode; 1086 u16 bw_mhz; 1087 } __packed; 1088 1089 enum htt_ppdu_stats_gi { 1090 HTT_PPDU_STATS_SGI_0_8_US, 1091 HTT_PPDU_STATS_SGI_0_4_US, 1092 HTT_PPDU_STATS_SGI_1_6_US, 1093 HTT_PPDU_STATS_SGI_3_2_US, 1094 }; 1095 1096 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1097 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1098 1099 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1100 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1101 1102 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1103 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1104 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1105 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1106 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1107 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1108 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1109 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1110 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1111 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1112 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1113 1114 #define HTT_USR_RATE_PREAMBLE(_val) \ 1115 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1116 #define HTT_USR_RATE_BW(_val) \ 1117 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1118 #define HTT_USR_RATE_NSS(_val) \ 1119 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1120 #define HTT_USR_RATE_MCS(_val) \ 1121 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1122 #define HTT_USR_RATE_GI(_val) \ 1123 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1124 #define HTT_USR_RATE_DCM(_val) \ 1125 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1126 1127 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1128 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1129 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1130 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1131 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1132 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1133 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1134 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1135 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1136 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1137 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1138 1139 struct htt_ppdu_stats_user_rate { 1140 u8 tid_num; 1141 u8 reserved0; 1142 u16 sw_peer_id; 1143 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1144 u16 ru_end; 1145 u16 ru_start; 1146 u16 resp_ru_end; 1147 u16 resp_ru_start; 1148 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1149 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1150 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1151 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1152 } __packed; 1153 1154 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1155 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1156 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1157 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1158 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1159 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1160 1161 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1162 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1163 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1164 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1165 #define HTT_TX_INFO_RATECODE(_flags) \ 1166 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1167 #define HTT_TX_INFO_PEERID(_flags) \ 1168 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1169 1170 struct htt_tx_ppdu_stats_info { 1171 struct htt_tlv tlv_hdr; 1172 u32 tx_success_bytes; 1173 u32 tx_retry_bytes; 1174 u32 tx_failed_bytes; 1175 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1176 u16 tx_success_msdus; 1177 u16 tx_retry_msdus; 1178 u16 tx_failed_msdus; 1179 u16 tx_duration; /* united in us */ 1180 } __packed; 1181 1182 enum htt_ppdu_stats_usr_compln_status { 1183 HTT_PPDU_STATS_USER_STATUS_OK, 1184 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1185 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1186 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1187 HTT_PPDU_STATS_USER_STATUS_ABORT, 1188 }; 1189 1190 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1191 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1192 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1193 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1194 1195 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1196 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1197 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1198 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1199 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1200 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1201 1202 struct htt_ppdu_stats_usr_cmpltn_cmn { 1203 u8 status; 1204 u8 tid_num; 1205 u16 sw_peer_id; 1206 /* RSSI value of last ack packet (units = dB above noise floor) */ 1207 u32 ack_rssi; 1208 u16 mpdu_tried; 1209 u16 mpdu_success; 1210 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1211 } __packed; 1212 1213 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1214 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1215 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1216 1217 #define HTT_PPDU_STATS_NON_QOS_TID 16 1218 1219 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1220 u32 ppdu_id; 1221 u16 sw_peer_id; 1222 u16 reserved0; 1223 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1224 u16 current_seq; 1225 u16 start_seq; 1226 u32 success_bytes; 1227 } __packed; 1228 1229 struct htt_ppdu_stats_usr_cmn_array { 1230 struct htt_tlv tlv_hdr; 1231 u32 num_ppdu_stats; 1232 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1233 * elements. 1234 * tx_ppdu_stats_info is variable length, with length = 1235 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1236 */ 1237 struct htt_tx_ppdu_stats_info tx_ppdu_info[0]; 1238 } __packed; 1239 1240 struct htt_ppdu_user_stats { 1241 u16 peer_id; 1242 u32 tlv_flags; 1243 bool is_valid_peer_id; 1244 struct htt_ppdu_stats_user_rate rate; 1245 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1246 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1247 }; 1248 1249 #define HTT_PPDU_STATS_MAX_USERS 8 1250 #define HTT_PPDU_DESC_MAX_DEPTH 16 1251 1252 struct htt_ppdu_stats { 1253 struct htt_ppdu_stats_common common; 1254 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1255 }; 1256 1257 struct htt_ppdu_stats_info { 1258 u32 ppdu_id; 1259 struct htt_ppdu_stats ppdu_stats; 1260 struct list_head list; 1261 }; 1262 1263 /** 1264 * @brief target -> host packet log message 1265 * 1266 * @details 1267 * The following field definitions describe the format of the packet log 1268 * message sent from the target to the host. 1269 * The message consists of a 4-octet header,followed by a variable number 1270 * of 32-bit character values. 1271 * 1272 * |31 16|15 12|11 10|9 8|7 0| 1273 * |------------------------------------------------------------------| 1274 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1275 * |------------------------------------------------------------------| 1276 * | payload | 1277 * |------------------------------------------------------------------| 1278 * - MSG_TYPE 1279 * Bits 7:0 1280 * Purpose: identifies this as a pktlog message 1281 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1282 * - mac_id 1283 * Bits 9:8 1284 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1285 * Value: 0-3 1286 * - pdev_id 1287 * Bits 11:10 1288 * Purpose: pdev_id 1289 * Value: 0-3 1290 * 0 (for rings at SOC level), 1291 * 1/2/3 PDEV -> 0/1/2 1292 * - payload_size 1293 * Bits 31:16 1294 * Purpose: explicitly specify the payload size 1295 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1296 */ 1297 struct htt_pktlog_msg { 1298 u32 hdr; 1299 u8 payload[0]; 1300 }; 1301 1302 /** 1303 * @brief host -> target FW extended statistics retrieve 1304 * 1305 * @details 1306 * The following field definitions describe the format of the HTT host 1307 * to target FW extended stats retrieve message. 1308 * The message specifies the type of stats the host wants to retrieve. 1309 * 1310 * |31 24|23 16|15 8|7 0| 1311 * |-----------------------------------------------------------| 1312 * | reserved | stats type | pdev_mask | msg type | 1313 * |-----------------------------------------------------------| 1314 * | config param [0] | 1315 * |-----------------------------------------------------------| 1316 * | config param [1] | 1317 * |-----------------------------------------------------------| 1318 * | config param [2] | 1319 * |-----------------------------------------------------------| 1320 * | config param [3] | 1321 * |-----------------------------------------------------------| 1322 * | reserved | 1323 * |-----------------------------------------------------------| 1324 * | cookie LSBs | 1325 * |-----------------------------------------------------------| 1326 * | cookie MSBs | 1327 * |-----------------------------------------------------------| 1328 * Header fields: 1329 * - MSG_TYPE 1330 * Bits 7:0 1331 * Purpose: identifies this is a extended stats upload request message 1332 * Value: 0x10 1333 * - PDEV_MASK 1334 * Bits 8:15 1335 * Purpose: identifies the mask of PDEVs to retrieve stats from 1336 * Value: This is a overloaded field, refer to usage and interpretation of 1337 * PDEV in interface document. 1338 * Bit 8 : Reserved for SOC stats 1339 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1340 * Indicates MACID_MASK in DBS 1341 * - STATS_TYPE 1342 * Bits 23:16 1343 * Purpose: identifies which FW statistics to upload 1344 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1345 * - Reserved 1346 * Bits 31:24 1347 * - CONFIG_PARAM [0] 1348 * Bits 31:0 1349 * Purpose: give an opaque configuration value to the specified stats type 1350 * Value: stats-type specific configuration value 1351 * Refer to htt_stats.h for interpretation for each stats sub_type 1352 * - CONFIG_PARAM [1] 1353 * Bits 31:0 1354 * Purpose: give an opaque configuration value to the specified stats type 1355 * Value: stats-type specific configuration value 1356 * Refer to htt_stats.h for interpretation for each stats sub_type 1357 * - CONFIG_PARAM [2] 1358 * Bits 31:0 1359 * Purpose: give an opaque configuration value to the specified stats type 1360 * Value: stats-type specific configuration value 1361 * Refer to htt_stats.h for interpretation for each stats sub_type 1362 * - CONFIG_PARAM [3] 1363 * Bits 31:0 1364 * Purpose: give an opaque configuration value to the specified stats type 1365 * Value: stats-type specific configuration value 1366 * Refer to htt_stats.h for interpretation for each stats sub_type 1367 * - Reserved [31:0] for future use. 1368 * - COOKIE_LSBS 1369 * Bits 31:0 1370 * Purpose: Provide a mechanism to match a target->host stats confirmation 1371 * message with its preceding host->target stats request message. 1372 * Value: LSBs of the opaque cookie specified by the host-side requestor 1373 * - COOKIE_MSBS 1374 * Bits 31:0 1375 * Purpose: Provide a mechanism to match a target->host stats confirmation 1376 * message with its preceding host->target stats request message. 1377 * Value: MSBs of the opaque cookie specified by the host-side requestor 1378 */ 1379 1380 struct htt_ext_stats_cfg_hdr { 1381 u8 msg_type; 1382 u8 pdev_mask; 1383 u8 stats_type; 1384 u8 reserved; 1385 } __packed; 1386 1387 struct htt_ext_stats_cfg_cmd { 1388 struct htt_ext_stats_cfg_hdr hdr; 1389 u32 cfg_param0; 1390 u32 cfg_param1; 1391 u32 cfg_param2; 1392 u32 cfg_param3; 1393 u32 reserved; 1394 u32 cookie_lsb; 1395 u32 cookie_msb; 1396 } __packed; 1397 1398 /* htt stats config default params */ 1399 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1400 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1401 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1402 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1403 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1404 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1405 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1406 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1407 1408 /* HTT_DBG_EXT_STATS_PEER_INFO 1409 * PARAMS: 1410 * @config_param0: 1411 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1412 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1413 * [Bit31 : Bit16] sw_peer_id 1414 * @config_param1: 1415 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1416 * 0 bit htt_peer_stats_cmn_tlv 1417 * 1 bit htt_peer_details_tlv 1418 * 2 bit htt_tx_peer_rate_stats_tlv 1419 * 3 bit htt_rx_peer_rate_stats_tlv 1420 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1421 * 5 bit htt_rx_tid_stats_tlv 1422 * 6 bit htt_msdu_flow_stats_tlv 1423 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1424 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1425 * [Bit31 : Bit16] reserved 1426 */ 1427 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1428 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1429 1430 /* Used to set different configs to the specified stats type.*/ 1431 struct htt_ext_stats_cfg_params { 1432 u32 cfg0; 1433 u32 cfg1; 1434 u32 cfg2; 1435 u32 cfg3; 1436 }; 1437 1438 /** 1439 * @brief target -> host extended statistics upload 1440 * 1441 * @details 1442 * The following field definitions describe the format of the HTT target 1443 * to host stats upload confirmation message. 1444 * The message contains a cookie echoed from the HTT host->target stats 1445 * upload request, which identifies which request the confirmation is 1446 * for, and a single stats can span over multiple HTT stats indication 1447 * due to the HTT message size limitation so every HTT ext stats indication 1448 * will have tag-length-value stats information elements. 1449 * The tag-length header for each HTT stats IND message also includes a 1450 * status field, to indicate whether the request for the stat type in 1451 * question was fully met, partially met, unable to be met, or invalid 1452 * (if the stat type in question is disabled in the target). 1453 * A Done bit 1's indicate the end of the of stats info elements. 1454 * 1455 * 1456 * |31 16|15 12|11|10 8|7 5|4 0| 1457 * |--------------------------------------------------------------| 1458 * | reserved | msg type | 1459 * |--------------------------------------------------------------| 1460 * | cookie LSBs | 1461 * |--------------------------------------------------------------| 1462 * | cookie MSBs | 1463 * |--------------------------------------------------------------| 1464 * | stats entry length | rsvd | D| S | stat type | 1465 * |--------------------------------------------------------------| 1466 * | type-specific stats info | 1467 * | (see htt_stats.h) | 1468 * |--------------------------------------------------------------| 1469 * Header fields: 1470 * - MSG_TYPE 1471 * Bits 7:0 1472 * Purpose: Identifies this is a extended statistics upload confirmation 1473 * message. 1474 * Value: 0x1c 1475 * - COOKIE_LSBS 1476 * Bits 31:0 1477 * Purpose: Provide a mechanism to match a target->host stats confirmation 1478 * message with its preceding host->target stats request message. 1479 * Value: LSBs of the opaque cookie specified by the host-side requestor 1480 * - COOKIE_MSBS 1481 * Bits 31:0 1482 * Purpose: Provide a mechanism to match a target->host stats confirmation 1483 * message with its preceding host->target stats request message. 1484 * Value: MSBs of the opaque cookie specified by the host-side requestor 1485 * 1486 * Stats Information Element tag-length header fields: 1487 * - STAT_TYPE 1488 * Bits 7:0 1489 * Purpose: identifies the type of statistics info held in the 1490 * following information element 1491 * Value: htt_dbg_ext_stats_type 1492 * - STATUS 1493 * Bits 10:8 1494 * Purpose: indicate whether the requested stats are present 1495 * Value: htt_dbg_ext_stats_status 1496 * - DONE 1497 * Bits 11 1498 * Purpose: 1499 * Indicates the completion of the stats entry, this will be the last 1500 * stats conf HTT segment for the requested stats type. 1501 * Value: 1502 * 0 -> the stats retrieval is ongoing 1503 * 1 -> the stats retrieval is complete 1504 * - LENGTH 1505 * Bits 31:16 1506 * Purpose: indicate the stats information size 1507 * Value: This field specifies the number of bytes of stats information 1508 * that follows the element tag-length header. 1509 * It is expected but not required that this length is a multiple of 1510 * 4 bytes. 1511 */ 1512 1513 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1514 1515 struct ath11k_htt_extd_stats_msg { 1516 u32 info0; 1517 u64 cookie; 1518 u32 info1; 1519 u8 data[0]; 1520 } __packed; 1521 1522 struct htt_mac_addr { 1523 u32 mac_addr_l32; 1524 u32 mac_addr_h16; 1525 }; 1526 1527 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1528 { 1529 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1530 addr_l32 = swab32(addr_l32); 1531 addr_h16 = swab16(addr_h16); 1532 } 1533 1534 memcpy(addr, &addr_l32, 4); 1535 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1536 } 1537 1538 int ath11k_dp_service_srng(struct ath11k_base *ab, 1539 struct ath11k_ext_irq_grp *irq_grp, 1540 int budget); 1541 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1542 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1543 void ath11k_dp_free(struct ath11k_base *ab); 1544 int ath11k_dp_alloc(struct ath11k_base *ab); 1545 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1546 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1547 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1548 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1549 int mac_id, enum hal_ring_type ring_type); 1550 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1551 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1552 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1553 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1554 enum hal_ring_type type, int ring_num, 1555 int mac_id, int num_entries); 1556 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1557 struct dp_link_desc_bank *desc_bank, 1558 u32 ring_type, struct dp_srng *ring); 1559 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1560 struct dp_link_desc_bank *link_desc_banks, 1561 u32 ring_type, struct hal_srng *srng, 1562 u32 n_link_desc); 1563 1564 #endif 1565