1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_DP_H 8 #define ATH11K_DP_H 9 10 #include "hal_rx.h" 11 12 #define MAX_RXDMA_PER_PDEV 2 13 14 struct ath11k_base; 15 struct ath11k_peer; 16 struct ath11k_dp; 17 struct ath11k_vif; 18 struct hal_tcl_status_ring; 19 struct ath11k_ext_irq_grp; 20 21 struct dp_rx_tid { 22 u8 tid; 23 u32 *vaddr; 24 dma_addr_t paddr; 25 u32 size; 26 u32 ba_win_sz; 27 bool active; 28 29 /* Info related to rx fragments */ 30 u32 cur_sn; 31 u16 last_frag_no; 32 u16 rx_frag_bitmap; 33 34 struct sk_buff_head rx_frags; 35 struct hal_reo_dest_ring *dst_ring_desc; 36 37 /* Timer info related to fragments */ 38 struct timer_list frag_timer; 39 struct ath11k_base *ab; 40 }; 41 42 #define DP_REO_DESC_FREE_THRESHOLD 64 43 #define DP_REO_DESC_FREE_TIMEOUT_MS 1000 44 #define DP_MON_PURGE_TIMEOUT_MS 100 45 #define DP_MON_SERVICE_BUDGET 128 46 47 struct dp_reo_cache_flush_elem { 48 struct list_head list; 49 struct dp_rx_tid data; 50 unsigned long ts; 51 }; 52 53 struct dp_reo_cmd { 54 struct list_head list; 55 struct dp_rx_tid data; 56 int cmd_num; 57 void (*handler)(struct ath11k_dp *, void *, 58 enum hal_reo_cmd_status status); 59 }; 60 61 struct dp_srng { 62 u32 *vaddr_unaligned; 63 u32 *vaddr; 64 dma_addr_t paddr_unaligned; 65 dma_addr_t paddr; 66 int size; 67 u32 ring_id; 68 u8 cached; 69 }; 70 71 struct dp_rxdma_ring { 72 struct dp_srng refill_buf_ring; 73 struct idr bufs_idr; 74 /* Protects bufs_idr */ 75 spinlock_t idr_lock; 76 int bufs_max; 77 }; 78 79 #define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 80 81 struct dp_tx_ring { 82 u8 tcl_data_ring_id; 83 struct dp_srng tcl_data_ring; 84 struct dp_srng tcl_comp_ring; 85 struct idr txbuf_idr; 86 /* Protects txbuf_idr and num_pending */ 87 spinlock_t tx_idr_lock; 88 struct hal_wbm_release_ring *tx_status; 89 int tx_status_head; 90 int tx_status_tail; 91 }; 92 93 enum dp_mon_status_buf_state { 94 /* PPDU id matches in dst ring and status ring */ 95 DP_MON_STATUS_MATCH, 96 /* status ring dma is not done */ 97 DP_MON_STATUS_NO_DMA, 98 /* status ring is lagging, reap status ring */ 99 DP_MON_STATUS_LAG, 100 /* status ring is leading, reap dst ring and drop */ 101 DP_MON_STATUS_LEAD, 102 /* replinish monitor status ring */ 103 DP_MON_STATUS_REPLINISH, 104 }; 105 106 struct ath11k_pdev_mon_stats { 107 u32 status_ppdu_state; 108 u32 status_ppdu_start; 109 u32 status_ppdu_end; 110 u32 status_ppdu_compl; 111 u32 status_ppdu_start_mis; 112 u32 status_ppdu_end_mis; 113 u32 status_ppdu_done; 114 u32 dest_ppdu_done; 115 u32 dest_mpdu_done; 116 u32 dest_mpdu_drop; 117 u32 dup_mon_linkdesc_cnt; 118 u32 dup_mon_buf_cnt; 119 u32 dest_mon_stuck; 120 u32 dest_mon_not_reaped; 121 }; 122 123 struct dp_full_mon_mpdu { 124 struct list_head list; 125 struct sk_buff *head; 126 struct sk_buff *tail; 127 }; 128 129 struct dp_link_desc_bank { 130 void *vaddr_unaligned; 131 void *vaddr; 132 dma_addr_t paddr_unaligned; 133 dma_addr_t paddr; 134 u32 size; 135 }; 136 137 /* Size to enforce scatter idle list mode */ 138 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 139 #define DP_LINK_DESC_BANKS_MAX 8 140 141 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 142 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 143 #define DP_RX_DESC_COOKIE_MAX \ 144 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 145 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 146 147 enum ath11k_dp_ppdu_state { 148 DP_PPDU_STATUS_START, 149 DP_PPDU_STATUS_DONE, 150 }; 151 152 struct ath11k_mon_data { 153 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 154 struct hal_rx_mon_ppdu_info mon_ppdu_info; 155 156 u32 mon_ppdu_status; 157 u32 mon_last_buf_cookie; 158 u64 mon_last_linkdesc_paddr; 159 u16 chan_noise_floor; 160 bool hold_mon_dst_ring; 161 enum dp_mon_status_buf_state buf_state; 162 dma_addr_t mon_status_paddr; 163 struct dp_full_mon_mpdu *mon_mpdu; 164 struct hal_sw_mon_ring_entries sw_mon_entries; 165 struct ath11k_pdev_mon_stats rx_mon_stats; 166 /* lock for monitor data */ 167 spinlock_t mon_lock; 168 struct sk_buff_head rx_status_q; 169 }; 170 171 struct ath11k_pdev_dp { 172 u32 mac_id; 173 u32 mon_dest_ring_stuck_cnt; 174 atomic_t num_tx_pending; 175 wait_queue_head_t tx_empty_waitq; 176 struct dp_rxdma_ring rx_refill_buf_ring; 177 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 178 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 179 struct dp_srng rxdma_mon_dst_ring; 180 struct dp_srng rxdma_mon_desc_ring; 181 182 struct dp_rxdma_ring rxdma_mon_buf_ring; 183 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 184 struct ieee80211_rx_status rx_status; 185 struct ath11k_mon_data mon_data; 186 }; 187 188 #define DP_NUM_CLIENTS_MAX 64 189 #define DP_AVG_TIDS_PER_CLIENT 2 190 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 191 #define DP_AVG_MSDUS_PER_FLOW 128 192 #define DP_AVG_FLOWS_PER_TID 2 193 #define DP_AVG_MPDUS_PER_TID_MAX 128 194 #define DP_AVG_MSDUS_PER_MPDU 4 195 196 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 197 198 #define DP_BA_WIN_SZ_MAX 256 199 200 #define DP_TCL_NUM_RING_MAX 3 201 #define DP_TCL_NUM_RING_MAX_QCA6390 1 202 203 #define DP_IDLE_SCATTER_BUFS_MAX 16 204 205 #define DP_WBM_RELEASE_RING_SIZE 64 206 #define DP_TCL_DATA_RING_SIZE 512 207 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048 208 #define DP_TX_COMP_RING_SIZE 32768 209 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 210 #define DP_TCL_CMD_RING_SIZE 32 211 #define DP_TCL_STATUS_RING_SIZE 32 212 #define DP_REO_DST_RING_MAX 4 213 #define DP_REO_DST_RING_SIZE 2048 214 #define DP_REO_REINJECT_RING_SIZE 32 215 #define DP_RX_RELEASE_RING_SIZE 1024 216 #define DP_REO_EXCEPTION_RING_SIZE 128 217 #define DP_REO_CMD_RING_SIZE 128 218 #define DP_REO_STATUS_RING_SIZE 2048 219 #define DP_RXDMA_BUF_RING_SIZE 4096 220 #define DP_RXDMA_REFILL_RING_SIZE 2048 221 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 222 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 223 #define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 224 #define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 225 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 226 227 #define DP_RX_RELEASE_RING_NUM 3 228 229 #define DP_RX_BUFFER_SIZE 2048 230 #define DP_RX_BUFFER_SIZE_LITE 1024 231 #define DP_RX_BUFFER_ALIGN_SIZE 128 232 233 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 234 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 235 236 #define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 237 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 238 239 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 240 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 241 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 242 243 #define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 244 #define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 245 246 struct ath11k_hp_update_timer { 247 struct timer_list timer; 248 bool started; 249 bool init; 250 u32 tx_num; 251 u32 timer_tx_num; 252 u32 ring_id; 253 u32 interval; 254 struct ath11k_base *ab; 255 }; 256 257 struct ath11k_dp { 258 struct ath11k_base *ab; 259 enum ath11k_htc_ep_id eid; 260 struct completion htt_tgt_version_received; 261 u8 htt_tgt_ver_major; 262 u8 htt_tgt_ver_minor; 263 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 264 struct dp_srng wbm_idle_ring; 265 struct dp_srng wbm_desc_rel_ring; 266 struct dp_srng tcl_cmd_ring; 267 struct dp_srng tcl_status_ring; 268 struct dp_srng reo_reinject_ring; 269 struct dp_srng rx_rel_ring; 270 struct dp_srng reo_except_ring; 271 struct dp_srng reo_cmd_ring; 272 struct dp_srng reo_status_ring; 273 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 274 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 275 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 276 struct list_head reo_cmd_list; 277 struct list_head reo_cmd_cache_flush_list; 278 struct list_head dp_full_mon_mpdu_list; 279 u32 reo_cmd_cache_flush_count; 280 /** 281 * protects access to below fields, 282 * - reo_cmd_list 283 * - reo_cmd_cache_flush_list 284 * - reo_cmd_cache_flush_count 285 */ 286 spinlock_t reo_cmd_lock; 287 struct ath11k_hp_update_timer reo_cmd_timer; 288 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 289 }; 290 291 /* HTT definitions */ 292 293 #define HTT_TCL_META_DATA_TYPE BIT(0) 294 #define HTT_TCL_META_DATA_VALID_HTT BIT(1) 295 296 /* vdev meta data */ 297 #define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 298 #define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 299 #define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 300 301 /* peer meta data */ 302 #define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 303 304 #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 305 306 /* HTT tx completion is overlaid in wbm_release_ring */ 307 #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 308 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 309 #define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 310 311 #define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 312 313 struct htt_tx_wbm_completion { 314 u32 info0; 315 u32 info1; 316 u32 info2; 317 u32 info3; 318 } __packed; 319 320 enum htt_h2t_msg_type { 321 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 322 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 323 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 324 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 325 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 326 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 327 }; 328 329 #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 330 331 struct htt_ver_req_cmd { 332 u32 ver_reg_info; 333 } __packed; 334 335 enum htt_srng_ring_type { 336 HTT_HW_TO_SW_RING, 337 HTT_SW_TO_HW_RING, 338 HTT_SW_TO_SW_RING, 339 }; 340 341 enum htt_srng_ring_id { 342 HTT_RXDMA_HOST_BUF_RING, 343 HTT_RXDMA_MONITOR_STATUS_RING, 344 HTT_RXDMA_MONITOR_BUF_RING, 345 HTT_RXDMA_MONITOR_DESC_RING, 346 HTT_RXDMA_MONITOR_DEST_RING, 347 HTT_HOST1_TO_FW_RXBUF_RING, 348 HTT_HOST2_TO_FW_RXBUF_RING, 349 HTT_RXDMA_NON_MONITOR_DEST_RING, 350 }; 351 352 /* host -> target HTT_SRING_SETUP message 353 * 354 * After target is booted up, Host can send SRING setup message for 355 * each host facing LMAC SRING. Target setups up HW registers based 356 * on setup message and confirms back to Host if response_required is set. 357 * Host should wait for confirmation message before sending new SRING 358 * setup message 359 * 360 * The message would appear as follows: 361 * 362 * |31 24|23 20|19|18 16|15|14 8|7 0| 363 * |--------------- +-----------------+----------------+------------------| 364 * | ring_type | ring_id | pdev_id | msg_type | 365 * |----------------------------------------------------------------------| 366 * | ring_base_addr_lo | 367 * |----------------------------------------------------------------------| 368 * | ring_base_addr_hi | 369 * |----------------------------------------------------------------------| 370 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 371 * |----------------------------------------------------------------------| 372 * | ring_head_offset32_remote_addr_lo | 373 * |----------------------------------------------------------------------| 374 * | ring_head_offset32_remote_addr_hi | 375 * |----------------------------------------------------------------------| 376 * | ring_tail_offset32_remote_addr_lo | 377 * |----------------------------------------------------------------------| 378 * | ring_tail_offset32_remote_addr_hi | 379 * |----------------------------------------------------------------------| 380 * | ring_msi_addr_lo | 381 * |----------------------------------------------------------------------| 382 * | ring_msi_addr_hi | 383 * |----------------------------------------------------------------------| 384 * | ring_msi_data | 385 * |----------------------------------------------------------------------| 386 * | intr_timer_th |IM| intr_batch_counter_th | 387 * |----------------------------------------------------------------------| 388 * | reserved |RR|PTCF| intr_low_threshold | 389 * |----------------------------------------------------------------------| 390 * Where 391 * IM = sw_intr_mode 392 * RR = response_required 393 * PTCF = prefetch_timer_cfg 394 * 395 * The message is interpreted as follows: 396 * dword0 - b'0:7 - msg_type: This will be set to 397 * HTT_H2T_MSG_TYPE_SRING_SETUP 398 * b'8:15 - pdev_id: 399 * 0 (for rings at SOC/UMAC level), 400 * 1/2/3 mac id (for rings at LMAC level) 401 * b'16:23 - ring_id: identify which ring is to setup, 402 * more details can be got from enum htt_srng_ring_id 403 * b'24:31 - ring_type: identify type of host rings, 404 * more details can be got from enum htt_srng_ring_type 405 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 406 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 407 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 408 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 409 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 410 * SW_TO_HW_RING. 411 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 412 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 413 * Lower 32 bits of memory address of the remote variable 414 * storing the 4-byte word offset that identifies the head 415 * element within the ring. 416 * (The head offset variable has type u32.) 417 * Valid for HW_TO_SW and SW_TO_SW rings. 418 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 419 * Upper 32 bits of memory address of the remote variable 420 * storing the 4-byte word offset that identifies the head 421 * element within the ring. 422 * (The head offset variable has type u32.) 423 * Valid for HW_TO_SW and SW_TO_SW rings. 424 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 425 * Lower 32 bits of memory address of the remote variable 426 * storing the 4-byte word offset that identifies the tail 427 * element within the ring. 428 * (The tail offset variable has type u32.) 429 * Valid for HW_TO_SW and SW_TO_SW rings. 430 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 431 * Upper 32 bits of memory address of the remote variable 432 * storing the 4-byte word offset that identifies the tail 433 * element within the ring. 434 * (The tail offset variable has type u32.) 435 * Valid for HW_TO_SW and SW_TO_SW rings. 436 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 437 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 438 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 439 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 440 * dword10 - b'0:31 - ring_msi_data: MSI data 441 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 442 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 443 * dword11 - b'0:14 - intr_batch_counter_th: 444 * batch counter threshold is in units of 4-byte words. 445 * HW internally maintains and increments batch count. 446 * (see SRING spec for detail description). 447 * When batch count reaches threshold value, an interrupt 448 * is generated by HW. 449 * b'15 - sw_intr_mode: 450 * This configuration shall be static. 451 * Only programmed at power up. 452 * 0: generate pulse style sw interrupts 453 * 1: generate level style sw interrupts 454 * b'16:31 - intr_timer_th: 455 * The timer init value when timer is idle or is 456 * initialized to start downcounting. 457 * In 8us units (to cover a range of 0 to 524 ms) 458 * dword12 - b'0:15 - intr_low_threshold: 459 * Used only by Consumer ring to generate ring_sw_int_p. 460 * Ring entries low threshold water mark, that is used 461 * in combination with the interrupt timer as well as 462 * the clearing of the level interrupt. 463 * b'16:18 - prefetch_timer_cfg: 464 * Used only by Consumer ring to set timer mode to 465 * support Application prefetch handling. 466 * The external tail offset/pointer will be updated 467 * at following intervals: 468 * 3'b000: (Prefetch feature disabled; used only for debug) 469 * 3'b001: 1 usec 470 * 3'b010: 4 usec 471 * 3'b011: 8 usec (default) 472 * 3'b100: 16 usec 473 * Others: Reserved 474 * b'19 - response_required: 475 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 476 * b'20:31 - reserved: reserved for future use 477 */ 478 479 #define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 480 #define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 481 #define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 482 #define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 483 484 #define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 485 #define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 486 #define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 487 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 488 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 489 #define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 490 491 #define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 492 #define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 493 #define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 494 495 #define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 496 #define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 497 #define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 498 499 struct htt_srng_setup_cmd { 500 u32 info0; 501 u32 ring_base_addr_lo; 502 u32 ring_base_addr_hi; 503 u32 info1; 504 u32 ring_head_off32_remote_addr_lo; 505 u32 ring_head_off32_remote_addr_hi; 506 u32 ring_tail_off32_remote_addr_lo; 507 u32 ring_tail_off32_remote_addr_hi; 508 u32 ring_msi_addr_lo; 509 u32 ring_msi_addr_hi; 510 u32 msi_data; 511 u32 intr_info; 512 u32 info2; 513 } __packed; 514 515 /* host -> target FW PPDU_STATS config message 516 * 517 * @details 518 * The following field definitions describe the format of the HTT host 519 * to target FW for PPDU_STATS_CFG msg. 520 * The message allows the host to configure the PPDU_STATS_IND messages 521 * produced by the target. 522 * 523 * |31 24|23 16|15 8|7 0| 524 * |-----------------------------------------------------------| 525 * | REQ bit mask | pdev_mask | msg type | 526 * |-----------------------------------------------------------| 527 * Header fields: 528 * - MSG_TYPE 529 * Bits 7:0 530 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 531 * Value: 0x11 532 * - PDEV_MASK 533 * Bits 8:15 534 * Purpose: identifies which pdevs this PPDU stats configuration applies to 535 * Value: This is a overloaded field, refer to usage and interpretation of 536 * PDEV in interface document. 537 * Bit 8 : Reserved for SOC stats 538 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 539 * Indicates MACID_MASK in DBS 540 * - REQ_TLV_BIT_MASK 541 * Bits 16:31 542 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 543 * needs to be included in the target's PPDU_STATS_IND messages. 544 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 545 * 546 */ 547 548 struct htt_ppdu_stats_cfg_cmd { 549 u32 msg; 550 } __packed; 551 552 #define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 553 #define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 554 #define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 555 #define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 556 557 enum htt_ppdu_stats_tag_type { 558 HTT_PPDU_STATS_TAG_COMMON, 559 HTT_PPDU_STATS_TAG_USR_COMMON, 560 HTT_PPDU_STATS_TAG_USR_RATE, 561 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 562 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 563 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 564 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 565 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 566 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 567 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 568 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 569 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 570 HTT_PPDU_STATS_TAG_INFO, 571 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 572 573 /* New TLV's are added above to this line */ 574 HTT_PPDU_STATS_TAG_MAX, 575 }; 576 577 #define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 578 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 579 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 580 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 581 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 582 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 583 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 584 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 585 586 #define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 587 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 588 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 589 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 590 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 591 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 592 HTT_PPDU_STATS_TAG_DEFAULT) 593 594 /* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 595 * 596 * details: 597 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 598 * configure RXDMA rings. 599 * The configuration is per ring based and includes both packet subtypes 600 * and PPDU/MPDU TLVs. 601 * 602 * The message would appear as follows: 603 * 604 * |31 26|25|24|23 16|15 8|7 0| 605 * |-----------------+----------------+----------------+---------------| 606 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 607 * |-------------------------------------------------------------------| 608 * | rsvd2 | ring_buffer_size | 609 * |-------------------------------------------------------------------| 610 * | packet_type_enable_flags_0 | 611 * |-------------------------------------------------------------------| 612 * | packet_type_enable_flags_1 | 613 * |-------------------------------------------------------------------| 614 * | packet_type_enable_flags_2 | 615 * |-------------------------------------------------------------------| 616 * | packet_type_enable_flags_3 | 617 * |-------------------------------------------------------------------| 618 * | tlv_filter_in_flags | 619 * |-------------------------------------------------------------------| 620 * Where: 621 * PS = pkt_swap 622 * SS = status_swap 623 * The message is interpreted as follows: 624 * dword0 - b'0:7 - msg_type: This will be set to 625 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 626 * b'8:15 - pdev_id: 627 * 0 (for rings at SOC/UMAC level), 628 * 1/2/3 mac id (for rings at LMAC level) 629 * b'16:23 - ring_id : Identify the ring to configure. 630 * More details can be got from enum htt_srng_ring_id 631 * b'24 - status_swap: 1 is to swap status TLV 632 * b'25 - pkt_swap: 1 is to swap packet TLV 633 * b'26:31 - rsvd1: reserved for future use 634 * dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring, 635 * in byte units. 636 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 637 * - b'16:31 - rsvd2: Reserved for future use 638 * dword2 - b'0:31 - packet_type_enable_flags_0: 639 * Enable MGMT packet from 0b0000 to 0b1001 640 * bits from low to high: FP, MD, MO - 3 bits 641 * FP: Filter_Pass 642 * MD: Monitor_Direct 643 * MO: Monitor_Other 644 * 10 mgmt subtypes * 3 bits -> 30 bits 645 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 646 * dword3 - b'0:31 - packet_type_enable_flags_1: 647 * Enable MGMT packet from 0b1010 to 0b1111 648 * bits from low to high: FP, MD, MO - 3 bits 649 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 650 * dword4 - b'0:31 - packet_type_enable_flags_2: 651 * Enable CTRL packet from 0b0000 to 0b1001 652 * bits from low to high: FP, MD, MO - 3 bits 653 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 654 * dword5 - b'0:31 - packet_type_enable_flags_3: 655 * Enable CTRL packet from 0b1010 to 0b1111, 656 * MCAST_DATA, UCAST_DATA, NULL_DATA 657 * bits from low to high: FP, MD, MO - 3 bits 658 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 659 * dword6 - b'0:31 - tlv_filter_in_flags: 660 * Filter in Attention/MPDU/PPDU/Header/User tlvs 661 * Refer to CFG_TLV_FILTER_IN_FLAG defs 662 */ 663 664 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 665 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 666 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 667 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 668 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 669 670 #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 671 672 enum htt_rx_filter_tlv_flags { 673 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 674 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 675 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 676 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 677 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 678 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 679 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 680 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 681 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 682 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 683 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 684 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 685 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 686 }; 687 688 enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 689 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 690 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 691 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 692 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 693 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 694 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 695 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 696 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 697 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 698 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 699 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 700 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 701 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 702 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 703 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 704 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 705 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 706 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 707 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 708 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 709 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 710 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 711 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 712 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 713 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 714 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 715 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 716 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 717 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 718 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 719 }; 720 721 enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 722 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 723 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 724 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 725 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 726 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 727 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 728 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 729 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 730 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 731 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 732 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 733 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 734 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 735 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 736 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 737 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 738 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 739 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 740 }; 741 742 enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 743 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 744 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 745 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 746 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 747 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 748 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 749 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 750 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 751 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 752 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 753 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 754 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 755 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 756 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 757 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 758 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 759 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 760 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 761 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 762 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 763 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 764 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 765 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 766 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 767 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 768 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 769 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 770 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 771 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 772 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 773 }; 774 775 enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 776 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 777 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 778 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 779 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 780 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 781 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 782 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 783 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 784 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 785 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 786 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 787 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 788 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 789 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 790 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 791 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 792 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 793 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 794 }; 795 796 enum htt_rx_data_pkt_filter_tlv_flasg3 { 797 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 798 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 799 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 800 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 801 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 802 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 803 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 804 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 805 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 806 }; 807 808 #define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 809 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 810 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 811 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 812 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 813 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 814 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 815 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 816 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 817 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 818 819 #define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 820 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 821 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 822 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 823 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 824 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 825 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 826 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 827 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 828 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 829 830 #define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 831 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 832 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 833 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 834 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 835 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 836 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 837 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 838 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 839 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 840 841 #define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 842 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 843 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 844 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 845 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 846 847 #define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 848 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 849 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 850 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 851 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 852 853 #define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 854 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 855 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 856 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 857 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 858 859 #define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 860 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 861 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 862 863 #define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 864 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 865 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 866 867 #define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 868 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 869 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 870 871 #define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 872 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 873 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 874 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 875 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 876 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 877 878 #define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 879 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 880 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 881 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 882 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 883 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 884 885 #define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 886 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 887 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 888 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 889 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 890 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 891 892 #define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 893 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 894 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 895 896 #define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 897 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 898 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 899 900 #define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 901 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 902 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 903 904 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 905 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 906 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 907 908 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 909 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 910 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 911 912 #define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 913 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 914 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 915 916 #define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 917 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 918 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 919 920 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 921 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 922 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 923 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 924 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 925 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 926 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 927 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 928 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 929 930 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 931 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 932 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 933 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 934 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 935 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 936 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 937 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 938 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 939 940 #define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 941 942 #define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 943 944 #define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 945 946 #define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 947 948 #define HTT_RX_MON_FILTER_TLV_FLAGS \ 949 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 950 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 951 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 952 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 953 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 954 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 955 956 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 957 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 958 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 959 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 960 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 961 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 962 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 963 964 #define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 965 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 966 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 967 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 968 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 969 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 970 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 971 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 972 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 973 974 struct htt_rx_ring_selection_cfg_cmd { 975 u32 info0; 976 u32 info1; 977 u32 pkt_type_en_flags0; 978 u32 pkt_type_en_flags1; 979 u32 pkt_type_en_flags2; 980 u32 pkt_type_en_flags3; 981 u32 rx_filter_tlv; 982 } __packed; 983 984 struct htt_rx_ring_tlv_filter { 985 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 986 u32 pkt_filter_flags0; /* MGMT */ 987 u32 pkt_filter_flags1; /* MGMT */ 988 u32 pkt_filter_flags2; /* CTRL */ 989 u32 pkt_filter_flags3; /* DATA */ 990 }; 991 992 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 993 #define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 994 995 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 996 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 997 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 998 #define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 999 1000 /* Enumeration for full monitor mode destination ring select 1001 * 0 - REO destination ring select 1002 * 1 - FW destination ring select 1003 * 2 - SW destination ring select 1004 * 3 - Release destination ring select 1005 */ 1006 enum htt_rx_full_mon_release_ring { 1007 HTT_RX_MON_RING_REO, 1008 HTT_RX_MON_RING_FW, 1009 HTT_RX_MON_RING_SW, 1010 HTT_RX_MON_RING_RELEASE, 1011 }; 1012 1013 struct htt_rx_full_monitor_mode_cfg_cmd { 1014 u32 info0; 1015 u32 cfg; 1016 } __packed; 1017 1018 /* HTT message target->host */ 1019 1020 enum htt_t2h_msg_type { 1021 HTT_T2H_MSG_TYPE_VERSION_CONF, 1022 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1023 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1024 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1025 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1026 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1027 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1028 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1029 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1030 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1031 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1032 }; 1033 1034 #define HTT_TARGET_VERSION_MAJOR 3 1035 1036 #define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1037 #define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1038 #define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1039 1040 struct htt_t2h_version_conf_msg { 1041 u32 version; 1042 } __packed; 1043 1044 #define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1045 #define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1046 #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1047 #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1048 #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1049 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1050 #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1051 1052 struct htt_t2h_peer_map_event { 1053 u32 info; 1054 u32 mac_addr_l32; 1055 u32 info1; 1056 u32 info2; 1057 } __packed; 1058 1059 #define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1060 #define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1061 #define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1062 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1063 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1064 #define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1065 1066 struct htt_t2h_peer_unmap_event { 1067 u32 info; 1068 u32 mac_addr_l32; 1069 u32 info1; 1070 } __packed; 1071 1072 struct htt_resp_msg { 1073 union { 1074 struct htt_t2h_version_conf_msg version_msg; 1075 struct htt_t2h_peer_map_event peer_map_ev; 1076 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1077 }; 1078 } __packed; 1079 1080 #define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1081 #define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1082 #define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1083 1084 #define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1085 #define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1086 1087 #define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1088 #define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1089 1090 enum htt_backpressure_umac_ringid { 1091 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1092 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1093 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1094 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1095 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1096 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1097 HTT_SW_RING_IDX_REO_REO2FW_RING, 1098 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1099 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1100 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1101 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1102 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1103 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1104 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1105 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1106 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1107 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1108 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1109 HTT_SW_UMAC_RING_IDX_MAX, 1110 }; 1111 1112 enum htt_backpressure_lmac_ringid { 1113 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1114 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1115 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1116 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1117 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1118 HTT_SW_RING_IDX_RXDMA2FW_RING, 1119 HTT_SW_RING_IDX_RXDMA2SW_RING, 1120 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1121 HTT_SW_RING_IDX_RXDMA2REO_RING, 1122 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1123 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1124 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1125 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1126 HTT_SW_LMAC_RING_IDX_MAX, 1127 }; 1128 1129 /* ppdu stats 1130 * 1131 * @details 1132 * The following field definitions describe the format of the HTT target 1133 * to host ppdu stats indication message. 1134 * 1135 * 1136 * |31 16|15 12|11 10|9 8|7 0 | 1137 * |----------------------------------------------------------------------| 1138 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1139 * |----------------------------------------------------------------------| 1140 * | ppdu_id | 1141 * |----------------------------------------------------------------------| 1142 * | Timestamp in us | 1143 * |----------------------------------------------------------------------| 1144 * | reserved | 1145 * |----------------------------------------------------------------------| 1146 * | type-specific stats info | 1147 * | (see htt_ppdu_stats.h) | 1148 * |----------------------------------------------------------------------| 1149 * Header fields: 1150 * - MSG_TYPE 1151 * Bits 7:0 1152 * Purpose: Identifies this is a PPDU STATS indication 1153 * message. 1154 * Value: 0x1d 1155 * - mac_id 1156 * Bits 9:8 1157 * Purpose: mac_id of this ppdu_id 1158 * Value: 0-3 1159 * - pdev_id 1160 * Bits 11:10 1161 * Purpose: pdev_id of this ppdu_id 1162 * Value: 0-3 1163 * 0 (for rings at SOC level), 1164 * 1/2/3 PDEV -> 0/1/2 1165 * - payload_size 1166 * Bits 31:16 1167 * Purpose: total tlv size 1168 * Value: payload_size in bytes 1169 */ 1170 1171 #define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1172 #define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1173 1174 struct ath11k_htt_ppdu_stats_msg { 1175 u32 info; 1176 u32 ppdu_id; 1177 u32 timestamp; 1178 u32 rsvd; 1179 u8 data[]; 1180 } __packed; 1181 1182 struct htt_tlv { 1183 u32 header; 1184 u8 value[]; 1185 } __packed; 1186 1187 #define HTT_TLV_TAG GENMASK(11, 0) 1188 #define HTT_TLV_LEN GENMASK(23, 12) 1189 1190 enum HTT_PPDU_STATS_BW { 1191 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1192 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1193 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1194 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1195 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1196 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1197 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1198 }; 1199 1200 #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1201 #define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1202 /* bw - HTT_PPDU_STATS_BW */ 1203 #define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1204 1205 struct htt_ppdu_stats_common { 1206 u32 ppdu_id; 1207 u16 sched_cmdid; 1208 u8 ring_id; 1209 u8 num_users; 1210 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1211 u32 chain_mask; 1212 u32 fes_duration_us; /* frame exchange sequence */ 1213 u32 ppdu_sch_eval_start_tstmp_us; 1214 u32 ppdu_sch_end_tstmp_us; 1215 u32 ppdu_start_tstmp_us; 1216 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1217 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1218 */ 1219 u16 phy_mode; 1220 u16 bw_mhz; 1221 } __packed; 1222 1223 enum htt_ppdu_stats_gi { 1224 HTT_PPDU_STATS_SGI_0_8_US, 1225 HTT_PPDU_STATS_SGI_0_4_US, 1226 HTT_PPDU_STATS_SGI_1_6_US, 1227 HTT_PPDU_STATS_SGI_3_2_US, 1228 }; 1229 1230 #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1231 #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1232 1233 #define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1234 #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1235 1236 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1237 #define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1238 #define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1239 #define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1240 #define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1241 #define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1242 #define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1243 #define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1244 #define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1245 #define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1246 #define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1247 1248 #define HTT_USR_RATE_PREAMBLE(_val) \ 1249 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1250 #define HTT_USR_RATE_BW(_val) \ 1251 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1252 #define HTT_USR_RATE_NSS(_val) \ 1253 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1254 #define HTT_USR_RATE_MCS(_val) \ 1255 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1256 #define HTT_USR_RATE_GI(_val) \ 1257 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1258 #define HTT_USR_RATE_DCM(_val) \ 1259 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1260 1261 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1262 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1263 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1264 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1265 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1266 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1267 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1268 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1269 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1270 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1271 #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1272 1273 struct htt_ppdu_stats_user_rate { 1274 u8 tid_num; 1275 u8 reserved0; 1276 u16 sw_peer_id; 1277 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1278 u16 ru_end; 1279 u16 ru_start; 1280 u16 resp_ru_end; 1281 u16 resp_ru_start; 1282 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1283 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1284 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1285 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1286 } __packed; 1287 1288 #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1289 #define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1290 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1291 #define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1292 #define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1293 #define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1294 1295 #define HTT_TX_INFO_IS_AMSDU(_flags) \ 1296 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1297 #define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1298 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1299 #define HTT_TX_INFO_RATECODE(_flags) \ 1300 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1301 #define HTT_TX_INFO_PEERID(_flags) \ 1302 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1303 1304 struct htt_tx_ppdu_stats_info { 1305 struct htt_tlv tlv_hdr; 1306 u32 tx_success_bytes; 1307 u32 tx_retry_bytes; 1308 u32 tx_failed_bytes; 1309 u32 flags; /* %HTT_PPDU_STATS_TX_INFO_FLAGS_ */ 1310 u16 tx_success_msdus; 1311 u16 tx_retry_msdus; 1312 u16 tx_failed_msdus; 1313 u16 tx_duration; /* united in us */ 1314 } __packed; 1315 1316 enum htt_ppdu_stats_usr_compln_status { 1317 HTT_PPDU_STATS_USER_STATUS_OK, 1318 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1319 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1320 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1321 HTT_PPDU_STATS_USER_STATUS_ABORT, 1322 }; 1323 1324 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1325 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1326 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1327 #define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1328 1329 #define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1330 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1331 #define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1332 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1333 #define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1334 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1335 1336 struct htt_ppdu_stats_usr_cmpltn_cmn { 1337 u8 status; 1338 u8 tid_num; 1339 u16 sw_peer_id; 1340 /* RSSI value of last ack packet (units = dB above noise floor) */ 1341 u32 ack_rssi; 1342 u16 mpdu_tried; 1343 u16 mpdu_success; 1344 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1345 } __packed; 1346 1347 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1348 #define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1349 #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1350 1351 #define HTT_PPDU_STATS_NON_QOS_TID 16 1352 1353 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1354 u32 ppdu_id; 1355 u16 sw_peer_id; 1356 u16 reserved0; 1357 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1358 u16 current_seq; 1359 u16 start_seq; 1360 u32 success_bytes; 1361 } __packed; 1362 1363 struct htt_ppdu_stats_usr_cmn_array { 1364 struct htt_tlv tlv_hdr; 1365 u32 num_ppdu_stats; 1366 /* tx_ppdu_stats_info is filled by multiple struct htt_tx_ppdu_stats_info 1367 * elements. 1368 * tx_ppdu_stats_info is variable length, with length = 1369 * number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info) 1370 */ 1371 struct htt_tx_ppdu_stats_info tx_ppdu_info[]; 1372 } __packed; 1373 1374 struct htt_ppdu_user_stats { 1375 u16 peer_id; 1376 u32 tlv_flags; 1377 bool is_valid_peer_id; 1378 struct htt_ppdu_stats_user_rate rate; 1379 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1380 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1381 }; 1382 1383 #define HTT_PPDU_STATS_MAX_USERS 8 1384 #define HTT_PPDU_DESC_MAX_DEPTH 16 1385 1386 struct htt_ppdu_stats { 1387 struct htt_ppdu_stats_common common; 1388 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1389 }; 1390 1391 struct htt_ppdu_stats_info { 1392 u32 ppdu_id; 1393 struct htt_ppdu_stats ppdu_stats; 1394 struct list_head list; 1395 }; 1396 1397 /* @brief target -> host packet log message 1398 * 1399 * @details 1400 * The following field definitions describe the format of the packet log 1401 * message sent from the target to the host. 1402 * The message consists of a 4-octet header,followed by a variable number 1403 * of 32-bit character values. 1404 * 1405 * |31 16|15 12|11 10|9 8|7 0| 1406 * |------------------------------------------------------------------| 1407 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1408 * |------------------------------------------------------------------| 1409 * | payload | 1410 * |------------------------------------------------------------------| 1411 * - MSG_TYPE 1412 * Bits 7:0 1413 * Purpose: identifies this as a pktlog message 1414 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1415 * - mac_id 1416 * Bits 9:8 1417 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1418 * Value: 0-3 1419 * - pdev_id 1420 * Bits 11:10 1421 * Purpose: pdev_id 1422 * Value: 0-3 1423 * 0 (for rings at SOC level), 1424 * 1/2/3 PDEV -> 0/1/2 1425 * - payload_size 1426 * Bits 31:16 1427 * Purpose: explicitly specify the payload size 1428 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1429 */ 1430 struct htt_pktlog_msg { 1431 u32 hdr; 1432 u8 payload[]; 1433 }; 1434 1435 /* @brief host -> target FW extended statistics retrieve 1436 * 1437 * @details 1438 * The following field definitions describe the format of the HTT host 1439 * to target FW extended stats retrieve message. 1440 * The message specifies the type of stats the host wants to retrieve. 1441 * 1442 * |31 24|23 16|15 8|7 0| 1443 * |-----------------------------------------------------------| 1444 * | reserved | stats type | pdev_mask | msg type | 1445 * |-----------------------------------------------------------| 1446 * | config param [0] | 1447 * |-----------------------------------------------------------| 1448 * | config param [1] | 1449 * |-----------------------------------------------------------| 1450 * | config param [2] | 1451 * |-----------------------------------------------------------| 1452 * | config param [3] | 1453 * |-----------------------------------------------------------| 1454 * | reserved | 1455 * |-----------------------------------------------------------| 1456 * | cookie LSBs | 1457 * |-----------------------------------------------------------| 1458 * | cookie MSBs | 1459 * |-----------------------------------------------------------| 1460 * Header fields: 1461 * - MSG_TYPE 1462 * Bits 7:0 1463 * Purpose: identifies this is a extended stats upload request message 1464 * Value: 0x10 1465 * - PDEV_MASK 1466 * Bits 8:15 1467 * Purpose: identifies the mask of PDEVs to retrieve stats from 1468 * Value: This is a overloaded field, refer to usage and interpretation of 1469 * PDEV in interface document. 1470 * Bit 8 : Reserved for SOC stats 1471 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1472 * Indicates MACID_MASK in DBS 1473 * - STATS_TYPE 1474 * Bits 23:16 1475 * Purpose: identifies which FW statistics to upload 1476 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1477 * - Reserved 1478 * Bits 31:24 1479 * - CONFIG_PARAM [0] 1480 * Bits 31:0 1481 * Purpose: give an opaque configuration value to the specified stats type 1482 * Value: stats-type specific configuration value 1483 * Refer to htt_stats.h for interpretation for each stats sub_type 1484 * - CONFIG_PARAM [1] 1485 * Bits 31:0 1486 * Purpose: give an opaque configuration value to the specified stats type 1487 * Value: stats-type specific configuration value 1488 * Refer to htt_stats.h for interpretation for each stats sub_type 1489 * - CONFIG_PARAM [2] 1490 * Bits 31:0 1491 * Purpose: give an opaque configuration value to the specified stats type 1492 * Value: stats-type specific configuration value 1493 * Refer to htt_stats.h for interpretation for each stats sub_type 1494 * - CONFIG_PARAM [3] 1495 * Bits 31:0 1496 * Purpose: give an opaque configuration value to the specified stats type 1497 * Value: stats-type specific configuration value 1498 * Refer to htt_stats.h for interpretation for each stats sub_type 1499 * - Reserved [31:0] for future use. 1500 * - COOKIE_LSBS 1501 * Bits 31:0 1502 * Purpose: Provide a mechanism to match a target->host stats confirmation 1503 * message with its preceding host->target stats request message. 1504 * Value: LSBs of the opaque cookie specified by the host-side requestor 1505 * - COOKIE_MSBS 1506 * Bits 31:0 1507 * Purpose: Provide a mechanism to match a target->host stats confirmation 1508 * message with its preceding host->target stats request message. 1509 * Value: MSBs of the opaque cookie specified by the host-side requestor 1510 */ 1511 1512 struct htt_ext_stats_cfg_hdr { 1513 u8 msg_type; 1514 u8 pdev_mask; 1515 u8 stats_type; 1516 u8 reserved; 1517 } __packed; 1518 1519 struct htt_ext_stats_cfg_cmd { 1520 struct htt_ext_stats_cfg_hdr hdr; 1521 u32 cfg_param0; 1522 u32 cfg_param1; 1523 u32 cfg_param2; 1524 u32 cfg_param3; 1525 u32 reserved; 1526 u32 cookie_lsb; 1527 u32 cookie_msb; 1528 } __packed; 1529 1530 /* htt stats config default params */ 1531 #define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1532 #define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1533 #define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1534 #define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1535 #define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1536 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1537 #define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1538 #define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1539 1540 /* HTT_DBG_EXT_STATS_PEER_INFO 1541 * PARAMS: 1542 * @config_param0: 1543 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1544 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1545 * [Bit31 : Bit16] sw_peer_id 1546 * @config_param1: 1547 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1548 * 0 bit htt_peer_stats_cmn_tlv 1549 * 1 bit htt_peer_details_tlv 1550 * 2 bit htt_tx_peer_rate_stats_tlv 1551 * 3 bit htt_rx_peer_rate_stats_tlv 1552 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1553 * 5 bit htt_rx_tid_stats_tlv 1554 * 6 bit htt_msdu_flow_stats_tlv 1555 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1556 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1557 * [Bit31 : Bit16] reserved 1558 */ 1559 #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1560 #define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1561 1562 /* Used to set different configs to the specified stats type.*/ 1563 struct htt_ext_stats_cfg_params { 1564 u32 cfg0; 1565 u32 cfg1; 1566 u32 cfg2; 1567 u32 cfg3; 1568 }; 1569 1570 /* @brief target -> host extended statistics upload 1571 * 1572 * @details 1573 * The following field definitions describe the format of the HTT target 1574 * to host stats upload confirmation message. 1575 * The message contains a cookie echoed from the HTT host->target stats 1576 * upload request, which identifies which request the confirmation is 1577 * for, and a single stats can span over multiple HTT stats indication 1578 * due to the HTT message size limitation so every HTT ext stats indication 1579 * will have tag-length-value stats information elements. 1580 * The tag-length header for each HTT stats IND message also includes a 1581 * status field, to indicate whether the request for the stat type in 1582 * question was fully met, partially met, unable to be met, or invalid 1583 * (if the stat type in question is disabled in the target). 1584 * A Done bit 1's indicate the end of the of stats info elements. 1585 * 1586 * 1587 * |31 16|15 12|11|10 8|7 5|4 0| 1588 * |--------------------------------------------------------------| 1589 * | reserved | msg type | 1590 * |--------------------------------------------------------------| 1591 * | cookie LSBs | 1592 * |--------------------------------------------------------------| 1593 * | cookie MSBs | 1594 * |--------------------------------------------------------------| 1595 * | stats entry length | rsvd | D| S | stat type | 1596 * |--------------------------------------------------------------| 1597 * | type-specific stats info | 1598 * | (see htt_stats.h) | 1599 * |--------------------------------------------------------------| 1600 * Header fields: 1601 * - MSG_TYPE 1602 * Bits 7:0 1603 * Purpose: Identifies this is a extended statistics upload confirmation 1604 * message. 1605 * Value: 0x1c 1606 * - COOKIE_LSBS 1607 * Bits 31:0 1608 * Purpose: Provide a mechanism to match a target->host stats confirmation 1609 * message with its preceding host->target stats request message. 1610 * Value: LSBs of the opaque cookie specified by the host-side requestor 1611 * - COOKIE_MSBS 1612 * Bits 31:0 1613 * Purpose: Provide a mechanism to match a target->host stats confirmation 1614 * message with its preceding host->target stats request message. 1615 * Value: MSBs of the opaque cookie specified by the host-side requestor 1616 * 1617 * Stats Information Element tag-length header fields: 1618 * - STAT_TYPE 1619 * Bits 7:0 1620 * Purpose: identifies the type of statistics info held in the 1621 * following information element 1622 * Value: htt_dbg_ext_stats_type 1623 * - STATUS 1624 * Bits 10:8 1625 * Purpose: indicate whether the requested stats are present 1626 * Value: htt_dbg_ext_stats_status 1627 * - DONE 1628 * Bits 11 1629 * Purpose: 1630 * Indicates the completion of the stats entry, this will be the last 1631 * stats conf HTT segment for the requested stats type. 1632 * Value: 1633 * 0 -> the stats retrieval is ongoing 1634 * 1 -> the stats retrieval is complete 1635 * - LENGTH 1636 * Bits 31:16 1637 * Purpose: indicate the stats information size 1638 * Value: This field specifies the number of bytes of stats information 1639 * that follows the element tag-length header. 1640 * It is expected but not required that this length is a multiple of 1641 * 4 bytes. 1642 */ 1643 1644 #define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1645 #define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1646 1647 struct ath11k_htt_extd_stats_msg { 1648 u32 info0; 1649 u64 cookie; 1650 u32 info1; 1651 u8 data[]; 1652 } __packed; 1653 1654 #define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1655 #define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1656 #define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1657 #define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1658 #define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1659 #define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1660 1661 struct htt_mac_addr { 1662 u32 mac_addr_l32; 1663 u32 mac_addr_h16; 1664 }; 1665 1666 static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1667 { 1668 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1669 addr_l32 = swab32(addr_l32); 1670 addr_h16 = swab16(addr_h16); 1671 } 1672 1673 memcpy(addr, &addr_l32, 4); 1674 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1675 } 1676 1677 int ath11k_dp_service_srng(struct ath11k_base *ab, 1678 struct ath11k_ext_irq_grp *irq_grp, 1679 int budget); 1680 int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1681 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1682 void ath11k_dp_free(struct ath11k_base *ab); 1683 int ath11k_dp_alloc(struct ath11k_base *ab); 1684 int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1685 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1686 void ath11k_dp_pdev_free(struct ath11k_base *ab); 1687 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1688 int mac_id, enum hal_ring_type ring_type); 1689 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1690 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1691 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1692 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1693 enum hal_ring_type type, int ring_num, 1694 int mac_id, int num_entries); 1695 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1696 struct dp_link_desc_bank *desc_bank, 1697 u32 ring_type, struct dp_srng *ring); 1698 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1699 struct dp_link_desc_bank *link_desc_banks, 1700 u32 ring_type, struct hal_srng *srng, 1701 u32 n_link_desc); 1702 void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1703 struct hal_srng *srng, 1704 struct ath11k_hp_update_timer *update_timer); 1705 void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1706 struct ath11k_hp_update_timer *update_timer); 1707 void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1708 struct ath11k_hp_update_timer *update_timer, 1709 u32 interval, u32 ring_id); 1710 void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1711 1712 #endif 1713