1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <crypto/hash.h> 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "hal_tx.h" 10 #include "hif.h" 11 #include "debug.h" 12 #include "dp_rx.h" 13 #include "peer.h" 14 15 static void ath11k_dp_htt_htc_tx_complete(struct ath11k_base *ab, 16 struct sk_buff *skb) 17 { 18 dev_kfree_skb_any(skb); 19 } 20 21 void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr) 22 { 23 struct ath11k_base *ab = ar->ab; 24 struct ath11k_peer *peer; 25 26 /* TODO: Any other peer specific DP cleanup */ 27 28 spin_lock_bh(&ab->base_lock); 29 peer = ath11k_peer_find(ab, vdev_id, addr); 30 if (!peer) { 31 ath11k_warn(ab, "failed to lookup peer %pM on vdev %d\n", 32 addr, vdev_id); 33 spin_unlock_bh(&ab->base_lock); 34 return; 35 } 36 37 ath11k_peer_rx_tid_cleanup(ar, peer); 38 crypto_free_shash(peer->tfm_mmic); 39 spin_unlock_bh(&ab->base_lock); 40 } 41 42 int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr) 43 { 44 struct ath11k_base *ab = ar->ab; 45 struct ath11k_peer *peer; 46 u32 reo_dest; 47 int ret = 0, tid; 48 49 /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ 50 reo_dest = ar->dp.mac_id + 1; 51 ret = ath11k_wmi_set_peer_param(ar, addr, vdev_id, 52 WMI_PEER_SET_DEFAULT_ROUTING, 53 DP_RX_HASH_ENABLE | (reo_dest << 1)); 54 55 if (ret) { 56 ath11k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", 57 ret, addr, vdev_id); 58 return ret; 59 } 60 61 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 62 ret = ath11k_peer_rx_tid_setup(ar, addr, vdev_id, tid, 1, 0, 63 HAL_PN_TYPE_NONE); 64 if (ret) { 65 ath11k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", 66 tid, ret); 67 goto peer_clean; 68 } 69 } 70 71 ret = ath11k_peer_rx_frag_setup(ar, addr, vdev_id); 72 if (ret) { 73 ath11k_warn(ab, "failed to setup rx defrag context\n"); 74 return ret; 75 } 76 77 /* TODO: Setup other peer specific resource used in data path */ 78 79 return 0; 80 81 peer_clean: 82 spin_lock_bh(&ab->base_lock); 83 84 peer = ath11k_peer_find(ab, vdev_id, addr); 85 if (!peer) { 86 ath11k_warn(ab, "failed to find the peer to del rx tid\n"); 87 spin_unlock_bh(&ab->base_lock); 88 return -ENOENT; 89 } 90 91 for (; tid >= 0; tid--) 92 ath11k_peer_rx_tid_delete(ar, peer, tid); 93 94 spin_unlock_bh(&ab->base_lock); 95 96 return ret; 97 } 98 99 void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring) 100 { 101 if (!ring->vaddr_unaligned) 102 return; 103 104 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, 105 ring->paddr_unaligned); 106 107 ring->vaddr_unaligned = NULL; 108 } 109 110 static int ath11k_dp_srng_find_ring_in_mask(int ring_num, const u8 *grp_mask) 111 { 112 int ext_group_num; 113 u8 mask = 1 << ring_num; 114 115 for (ext_group_num = 0; ext_group_num < ATH11K_EXT_IRQ_GRP_NUM_MAX; 116 ext_group_num++) { 117 if (mask & grp_mask[ext_group_num]) 118 return ext_group_num; 119 } 120 121 return -ENOENT; 122 } 123 124 static int ath11k_dp_srng_calculate_msi_group(struct ath11k_base *ab, 125 enum hal_ring_type type, int ring_num) 126 { 127 const u8 *grp_mask; 128 129 switch (type) { 130 case HAL_WBM2SW_RELEASE: 131 if (ring_num < 3) { 132 grp_mask = &ab->hw_params.ring_mask->tx[0]; 133 } else if (ring_num == 3) { 134 grp_mask = &ab->hw_params.ring_mask->rx_wbm_rel[0]; 135 ring_num = 0; 136 } else { 137 return -ENOENT; 138 } 139 break; 140 case HAL_REO_EXCEPTION: 141 grp_mask = &ab->hw_params.ring_mask->rx_err[0]; 142 break; 143 case HAL_REO_DST: 144 grp_mask = &ab->hw_params.ring_mask->rx[0]; 145 break; 146 case HAL_REO_STATUS: 147 grp_mask = &ab->hw_params.ring_mask->reo_status[0]; 148 break; 149 case HAL_RXDMA_MONITOR_STATUS: 150 case HAL_RXDMA_MONITOR_DST: 151 grp_mask = &ab->hw_params.ring_mask->rx_mon_status[0]; 152 break; 153 case HAL_RXDMA_DST: 154 grp_mask = &ab->hw_params.ring_mask->rxdma2host[0]; 155 break; 156 case HAL_RXDMA_BUF: 157 grp_mask = &ab->hw_params.ring_mask->host2rxdma[0]; 158 break; 159 case HAL_RXDMA_MONITOR_BUF: 160 case HAL_TCL_DATA: 161 case HAL_TCL_CMD: 162 case HAL_REO_CMD: 163 case HAL_SW2WBM_RELEASE: 164 case HAL_WBM_IDLE_LINK: 165 case HAL_TCL_STATUS: 166 case HAL_REO_REINJECT: 167 case HAL_CE_SRC: 168 case HAL_CE_DST: 169 case HAL_CE_DST_STATUS: 170 default: 171 return -ENOENT; 172 } 173 174 return ath11k_dp_srng_find_ring_in_mask(ring_num, grp_mask); 175 } 176 177 static void ath11k_dp_srng_msi_setup(struct ath11k_base *ab, 178 struct hal_srng_params *ring_params, 179 enum hal_ring_type type, int ring_num) 180 { 181 int msi_group_number, msi_data_count; 182 u32 msi_data_start, msi_irq_start, addr_lo, addr_hi; 183 int ret; 184 185 ret = ath11k_get_user_msi_vector(ab, "DP", 186 &msi_data_count, &msi_data_start, 187 &msi_irq_start); 188 if (ret) 189 return; 190 191 msi_group_number = ath11k_dp_srng_calculate_msi_group(ab, type, 192 ring_num); 193 if (msi_group_number < 0) { 194 ath11k_dbg(ab, ATH11K_DBG_PCI, 195 "ring not part of an ext_group; ring_type: %d,ring_num %d", 196 type, ring_num); 197 ring_params->msi_addr = 0; 198 ring_params->msi_data = 0; 199 return; 200 } 201 202 if (msi_group_number > msi_data_count) { 203 ath11k_dbg(ab, ATH11K_DBG_PCI, 204 "multiple msi_groups share one msi, msi_group_num %d", 205 msi_group_number); 206 } 207 208 ath11k_get_msi_address(ab, &addr_lo, &addr_hi); 209 210 ring_params->msi_addr = addr_lo; 211 ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); 212 ring_params->msi_data = (msi_group_number % msi_data_count) 213 + msi_data_start; 214 ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; 215 } 216 217 int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 218 enum hal_ring_type type, int ring_num, 219 int mac_id, int num_entries) 220 { 221 struct hal_srng_params params = { 0 }; 222 int entry_sz = ath11k_hal_srng_get_entrysize(ab, type); 223 int max_entries = ath11k_hal_srng_get_max_entries(ab, type); 224 int ret; 225 226 if (max_entries < 0 || entry_sz < 0) 227 return -EINVAL; 228 229 if (num_entries > max_entries) 230 num_entries = max_entries; 231 232 ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; 233 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, 234 &ring->paddr_unaligned, 235 GFP_KERNEL); 236 if (!ring->vaddr_unaligned) 237 return -ENOMEM; 238 239 ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); 240 ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - 241 (unsigned long)ring->vaddr_unaligned); 242 243 params.ring_base_vaddr = ring->vaddr; 244 params.ring_base_paddr = ring->paddr; 245 params.num_entries = num_entries; 246 ath11k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id); 247 248 switch (type) { 249 case HAL_REO_DST: 250 params.intr_batch_cntr_thres_entries = 251 HAL_SRNG_INT_BATCH_THRESHOLD_RX; 252 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 253 break; 254 case HAL_RXDMA_BUF: 255 case HAL_RXDMA_MONITOR_BUF: 256 case HAL_RXDMA_MONITOR_STATUS: 257 params.low_threshold = num_entries >> 3; 258 params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; 259 params.intr_batch_cntr_thres_entries = 0; 260 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; 261 break; 262 case HAL_WBM2SW_RELEASE: 263 if (ring_num < 3) { 264 params.intr_batch_cntr_thres_entries = 265 HAL_SRNG_INT_BATCH_THRESHOLD_TX; 266 params.intr_timer_thres_us = 267 HAL_SRNG_INT_TIMER_THRESHOLD_TX; 268 break; 269 } 270 /* follow through when ring_num >= 3 */ 271 fallthrough; 272 case HAL_REO_EXCEPTION: 273 case HAL_REO_REINJECT: 274 case HAL_REO_CMD: 275 case HAL_REO_STATUS: 276 case HAL_TCL_DATA: 277 case HAL_TCL_CMD: 278 case HAL_TCL_STATUS: 279 case HAL_WBM_IDLE_LINK: 280 case HAL_SW2WBM_RELEASE: 281 case HAL_RXDMA_DST: 282 case HAL_RXDMA_MONITOR_DST: 283 case HAL_RXDMA_MONITOR_DESC: 284 params.intr_batch_cntr_thres_entries = 285 HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; 286 params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; 287 break; 288 case HAL_RXDMA_DIR_BUF: 289 break; 290 default: 291 ath11k_warn(ab, "Not a valid ring type in dp :%d\n", type); 292 return -EINVAL; 293 } 294 295 ret = ath11k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); 296 if (ret < 0) { 297 ath11k_warn(ab, "failed to setup srng: %d ring_id %d\n", 298 ret, ring_num); 299 return ret; 300 } 301 302 ring->ring_id = ret; 303 304 return 0; 305 } 306 307 static void ath11k_dp_srng_common_cleanup(struct ath11k_base *ab) 308 { 309 struct ath11k_dp *dp = &ab->dp; 310 int i; 311 312 ath11k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); 313 ath11k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring); 314 ath11k_dp_srng_cleanup(ab, &dp->tcl_status_ring); 315 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 316 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); 317 ath11k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); 318 } 319 ath11k_dp_srng_cleanup(ab, &dp->reo_reinject_ring); 320 ath11k_dp_srng_cleanup(ab, &dp->rx_rel_ring); 321 ath11k_dp_srng_cleanup(ab, &dp->reo_except_ring); 322 ath11k_dp_srng_cleanup(ab, &dp->reo_cmd_ring); 323 ath11k_dp_srng_cleanup(ab, &dp->reo_status_ring); 324 } 325 326 static int ath11k_dp_srng_common_setup(struct ath11k_base *ab) 327 { 328 struct ath11k_dp *dp = &ab->dp; 329 struct hal_srng *srng; 330 int i, ret; 331 u32 ring_hash_map; 332 333 ret = ath11k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, 334 HAL_SW2WBM_RELEASE, 0, 0, 335 DP_WBM_RELEASE_RING_SIZE); 336 if (ret) { 337 ath11k_warn(ab, "failed to set up wbm2sw_release ring :%d\n", 338 ret); 339 goto err; 340 } 341 342 ret = ath11k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0, 343 DP_TCL_CMD_RING_SIZE); 344 if (ret) { 345 ath11k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret); 346 goto err; 347 } 348 349 ret = ath11k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS, 350 0, 0, DP_TCL_STATUS_RING_SIZE); 351 if (ret) { 352 ath11k_warn(ab, "failed to set up tcl_status ring :%d\n", ret); 353 goto err; 354 } 355 356 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 357 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, 358 HAL_TCL_DATA, i, 0, 359 DP_TCL_DATA_RING_SIZE); 360 if (ret) { 361 ath11k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n", 362 i, ret); 363 goto err; 364 } 365 366 ret = ath11k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, 367 HAL_WBM2SW_RELEASE, i, 0, 368 DP_TX_COMP_RING_SIZE); 369 if (ret) { 370 ath11k_warn(ab, "failed to set up tcl_comp ring ring (%d) :%d\n", 371 i, ret); 372 goto err; 373 } 374 375 srng = &ab->hal.srng_list[dp->tx_ring[i].tcl_data_ring.ring_id]; 376 ath11k_hal_tx_init_data_ring(ab, srng); 377 } 378 379 ret = ath11k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT, 380 0, 0, DP_REO_REINJECT_RING_SIZE); 381 if (ret) { 382 ath11k_warn(ab, "failed to set up reo_reinject ring :%d\n", 383 ret); 384 goto err; 385 } 386 387 ret = ath11k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE, 388 3, 0, DP_RX_RELEASE_RING_SIZE); 389 if (ret) { 390 ath11k_warn(ab, "failed to set up rx_rel ring :%d\n", ret); 391 goto err; 392 } 393 394 ret = ath11k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION, 395 0, 0, DP_REO_EXCEPTION_RING_SIZE); 396 if (ret) { 397 ath11k_warn(ab, "failed to set up reo_exception ring :%d\n", 398 ret); 399 goto err; 400 } 401 402 ret = ath11k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD, 403 0, 0, DP_REO_CMD_RING_SIZE); 404 if (ret) { 405 ath11k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret); 406 goto err; 407 } 408 409 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 410 ath11k_hal_reo_init_cmd_ring(ab, srng); 411 412 ret = ath11k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS, 413 0, 0, DP_REO_STATUS_RING_SIZE); 414 if (ret) { 415 ath11k_warn(ab, "failed to set up reo_status ring :%d\n", ret); 416 goto err; 417 } 418 419 /* When hash based routing of rx packet is enabled, 32 entries to map 420 * the hash values to the ring will be configured. Each hash entry uses 421 * three bits to map to a particular ring. The ring mapping will be 422 * 0:TCL, 1:SW1, 2:SW2, 3:SW3, 4:SW4, 5:Release, 6:FW and 7:Not used. 423 */ 424 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 425 HAL_HASH_ROUTING_RING_SW2 << 3 | 426 HAL_HASH_ROUTING_RING_SW3 << 6 | 427 HAL_HASH_ROUTING_RING_SW4 << 9 | 428 HAL_HASH_ROUTING_RING_SW1 << 12 | 429 HAL_HASH_ROUTING_RING_SW2 << 15 | 430 HAL_HASH_ROUTING_RING_SW3 << 18 | 431 HAL_HASH_ROUTING_RING_SW4 << 21; 432 433 ath11k_hal_reo_hw_setup(ab, ring_hash_map); 434 435 return 0; 436 437 err: 438 ath11k_dp_srng_common_cleanup(ab); 439 440 return ret; 441 } 442 443 static void ath11k_dp_scatter_idle_link_desc_cleanup(struct ath11k_base *ab) 444 { 445 struct ath11k_dp *dp = &ab->dp; 446 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 447 int i; 448 449 for (i = 0; i < DP_IDLE_SCATTER_BUFS_MAX; i++) { 450 if (!slist[i].vaddr) 451 continue; 452 453 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 454 slist[i].vaddr, slist[i].paddr); 455 slist[i].vaddr = NULL; 456 } 457 } 458 459 static int ath11k_dp_scatter_idle_link_desc_setup(struct ath11k_base *ab, 460 int size, 461 u32 n_link_desc_bank, 462 u32 n_link_desc, 463 u32 last_bank_sz) 464 { 465 struct ath11k_dp *dp = &ab->dp; 466 struct dp_link_desc_bank *link_desc_banks = dp->link_desc_banks; 467 struct hal_wbm_idle_scatter_list *slist = dp->scatter_list; 468 u32 n_entries_per_buf; 469 int num_scatter_buf, scatter_idx; 470 struct hal_wbm_link_desc *scatter_buf; 471 int align_bytes, n_entries; 472 dma_addr_t paddr; 473 int rem_entries; 474 int i; 475 int ret = 0; 476 u32 end_offset; 477 478 n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 479 ath11k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK); 480 num_scatter_buf = DIV_ROUND_UP(size, HAL_WBM_IDLE_SCATTER_BUF_SIZE); 481 482 if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) 483 return -EINVAL; 484 485 for (i = 0; i < num_scatter_buf; i++) { 486 slist[i].vaddr = dma_alloc_coherent(ab->dev, 487 HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, 488 &slist[i].paddr, GFP_KERNEL); 489 if (!slist[i].vaddr) { 490 ret = -ENOMEM; 491 goto err; 492 } 493 } 494 495 scatter_idx = 0; 496 scatter_buf = slist[scatter_idx].vaddr; 497 rem_entries = n_entries_per_buf; 498 499 for (i = 0; i < n_link_desc_bank; i++) { 500 align_bytes = link_desc_banks[i].vaddr - 501 link_desc_banks[i].vaddr_unaligned; 502 n_entries = (DP_LINK_DESC_ALLOC_SIZE_THRESH - align_bytes) / 503 HAL_LINK_DESC_SIZE; 504 paddr = link_desc_banks[i].paddr; 505 while (n_entries) { 506 ath11k_hal_set_link_desc_addr(scatter_buf, i, paddr); 507 n_entries--; 508 paddr += HAL_LINK_DESC_SIZE; 509 if (rem_entries) { 510 rem_entries--; 511 scatter_buf++; 512 continue; 513 } 514 515 rem_entries = n_entries_per_buf; 516 scatter_idx++; 517 scatter_buf = slist[scatter_idx].vaddr; 518 } 519 } 520 521 end_offset = (scatter_buf - slist[scatter_idx].vaddr) * 522 sizeof(struct hal_wbm_link_desc); 523 ath11k_hal_setup_link_idle_list(ab, slist, num_scatter_buf, 524 n_link_desc, end_offset); 525 526 return 0; 527 528 err: 529 ath11k_dp_scatter_idle_link_desc_cleanup(ab); 530 531 return ret; 532 } 533 534 static void 535 ath11k_dp_link_desc_bank_free(struct ath11k_base *ab, 536 struct dp_link_desc_bank *link_desc_banks) 537 { 538 int i; 539 540 for (i = 0; i < DP_LINK_DESC_BANKS_MAX; i++) { 541 if (link_desc_banks[i].vaddr_unaligned) { 542 dma_free_coherent(ab->dev, 543 link_desc_banks[i].size, 544 link_desc_banks[i].vaddr_unaligned, 545 link_desc_banks[i].paddr_unaligned); 546 link_desc_banks[i].vaddr_unaligned = NULL; 547 } 548 } 549 } 550 551 static int ath11k_dp_link_desc_bank_alloc(struct ath11k_base *ab, 552 struct dp_link_desc_bank *desc_bank, 553 int n_link_desc_bank, 554 int last_bank_sz) 555 { 556 struct ath11k_dp *dp = &ab->dp; 557 int i; 558 int ret = 0; 559 int desc_sz = DP_LINK_DESC_ALLOC_SIZE_THRESH; 560 561 for (i = 0; i < n_link_desc_bank; i++) { 562 if (i == (n_link_desc_bank - 1) && last_bank_sz) 563 desc_sz = last_bank_sz; 564 565 desc_bank[i].vaddr_unaligned = 566 dma_alloc_coherent(ab->dev, desc_sz, 567 &desc_bank[i].paddr_unaligned, 568 GFP_KERNEL); 569 if (!desc_bank[i].vaddr_unaligned) { 570 ret = -ENOMEM; 571 goto err; 572 } 573 574 desc_bank[i].vaddr = PTR_ALIGN(desc_bank[i].vaddr_unaligned, 575 HAL_LINK_DESC_ALIGN); 576 desc_bank[i].paddr = desc_bank[i].paddr_unaligned + 577 ((unsigned long)desc_bank[i].vaddr - 578 (unsigned long)desc_bank[i].vaddr_unaligned); 579 desc_bank[i].size = desc_sz; 580 } 581 582 return 0; 583 584 err: 585 ath11k_dp_link_desc_bank_free(ab, dp->link_desc_banks); 586 587 return ret; 588 } 589 590 void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 591 struct dp_link_desc_bank *desc_bank, 592 u32 ring_type, struct dp_srng *ring) 593 { 594 ath11k_dp_link_desc_bank_free(ab, desc_bank); 595 596 if (ring_type != HAL_RXDMA_MONITOR_DESC) { 597 ath11k_dp_srng_cleanup(ab, ring); 598 ath11k_dp_scatter_idle_link_desc_cleanup(ab); 599 } 600 } 601 602 static int ath11k_wbm_idle_ring_setup(struct ath11k_base *ab, u32 *n_link_desc) 603 { 604 struct ath11k_dp *dp = &ab->dp; 605 u32 n_mpdu_link_desc, n_mpdu_queue_desc; 606 u32 n_tx_msdu_link_desc, n_rx_msdu_link_desc; 607 int ret = 0; 608 609 n_mpdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX) / 610 HAL_NUM_MPDUS_PER_LINK_DESC; 611 612 n_mpdu_queue_desc = n_mpdu_link_desc / 613 HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC; 614 615 n_tx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_FLOWS_PER_TID * 616 DP_AVG_MSDUS_PER_FLOW) / 617 HAL_NUM_TX_MSDUS_PER_LINK_DESC; 618 619 n_rx_msdu_link_desc = (DP_NUM_TIDS_MAX * DP_AVG_MPDUS_PER_TID_MAX * 620 DP_AVG_MSDUS_PER_MPDU) / 621 HAL_NUM_RX_MSDUS_PER_LINK_DESC; 622 623 *n_link_desc = n_mpdu_link_desc + n_mpdu_queue_desc + 624 n_tx_msdu_link_desc + n_rx_msdu_link_desc; 625 626 if (*n_link_desc & (*n_link_desc - 1)) 627 *n_link_desc = 1 << fls(*n_link_desc); 628 629 ret = ath11k_dp_srng_setup(ab, &dp->wbm_idle_ring, 630 HAL_WBM_IDLE_LINK, 0, 0, *n_link_desc); 631 if (ret) { 632 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 633 return ret; 634 } 635 return ret; 636 } 637 638 int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 639 struct dp_link_desc_bank *link_desc_banks, 640 u32 ring_type, struct hal_srng *srng, 641 u32 n_link_desc) 642 { 643 u32 tot_mem_sz; 644 u32 n_link_desc_bank, last_bank_sz; 645 u32 entry_sz, align_bytes, n_entries; 646 u32 paddr; 647 u32 *desc; 648 int i, ret; 649 650 tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; 651 tot_mem_sz += HAL_LINK_DESC_ALIGN; 652 653 if (tot_mem_sz <= DP_LINK_DESC_ALLOC_SIZE_THRESH) { 654 n_link_desc_bank = 1; 655 last_bank_sz = tot_mem_sz; 656 } else { 657 n_link_desc_bank = tot_mem_sz / 658 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 659 HAL_LINK_DESC_ALIGN); 660 last_bank_sz = tot_mem_sz % 661 (DP_LINK_DESC_ALLOC_SIZE_THRESH - 662 HAL_LINK_DESC_ALIGN); 663 664 if (last_bank_sz) 665 n_link_desc_bank += 1; 666 } 667 668 if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) 669 return -EINVAL; 670 671 ret = ath11k_dp_link_desc_bank_alloc(ab, link_desc_banks, 672 n_link_desc_bank, last_bank_sz); 673 if (ret) 674 return ret; 675 676 /* Setup link desc idle list for HW internal usage */ 677 entry_sz = ath11k_hal_srng_get_entrysize(ab, ring_type); 678 tot_mem_sz = entry_sz * n_link_desc; 679 680 /* Setup scatter desc list when the total memory requirement is more */ 681 if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && 682 ring_type != HAL_RXDMA_MONITOR_DESC) { 683 ret = ath11k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, 684 n_link_desc_bank, 685 n_link_desc, 686 last_bank_sz); 687 if (ret) { 688 ath11k_warn(ab, "failed to setup scatting idle list descriptor :%d\n", 689 ret); 690 goto fail_desc_bank_free; 691 } 692 693 return 0; 694 } 695 696 spin_lock_bh(&srng->lock); 697 698 ath11k_hal_srng_access_begin(ab, srng); 699 700 for (i = 0; i < n_link_desc_bank; i++) { 701 align_bytes = link_desc_banks[i].vaddr - 702 link_desc_banks[i].vaddr_unaligned; 703 n_entries = (link_desc_banks[i].size - align_bytes) / 704 HAL_LINK_DESC_SIZE; 705 paddr = link_desc_banks[i].paddr; 706 while (n_entries && 707 (desc = ath11k_hal_srng_src_get_next_entry(ab, srng))) { 708 ath11k_hal_set_link_desc_addr((struct hal_wbm_link_desc *)desc, 709 i, paddr); 710 n_entries--; 711 paddr += HAL_LINK_DESC_SIZE; 712 } 713 } 714 715 ath11k_hal_srng_access_end(ab, srng); 716 717 spin_unlock_bh(&srng->lock); 718 719 return 0; 720 721 fail_desc_bank_free: 722 ath11k_dp_link_desc_bank_free(ab, link_desc_banks); 723 724 return ret; 725 } 726 727 int ath11k_dp_service_srng(struct ath11k_base *ab, 728 struct ath11k_ext_irq_grp *irq_grp, 729 int budget) 730 { 731 struct napi_struct *napi = &irq_grp->napi; 732 int grp_id = irq_grp->grp_id; 733 int work_done = 0; 734 int i = 0, j; 735 int tot_work_done = 0; 736 737 while (ab->hw_params.ring_mask->tx[grp_id] >> i) { 738 if (ab->hw_params.ring_mask->tx[grp_id] & BIT(i)) 739 ath11k_dp_tx_completion_handler(ab, i); 740 i++; 741 } 742 743 if (ab->hw_params.ring_mask->rx_err[grp_id]) { 744 work_done = ath11k_dp_process_rx_err(ab, napi, budget); 745 budget -= work_done; 746 tot_work_done += work_done; 747 if (budget <= 0) 748 goto done; 749 } 750 751 if (ab->hw_params.ring_mask->rx_wbm_rel[grp_id]) { 752 work_done = ath11k_dp_rx_process_wbm_err(ab, 753 napi, 754 budget); 755 budget -= work_done; 756 tot_work_done += work_done; 757 758 if (budget <= 0) 759 goto done; 760 } 761 762 if (ab->hw_params.ring_mask->rx[grp_id]) { 763 i = fls(ab->hw_params.ring_mask->rx[grp_id]) - 1; 764 work_done = ath11k_dp_process_rx(ab, i, napi, 765 budget); 766 budget -= work_done; 767 tot_work_done += work_done; 768 if (budget <= 0) 769 goto done; 770 } 771 772 if (ab->hw_params.ring_mask->rx_mon_status[grp_id]) { 773 for (i = 0; i < ab->num_radios; i++) { 774 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) { 775 int id = i * ab->hw_params.num_rxmda_per_pdev + j; 776 777 if (ab->hw_params.ring_mask->rx_mon_status[grp_id] & 778 BIT(id)) { 779 work_done = 780 ath11k_dp_rx_process_mon_rings(ab, 781 id, 782 napi, budget); 783 budget -= work_done; 784 tot_work_done += work_done; 785 786 if (budget <= 0) 787 goto done; 788 } 789 } 790 } 791 } 792 793 if (ab->hw_params.ring_mask->reo_status[grp_id]) 794 ath11k_dp_process_reo_status(ab); 795 796 for (i = 0; i < ab->num_radios; i++) { 797 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) { 798 int id = i * ab->hw_params.num_rxmda_per_pdev + j; 799 800 if (ab->hw_params.ring_mask->rxdma2host[grp_id] & BIT(id)) { 801 work_done = ath11k_dp_process_rxdma_err(ab, id, budget); 802 budget -= work_done; 803 tot_work_done += work_done; 804 } 805 806 if (budget <= 0) 807 goto done; 808 809 if (ab->hw_params.ring_mask->host2rxdma[grp_id] & BIT(id)) { 810 struct ath11k *ar = ath11k_ab_to_ar(ab, id); 811 struct ath11k_pdev_dp *dp = &ar->dp; 812 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 813 814 ath11k_dp_rxbufs_replenish(ab, id, rx_ring, 0, 815 HAL_RX_BUF_RBM_SW3_BM, 816 GFP_ATOMIC); 817 } 818 } 819 } 820 /* TODO: Implement handler for other interrupts */ 821 822 done: 823 return tot_work_done; 824 } 825 EXPORT_SYMBOL(ath11k_dp_service_srng); 826 827 void ath11k_dp_pdev_free(struct ath11k_base *ab) 828 { 829 struct ath11k *ar; 830 int i; 831 832 for (i = 0; i < ab->num_radios; i++) { 833 ar = ab->pdevs[i].ar; 834 ath11k_dp_rx_pdev_free(ab, i); 835 ath11k_debugfs_unregister(ar); 836 ath11k_dp_rx_pdev_mon_detach(ar); 837 } 838 } 839 840 void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab) 841 { 842 struct ath11k *ar; 843 struct ath11k_pdev_dp *dp; 844 int i; 845 int j; 846 847 for (i = 0; i < ab->num_radios; i++) { 848 ar = ab->pdevs[i].ar; 849 dp = &ar->dp; 850 dp->mac_id = i; 851 idr_init(&dp->rx_refill_buf_ring.bufs_idr); 852 spin_lock_init(&dp->rx_refill_buf_ring.idr_lock); 853 atomic_set(&dp->num_tx_pending, 0); 854 init_waitqueue_head(&dp->tx_empty_waitq); 855 for (j = 0; j < ab->hw_params.num_rxmda_per_pdev; j++) { 856 idr_init(&dp->rx_mon_status_refill_ring[j].bufs_idr); 857 spin_lock_init(&dp->rx_mon_status_refill_ring[j].idr_lock); 858 } 859 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 860 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 861 } 862 } 863 864 int ath11k_dp_pdev_alloc(struct ath11k_base *ab) 865 { 866 struct ath11k *ar; 867 int ret; 868 int i; 869 870 /* TODO:Per-pdev rx ring unlike tx ring which is mapped to different AC's */ 871 for (i = 0; i < ab->num_radios; i++) { 872 ar = ab->pdevs[i].ar; 873 ret = ath11k_dp_rx_pdev_alloc(ab, i); 874 if (ret) { 875 ath11k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n", 876 i); 877 goto err; 878 } 879 ret = ath11k_dp_rx_pdev_mon_attach(ar); 880 if (ret) { 881 ath11k_warn(ab, "failed to initialize mon pdev %d\n", 882 i); 883 goto err; 884 } 885 } 886 887 return 0; 888 889 err: 890 ath11k_dp_pdev_free(ab); 891 892 return ret; 893 } 894 895 int ath11k_dp_htt_connect(struct ath11k_dp *dp) 896 { 897 struct ath11k_htc_svc_conn_req conn_req; 898 struct ath11k_htc_svc_conn_resp conn_resp; 899 int status; 900 901 memset(&conn_req, 0, sizeof(conn_req)); 902 memset(&conn_resp, 0, sizeof(conn_resp)); 903 904 conn_req.ep_ops.ep_tx_complete = ath11k_dp_htt_htc_tx_complete; 905 conn_req.ep_ops.ep_rx_complete = ath11k_dp_htt_htc_t2h_msg_handler; 906 907 /* connect to control service */ 908 conn_req.service_id = ATH11K_HTC_SVC_ID_HTT_DATA_MSG; 909 910 status = ath11k_htc_connect_service(&dp->ab->htc, &conn_req, 911 &conn_resp); 912 913 if (status) 914 return status; 915 916 dp->eid = conn_resp.eid; 917 918 return 0; 919 } 920 921 static void ath11k_dp_update_vdev_search(struct ath11k_vif *arvif) 922 { 923 /* When v2_map_support is true:for STA mode, enable address 924 * search index, tcl uses ast_hash value in the descriptor. 925 * When v2_map_support is false: for STA mode, dont' enable 926 * address search index. 927 */ 928 switch (arvif->vdev_type) { 929 case WMI_VDEV_TYPE_STA: 930 if (arvif->ar->ab->hw_params.htt_peer_map_v2) { 931 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 932 arvif->search_type = HAL_TX_ADDR_SEARCH_INDEX; 933 } else { 934 arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN; 935 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 936 } 937 break; 938 case WMI_VDEV_TYPE_AP: 939 case WMI_VDEV_TYPE_IBSS: 940 arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; 941 arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; 942 break; 943 case WMI_VDEV_TYPE_MONITOR: 944 default: 945 return; 946 } 947 } 948 949 void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif) 950 { 951 arvif->tcl_metadata |= FIELD_PREP(HTT_TCL_META_DATA_TYPE, 1) | 952 FIELD_PREP(HTT_TCL_META_DATA_VDEV_ID, 953 arvif->vdev_id) | 954 FIELD_PREP(HTT_TCL_META_DATA_PDEV_ID, 955 ar->pdev->pdev_id); 956 957 /* set HTT extension valid bit to 0 by default */ 958 arvif->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; 959 960 ath11k_dp_update_vdev_search(arvif); 961 } 962 963 static int ath11k_dp_tx_pending_cleanup(int buf_id, void *skb, void *ctx) 964 { 965 struct ath11k_base *ab = (struct ath11k_base *)ctx; 966 struct sk_buff *msdu = skb; 967 968 dma_unmap_single(ab->dev, ATH11K_SKB_CB(msdu)->paddr, msdu->len, 969 DMA_TO_DEVICE); 970 971 dev_kfree_skb_any(msdu); 972 973 return 0; 974 } 975 976 void ath11k_dp_free(struct ath11k_base *ab) 977 { 978 struct ath11k_dp *dp = &ab->dp; 979 int i; 980 981 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 982 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 983 984 ath11k_dp_srng_common_cleanup(ab); 985 986 ath11k_dp_reo_cmd_list_cleanup(ab); 987 988 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 989 spin_lock_bh(&dp->tx_ring[i].tx_idr_lock); 990 idr_for_each(&dp->tx_ring[i].txbuf_idr, 991 ath11k_dp_tx_pending_cleanup, ab); 992 idr_destroy(&dp->tx_ring[i].txbuf_idr); 993 spin_unlock_bh(&dp->tx_ring[i].tx_idr_lock); 994 kfree(dp->tx_ring[i].tx_status); 995 } 996 997 /* Deinit any SOC level resource */ 998 } 999 1000 int ath11k_dp_alloc(struct ath11k_base *ab) 1001 { 1002 struct ath11k_dp *dp = &ab->dp; 1003 struct hal_srng *srng = NULL; 1004 size_t size = 0; 1005 u32 n_link_desc = 0; 1006 int ret; 1007 int i; 1008 1009 dp->ab = ab; 1010 1011 INIT_LIST_HEAD(&dp->reo_cmd_list); 1012 INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); 1013 spin_lock_init(&dp->reo_cmd_lock); 1014 1015 dp->reo_cmd_cache_flush_count = 0; 1016 1017 ret = ath11k_wbm_idle_ring_setup(ab, &n_link_desc); 1018 if (ret) { 1019 ath11k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); 1020 return ret; 1021 } 1022 1023 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; 1024 1025 ret = ath11k_dp_link_desc_setup(ab, dp->link_desc_banks, 1026 HAL_WBM_IDLE_LINK, srng, n_link_desc); 1027 if (ret) { 1028 ath11k_warn(ab, "failed to setup link desc: %d\n", ret); 1029 return ret; 1030 } 1031 1032 ret = ath11k_dp_srng_common_setup(ab); 1033 if (ret) 1034 goto fail_link_desc_cleanup; 1035 1036 size = sizeof(struct hal_wbm_release_ring) * DP_TX_COMP_RING_SIZE; 1037 1038 for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) { 1039 idr_init(&dp->tx_ring[i].txbuf_idr); 1040 spin_lock_init(&dp->tx_ring[i].tx_idr_lock); 1041 dp->tx_ring[i].tcl_data_ring_id = i; 1042 1043 dp->tx_ring[i].tx_status_head = 0; 1044 dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1; 1045 dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); 1046 if (!dp->tx_ring[i].tx_status) { 1047 ret = -ENOMEM; 1048 goto fail_cmn_srng_cleanup; 1049 } 1050 } 1051 1052 for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) 1053 ath11k_hal_tx_set_dscp_tid_map(ab, i); 1054 1055 /* Init any SOC level resource for DP */ 1056 1057 return 0; 1058 1059 fail_cmn_srng_cleanup: 1060 ath11k_dp_srng_common_cleanup(ab); 1061 1062 fail_link_desc_cleanup: 1063 ath11k_dp_link_desc_cleanup(ab, dp->link_desc_banks, 1064 HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); 1065 1066 return ret; 1067 } 1068