1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef DEBUG_HTT_STATS_H 7 #define DEBUG_HTT_STATS_H 8 9 #define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 10 #define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 11 #define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 12 13 enum htt_tlv_tag_t { 14 HTT_STATS_TX_PDEV_CMN_TAG = 0, 15 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 16 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 17 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 18 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, 19 HTT_STATS_STRING_TAG = 5, 20 HTT_STATS_TX_HWQ_CMN_TAG = 6, 21 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, 22 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, 23 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, 24 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, 25 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 26 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 27 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 28 HTT_STATS_TX_TQM_CMN_TAG = 14, 29 HTT_STATS_TX_TQM_PDEV_TAG = 15, 30 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, 31 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 32 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 33 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 34 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 35 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 36 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 37 HTT_STATS_TX_DE_CMN_TAG = 23, 38 HTT_STATS_RING_IF_TAG = 24, 39 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 40 HTT_STATS_SFM_CMN_TAG = 26, 41 HTT_STATS_SRING_STATS_TAG = 27, 42 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, 43 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, 44 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, 45 HTT_STATS_RX_SOC_FW_STATS_TAG = 31, 46 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, 47 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, 48 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 49 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 50 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 51 HTT_STATS_TX_SCHED_CMN_TAG = 37, 52 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, 53 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 54 HTT_STATS_RING_IF_CMN_TAG = 40, 55 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 56 HTT_STATS_SFM_CLIENT_TAG = 42, 57 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 58 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 59 HTT_STATS_SRING_CMN_TAG = 45, 60 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 61 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 62 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 63 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 64 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 65 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, 66 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, 67 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, 68 HTT_STATS_HW_INTR_MISC_TAG = 54, 69 HTT_STATS_HW_WD_TIMEOUT_TAG = 55, 70 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 71 HTT_STATS_COUNTER_NAME_TAG = 57, 72 HTT_STATS_TX_TID_DETAILS_TAG = 58, 73 HTT_STATS_RX_TID_DETAILS_TAG = 59, 74 HTT_STATS_PEER_STATS_CMN_TAG = 60, 75 HTT_STATS_PEER_DETAILS_TAG = 61, 76 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, 77 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, 78 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, 79 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 80 HTT_STATS_WHAL_TX_TAG = 66, 81 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 82 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, 83 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, 84 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 85 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 86 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 87 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 88 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 89 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, 90 HTT_STATS_PDEV_TWT_SESSION_TAG = 76, 91 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, 92 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, 93 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, 94 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 95 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, 96 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, 97 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, 98 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, 99 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, 100 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 101 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 102 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 103 HTT_STATS_HW_WAR_TAG = 89, 104 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, 105 106 HTT_STATS_MAX_TAG, 107 }; 108 109 #define HTT_STATS_MAX_STRING_SZ32 4 110 #define HTT_STATS_MACID_INVALID 0xff 111 #define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 112 #define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 113 #define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 114 #define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 115 116 enum htt_tx_pdev_underrun_enum { 117 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 118 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 119 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 120 HTT_TX_PDEV_MAX_URRN_STATS = 3, 121 }; 122 123 #define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71 124 #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 125 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 126 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 127 #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 128 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 129 130 #define HTT_RX_STATS_REFILL_MAX_RING 4 131 #define HTT_RX_STATS_RXDMA_MAX_ERR 16 132 #define HTT_RX_STATS_FW_DROP_REASON_MAX 16 133 134 /* Bytes stored in little endian order */ 135 /* Length should be multiple of DWORD */ 136 struct htt_stats_string_tlv { 137 u32 data[0]; /* Can be variable length */ 138 } __packed; 139 140 /* == TX PDEV STATS == */ 141 struct htt_tx_pdev_stats_cmn_tlv { 142 u32 mac_id__word; 143 u32 hw_queued; 144 u32 hw_reaped; 145 u32 underrun; 146 u32 hw_paused; 147 u32 hw_flush; 148 u32 hw_filt; 149 u32 tx_abort; 150 u32 mpdu_requed; 151 u32 tx_xretry; 152 u32 data_rc; 153 u32 mpdu_dropped_xretry; 154 u32 illgl_rate_phy_err; 155 u32 cont_xretry; 156 u32 tx_timeout; 157 u32 pdev_resets; 158 u32 phy_underrun; 159 u32 txop_ovf; 160 u32 seq_posted; 161 u32 seq_failed_queueing; 162 u32 seq_completed; 163 u32 seq_restarted; 164 u32 mu_seq_posted; 165 u32 seq_switch_hw_paused; 166 u32 next_seq_posted_dsr; 167 u32 seq_posted_isr; 168 u32 seq_ctrl_cached; 169 u32 mpdu_count_tqm; 170 u32 msdu_count_tqm; 171 u32 mpdu_removed_tqm; 172 u32 msdu_removed_tqm; 173 u32 mpdus_sw_flush; 174 u32 mpdus_hw_filter; 175 u32 mpdus_truncated; 176 u32 mpdus_ack_failed; 177 u32 mpdus_expired; 178 u32 mpdus_seq_hw_retry; 179 u32 ack_tlv_proc; 180 u32 coex_abort_mpdu_cnt_valid; 181 u32 coex_abort_mpdu_cnt; 182 u32 num_total_ppdus_tried_ota; 183 u32 num_data_ppdus_tried_ota; 184 u32 local_ctrl_mgmt_enqued; 185 u32 local_ctrl_mgmt_freed; 186 u32 local_data_enqued; 187 u32 local_data_freed; 188 u32 mpdu_tried; 189 u32 isr_wait_seq_posted; 190 191 u32 tx_active_dur_us_low; 192 u32 tx_active_dur_us_high; 193 }; 194 195 /* NOTE: Variable length TLV, use length spec to infer array size */ 196 struct htt_tx_pdev_stats_urrn_tlv_v { 197 u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */ 198 }; 199 200 /* NOTE: Variable length TLV, use length spec to infer array size */ 201 struct htt_tx_pdev_stats_flush_tlv_v { 202 u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ 203 }; 204 205 /* NOTE: Variable length TLV, use length spec to infer array size */ 206 struct htt_tx_pdev_stats_sifs_tlv_v { 207 u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ 208 }; 209 210 /* NOTE: Variable length TLV, use length spec to infer array size */ 211 struct htt_tx_pdev_stats_phy_err_tlv_v { 212 u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ 213 }; 214 215 /* NOTE: Variable length TLV, use length spec to infer array size */ 216 struct htt_tx_pdev_stats_sifs_hist_tlv_v { 217 u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ 218 }; 219 220 struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { 221 u32 num_data_ppdus_legacy_su; 222 u32 num_data_ppdus_ac_su; 223 u32 num_data_ppdus_ax_su; 224 u32 num_data_ppdus_ac_su_txbf; 225 u32 num_data_ppdus_ax_su_txbf; 226 }; 227 228 /* NOTE: Variable length TLV, use length spec to infer array size . 229 * 230 * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. 231 * The tries here is the count of the MPDUS within a PPDU that the 232 * HW had attempted to transmit on air, for the HWSCH Schedule 233 * command submitted by FW.It is not the retry attempts. 234 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are 235 * 10 bins in this histogram. They are defined in FW using the 236 * following macros 237 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 238 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 239 */ 240 struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v { 241 u32 hist_bin_size; 242 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ 243 }; 244 245 /* == SOC ERROR STATS == */ 246 247 /* =============== PDEV ERROR STATS ============== */ 248 #define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 249 struct htt_hw_stats_intr_misc_tlv { 250 /* Stored as little endian */ 251 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; 252 u32 mask; 253 u32 count; 254 }; 255 256 #define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 257 struct htt_hw_stats_wd_timeout_tlv { 258 /* Stored as little endian */ 259 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; 260 u32 count; 261 }; 262 263 struct htt_hw_stats_pdev_errs_tlv { 264 u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */ 265 u32 tx_abort; 266 u32 tx_abort_fail_count; 267 u32 rx_abort; 268 u32 rx_abort_fail_count; 269 u32 warm_reset; 270 u32 cold_reset; 271 u32 tx_flush; 272 u32 tx_glb_reset; 273 u32 tx_txq_reset; 274 u32 rx_timeout_reset; 275 }; 276 277 struct htt_hw_stats_whal_tx_tlv { 278 u32 mac_id__word; 279 u32 last_unpause_ppdu_id; 280 u32 hwsch_unpause_wait_tqm_write; 281 u32 hwsch_dummy_tlv_skipped; 282 u32 hwsch_misaligned_offset_received; 283 u32 hwsch_reset_count; 284 u32 hwsch_dev_reset_war; 285 u32 hwsch_delayed_pause; 286 u32 hwsch_long_delayed_pause; 287 u32 sch_rx_ppdu_no_response; 288 u32 sch_selfgen_response; 289 u32 sch_rx_sifs_resp_trigger; 290 }; 291 292 /* ============ PEER STATS ============ */ 293 struct htt_msdu_flow_stats_tlv { 294 u32 last_update_timestamp; 295 u32 last_add_timestamp; 296 u32 last_remove_timestamp; 297 u32 total_processed_msdu_count; 298 u32 cur_msdu_count_in_flowq; 299 u32 sw_peer_id; 300 u32 tx_flow_no__tid_num__drop_rule; 301 u32 last_cycle_enqueue_count; 302 u32 last_cycle_dequeue_count; 303 u32 last_cycle_drop_count; 304 u32 current_drop_th; 305 }; 306 307 #define MAX_HTT_TID_NAME 8 308 309 /* Tidq stats */ 310 struct htt_tx_tid_stats_tlv { 311 /* Stored as little endian */ 312 u8 tid_name[MAX_HTT_TID_NAME]; 313 u32 sw_peer_id__tid_num; 314 u32 num_sched_pending__num_ppdu_in_hwq; 315 u32 tid_flags; 316 u32 hw_queued; 317 u32 hw_reaped; 318 u32 mpdus_hw_filter; 319 320 u32 qdepth_bytes; 321 u32 qdepth_num_msdu; 322 u32 qdepth_num_mpdu; 323 u32 last_scheduled_tsmp; 324 u32 pause_module_id; 325 u32 block_module_id; 326 u32 tid_tx_airtime; 327 }; 328 329 /* Tidq stats */ 330 struct htt_tx_tid_stats_v1_tlv { 331 /* Stored as little endian */ 332 u8 tid_name[MAX_HTT_TID_NAME]; 333 u32 sw_peer_id__tid_num; 334 u32 num_sched_pending__num_ppdu_in_hwq; 335 u32 tid_flags; 336 u32 max_qdepth_bytes; 337 u32 max_qdepth_n_msdus; 338 u32 rsvd; 339 340 u32 qdepth_bytes; 341 u32 qdepth_num_msdu; 342 u32 qdepth_num_mpdu; 343 u32 last_scheduled_tsmp; 344 u32 pause_module_id; 345 u32 block_module_id; 346 u32 tid_tx_airtime; 347 u32 allow_n_flags; 348 u32 sendn_frms_allowed; 349 }; 350 351 struct htt_rx_tid_stats_tlv { 352 u32 sw_peer_id__tid_num; 353 u8 tid_name[MAX_HTT_TID_NAME]; 354 u32 dup_in_reorder; 355 u32 dup_past_outside_window; 356 u32 dup_past_within_window; 357 u32 rxdesc_err_decrypt; 358 u32 tid_rx_airtime; 359 }; 360 361 #define HTT_MAX_COUNTER_NAME 8 362 struct htt_counter_tlv { 363 u8 counter_name[HTT_MAX_COUNTER_NAME]; 364 u32 count; 365 }; 366 367 struct htt_peer_stats_cmn_tlv { 368 u32 ppdu_cnt; 369 u32 mpdu_cnt; 370 u32 msdu_cnt; 371 u32 pause_bitmap; 372 u32 block_bitmap; 373 u32 current_timestamp; 374 u32 peer_tx_airtime; 375 u32 peer_rx_airtime; 376 s32 rssi; 377 u32 peer_enqueued_count_low; 378 u32 peer_enqueued_count_high; 379 u32 peer_dequeued_count_low; 380 u32 peer_dequeued_count_high; 381 u32 peer_dropped_count_low; 382 u32 peer_dropped_count_high; 383 u32 ppdu_transmitted_bytes_low; 384 u32 ppdu_transmitted_bytes_high; 385 u32 peer_ttl_removed_count; 386 u32 inactive_time; 387 }; 388 389 struct htt_peer_details_tlv { 390 u32 peer_type; 391 u32 sw_peer_id; 392 u32 vdev_pdev_ast_idx; 393 struct htt_mac_addr mac_addr; 394 u32 peer_flags; 395 u32 qpeer_flags; 396 }; 397 398 enum htt_stats_param_type { 399 HTT_STATS_PREAM_OFDM, 400 HTT_STATS_PREAM_CCK, 401 HTT_STATS_PREAM_HT, 402 HTT_STATS_PREAM_VHT, 403 HTT_STATS_PREAM_HE, 404 HTT_STATS_PREAM_RSVD, 405 HTT_STATS_PREAM_RSVD1, 406 407 HTT_STATS_PREAM_COUNT, 408 }; 409 410 #define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 411 #define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 412 #define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 413 #define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 414 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 415 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 416 417 struct htt_tx_peer_rate_stats_tlv { 418 u32 tx_ldpc; 419 u32 rts_cnt; 420 u32 ack_rssi; 421 422 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 423 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 424 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 425 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 426 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; 427 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 428 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; 429 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 430 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; 431 432 /* Counters to track number of tx packets in each GI 433 * (400us, 800us, 1600us & 3200us) in each mcs (0-11) 434 */ 435 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; 436 437 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 438 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; 439 440 }; 441 442 #define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 443 #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 444 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 445 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 446 #define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 447 #define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 448 449 struct htt_rx_peer_rate_stats_tlv { 450 u32 nsts; 451 452 /* Number of rx ldpc packets */ 453 u32 rx_ldpc; 454 /* Number of rx rts packets */ 455 u32 rts_cnt; 456 457 u32 rssi_mgmt; /* units = dB above noise floor */ 458 u32 rssi_data; /* units = dB above noise floor */ 459 u32 rssi_comb; /* units = dB above noise floor */ 460 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 461 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 462 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; 463 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; 464 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 465 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 466 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 467 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; 468 /* units = dB above noise floor */ 469 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] 470 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; 471 472 /* Counters to track number of rx packets in each GI in each mcs (0-11) */ 473 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] 474 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; 475 }; 476 477 enum htt_peer_stats_req_mode { 478 HTT_PEER_STATS_REQ_MODE_NO_QUERY, 479 HTT_PEER_STATS_REQ_MODE_QUERY_TQM, 480 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, 481 }; 482 483 enum htt_peer_stats_tlv_enum { 484 HTT_PEER_STATS_CMN_TLV = 0, 485 HTT_PEER_DETAILS_TLV = 1, 486 HTT_TX_PEER_RATE_STATS_TLV = 2, 487 HTT_RX_PEER_RATE_STATS_TLV = 3, 488 HTT_TX_TID_STATS_TLV = 4, 489 HTT_RX_TID_STATS_TLV = 5, 490 HTT_MSDU_FLOW_STATS_TLV = 6, 491 492 HTT_PEER_STATS_MAX_TLV = 31, 493 }; 494 495 /* =========== MUMIMO HWQ stats =========== */ 496 /* MU MIMO stats per hwQ */ 497 struct htt_tx_hwq_mu_mimo_sch_stats_tlv { 498 u32 mu_mimo_sch_posted; 499 u32 mu_mimo_sch_failed; 500 u32 mu_mimo_ppdu_posted; 501 }; 502 503 struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv { 504 u32 mu_mimo_mpdus_queued_usr; 505 u32 mu_mimo_mpdus_tried_usr; 506 u32 mu_mimo_mpdus_failed_usr; 507 u32 mu_mimo_mpdus_requeued_usr; 508 u32 mu_mimo_err_no_ba_usr; 509 u32 mu_mimo_mpdu_underrun_usr; 510 u32 mu_mimo_ampdu_underrun_usr; 511 }; 512 513 struct htt_tx_hwq_mu_mimo_cmn_stats_tlv { 514 u32 mac_id__hwq_id__word; 515 }; 516 517 /* == TX HWQ STATS == */ 518 struct htt_tx_hwq_stats_cmn_tlv { 519 u32 mac_id__hwq_id__word; 520 521 /* PPDU level stats */ 522 u32 xretry; 523 u32 underrun_cnt; 524 u32 flush_cnt; 525 u32 filt_cnt; 526 u32 null_mpdu_bmap; 527 u32 user_ack_failure; 528 u32 ack_tlv_proc; 529 u32 sched_id_proc; 530 u32 null_mpdu_tx_count; 531 u32 mpdu_bmap_not_recvd; 532 533 /* Selfgen stats per hwQ */ 534 u32 num_bar; 535 u32 rts; 536 u32 cts2self; 537 u32 qos_null; 538 539 /* MPDU level stats */ 540 u32 mpdu_tried_cnt; 541 u32 mpdu_queued_cnt; 542 u32 mpdu_ack_fail_cnt; 543 u32 mpdu_filt_cnt; 544 u32 false_mpdu_ack_count; 545 546 u32 txq_timeout; 547 }; 548 549 /* NOTE: Variable length TLV, use length spec to infer array size */ 550 struct htt_tx_hwq_difs_latency_stats_tlv_v { 551 u32 hist_intvl; 552 /* histogram of ppdu post to hwsch - > cmd status received */ 553 u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ 554 }; 555 556 /* NOTE: Variable length TLV, use length spec to infer array size */ 557 struct htt_tx_hwq_cmd_result_stats_tlv_v { 558 /* Histogram of sched cmd result */ 559 u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ 560 }; 561 562 /* NOTE: Variable length TLV, use length spec to infer array size */ 563 struct htt_tx_hwq_cmd_stall_stats_tlv_v { 564 /* Histogram of various pause conitions */ 565 u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ 566 }; 567 568 /* NOTE: Variable length TLV, use length spec to infer array size */ 569 struct htt_tx_hwq_fes_result_stats_tlv_v { 570 /* Histogram of number of user fes result */ 571 u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ 572 }; 573 574 /* NOTE: Variable length TLV, use length spec to infer array size 575 * 576 * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. 577 * The tries here is the count of the MPDUS within a PPDU that the HW 578 * had attempted to transmit on air, for the HWSCH Schedule command 579 * submitted by FW in this HWQ .It is not the retry attempts. The 580 * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins 581 * in this histogram. 582 * they are defined in FW using the following macros 583 * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 584 * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 585 */ 586 struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v { 587 u32 hist_bin_size; 588 /* Histogram of number of mpdus on tried mpdu */ 589 u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ 590 }; 591 592 /* NOTE: Variable length TLV, use length spec to infer array size 593 * 594 * The txop_used_cnt_hist is the histogram of txop per burst. After 595 * completing the burst, we identify the txop used in the burst and 596 * incr the corresponding bin. 597 * Each bin represents 1ms & we have 10 bins in this histogram. 598 * they are deined in FW using the following macros 599 * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 600 * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) 601 */ 602 struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { 603 /* Histogram of txop used cnt */ 604 u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ 605 }; 606 607 /* == TX SELFGEN STATS == */ 608 struct htt_tx_selfgen_cmn_stats_tlv { 609 u32 mac_id__word; 610 u32 su_bar; 611 u32 rts; 612 u32 cts2self; 613 u32 qos_null; 614 u32 delayed_bar_1; /* MU user 1 */ 615 u32 delayed_bar_2; /* MU user 2 */ 616 u32 delayed_bar_3; /* MU user 3 */ 617 u32 delayed_bar_4; /* MU user 4 */ 618 u32 delayed_bar_5; /* MU user 5 */ 619 u32 delayed_bar_6; /* MU user 6 */ 620 u32 delayed_bar_7; /* MU user 7 */ 621 }; 622 623 struct htt_tx_selfgen_ac_stats_tlv { 624 /* 11AC */ 625 u32 ac_su_ndpa; 626 u32 ac_su_ndp; 627 u32 ac_mu_mimo_ndpa; 628 u32 ac_mu_mimo_ndp; 629 u32 ac_mu_mimo_brpoll_1; /* MU user 1 */ 630 u32 ac_mu_mimo_brpoll_2; /* MU user 2 */ 631 u32 ac_mu_mimo_brpoll_3; /* MU user 3 */ 632 }; 633 634 struct htt_tx_selfgen_ax_stats_tlv { 635 /* 11AX */ 636 u32 ax_su_ndpa; 637 u32 ax_su_ndp; 638 u32 ax_mu_mimo_ndpa; 639 u32 ax_mu_mimo_ndp; 640 u32 ax_mu_mimo_brpoll_1; /* MU user 1 */ 641 u32 ax_mu_mimo_brpoll_2; /* MU user 2 */ 642 u32 ax_mu_mimo_brpoll_3; /* MU user 3 */ 643 u32 ax_mu_mimo_brpoll_4; /* MU user 4 */ 644 u32 ax_mu_mimo_brpoll_5; /* MU user 5 */ 645 u32 ax_mu_mimo_brpoll_6; /* MU user 6 */ 646 u32 ax_mu_mimo_brpoll_7; /* MU user 7 */ 647 u32 ax_basic_trigger; 648 u32 ax_bsr_trigger; 649 u32 ax_mu_bar_trigger; 650 u32 ax_mu_rts_trigger; 651 }; 652 653 struct htt_tx_selfgen_ac_err_stats_tlv { 654 /* 11AC error stats */ 655 u32 ac_su_ndp_err; 656 u32 ac_su_ndpa_err; 657 u32 ac_mu_mimo_ndpa_err; 658 u32 ac_mu_mimo_ndp_err; 659 u32 ac_mu_mimo_brp1_err; 660 u32 ac_mu_mimo_brp2_err; 661 u32 ac_mu_mimo_brp3_err; 662 }; 663 664 struct htt_tx_selfgen_ax_err_stats_tlv { 665 /* 11AX error stats */ 666 u32 ax_su_ndp_err; 667 u32 ax_su_ndpa_err; 668 u32 ax_mu_mimo_ndpa_err; 669 u32 ax_mu_mimo_ndp_err; 670 u32 ax_mu_mimo_brp1_err; 671 u32 ax_mu_mimo_brp2_err; 672 u32 ax_mu_mimo_brp3_err; 673 u32 ax_mu_mimo_brp4_err; 674 u32 ax_mu_mimo_brp5_err; 675 u32 ax_mu_mimo_brp6_err; 676 u32 ax_mu_mimo_brp7_err; 677 u32 ax_basic_trigger_err; 678 u32 ax_bsr_trigger_err; 679 u32 ax_mu_bar_trigger_err; 680 u32 ax_mu_rts_trigger_err; 681 }; 682 683 /* == TX MU STATS == */ 684 #define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 685 #define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 686 #define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 687 688 struct htt_tx_pdev_mu_mimo_sch_stats_tlv { 689 /* mu-mimo sw sched cmd stats */ 690 u32 mu_mimo_sch_posted; 691 u32 mu_mimo_sch_failed; 692 /* MU PPDU stats per hwQ */ 693 u32 mu_mimo_ppdu_posted; 694 /* 695 * Counts the number of users in each transmission of 696 * the given TX mode. 697 * 698 * Index is the number of users - 1. 699 */ 700 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; 701 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; 702 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; 703 }; 704 705 struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv { 706 u32 mu_mimo_mpdus_queued_usr; 707 u32 mu_mimo_mpdus_tried_usr; 708 u32 mu_mimo_mpdus_failed_usr; 709 u32 mu_mimo_mpdus_requeued_usr; 710 u32 mu_mimo_err_no_ba_usr; 711 u32 mu_mimo_mpdu_underrun_usr; 712 u32 mu_mimo_ampdu_underrun_usr; 713 714 u32 ax_mu_mimo_mpdus_queued_usr; 715 u32 ax_mu_mimo_mpdus_tried_usr; 716 u32 ax_mu_mimo_mpdus_failed_usr; 717 u32 ax_mu_mimo_mpdus_requeued_usr; 718 u32 ax_mu_mimo_err_no_ba_usr; 719 u32 ax_mu_mimo_mpdu_underrun_usr; 720 u32 ax_mu_mimo_ampdu_underrun_usr; 721 722 u32 ax_ofdma_mpdus_queued_usr; 723 u32 ax_ofdma_mpdus_tried_usr; 724 u32 ax_ofdma_mpdus_failed_usr; 725 u32 ax_ofdma_mpdus_requeued_usr; 726 u32 ax_ofdma_err_no_ba_usr; 727 u32 ax_ofdma_mpdu_underrun_usr; 728 u32 ax_ofdma_ampdu_underrun_usr; 729 }; 730 731 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 732 #define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 733 #define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 734 735 struct htt_tx_pdev_mpdu_stats_tlv { 736 /* mpdu level stats */ 737 u32 mpdus_queued_usr; 738 u32 mpdus_tried_usr; 739 u32 mpdus_failed_usr; 740 u32 mpdus_requeued_usr; 741 u32 err_no_ba_usr; 742 u32 mpdu_underrun_usr; 743 u32 ampdu_underrun_usr; 744 u32 user_index; 745 u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ 746 }; 747 748 /* == TX SCHED STATS == */ 749 /* NOTE: Variable length TLV, use length spec to infer array size */ 750 struct htt_sched_txq_cmd_posted_tlv_v { 751 u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 752 }; 753 754 /* NOTE: Variable length TLV, use length spec to infer array size */ 755 struct htt_sched_txq_cmd_reaped_tlv_v { 756 u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ 757 }; 758 759 /* NOTE: Variable length TLV, use length spec to infer array size */ 760 struct htt_sched_txq_sched_order_su_tlv_v { 761 u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ 762 }; 763 764 enum htt_sched_txq_sched_ineligibility_tlv_enum { 765 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, 766 HTT_SCHED_TID_SKIP_NOTIFY_MPDU, 767 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, 768 HTT_SCHED_TID_SKIP_SCHED_DISABLED, 769 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, 770 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, 771 772 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, 773 HTT_SCHED_TID_SKIP_NO_ENQ, 774 HTT_SCHED_TID_SKIP_LOW_ENQ, 775 HTT_SCHED_TID_SKIP_PAUSED, 776 HTT_SCHED_TID_SKIP_UL, 777 HTT_SCHED_TID_REMOVE_PAUSED, 778 HTT_SCHED_TID_REMOVE_NO_ENQ, 779 HTT_SCHED_TID_REMOVE_UL, 780 HTT_SCHED_TID_QUERY, 781 HTT_SCHED_TID_SU_ONLY, 782 HTT_SCHED_TID_ELIGIBLE, 783 HTT_SCHED_INELIGIBILITY_MAX, 784 }; 785 786 /* NOTE: Variable length TLV, use length spec to infer array size */ 787 struct htt_sched_txq_sched_ineligibility_tlv_v { 788 /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ 789 u32 sched_ineligibility[0]; 790 }; 791 792 struct htt_tx_pdev_stats_sched_per_txq_tlv { 793 u32 mac_id__txq_id__word; 794 u32 sched_policy; 795 u32 last_sched_cmd_posted_timestamp; 796 u32 last_sched_cmd_compl_timestamp; 797 u32 sched_2_tac_lwm_count; 798 u32 sched_2_tac_ring_full; 799 u32 sched_cmd_post_failure; 800 u32 num_active_tids; 801 u32 num_ps_schedules; 802 u32 sched_cmds_pending; 803 u32 num_tid_register; 804 u32 num_tid_unregister; 805 u32 num_qstats_queried; 806 u32 qstats_update_pending; 807 u32 last_qstats_query_timestamp; 808 u32 num_tqm_cmdq_full; 809 u32 num_de_sched_algo_trigger; 810 u32 num_rt_sched_algo_trigger; 811 u32 num_tqm_sched_algo_trigger; 812 u32 notify_sched; 813 u32 dur_based_sendn_term; 814 }; 815 816 struct htt_stats_tx_sched_cmn_tlv { 817 /* BIT [ 7 : 0] :- mac_id 818 * BIT [31 : 8] :- reserved 819 */ 820 u32 mac_id__word; 821 /* Current timestamp */ 822 u32 current_timestamp; 823 }; 824 825 /* == TQM STATS == */ 826 #define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16 827 #define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 828 #define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 829 830 /* NOTE: Variable length TLV, use length spec to infer array size */ 831 struct htt_tx_tqm_gen_mpdu_stats_tlv_v { 832 u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ 833 }; 834 835 /* NOTE: Variable length TLV, use length spec to infer array size */ 836 struct htt_tx_tqm_list_mpdu_stats_tlv_v { 837 u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ 838 }; 839 840 /* NOTE: Variable length TLV, use length spec to infer array size */ 841 struct htt_tx_tqm_list_mpdu_cnt_tlv_v { 842 u32 list_mpdu_cnt_hist[0]; 843 /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ 844 }; 845 846 struct htt_tx_tqm_pdev_stats_tlv_v { 847 u32 msdu_count; 848 u32 mpdu_count; 849 u32 remove_msdu; 850 u32 remove_mpdu; 851 u32 remove_msdu_ttl; 852 u32 send_bar; 853 u32 bar_sync; 854 u32 notify_mpdu; 855 u32 sync_cmd; 856 u32 write_cmd; 857 u32 hwsch_trigger; 858 u32 ack_tlv_proc; 859 u32 gen_mpdu_cmd; 860 u32 gen_list_cmd; 861 u32 remove_mpdu_cmd; 862 u32 remove_mpdu_tried_cmd; 863 u32 mpdu_queue_stats_cmd; 864 u32 mpdu_head_info_cmd; 865 u32 msdu_flow_stats_cmd; 866 u32 remove_msdu_cmd; 867 u32 remove_msdu_ttl_cmd; 868 u32 flush_cache_cmd; 869 u32 update_mpduq_cmd; 870 u32 enqueue; 871 u32 enqueue_notify; 872 u32 notify_mpdu_at_head; 873 u32 notify_mpdu_state_valid; 874 /* 875 * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued 876 * the flow is non empty), if the number of MSDUs is greater than the threshold, 877 * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are 878 * for non-UDP MSDUs. 879 * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented 880 * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented 881 * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented 882 * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented 883 * 884 * Notify signifies that we trigger the scheduler. 885 */ 886 u32 sched_udp_notify1; 887 u32 sched_udp_notify2; 888 u32 sched_nonudp_notify1; 889 u32 sched_nonudp_notify2; 890 }; 891 892 struct htt_tx_tqm_cmn_stats_tlv { 893 u32 mac_id__word; 894 u32 max_cmdq_id; 895 u32 list_mpdu_cnt_hist_intvl; 896 897 /* Global stats */ 898 u32 add_msdu; 899 u32 q_empty; 900 u32 q_not_empty; 901 u32 drop_notification; 902 u32 desc_threshold; 903 }; 904 905 struct htt_tx_tqm_error_stats_tlv { 906 /* Error stats */ 907 u32 q_empty_failure; 908 u32 q_not_empty_failure; 909 u32 add_msdu_failure; 910 }; 911 912 /* == TQM CMDQ stats == */ 913 struct htt_tx_tqm_cmdq_status_tlv { 914 u32 mac_id__cmdq_id__word; 915 u32 sync_cmd; 916 u32 write_cmd; 917 u32 gen_mpdu_cmd; 918 u32 mpdu_queue_stats_cmd; 919 u32 mpdu_head_info_cmd; 920 u32 msdu_flow_stats_cmd; 921 u32 remove_mpdu_cmd; 922 u32 remove_msdu_cmd; 923 u32 flush_cache_cmd; 924 u32 update_mpduq_cmd; 925 u32 update_msduq_cmd; 926 }; 927 928 /* == TX-DE STATS == */ 929 /* Structures for tx de stats */ 930 struct htt_tx_de_eapol_packets_stats_tlv { 931 u32 m1_packets; 932 u32 m2_packets; 933 u32 m3_packets; 934 u32 m4_packets; 935 u32 g1_packets; 936 u32 g2_packets; 937 }; 938 939 struct htt_tx_de_classify_failed_stats_tlv { 940 u32 ap_bss_peer_not_found; 941 u32 ap_bcast_mcast_no_peer; 942 u32 sta_delete_in_progress; 943 u32 ibss_no_bss_peer; 944 u32 invalid_vdev_type; 945 u32 invalid_ast_peer_entry; 946 u32 peer_entry_invalid; 947 u32 ethertype_not_ip; 948 u32 eapol_lookup_failed; 949 u32 qpeer_not_allow_data; 950 u32 fse_tid_override; 951 u32 ipv6_jumbogram_zero_length; 952 u32 qos_to_non_qos_in_prog; 953 }; 954 955 struct htt_tx_de_classify_stats_tlv { 956 u32 arp_packets; 957 u32 igmp_packets; 958 u32 dhcp_packets; 959 u32 host_inspected; 960 u32 htt_included; 961 u32 htt_valid_mcs; 962 u32 htt_valid_nss; 963 u32 htt_valid_preamble_type; 964 u32 htt_valid_chainmask; 965 u32 htt_valid_guard_interval; 966 u32 htt_valid_retries; 967 u32 htt_valid_bw_info; 968 u32 htt_valid_power; 969 u32 htt_valid_key_flags; 970 u32 htt_valid_no_encryption; 971 u32 fse_entry_count; 972 u32 fse_priority_be; 973 u32 fse_priority_high; 974 u32 fse_priority_low; 975 u32 fse_traffic_ptrn_be; 976 u32 fse_traffic_ptrn_over_sub; 977 u32 fse_traffic_ptrn_bursty; 978 u32 fse_traffic_ptrn_interactive; 979 u32 fse_traffic_ptrn_periodic; 980 u32 fse_hwqueue_alloc; 981 u32 fse_hwqueue_created; 982 u32 fse_hwqueue_send_to_host; 983 u32 mcast_entry; 984 u32 bcast_entry; 985 u32 htt_update_peer_cache; 986 u32 htt_learning_frame; 987 u32 fse_invalid_peer; 988 /* 989 * mec_notify is HTT TX WBM multicast echo check notification 990 * from firmware to host. FW sends SA addresses to host for all 991 * multicast/broadcast packets received on STA side. 992 */ 993 u32 mec_notify; 994 }; 995 996 struct htt_tx_de_classify_status_stats_tlv { 997 u32 eok; 998 u32 classify_done; 999 u32 lookup_failed; 1000 u32 send_host_dhcp; 1001 u32 send_host_mcast; 1002 u32 send_host_unknown_dest; 1003 u32 send_host; 1004 u32 status_invalid; 1005 }; 1006 1007 struct htt_tx_de_enqueue_packets_stats_tlv { 1008 u32 enqueued_pkts; 1009 u32 to_tqm; 1010 u32 to_tqm_bypass; 1011 }; 1012 1013 struct htt_tx_de_enqueue_discard_stats_tlv { 1014 u32 discarded_pkts; 1015 u32 local_frames; 1016 u32 is_ext_msdu; 1017 }; 1018 1019 struct htt_tx_de_compl_stats_tlv { 1020 u32 tcl_dummy_frame; 1021 u32 tqm_dummy_frame; 1022 u32 tqm_notify_frame; 1023 u32 fw2wbm_enq; 1024 u32 tqm_bypass_frame; 1025 }; 1026 1027 /* 1028 * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited 1029 * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release 1030 * ring,which may fail, due to non availability of buffer. Hence we sleep for 1031 * 200us & again request for it. This is a histogram of time we wait, with 1032 * bin of 200ms & there are 10 bin (2 seconds max) 1033 * They are defined by the following macros in FW 1034 * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms 1035 * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / 1036 * ENTRIES_PER_BIN_COUNT) 1037 */ 1038 struct htt_tx_de_fw2wbm_ring_full_hist_tlv { 1039 u32 fw2wbm_ring_full_hist[0]; 1040 }; 1041 1042 struct htt_tx_de_cmn_stats_tlv { 1043 u32 mac_id__word; 1044 1045 /* Global Stats */ 1046 u32 tcl2fw_entry_count; 1047 u32 not_to_fw; 1048 u32 invalid_pdev_vdev_peer; 1049 u32 tcl_res_invalid_addrx; 1050 u32 wbm2fw_entry_count; 1051 u32 invalid_pdev; 1052 }; 1053 1054 /* == RING-IF STATS == */ 1055 #define HTT_STATS_LOW_WM_BINS 5 1056 #define HTT_STATS_HIGH_WM_BINS 5 1057 1058 struct htt_ring_if_stats_tlv { 1059 u32 base_addr; /* DWORD aligned base memory address of the ring */ 1060 u32 elem_size; 1061 u32 num_elems__prefetch_tail_idx; 1062 u32 head_idx__tail_idx; 1063 u32 shadow_head_idx__shadow_tail_idx; 1064 u32 num_tail_incr; 1065 u32 lwm_thresh__hwm_thresh; 1066 u32 overrun_hit_count; 1067 u32 underrun_hit_count; 1068 u32 prod_blockwait_count; 1069 u32 cons_blockwait_count; 1070 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; 1071 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; 1072 }; 1073 1074 struct htt_ring_if_cmn_tlv { 1075 u32 mac_id__word; 1076 u32 num_records; 1077 }; 1078 1079 /* == SFM STATS == */ 1080 /* NOTE: Variable length TLV, use length spec to infer array size */ 1081 struct htt_sfm_client_user_tlv_v { 1082 /* Number of DWORDS used per user and per client */ 1083 u32 dwords_used_by_user_n[0]; 1084 }; 1085 1086 struct htt_sfm_client_tlv { 1087 /* Client ID */ 1088 u32 client_id; 1089 /* Minimum number of buffers */ 1090 u32 buf_min; 1091 /* Maximum number of buffers */ 1092 u32 buf_max; 1093 /* Number of Busy buffers */ 1094 u32 buf_busy; 1095 /* Number of Allocated buffers */ 1096 u32 buf_alloc; 1097 /* Number of Available/Usable buffers */ 1098 u32 buf_avail; 1099 /* Number of users */ 1100 u32 num_users; 1101 }; 1102 1103 struct htt_sfm_cmn_tlv { 1104 u32 mac_id__word; 1105 /* Indicates the total number of 128 byte buffers 1106 * in the CMEM that are available for buffer sharing 1107 */ 1108 u32 buf_total; 1109 /* Indicates for certain client or all the clients 1110 * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY 1111 */ 1112 u32 mem_empty; 1113 /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ 1114 u32 deallocate_bufs; 1115 /* Number of Records */ 1116 u32 num_records; 1117 }; 1118 1119 /* == SRNG STATS == */ 1120 struct htt_sring_stats_tlv { 1121 u32 mac_id__ring_id__arena__ep; 1122 u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ 1123 u32 base_addr_msb; 1124 u32 ring_size; 1125 u32 elem_size; 1126 1127 u32 num_avail_words__num_valid_words; 1128 u32 head_ptr__tail_ptr; 1129 u32 consumer_empty__producer_full; 1130 u32 prefetch_count__internal_tail_ptr; 1131 }; 1132 1133 struct htt_sring_cmn_tlv { 1134 u32 num_records; 1135 }; 1136 1137 /* == PDEV TX RATE CTRL STATS == */ 1138 #define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 1139 #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 1140 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 1141 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1142 #define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1143 #define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1144 #define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1145 #define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1146 #define HTT_TX_PDEV_STATS_NUM_LTF 4 1147 1148 #define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1149 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1150 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) 1151 1152 struct htt_tx_pdev_rate_stats_tlv { 1153 u32 mac_id__word; 1154 u32 tx_ldpc; 1155 u32 rts_cnt; 1156 /* RSSI value of last ack packet (units = dB above noise floor) */ 1157 u32 ack_rssi; 1158 1159 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1160 1161 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1162 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1163 1164 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1165 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1166 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1167 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1168 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1169 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1170 1171 /* Counters to track number of tx packets 1172 * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) 1173 */ 1174 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1175 1176 /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ 1177 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 1178 /* Number of CTS-acknowledged RTS packets */ 1179 u32 rts_success; 1180 1181 /* 1182 * Counters for legacy 11a and 11b transmissions. 1183 * 1184 * The index corresponds to: 1185 * 1186 * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps 1187 * 1188 * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, 1189 * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps 1190 */ 1191 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1192 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1193 1194 u32 ac_mu_mimo_tx_ldpc; 1195 u32 ax_mu_mimo_tx_ldpc; 1196 u32 ofdma_tx_ldpc; 1197 1198 /* 1199 * Counters for 11ax HE LTF selection during TX. 1200 * 1201 * The index corresponds to: 1202 * 1203 * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF 1204 */ 1205 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; 1206 1207 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1208 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1209 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1210 1211 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1212 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1213 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1214 1215 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1216 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1217 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1218 1219 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1220 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1221 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1222 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1223 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1224 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 1225 }; 1226 1227 /* == PDEV RX RATE CTRL STATS == */ 1228 #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 1229 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1230 #define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 1231 #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 1232 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 1233 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 1234 #define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1235 #define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT 1236 #define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 1237 #define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 1238 1239 struct htt_rx_pdev_rate_stats_tlv { 1240 u32 mac_id__word; 1241 u32 nsts; 1242 1243 u32 rx_ldpc; 1244 u32 rts_cnt; 1245 1246 u32 rssi_mgmt; /* units = dB above noise floor */ 1247 u32 rssi_data; /* units = dB above noise floor */ 1248 u32 rssi_comb; /* units = dB above noise floor */ 1249 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1250 /* element 0,1, ...7 -> NSS 1,2, ...8 */ 1251 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1252 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 1253 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1254 /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ 1255 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1256 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 1257 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1258 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1259 /* units = dB above noise floor */ 1260 1261 /* Counters to track number of rx packets 1262 * in each GI in each mcs (0-11) 1263 */ 1264 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1265 s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ 1266 1267 u32 rx_11ax_su_ext; 1268 u32 rx_11ac_mumimo; 1269 u32 rx_11ax_mumimo; 1270 u32 rx_11ax_ofdma; 1271 u32 txbf; 1272 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 1273 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1274 u32 rx_active_dur_us_low; 1275 u32 rx_active_dur_us_high; 1276 1277 u32 rx_11ax_ul_ofdma; 1278 1279 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1280 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 1281 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 1282 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1283 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 1284 u32 ul_ofdma_rx_stbc; 1285 u32 ul_ofdma_rx_ldpc; 1286 1287 /* record the stats for each user index */ 1288 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1289 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ 1290 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1291 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ 1292 1293 u32 nss_count; 1294 u32 pilot_count; 1295 /* RxEVM stats in dB */ 1296 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1297 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; 1298 /* rx_pilot_evm_db_mean: 1299 * EVM mean across pilots, computed as 1300 * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db) 1301 */ 1302 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1303 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1304 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ 1305 /* per_chain_rssi_pkt_type: 1306 * This field shows what type of rx frame the per-chain RSSI was computed 1307 * on, by recording the frame type and sub-type as bit-fields within this 1308 * field: 1309 * BIT [3 : 0] :- IEEE80211_FC0_TYPE 1310 * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE 1311 * BIT [31 : 8] :- Reserved 1312 */ 1313 u32 per_chain_rssi_pkt_type; 1314 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 1315 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 1316 }; 1317 1318 /* == RX PDEV/SOC STATS == */ 1319 struct htt_rx_soc_fw_stats_tlv { 1320 u32 fw_reo_ring_data_msdu; 1321 u32 fw_to_host_data_msdu_bcmc; 1322 u32 fw_to_host_data_msdu_uc; 1323 u32 ofld_remote_data_buf_recycle_cnt; 1324 u32 ofld_remote_free_buf_indication_cnt; 1325 1326 u32 ofld_buf_to_host_data_msdu_uc; 1327 u32 reo_fw_ring_to_host_data_msdu_uc; 1328 1329 u32 wbm_sw_ring_reap; 1330 u32 wbm_forward_to_host_cnt; 1331 u32 wbm_target_recycle_cnt; 1332 1333 u32 target_refill_ring_recycle_cnt; 1334 }; 1335 1336 /* NOTE: Variable length TLV, use length spec to infer array size */ 1337 struct htt_rx_soc_fw_refill_ring_empty_tlv_v { 1338 u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ 1339 }; 1340 1341 /* NOTE: Variable length TLV, use length spec to infer array size */ 1342 struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { 1343 u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ 1344 }; 1345 1346 /* RXDMA error code from WBM released packets */ 1347 enum htt_rx_rxdma_error_code_enum { 1348 HTT_RX_RXDMA_OVERFLOW_ERR = 0, 1349 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, 1350 HTT_RX_RXDMA_FCS_ERR = 2, 1351 HTT_RX_RXDMA_DECRYPT_ERR = 3, 1352 HTT_RX_RXDMA_TKIP_MIC_ERR = 4, 1353 HTT_RX_RXDMA_UNECRYPTED_ERR = 5, 1354 HTT_RX_RXDMA_MSDU_LEN_ERR = 6, 1355 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, 1356 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, 1357 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, 1358 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, 1359 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, 1360 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, 1361 HTT_RX_RXDMA_FLUSH_REQUEST = 13, 1362 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, 1363 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, 1364 1365 /* This MAX_ERR_CODE should not be used in any host/target messages, 1366 * so that even though it is defined within a host/target interface 1367 * definition header file, it isn't actually part of the host/target 1368 * interface, and thus can be modified. 1369 */ 1370 HTT_RX_RXDMA_MAX_ERR_CODE 1371 }; 1372 1373 /* NOTE: Variable length TLV, use length spec to infer array size */ 1374 struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { 1375 u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ 1376 }; 1377 1378 /* REO error code from WBM released packets */ 1379 enum htt_rx_reo_error_code_enum { 1380 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, 1381 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, 1382 HTT_RX_AMPDU_IN_NON_BA = 2, 1383 HTT_RX_NON_BA_DUPLICATE = 3, 1384 HTT_RX_BA_DUPLICATE = 4, 1385 HTT_RX_REGULAR_FRAME_2K_JUMP = 5, 1386 HTT_RX_BAR_FRAME_2K_JUMP = 6, 1387 HTT_RX_REGULAR_FRAME_OOR = 7, 1388 HTT_RX_BAR_FRAME_OOR = 8, 1389 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, 1390 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, 1391 HTT_RX_PN_CHECK_FAILED = 11, 1392 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, 1393 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, 1394 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, 1395 HTT_RX_REO_ERR_CODE_RVSD = 15, 1396 1397 /* This MAX_ERR_CODE should not be used in any host/target messages, 1398 * so that even though it is defined within a host/target interface 1399 * definition header file, it isn't actually part of the host/target 1400 * interface, and thus can be modified. 1401 */ 1402 HTT_RX_REO_MAX_ERR_CODE 1403 }; 1404 1405 /* NOTE: Variable length TLV, use length spec to infer array size */ 1406 struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { 1407 u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */ 1408 }; 1409 1410 /* == RX PDEV STATS == */ 1411 #define HTT_STATS_SUBTYPE_MAX 16 1412 1413 struct htt_rx_pdev_fw_stats_tlv { 1414 u32 mac_id__word; 1415 u32 ppdu_recvd; 1416 u32 mpdu_cnt_fcs_ok; 1417 u32 mpdu_cnt_fcs_err; 1418 u32 tcp_msdu_cnt; 1419 u32 tcp_ack_msdu_cnt; 1420 u32 udp_msdu_cnt; 1421 u32 other_msdu_cnt; 1422 u32 fw_ring_mpdu_ind; 1423 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; 1424 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; 1425 u32 fw_ring_mcast_data_msdu; 1426 u32 fw_ring_bcast_data_msdu; 1427 u32 fw_ring_ucast_data_msdu; 1428 u32 fw_ring_null_data_msdu; 1429 u32 fw_ring_mpdu_drop; 1430 u32 ofld_local_data_ind_cnt; 1431 u32 ofld_local_data_buf_recycle_cnt; 1432 u32 drx_local_data_ind_cnt; 1433 u32 drx_local_data_buf_recycle_cnt; 1434 u32 local_nondata_ind_cnt; 1435 u32 local_nondata_buf_recycle_cnt; 1436 1437 u32 fw_status_buf_ring_refill_cnt; 1438 u32 fw_status_buf_ring_empty_cnt; 1439 u32 fw_pkt_buf_ring_refill_cnt; 1440 u32 fw_pkt_buf_ring_empty_cnt; 1441 u32 fw_link_buf_ring_refill_cnt; 1442 u32 fw_link_buf_ring_empty_cnt; 1443 1444 u32 host_pkt_buf_ring_refill_cnt; 1445 u32 host_pkt_buf_ring_empty_cnt; 1446 u32 mon_pkt_buf_ring_refill_cnt; 1447 u32 mon_pkt_buf_ring_empty_cnt; 1448 u32 mon_status_buf_ring_refill_cnt; 1449 u32 mon_status_buf_ring_empty_cnt; 1450 u32 mon_desc_buf_ring_refill_cnt; 1451 u32 mon_desc_buf_ring_empty_cnt; 1452 u32 mon_dest_ring_update_cnt; 1453 u32 mon_dest_ring_full_cnt; 1454 1455 u32 rx_suspend_cnt; 1456 u32 rx_suspend_fail_cnt; 1457 u32 rx_resume_cnt; 1458 u32 rx_resume_fail_cnt; 1459 u32 rx_ring_switch_cnt; 1460 u32 rx_ring_restore_cnt; 1461 u32 rx_flush_cnt; 1462 u32 rx_recovery_reset_cnt; 1463 }; 1464 1465 #define HTT_STATS_PHY_ERR_MAX 43 1466 1467 struct htt_rx_pdev_fw_stats_phy_err_tlv { 1468 u32 mac_id__word; 1469 u32 total_phy_err_cnt; 1470 /* Counts of different types of phy errs 1471 * The mapping of PHY error types to phy_err array elements is HW dependent. 1472 * The only currently-supported mapping is shown below: 1473 * 1474 * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV 1475 * 1 phyrx_err_synth_off 1476 * 2 phyrx_err_ofdma_timing 1477 * 3 phyrx_err_ofdma_signal_parity 1478 * 4 phyrx_err_ofdma_rate_illegal 1479 * 5 phyrx_err_ofdma_length_illegal 1480 * 6 phyrx_err_ofdma_restart 1481 * 7 phyrx_err_ofdma_service 1482 * 8 phyrx_err_ppdu_ofdma_power_drop 1483 * 9 phyrx_err_cck_blokker 1484 * 10 phyrx_err_cck_timing 1485 * 11 phyrx_err_cck_header_crc 1486 * 12 phyrx_err_cck_rate_illegal 1487 * 13 phyrx_err_cck_length_illegal 1488 * 14 phyrx_err_cck_restart 1489 * 15 phyrx_err_cck_service 1490 * 16 phyrx_err_cck_power_drop 1491 * 17 phyrx_err_ht_crc_err 1492 * 18 phyrx_err_ht_length_illegal 1493 * 19 phyrx_err_ht_rate_illegal 1494 * 20 phyrx_err_ht_zlf 1495 * 21 phyrx_err_false_radar_ext 1496 * 22 phyrx_err_green_field 1497 * 23 phyrx_err_bw_gt_dyn_bw 1498 * 24 phyrx_err_leg_ht_mismatch 1499 * 25 phyrx_err_vht_crc_error 1500 * 26 phyrx_err_vht_siga_unsupported 1501 * 27 phyrx_err_vht_lsig_len_invalid 1502 * 28 phyrx_err_vht_ndp_or_zlf 1503 * 29 phyrx_err_vht_nsym_lt_zero 1504 * 30 phyrx_err_vht_rx_extra_symbol_mismatch 1505 * 31 phyrx_err_vht_rx_skip_group_id0 1506 * 32 phyrx_err_vht_rx_skip_group_id1to62 1507 * 33 phyrx_err_vht_rx_skip_group_id63 1508 * 34 phyrx_err_ofdm_ldpc_decoder_disabled 1509 * 35 phyrx_err_defer_nap 1510 * 36 phyrx_err_fdomain_timeout 1511 * 37 phyrx_err_lsig_rel_check 1512 * 38 phyrx_err_bt_collision 1513 * 39 phyrx_err_unsupported_mu_feedback 1514 * 40 phyrx_err_ppdu_tx_interrupt_rx 1515 * 41 phyrx_err_unsupported_cbf 1516 * 42 phyrx_err_other 1517 */ 1518 u32 phy_err[HTT_STATS_PHY_ERR_MAX]; 1519 }; 1520 1521 /* NOTE: Variable length TLV, use length spec to infer array size */ 1522 struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { 1523 /* Num error MPDU for each RxDMA error type */ 1524 u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ 1525 }; 1526 1527 /* NOTE: Variable length TLV, use length spec to infer array size */ 1528 struct htt_rx_pdev_fw_mpdu_drop_tlv_v { 1529 /* Num MPDU dropped */ 1530 u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ 1531 }; 1532 1533 #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) 1534 #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) 1535 #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) 1536 #define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) 1537 #define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) 1538 #define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) 1539 #define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) 1540 #define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) 1541 1542 struct htt_pdev_stats_cca_counters_tlv { 1543 /* Below values are obtained from the HW Cycles counter registers */ 1544 u32 tx_frame_usec; 1545 u32 rx_frame_usec; 1546 u32 rx_clear_usec; 1547 u32 my_rx_frame_usec; 1548 u32 usec_cnt; 1549 u32 med_rx_idle_usec; 1550 u32 med_tx_idle_global_usec; 1551 u32 cca_obss_usec; 1552 }; 1553 1554 struct htt_pdev_cca_stats_hist_v1_tlv { 1555 u32 chan_num; 1556 /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ 1557 u32 num_records; 1558 u32 valid_cca_counters_bitmap; 1559 u32 collection_interval; 1560 1561 /* This will be followed by an array which contains the CCA stats 1562 * collected in the last N intervals, 1563 * if the indication is for last N intervals CCA stats. 1564 * Then the pdev_cca_stats[0] element contains the oldest CCA stats 1565 * and pdev_cca_stats[N-1] will have the most recent CCA stats. 1566 * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; 1567 */ 1568 }; 1569 1570 struct htt_pdev_stats_twt_session_tlv { 1571 u32 vdev_id; 1572 struct htt_mac_addr peer_mac; 1573 u32 flow_id_flags; 1574 1575 /* TWT_DIALOG_ID_UNAVAILABLE is used 1576 * when TWT session is not initiated by host 1577 */ 1578 u32 dialog_id; 1579 u32 wake_dura_us; 1580 u32 wake_intvl_us; 1581 u32 sp_offset_us; 1582 }; 1583 1584 struct htt_pdev_stats_twt_sessions_tlv { 1585 u32 pdev_id; 1586 u32 num_sessions; 1587 struct htt_pdev_stats_twt_session_tlv twt_session[]; 1588 }; 1589 1590 enum htt_rx_reo_resource_sample_id_enum { 1591 /* Global link descriptor queued in REO */ 1592 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, 1593 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, 1594 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, 1595 /*Number of queue descriptors of this aging group */ 1596 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, 1597 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, 1598 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, 1599 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, 1600 /* Total number of MSDUs buffered in AC */ 1601 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, 1602 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, 1603 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, 1604 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, 1605 1606 HTT_RX_REO_RESOURCE_STATS_MAX = 16 1607 }; 1608 1609 struct htt_rx_reo_resource_stats_tlv_v { 1610 /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ 1611 u32 sample_id; 1612 u32 total_max; 1613 u32 total_avg; 1614 u32 total_sample; 1615 u32 non_zeros_avg; 1616 u32 non_zeros_sample; 1617 u32 last_non_zeros_max; 1618 u32 last_non_zeros_min; 1619 u32 last_non_zeros_avg; 1620 u32 last_non_zeros_sample; 1621 }; 1622 1623 /* == TX SOUNDING STATS == */ 1624 1625 enum htt_txbf_sound_steer_modes { 1626 HTT_IMPLICIT_TXBF_STEER_STATS = 0, 1627 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, 1628 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, 1629 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, 1630 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, 1631 HTT_TXBF_MAX_NUM_OF_MODES = 5 1632 }; 1633 1634 enum htt_stats_sounding_tx_mode { 1635 HTT_TX_AC_SOUNDING_MODE = 0, 1636 HTT_TX_AX_SOUNDING_MODE = 1, 1637 }; 1638 1639 struct htt_tx_sounding_stats_tlv { 1640 u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ 1641 /* Counts number of soundings for all steering modes in each bw */ 1642 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; 1643 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; 1644 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; 1645 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; 1646 /* 1647 * The sounding array is a 2-D array stored as an 1-D array of 1648 * u32. The stats for a particular user/bw combination is 1649 * referenced with the following: 1650 * 1651 * sounding[(user* max_bw) + bw] 1652 * 1653 * ... where max_bw == 4 for 160mhz 1654 */ 1655 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1656 }; 1657 1658 struct htt_pdev_obss_pd_stats_tlv { 1659 u32 num_obss_tx_ppdu_success; 1660 u32 num_obss_tx_ppdu_failure; 1661 }; 1662 1663 struct htt_ring_backpressure_stats_tlv { 1664 u32 pdev_id; 1665 u32 current_head_idx; 1666 u32 current_tail_idx; 1667 u32 num_htt_msgs_sent; 1668 /* Time in milliseconds for which the ring has been in 1669 * its current backpressure condition 1670 */ 1671 u32 backpressure_time_ms; 1672 /* backpressure_hist - histogram showing how many times 1673 * different degrees of backpressure duration occurred: 1674 * Index 0 indicates the number of times ring was 1675 * continuously in backpressure state for 100 - 200ms. 1676 * Index 1 indicates the number of times ring was 1677 * continuously in backpressure state for 200 - 300ms. 1678 * Index 2 indicates the number of times ring was 1679 * continuously in backpressure state for 300 - 400ms. 1680 * Index 3 indicates the number of times ring was 1681 * continuously in backpressure state for 400 - 500ms. 1682 * Index 4 indicates the number of times ring was 1683 * continuously in backpressure state beyond 500ms. 1684 */ 1685 u32 backpressure_hist[5]; 1686 }; 1687 1688 #ifdef CONFIG_ATH11K_DEBUGFS 1689 1690 void ath11k_debugfs_htt_stats_init(struct ath11k *ar); 1691 void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1692 struct sk_buff *skb); 1693 int ath11k_debugfs_htt_stats_req(struct ath11k *ar); 1694 1695 #else /* CONFIG_ATH11K_DEBUGFS */ 1696 1697 static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar) 1698 { 1699 } 1700 1701 static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab, 1702 struct sk_buff *skb) 1703 { 1704 } 1705 1706 static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar) 1707 { 1708 return 0; 1709 } 1710 1711 #endif /* CONFIG_ATH11K_DEBUGFS */ 1712 1713 #endif 1714