1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 static const struct ath11k_hw_params ath11k_hw_params[] = { 36 { 37 .hw_rev = ATH11K_HW_IPQ8074, 38 .name = "ipq8074 hw2.0", 39 .fw = { 40 .dir = "IPQ8074/hw2.0", 41 .board_size = 256 * 1024, 42 .cal_offset = 128 * 1024, 43 }, 44 .max_radios = 3, 45 .bdf_addr = 0x4B0C0000, 46 .hw_ops = &ipq8074_ops, 47 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 48 .internal_sleep_clock = false, 49 .regs = &ipq8074_regs, 50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 51 .host_ce_config = ath11k_host_ce_config_ipq8074, 52 .ce_count = 12, 53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 54 .target_ce_count = 11, 55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 56 .svc_to_ce_map_len = 21, 57 .single_pdev_only = false, 58 .rxdma1_enable = true, 59 .num_rxmda_per_pdev = 1, 60 .rx_mac_buf_ring = false, 61 .vdev_start_delay = false, 62 .htt_peer_map_v2 = true, 63 64 .spectral = { 65 .fft_sz = 2, 66 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 67 * so added pad size as 2 bytes to compensate the BIN size 68 */ 69 .fft_pad_sz = 2, 70 .summary_pad_sz = 0, 71 .fft_hdr_len = 16, 72 .max_fft_bins = 512, 73 }, 74 75 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 76 BIT(NL80211_IFTYPE_AP) | 77 BIT(NL80211_IFTYPE_MESH_POINT), 78 .supports_monitor = true, 79 .full_monitor_mode = false, 80 .supports_shadow_regs = false, 81 .idle_ps = false, 82 .supports_sta_ps = false, 83 .cold_boot_calib = true, 84 .fw_mem_mode = 0, 85 .num_vdevs = 16 + 1, 86 .num_peers = 512, 87 .supports_suspend = false, 88 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 89 .supports_regdb = false, 90 .fix_l1ss = true, 91 .credit_flow = false, 92 .max_tx_ring = DP_TCL_NUM_RING_MAX, 93 .hal_params = &ath11k_hw_hal_params_ipq8074, 94 .supports_dynamic_smps_6ghz = false, 95 .alloc_cacheable_memory = true, 96 .supports_rssi_stats = false, 97 .fw_wmi_diag_event = false, 98 .current_cc_support = false, 99 .dbr_debug_support = true, 100 .global_reset = false, 101 .bios_sar_capa = NULL, 102 .m3_fw_support = false, 103 .fixed_bdf_addr = true, 104 .fixed_mem_region = true, 105 .static_window_map = false, 106 .hybrid_bus_type = false, 107 .fixed_fw_mem = false, 108 .support_off_channel_tx = false, 109 }, 110 { 111 .hw_rev = ATH11K_HW_IPQ6018_HW10, 112 .name = "ipq6018 hw1.0", 113 .fw = { 114 .dir = "IPQ6018/hw1.0", 115 .board_size = 256 * 1024, 116 .cal_offset = 128 * 1024, 117 }, 118 .max_radios = 2, 119 .bdf_addr = 0x4ABC0000, 120 .hw_ops = &ipq6018_ops, 121 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 122 .internal_sleep_clock = false, 123 .regs = &ipq8074_regs, 124 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 125 .host_ce_config = ath11k_host_ce_config_ipq8074, 126 .ce_count = 12, 127 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 128 .target_ce_count = 11, 129 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 130 .svc_to_ce_map_len = 19, 131 .single_pdev_only = false, 132 .rxdma1_enable = true, 133 .num_rxmda_per_pdev = 1, 134 .rx_mac_buf_ring = false, 135 .vdev_start_delay = false, 136 .htt_peer_map_v2 = true, 137 138 .spectral = { 139 .fft_sz = 4, 140 .fft_pad_sz = 0, 141 .summary_pad_sz = 0, 142 .fft_hdr_len = 16, 143 .max_fft_bins = 512, 144 }, 145 146 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 147 BIT(NL80211_IFTYPE_AP) | 148 BIT(NL80211_IFTYPE_MESH_POINT), 149 .supports_monitor = true, 150 .full_monitor_mode = false, 151 .supports_shadow_regs = false, 152 .idle_ps = false, 153 .supports_sta_ps = false, 154 .cold_boot_calib = true, 155 .fw_mem_mode = 0, 156 .num_vdevs = 16 + 1, 157 .num_peers = 512, 158 .supports_suspend = false, 159 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 160 .supports_regdb = false, 161 .fix_l1ss = true, 162 .credit_flow = false, 163 .max_tx_ring = DP_TCL_NUM_RING_MAX, 164 .hal_params = &ath11k_hw_hal_params_ipq8074, 165 .supports_dynamic_smps_6ghz = false, 166 .alloc_cacheable_memory = true, 167 .supports_rssi_stats = false, 168 .fw_wmi_diag_event = false, 169 .current_cc_support = false, 170 .dbr_debug_support = true, 171 .global_reset = false, 172 .bios_sar_capa = NULL, 173 .m3_fw_support = false, 174 .fixed_bdf_addr = true, 175 .fixed_mem_region = true, 176 .static_window_map = false, 177 .hybrid_bus_type = false, 178 .fixed_fw_mem = false, 179 .support_off_channel_tx = false, 180 }, 181 { 182 .name = "qca6390 hw2.0", 183 .hw_rev = ATH11K_HW_QCA6390_HW20, 184 .fw = { 185 .dir = "QCA6390/hw2.0", 186 .board_size = 256 * 1024, 187 .cal_offset = 128 * 1024, 188 }, 189 .max_radios = 3, 190 .bdf_addr = 0x4B0C0000, 191 .hw_ops = &qca6390_ops, 192 .ring_mask = &ath11k_hw_ring_mask_qca6390, 193 .internal_sleep_clock = true, 194 .regs = &qca6390_regs, 195 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 196 .host_ce_config = ath11k_host_ce_config_qca6390, 197 .ce_count = 9, 198 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 199 .target_ce_count = 9, 200 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 201 .svc_to_ce_map_len = 14, 202 .single_pdev_only = true, 203 .rxdma1_enable = false, 204 .num_rxmda_per_pdev = 2, 205 .rx_mac_buf_ring = true, 206 .vdev_start_delay = true, 207 .htt_peer_map_v2 = false, 208 209 .spectral = { 210 .fft_sz = 0, 211 .fft_pad_sz = 0, 212 .summary_pad_sz = 0, 213 .fft_hdr_len = 0, 214 .max_fft_bins = 0, 215 }, 216 217 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 218 BIT(NL80211_IFTYPE_AP), 219 .supports_monitor = false, 220 .full_monitor_mode = false, 221 .supports_shadow_regs = true, 222 .idle_ps = true, 223 .supports_sta_ps = true, 224 .cold_boot_calib = false, 225 .fw_mem_mode = 0, 226 .num_vdevs = 16 + 1, 227 .num_peers = 512, 228 .supports_suspend = true, 229 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 230 .supports_regdb = false, 231 .fix_l1ss = true, 232 .credit_flow = true, 233 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 234 .hal_params = &ath11k_hw_hal_params_qca6390, 235 .supports_dynamic_smps_6ghz = false, 236 .alloc_cacheable_memory = false, 237 .supports_rssi_stats = true, 238 .fw_wmi_diag_event = true, 239 .current_cc_support = true, 240 .dbr_debug_support = false, 241 .global_reset = true, 242 .bios_sar_capa = NULL, 243 .m3_fw_support = true, 244 .fixed_bdf_addr = false, 245 .fixed_mem_region = false, 246 .static_window_map = false, 247 .hybrid_bus_type = false, 248 .fixed_fw_mem = false, 249 .support_off_channel_tx = true, 250 }, 251 { 252 .name = "qcn9074 hw1.0", 253 .hw_rev = ATH11K_HW_QCN9074_HW10, 254 .fw = { 255 .dir = "QCN9074/hw1.0", 256 .board_size = 256 * 1024, 257 .cal_offset = 128 * 1024, 258 }, 259 .max_radios = 1, 260 .single_pdev_only = false, 261 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 262 .hw_ops = &qcn9074_ops, 263 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 264 .internal_sleep_clock = false, 265 .regs = &qcn9074_regs, 266 .host_ce_config = ath11k_host_ce_config_qcn9074, 267 .ce_count = 6, 268 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 269 .target_ce_count = 9, 270 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 271 .svc_to_ce_map_len = 18, 272 .rxdma1_enable = true, 273 .num_rxmda_per_pdev = 1, 274 .rx_mac_buf_ring = false, 275 .vdev_start_delay = false, 276 .htt_peer_map_v2 = true, 277 278 .spectral = { 279 .fft_sz = 2, 280 .fft_pad_sz = 0, 281 .summary_pad_sz = 16, 282 .fft_hdr_len = 24, 283 .max_fft_bins = 1024, 284 }, 285 286 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 287 BIT(NL80211_IFTYPE_AP) | 288 BIT(NL80211_IFTYPE_MESH_POINT), 289 .supports_monitor = true, 290 .full_monitor_mode = true, 291 .supports_shadow_regs = false, 292 .idle_ps = false, 293 .supports_sta_ps = false, 294 .cold_boot_calib = false, 295 .fw_mem_mode = 2, 296 .num_vdevs = 8, 297 .num_peers = 128, 298 .supports_suspend = false, 299 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 300 .supports_regdb = false, 301 .fix_l1ss = true, 302 .credit_flow = false, 303 .max_tx_ring = DP_TCL_NUM_RING_MAX, 304 .hal_params = &ath11k_hw_hal_params_ipq8074, 305 .supports_dynamic_smps_6ghz = true, 306 .alloc_cacheable_memory = true, 307 .supports_rssi_stats = false, 308 .fw_wmi_diag_event = false, 309 .current_cc_support = false, 310 .dbr_debug_support = true, 311 .global_reset = false, 312 .bios_sar_capa = NULL, 313 .m3_fw_support = true, 314 .fixed_bdf_addr = false, 315 .fixed_mem_region = false, 316 .static_window_map = true, 317 .hybrid_bus_type = false, 318 .fixed_fw_mem = false, 319 .support_off_channel_tx = false, 320 }, 321 { 322 .name = "wcn6855 hw2.0", 323 .hw_rev = ATH11K_HW_WCN6855_HW20, 324 .fw = { 325 .dir = "WCN6855/hw2.0", 326 .board_size = 256 * 1024, 327 .cal_offset = 128 * 1024, 328 }, 329 .max_radios = 3, 330 .bdf_addr = 0x4B0C0000, 331 .hw_ops = &wcn6855_ops, 332 .ring_mask = &ath11k_hw_ring_mask_qca6390, 333 .internal_sleep_clock = true, 334 .regs = &wcn6855_regs, 335 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 336 .host_ce_config = ath11k_host_ce_config_qca6390, 337 .ce_count = 9, 338 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 339 .target_ce_count = 9, 340 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 341 .svc_to_ce_map_len = 14, 342 .single_pdev_only = true, 343 .rxdma1_enable = false, 344 .num_rxmda_per_pdev = 2, 345 .rx_mac_buf_ring = true, 346 .vdev_start_delay = true, 347 .htt_peer_map_v2 = false, 348 349 .spectral = { 350 .fft_sz = 0, 351 .fft_pad_sz = 0, 352 .summary_pad_sz = 0, 353 .fft_hdr_len = 0, 354 .max_fft_bins = 0, 355 }, 356 357 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 358 BIT(NL80211_IFTYPE_AP), 359 .supports_monitor = false, 360 .full_monitor_mode = false, 361 .supports_shadow_regs = true, 362 .idle_ps = true, 363 .supports_sta_ps = true, 364 .cold_boot_calib = false, 365 .fw_mem_mode = 0, 366 .num_vdevs = 16 + 1, 367 .num_peers = 512, 368 .supports_suspend = true, 369 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 370 .supports_regdb = true, 371 .fix_l1ss = false, 372 .credit_flow = true, 373 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 374 .hal_params = &ath11k_hw_hal_params_qca6390, 375 .supports_dynamic_smps_6ghz = false, 376 .alloc_cacheable_memory = false, 377 .supports_rssi_stats = true, 378 .fw_wmi_diag_event = true, 379 .current_cc_support = true, 380 .dbr_debug_support = false, 381 .global_reset = true, 382 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 383 .m3_fw_support = true, 384 .fixed_bdf_addr = false, 385 .fixed_mem_region = false, 386 .static_window_map = false, 387 .hybrid_bus_type = false, 388 .fixed_fw_mem = false, 389 .support_off_channel_tx = true, 390 }, 391 { 392 .name = "wcn6855 hw2.1", 393 .hw_rev = ATH11K_HW_WCN6855_HW21, 394 .fw = { 395 .dir = "WCN6855/hw2.1", 396 .board_size = 256 * 1024, 397 .cal_offset = 128 * 1024, 398 }, 399 .max_radios = 3, 400 .bdf_addr = 0x4B0C0000, 401 .hw_ops = &wcn6855_ops, 402 .ring_mask = &ath11k_hw_ring_mask_qca6390, 403 .internal_sleep_clock = true, 404 .regs = &wcn6855_regs, 405 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 406 .host_ce_config = ath11k_host_ce_config_qca6390, 407 .ce_count = 9, 408 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 409 .target_ce_count = 9, 410 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 411 .svc_to_ce_map_len = 14, 412 .single_pdev_only = true, 413 .rxdma1_enable = false, 414 .num_rxmda_per_pdev = 2, 415 .rx_mac_buf_ring = true, 416 .vdev_start_delay = true, 417 .htt_peer_map_v2 = false, 418 419 .spectral = { 420 .fft_sz = 0, 421 .fft_pad_sz = 0, 422 .summary_pad_sz = 0, 423 .fft_hdr_len = 0, 424 .max_fft_bins = 0, 425 }, 426 427 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 428 BIT(NL80211_IFTYPE_AP), 429 .supports_monitor = false, 430 .supports_shadow_regs = true, 431 .idle_ps = true, 432 .supports_sta_ps = true, 433 .cold_boot_calib = false, 434 .fw_mem_mode = 0, 435 .num_vdevs = 16 + 1, 436 .num_peers = 512, 437 .supports_suspend = true, 438 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 439 .supports_regdb = true, 440 .fix_l1ss = false, 441 .credit_flow = true, 442 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 443 .hal_params = &ath11k_hw_hal_params_qca6390, 444 .supports_dynamic_smps_6ghz = false, 445 .alloc_cacheable_memory = false, 446 .supports_rssi_stats = true, 447 .fw_wmi_diag_event = true, 448 .current_cc_support = true, 449 .dbr_debug_support = false, 450 .global_reset = true, 451 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 452 .m3_fw_support = true, 453 .fixed_bdf_addr = false, 454 .fixed_mem_region = false, 455 .static_window_map = false, 456 .hybrid_bus_type = false, 457 .fixed_fw_mem = false, 458 .support_off_channel_tx = true, 459 }, 460 { 461 .name = "wcn6750 hw1.0", 462 .hw_rev = ATH11K_HW_WCN6750_HW10, 463 .fw = { 464 .dir = "WCN6750/hw1.0", 465 .board_size = 256 * 1024, 466 .cal_offset = 128 * 1024, 467 }, 468 .max_radios = 1, 469 .bdf_addr = 0x4B0C0000, 470 .hw_ops = &wcn6750_ops, 471 .ring_mask = &ath11k_hw_ring_mask_qca6390, 472 .internal_sleep_clock = false, 473 .regs = &wcn6750_regs, 474 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 475 .host_ce_config = ath11k_host_ce_config_qca6390, 476 .ce_count = 9, 477 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 478 .target_ce_count = 9, 479 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 480 .svc_to_ce_map_len = 14, 481 .single_pdev_only = true, 482 .rxdma1_enable = false, 483 .num_rxmda_per_pdev = 1, 484 .rx_mac_buf_ring = true, 485 .vdev_start_delay = true, 486 .htt_peer_map_v2 = false, 487 488 .spectral = { 489 .fft_sz = 0, 490 .fft_pad_sz = 0, 491 .summary_pad_sz = 0, 492 .fft_hdr_len = 0, 493 .max_fft_bins = 0, 494 }, 495 496 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 497 BIT(NL80211_IFTYPE_AP), 498 .supports_monitor = false, 499 .supports_shadow_regs = true, 500 .idle_ps = true, 501 .supports_sta_ps = true, 502 .cold_boot_calib = false, 503 .fw_mem_mode = 0, 504 .num_vdevs = 16 + 1, 505 .num_peers = 512, 506 .supports_suspend = false, 507 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 508 .supports_regdb = true, 509 .fix_l1ss = false, 510 .credit_flow = true, 511 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 512 .hal_params = &ath11k_hw_hal_params_qca6390, 513 .supports_dynamic_smps_6ghz = false, 514 .alloc_cacheable_memory = false, 515 .supports_rssi_stats = true, 516 .fw_wmi_diag_event = false, 517 .current_cc_support = true, 518 .dbr_debug_support = false, 519 .global_reset = false, 520 .bios_sar_capa = NULL, 521 .m3_fw_support = false, 522 .fixed_bdf_addr = false, 523 .fixed_mem_region = false, 524 .static_window_map = true, 525 .hybrid_bus_type = true, 526 .fixed_fw_mem = true, 527 .support_off_channel_tx = false, 528 }, 529 }; 530 531 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 532 { 533 WARN_ON(!ab->hw_params.single_pdev_only); 534 535 return &ab->pdevs[0]; 536 } 537 538 int ath11k_core_suspend(struct ath11k_base *ab) 539 { 540 int ret; 541 struct ath11k_pdev *pdev; 542 struct ath11k *ar; 543 544 if (!ab->hw_params.supports_suspend) 545 return -EOPNOTSUPP; 546 547 /* so far single_pdev_only chips have supports_suspend as true 548 * and only the first pdev is valid. 549 */ 550 pdev = ath11k_core_get_single_pdev(ab); 551 ar = pdev->ar; 552 if (!ar || ar->state != ATH11K_STATE_OFF) 553 return 0; 554 555 ret = ath11k_dp_rx_pktlog_stop(ab, true); 556 if (ret) { 557 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 558 ret); 559 return ret; 560 } 561 562 ret = ath11k_mac_wait_tx_complete(ar); 563 if (ret) { 564 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 565 return ret; 566 } 567 568 ret = ath11k_wow_enable(ab); 569 if (ret) { 570 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 571 return ret; 572 } 573 574 ret = ath11k_dp_rx_pktlog_stop(ab, false); 575 if (ret) { 576 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 577 ret); 578 return ret; 579 } 580 581 ath11k_ce_stop_shadow_timers(ab); 582 ath11k_dp_stop_shadow_timers(ab); 583 584 ath11k_hif_irq_disable(ab); 585 ath11k_hif_ce_irq_disable(ab); 586 587 ret = ath11k_hif_suspend(ab); 588 if (ret) { 589 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 590 return ret; 591 } 592 593 return 0; 594 } 595 EXPORT_SYMBOL(ath11k_core_suspend); 596 597 int ath11k_core_resume(struct ath11k_base *ab) 598 { 599 int ret; 600 struct ath11k_pdev *pdev; 601 struct ath11k *ar; 602 603 if (!ab->hw_params.supports_suspend) 604 return -EOPNOTSUPP; 605 606 /* so far signle_pdev_only chips have supports_suspend as true 607 * and only the first pdev is valid. 608 */ 609 pdev = ath11k_core_get_single_pdev(ab); 610 ar = pdev->ar; 611 if (!ar || ar->state != ATH11K_STATE_OFF) 612 return 0; 613 614 ret = ath11k_hif_resume(ab); 615 if (ret) { 616 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 617 return ret; 618 } 619 620 ath11k_hif_ce_irq_enable(ab); 621 ath11k_hif_irq_enable(ab); 622 623 ret = ath11k_dp_rx_pktlog_start(ab); 624 if (ret) { 625 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 626 ret); 627 return ret; 628 } 629 630 ret = ath11k_wow_wakeup(ab); 631 if (ret) { 632 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 633 return ret; 634 } 635 636 return 0; 637 } 638 EXPORT_SYMBOL(ath11k_core_resume); 639 640 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 641 { 642 struct ath11k_base *ab = data; 643 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 644 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 645 ssize_t copied; 646 size_t len; 647 int i; 648 649 if (ab->qmi.target.bdf_ext[0] != '\0') 650 return; 651 652 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 653 return; 654 655 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 656 ath11k_dbg(ab, ATH11K_DBG_BOOT, 657 "wrong smbios bdf ext type length (%d).\n", 658 hdr->length); 659 return; 660 } 661 662 spin_lock_bh(&ab->base_lock); 663 664 switch (smbios->country_code_flag) { 665 case ATH11K_SMBIOS_CC_ISO: 666 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 667 ab->new_alpha2[1] = smbios->cc_code & 0xff; 668 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n", 669 ab->new_alpha2[0], ab->new_alpha2[1]); 670 break; 671 case ATH11K_SMBIOS_CC_WW: 672 ab->new_alpha2[0] = '0'; 673 ab->new_alpha2[1] = '0'; 674 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n"); 675 break; 676 default: 677 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n", 678 smbios->country_code_flag); 679 break; 680 } 681 682 spin_unlock_bh(&ab->base_lock); 683 684 if (!smbios->bdf_enabled) { 685 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 686 return; 687 } 688 689 /* Only one string exists (per spec) */ 690 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 691 ath11k_dbg(ab, ATH11K_DBG_BOOT, 692 "bdf variant magic does not match.\n"); 693 return; 694 } 695 696 len = min_t(size_t, 697 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 698 for (i = 0; i < len; i++) { 699 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 700 ath11k_dbg(ab, ATH11K_DBG_BOOT, 701 "bdf variant name contains non ascii chars.\n"); 702 return; 703 } 704 } 705 706 /* Copy extension name without magic prefix */ 707 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 708 sizeof(ab->qmi.target.bdf_ext)); 709 if (copied < 0) { 710 ath11k_dbg(ab, ATH11K_DBG_BOOT, 711 "bdf variant string is longer than the buffer can accommodate\n"); 712 return; 713 } 714 715 ath11k_dbg(ab, ATH11K_DBG_BOOT, 716 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 717 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 718 } 719 720 int ath11k_core_check_smbios(struct ath11k_base *ab) 721 { 722 ab->qmi.target.bdf_ext[0] = '\0'; 723 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 724 725 if (ab->qmi.target.bdf_ext[0] == '\0') 726 return -ENODATA; 727 728 return 0; 729 } 730 731 int ath11k_core_check_dt(struct ath11k_base *ab) 732 { 733 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 734 const char *variant = NULL; 735 struct device_node *node; 736 737 node = ab->dev->of_node; 738 if (!node) 739 return -ENOENT; 740 741 of_property_read_string(node, "qcom,ath11k-calibration-variant", 742 &variant); 743 if (!variant) 744 return -ENODATA; 745 746 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 747 ath11k_dbg(ab, ATH11K_DBG_BOOT, 748 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 749 variant); 750 751 return 0; 752 } 753 754 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 755 size_t name_len, bool with_variant) 756 { 757 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 758 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 759 760 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 761 scnprintf(variant, sizeof(variant), ",variant=%s", 762 ab->qmi.target.bdf_ext); 763 764 switch (ab->id.bdf_search) { 765 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 766 scnprintf(name, name_len, 767 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 768 ath11k_bus_str(ab->hif.bus), 769 ab->id.vendor, ab->id.device, 770 ab->id.subsystem_vendor, 771 ab->id.subsystem_device, 772 ab->qmi.target.chip_id, 773 ab->qmi.target.board_id, 774 variant); 775 break; 776 default: 777 scnprintf(name, name_len, 778 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 779 ath11k_bus_str(ab->hif.bus), 780 ab->qmi.target.chip_id, 781 ab->qmi.target.board_id, variant); 782 break; 783 } 784 785 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name); 786 787 return 0; 788 } 789 790 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 791 size_t name_len) 792 { 793 return __ath11k_core_create_board_name(ab, name, name_len, true); 794 } 795 796 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 797 size_t name_len) 798 { 799 return __ath11k_core_create_board_name(ab, name, name_len, false); 800 } 801 802 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 803 const char *file) 804 { 805 const struct firmware *fw; 806 char path[100]; 807 int ret; 808 809 if (file == NULL) 810 return ERR_PTR(-ENOENT); 811 812 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 813 814 ret = firmware_request_nowarn(&fw, path, ab->dev); 815 if (ret) 816 return ERR_PTR(ret); 817 818 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n", 819 path, fw->size); 820 821 return fw; 822 } 823 824 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 825 { 826 if (!IS_ERR(bd->fw)) 827 release_firmware(bd->fw); 828 829 memset(bd, 0, sizeof(*bd)); 830 } 831 832 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 833 struct ath11k_board_data *bd, 834 const void *buf, size_t buf_len, 835 const char *boardname, 836 int ie_id, 837 int name_id, 838 int data_id) 839 { 840 const struct ath11k_fw_ie *hdr; 841 bool name_match_found; 842 int ret, board_ie_id; 843 size_t board_ie_len; 844 const void *board_ie_data; 845 846 name_match_found = false; 847 848 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 849 while (buf_len > sizeof(struct ath11k_fw_ie)) { 850 hdr = buf; 851 board_ie_id = le32_to_cpu(hdr->id); 852 board_ie_len = le32_to_cpu(hdr->len); 853 board_ie_data = hdr->data; 854 855 buf_len -= sizeof(*hdr); 856 buf += sizeof(*hdr); 857 858 if (buf_len < ALIGN(board_ie_len, 4)) { 859 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 860 ath11k_bd_ie_type_str(ie_id), 861 buf_len, ALIGN(board_ie_len, 4)); 862 ret = -EINVAL; 863 goto out; 864 } 865 866 if (board_ie_id == name_id) { 867 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 868 board_ie_data, board_ie_len); 869 870 if (board_ie_len != strlen(boardname)) 871 goto next; 872 873 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 874 if (ret) 875 goto next; 876 877 name_match_found = true; 878 ath11k_dbg(ab, ATH11K_DBG_BOOT, 879 "boot found match %s for name '%s'", 880 ath11k_bd_ie_type_str(ie_id), 881 boardname); 882 } else if (board_ie_id == data_id) { 883 if (!name_match_found) 884 /* no match found */ 885 goto next; 886 887 ath11k_dbg(ab, ATH11K_DBG_BOOT, 888 "boot found %s for '%s'", 889 ath11k_bd_ie_type_str(ie_id), 890 boardname); 891 892 bd->data = board_ie_data; 893 bd->len = board_ie_len; 894 895 ret = 0; 896 goto out; 897 } else { 898 ath11k_warn(ab, "unknown %s id found: %d\n", 899 ath11k_bd_ie_type_str(ie_id), 900 board_ie_id); 901 } 902 next: 903 /* jump over the padding */ 904 board_ie_len = ALIGN(board_ie_len, 4); 905 906 buf_len -= board_ie_len; 907 buf += board_ie_len; 908 } 909 910 /* no match found */ 911 ret = -ENOENT; 912 913 out: 914 return ret; 915 } 916 917 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 918 struct ath11k_board_data *bd, 919 const char *boardname, 920 int ie_id_match, 921 int name_id, 922 int data_id) 923 { 924 size_t len, magic_len; 925 const u8 *data; 926 char *filename, filepath[100]; 927 size_t ie_len; 928 struct ath11k_fw_ie *hdr; 929 int ret, ie_id; 930 931 filename = ATH11K_BOARD_API2_FILE; 932 933 if (!bd->fw) 934 bd->fw = ath11k_core_firmware_request(ab, filename); 935 936 if (IS_ERR(bd->fw)) 937 return PTR_ERR(bd->fw); 938 939 data = bd->fw->data; 940 len = bd->fw->size; 941 942 ath11k_core_create_firmware_path(ab, filename, 943 filepath, sizeof(filepath)); 944 945 /* magic has extra null byte padded */ 946 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 947 if (len < magic_len) { 948 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 949 filepath, len); 950 ret = -EINVAL; 951 goto err; 952 } 953 954 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 955 ath11k_err(ab, "found invalid board magic\n"); 956 ret = -EINVAL; 957 goto err; 958 } 959 960 /* magic is padded to 4 bytes */ 961 magic_len = ALIGN(magic_len, 4); 962 if (len < magic_len) { 963 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 964 filepath, len); 965 ret = -EINVAL; 966 goto err; 967 } 968 969 data += magic_len; 970 len -= magic_len; 971 972 while (len > sizeof(struct ath11k_fw_ie)) { 973 hdr = (struct ath11k_fw_ie *)data; 974 ie_id = le32_to_cpu(hdr->id); 975 ie_len = le32_to_cpu(hdr->len); 976 977 len -= sizeof(*hdr); 978 data = hdr->data; 979 980 if (len < ALIGN(ie_len, 4)) { 981 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 982 ie_id, ie_len, len); 983 ret = -EINVAL; 984 goto err; 985 } 986 987 if (ie_id == ie_id_match) { 988 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 989 ie_len, 990 boardname, 991 ie_id_match, 992 name_id, 993 data_id); 994 if (ret == -ENOENT) 995 /* no match found, continue */ 996 goto next; 997 else if (ret) 998 /* there was an error, bail out */ 999 goto err; 1000 /* either found or error, so stop searching */ 1001 goto out; 1002 } 1003 next: 1004 /* jump over the padding */ 1005 ie_len = ALIGN(ie_len, 4); 1006 1007 len -= ie_len; 1008 data += ie_len; 1009 } 1010 1011 out: 1012 if (!bd->data || !bd->len) { 1013 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1014 "failed to fetch %s for %s from %s\n", 1015 ath11k_bd_ie_type_str(ie_id_match), 1016 boardname, filepath); 1017 ret = -ENODATA; 1018 goto err; 1019 } 1020 1021 return 0; 1022 1023 err: 1024 ath11k_core_free_bdf(ab, bd); 1025 return ret; 1026 } 1027 1028 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1029 struct ath11k_board_data *bd, 1030 const char *name) 1031 { 1032 bd->fw = ath11k_core_firmware_request(ab, name); 1033 1034 if (IS_ERR(bd->fw)) 1035 return PTR_ERR(bd->fw); 1036 1037 bd->data = bd->fw->data; 1038 bd->len = bd->fw->size; 1039 1040 return 0; 1041 } 1042 1043 #define BOARD_NAME_SIZE 200 1044 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1045 { 1046 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1047 char *filename, filepath[100]; 1048 int ret; 1049 1050 filename = ATH11K_BOARD_API2_FILE; 1051 1052 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1053 if (ret) { 1054 ath11k_err(ab, "failed to create board name: %d", ret); 1055 return ret; 1056 } 1057 1058 ab->bd_api = 2; 1059 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1060 ATH11K_BD_IE_BOARD, 1061 ATH11K_BD_IE_BOARD_NAME, 1062 ATH11K_BD_IE_BOARD_DATA); 1063 if (!ret) 1064 goto success; 1065 1066 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1067 sizeof(fallback_boardname)); 1068 if (ret) { 1069 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1070 return ret; 1071 } 1072 1073 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1074 ATH11K_BD_IE_BOARD, 1075 ATH11K_BD_IE_BOARD_NAME, 1076 ATH11K_BD_IE_BOARD_DATA); 1077 if (!ret) 1078 goto success; 1079 1080 ab->bd_api = 1; 1081 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1082 if (ret) { 1083 ath11k_core_create_firmware_path(ab, filename, 1084 filepath, sizeof(filepath)); 1085 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1086 boardname, filepath); 1087 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1088 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1089 fallback_boardname, filepath); 1090 1091 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1092 ab->hw_params.fw.dir); 1093 return ret; 1094 } 1095 1096 success: 1097 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1098 return 0; 1099 } 1100 1101 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1102 { 1103 char boardname[BOARD_NAME_SIZE]; 1104 int ret; 1105 1106 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1107 if (ret) { 1108 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1109 "failed to create board name for regdb: %d", ret); 1110 goto exit; 1111 } 1112 1113 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1114 ATH11K_BD_IE_REGDB, 1115 ATH11K_BD_IE_REGDB_NAME, 1116 ATH11K_BD_IE_REGDB_DATA); 1117 if (!ret) 1118 goto exit; 1119 1120 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1121 if (ret) 1122 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1123 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1124 1125 exit: 1126 if (!ret) 1127 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1128 1129 return ret; 1130 } 1131 1132 static void ath11k_core_stop(struct ath11k_base *ab) 1133 { 1134 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1135 ath11k_qmi_firmware_stop(ab); 1136 1137 ath11k_hif_stop(ab); 1138 ath11k_wmi_detach(ab); 1139 ath11k_dp_pdev_reo_cleanup(ab); 1140 1141 /* De-Init of components as needed */ 1142 } 1143 1144 static int ath11k_core_soc_create(struct ath11k_base *ab) 1145 { 1146 int ret; 1147 1148 ret = ath11k_qmi_init_service(ab); 1149 if (ret) { 1150 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1151 return ret; 1152 } 1153 1154 ret = ath11k_debugfs_soc_create(ab); 1155 if (ret) { 1156 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1157 goto err_qmi_deinit; 1158 } 1159 1160 ret = ath11k_hif_power_up(ab); 1161 if (ret) { 1162 ath11k_err(ab, "failed to power up :%d\n", ret); 1163 goto err_debugfs_reg; 1164 } 1165 1166 return 0; 1167 1168 err_debugfs_reg: 1169 ath11k_debugfs_soc_destroy(ab); 1170 err_qmi_deinit: 1171 ath11k_qmi_deinit_service(ab); 1172 return ret; 1173 } 1174 1175 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1176 { 1177 ath11k_debugfs_soc_destroy(ab); 1178 ath11k_dp_free(ab); 1179 ath11k_reg_free(ab); 1180 ath11k_qmi_deinit_service(ab); 1181 } 1182 1183 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1184 { 1185 int ret; 1186 1187 ret = ath11k_debugfs_pdev_create(ab); 1188 if (ret) { 1189 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1190 return ret; 1191 } 1192 1193 ret = ath11k_dp_pdev_alloc(ab); 1194 if (ret) { 1195 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1196 goto err_pdev_debug; 1197 } 1198 1199 ret = ath11k_mac_register(ab); 1200 if (ret) { 1201 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1202 goto err_dp_pdev_free; 1203 } 1204 1205 ret = ath11k_thermal_register(ab); 1206 if (ret) { 1207 ath11k_err(ab, "could not register thermal device: %d\n", 1208 ret); 1209 goto err_mac_unregister; 1210 } 1211 1212 ret = ath11k_spectral_init(ab); 1213 if (ret) { 1214 ath11k_err(ab, "failed to init spectral %d\n", ret); 1215 goto err_thermal_unregister; 1216 } 1217 1218 return 0; 1219 1220 err_thermal_unregister: 1221 ath11k_thermal_unregister(ab); 1222 err_mac_unregister: 1223 ath11k_mac_unregister(ab); 1224 err_dp_pdev_free: 1225 ath11k_dp_pdev_free(ab); 1226 err_pdev_debug: 1227 ath11k_debugfs_pdev_destroy(ab); 1228 1229 return ret; 1230 } 1231 1232 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1233 { 1234 ath11k_spectral_deinit(ab); 1235 ath11k_thermal_unregister(ab); 1236 ath11k_mac_unregister(ab); 1237 ath11k_hif_irq_disable(ab); 1238 ath11k_dp_pdev_free(ab); 1239 ath11k_debugfs_pdev_destroy(ab); 1240 } 1241 1242 static int ath11k_core_start(struct ath11k_base *ab) 1243 { 1244 int ret; 1245 1246 ret = ath11k_wmi_attach(ab); 1247 if (ret) { 1248 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1249 return ret; 1250 } 1251 1252 ret = ath11k_htc_init(ab); 1253 if (ret) { 1254 ath11k_err(ab, "failed to init htc: %d\n", ret); 1255 goto err_wmi_detach; 1256 } 1257 1258 ret = ath11k_hif_start(ab); 1259 if (ret) { 1260 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1261 goto err_wmi_detach; 1262 } 1263 1264 ret = ath11k_htc_wait_target(&ab->htc); 1265 if (ret) { 1266 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1267 goto err_hif_stop; 1268 } 1269 1270 ret = ath11k_dp_htt_connect(&ab->dp); 1271 if (ret) { 1272 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1273 goto err_hif_stop; 1274 } 1275 1276 ret = ath11k_wmi_connect(ab); 1277 if (ret) { 1278 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1279 goto err_hif_stop; 1280 } 1281 1282 ret = ath11k_htc_start(&ab->htc); 1283 if (ret) { 1284 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1285 goto err_hif_stop; 1286 } 1287 1288 ret = ath11k_wmi_wait_for_service_ready(ab); 1289 if (ret) { 1290 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1291 ret); 1292 goto err_hif_stop; 1293 } 1294 1295 ret = ath11k_mac_allocate(ab); 1296 if (ret) { 1297 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1298 ret); 1299 goto err_hif_stop; 1300 } 1301 1302 ath11k_dp_pdev_pre_alloc(ab); 1303 1304 ret = ath11k_dp_pdev_reo_setup(ab); 1305 if (ret) { 1306 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1307 goto err_mac_destroy; 1308 } 1309 1310 ret = ath11k_wmi_cmd_init(ab); 1311 if (ret) { 1312 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1313 goto err_reo_cleanup; 1314 } 1315 1316 ret = ath11k_wmi_wait_for_unified_ready(ab); 1317 if (ret) { 1318 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1319 ret); 1320 goto err_reo_cleanup; 1321 } 1322 1323 /* put hardware to DBS mode */ 1324 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1325 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1326 if (ret) { 1327 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1328 goto err_hif_stop; 1329 } 1330 } 1331 1332 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1333 if (ret) { 1334 ath11k_err(ab, "failed to send htt version request message: %d\n", 1335 ret); 1336 goto err_reo_cleanup; 1337 } 1338 1339 return 0; 1340 1341 err_reo_cleanup: 1342 ath11k_dp_pdev_reo_cleanup(ab); 1343 err_mac_destroy: 1344 ath11k_mac_destroy(ab); 1345 err_hif_stop: 1346 ath11k_hif_stop(ab); 1347 err_wmi_detach: 1348 ath11k_wmi_detach(ab); 1349 1350 return ret; 1351 } 1352 1353 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1354 enum ath11k_firmware_mode mode) 1355 { 1356 int ret; 1357 1358 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1359 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1360 1361 ret = ath11k_qmi_firmware_start(ab, mode); 1362 if (ret) { 1363 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1364 return ret; 1365 } 1366 1367 return ret; 1368 } 1369 1370 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1371 { 1372 int ret; 1373 1374 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); 1375 if (ret) { 1376 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1377 return ret; 1378 } 1379 1380 ret = ath11k_ce_init_pipes(ab); 1381 if (ret) { 1382 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1383 goto err_firmware_stop; 1384 } 1385 1386 ret = ath11k_dp_alloc(ab); 1387 if (ret) { 1388 ath11k_err(ab, "failed to init DP: %d\n", ret); 1389 goto err_firmware_stop; 1390 } 1391 1392 switch (ath11k_crypto_mode) { 1393 case ATH11K_CRYPT_MODE_SW: 1394 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1395 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1396 break; 1397 case ATH11K_CRYPT_MODE_HW: 1398 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1399 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1400 break; 1401 default: 1402 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1403 return -EINVAL; 1404 } 1405 1406 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1407 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1408 1409 mutex_lock(&ab->core_lock); 1410 ret = ath11k_core_start(ab); 1411 if (ret) { 1412 ath11k_err(ab, "failed to start core: %d\n", ret); 1413 goto err_dp_free; 1414 } 1415 1416 ret = ath11k_core_pdev_create(ab); 1417 if (ret) { 1418 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1419 goto err_core_stop; 1420 } 1421 ath11k_hif_irq_enable(ab); 1422 mutex_unlock(&ab->core_lock); 1423 1424 return 0; 1425 1426 err_core_stop: 1427 ath11k_core_stop(ab); 1428 ath11k_mac_destroy(ab); 1429 err_dp_free: 1430 ath11k_dp_free(ab); 1431 mutex_unlock(&ab->core_lock); 1432 err_firmware_stop: 1433 ath11k_qmi_firmware_stop(ab); 1434 1435 return ret; 1436 } 1437 1438 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1439 { 1440 int ret; 1441 1442 mutex_lock(&ab->core_lock); 1443 ath11k_thermal_unregister(ab); 1444 ath11k_hif_irq_disable(ab); 1445 ath11k_dp_pdev_free(ab); 1446 ath11k_spectral_deinit(ab); 1447 ath11k_hif_stop(ab); 1448 ath11k_wmi_detach(ab); 1449 ath11k_dp_pdev_reo_cleanup(ab); 1450 mutex_unlock(&ab->core_lock); 1451 1452 ath11k_dp_free(ab); 1453 ath11k_hal_srng_deinit(ab); 1454 1455 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1456 1457 ret = ath11k_hal_srng_init(ab); 1458 if (ret) 1459 return ret; 1460 1461 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1462 1463 ret = ath11k_core_qmi_firmware_ready(ab); 1464 if (ret) 1465 goto err_hal_srng_deinit; 1466 1467 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1468 1469 return 0; 1470 1471 err_hal_srng_deinit: 1472 ath11k_hal_srng_deinit(ab); 1473 return ret; 1474 } 1475 1476 void ath11k_core_halt(struct ath11k *ar) 1477 { 1478 struct ath11k_base *ab = ar->ab; 1479 1480 lockdep_assert_held(&ar->conf_mutex); 1481 1482 ar->num_created_vdevs = 0; 1483 ar->allocated_vdev_map = 0; 1484 1485 ath11k_mac_scan_finish(ar); 1486 ath11k_mac_peer_cleanup_all(ar); 1487 cancel_delayed_work_sync(&ar->scan.timeout); 1488 cancel_work_sync(&ar->regd_update_work); 1489 cancel_work_sync(&ab->update_11d_work); 1490 1491 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1492 synchronize_rcu(); 1493 INIT_LIST_HEAD(&ar->arvifs); 1494 idr_init(&ar->txmgmt_idr); 1495 } 1496 1497 static void ath11k_update_11d(struct work_struct *work) 1498 { 1499 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1500 struct ath11k *ar; 1501 struct ath11k_pdev *pdev; 1502 struct wmi_set_current_country_params set_current_param = {}; 1503 int ret, i; 1504 1505 spin_lock_bh(&ab->base_lock); 1506 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1507 spin_unlock_bh(&ab->base_lock); 1508 1509 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1510 set_current_param.alpha2[0], 1511 set_current_param.alpha2[1]); 1512 1513 for (i = 0; i < ab->num_radios; i++) { 1514 pdev = &ab->pdevs[i]; 1515 ar = pdev->ar; 1516 1517 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1518 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1519 if (ret) 1520 ath11k_warn(ar->ab, 1521 "pdev id %d failed set current country code: %d\n", 1522 i, ret); 1523 } 1524 } 1525 1526 static void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1527 { 1528 struct ath11k *ar; 1529 struct ath11k_pdev *pdev; 1530 int i; 1531 1532 spin_lock_bh(&ab->base_lock); 1533 ab->stats.fw_crash_counter++; 1534 spin_unlock_bh(&ab->base_lock); 1535 1536 for (i = 0; i < ab->num_radios; i++) { 1537 pdev = &ab->pdevs[i]; 1538 ar = pdev->ar; 1539 if (!ar || ar->state == ATH11K_STATE_OFF) 1540 continue; 1541 1542 ieee80211_stop_queues(ar->hw); 1543 ath11k_mac_drain_tx(ar); 1544 ar->state_11d = ATH11K_11D_IDLE; 1545 complete(&ar->completed_11d_scan); 1546 complete(&ar->scan.started); 1547 complete(&ar->scan.completed); 1548 complete(&ar->scan.on_channel); 1549 complete(&ar->peer_assoc_done); 1550 complete(&ar->peer_delete_done); 1551 complete(&ar->install_key_done); 1552 complete(&ar->vdev_setup_done); 1553 complete(&ar->vdev_delete_done); 1554 complete(&ar->bss_survey_done); 1555 complete(&ar->thermal.wmi_sync); 1556 1557 wake_up(&ar->dp.tx_empty_waitq); 1558 idr_for_each(&ar->txmgmt_idr, 1559 ath11k_mac_tx_mgmt_pending_free, ar); 1560 idr_destroy(&ar->txmgmt_idr); 1561 wake_up(&ar->txmgmt_empty_waitq); 1562 } 1563 1564 wake_up(&ab->wmi_ab.tx_credits_wq); 1565 wake_up(&ab->peer_mapping_wq); 1566 } 1567 1568 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1569 { 1570 struct ath11k *ar; 1571 struct ath11k_pdev *pdev; 1572 int i; 1573 1574 for (i = 0; i < ab->num_radios; i++) { 1575 pdev = &ab->pdevs[i]; 1576 ar = pdev->ar; 1577 if (!ar || ar->state == ATH11K_STATE_OFF) 1578 continue; 1579 1580 mutex_lock(&ar->conf_mutex); 1581 1582 switch (ar->state) { 1583 case ATH11K_STATE_ON: 1584 ar->state = ATH11K_STATE_RESTARTING; 1585 ath11k_core_halt(ar); 1586 ieee80211_restart_hw(ar->hw); 1587 break; 1588 case ATH11K_STATE_OFF: 1589 ath11k_warn(ab, 1590 "cannot restart radio %d that hasn't been started\n", 1591 i); 1592 break; 1593 case ATH11K_STATE_RESTARTING: 1594 break; 1595 case ATH11K_STATE_RESTARTED: 1596 ar->state = ATH11K_STATE_WEDGED; 1597 fallthrough; 1598 case ATH11K_STATE_WEDGED: 1599 ath11k_warn(ab, 1600 "device is wedged, will not restart radio %d\n", i); 1601 break; 1602 } 1603 mutex_unlock(&ar->conf_mutex); 1604 } 1605 complete(&ab->driver_recovery); 1606 } 1607 1608 static void ath11k_core_restart(struct work_struct *work) 1609 { 1610 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1611 int ret; 1612 1613 if (!ab->is_reset) 1614 ath11k_core_pre_reconfigure_recovery(ab); 1615 1616 ret = ath11k_core_reconfigure_on_crash(ab); 1617 if (ret) { 1618 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1619 return; 1620 } 1621 1622 if (ab->is_reset) 1623 complete_all(&ab->reconfigure_complete); 1624 1625 if (!ab->is_reset) 1626 ath11k_core_post_reconfigure_recovery(ab); 1627 } 1628 1629 static void ath11k_core_reset(struct work_struct *work) 1630 { 1631 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1632 int reset_count, fail_cont_count; 1633 long time_left; 1634 1635 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1636 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1637 return; 1638 } 1639 1640 /* Sometimes the recovery will fail and then the next all recovery fail, 1641 * this is to avoid infinite recovery since it can not recovery success. 1642 */ 1643 fail_cont_count = atomic_read(&ab->fail_cont_count); 1644 1645 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1646 return; 1647 1648 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1649 time_before(jiffies, ab->reset_fail_timeout)) 1650 return; 1651 1652 reset_count = atomic_inc_return(&ab->reset_count); 1653 1654 if (reset_count > 1) { 1655 /* Sometimes it happened another reset worker before the previous one 1656 * completed, then the second reset worker will destroy the previous one, 1657 * thus below is to avoid that. 1658 */ 1659 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1660 1661 reinit_completion(&ab->reset_complete); 1662 time_left = wait_for_completion_timeout(&ab->reset_complete, 1663 ATH11K_RESET_TIMEOUT_HZ); 1664 1665 if (time_left) { 1666 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1667 atomic_dec(&ab->reset_count); 1668 return; 1669 } 1670 1671 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1672 /* Record the continuous recovery fail count when recovery failed*/ 1673 atomic_inc(&ab->fail_cont_count); 1674 } 1675 1676 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1677 1678 ab->is_reset = true; 1679 atomic_set(&ab->recovery_count, 0); 1680 reinit_completion(&ab->recovery_start); 1681 atomic_set(&ab->recovery_start_count, 0); 1682 1683 ath11k_core_pre_reconfigure_recovery(ab); 1684 1685 reinit_completion(&ab->reconfigure_complete); 1686 ath11k_core_post_reconfigure_recovery(ab); 1687 1688 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1689 1690 time_left = wait_for_completion_timeout(&ab->recovery_start, 1691 ATH11K_RECOVER_START_TIMEOUT_HZ); 1692 1693 ath11k_hif_power_down(ab); 1694 ath11k_hif_power_up(ab); 1695 1696 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1697 } 1698 1699 static int ath11k_init_hw_params(struct ath11k_base *ab) 1700 { 1701 const struct ath11k_hw_params *hw_params = NULL; 1702 int i; 1703 1704 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1705 hw_params = &ath11k_hw_params[i]; 1706 1707 if (hw_params->hw_rev == ab->hw_rev) 1708 break; 1709 } 1710 1711 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1712 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1713 return -EINVAL; 1714 } 1715 1716 ab->hw_params = *hw_params; 1717 1718 ath11k_info(ab, "%s\n", ab->hw_params.name); 1719 1720 return 0; 1721 } 1722 1723 int ath11k_core_pre_init(struct ath11k_base *ab) 1724 { 1725 int ret; 1726 1727 ret = ath11k_init_hw_params(ab); 1728 if (ret) { 1729 ath11k_err(ab, "failed to get hw params: %d\n", ret); 1730 return ret; 1731 } 1732 1733 return 0; 1734 } 1735 EXPORT_SYMBOL(ath11k_core_pre_init); 1736 1737 int ath11k_core_init(struct ath11k_base *ab) 1738 { 1739 int ret; 1740 1741 ret = ath11k_core_soc_create(ab); 1742 if (ret) { 1743 ath11k_err(ab, "failed to create soc core: %d\n", ret); 1744 return ret; 1745 } 1746 1747 return 0; 1748 } 1749 EXPORT_SYMBOL(ath11k_core_init); 1750 1751 void ath11k_core_deinit(struct ath11k_base *ab) 1752 { 1753 mutex_lock(&ab->core_lock); 1754 1755 ath11k_core_pdev_destroy(ab); 1756 ath11k_core_stop(ab); 1757 1758 mutex_unlock(&ab->core_lock); 1759 1760 ath11k_hif_power_down(ab); 1761 ath11k_mac_destroy(ab); 1762 ath11k_core_soc_destroy(ab); 1763 } 1764 EXPORT_SYMBOL(ath11k_core_deinit); 1765 1766 void ath11k_core_free(struct ath11k_base *ab) 1767 { 1768 destroy_workqueue(ab->workqueue_aux); 1769 destroy_workqueue(ab->workqueue); 1770 1771 kfree(ab); 1772 } 1773 EXPORT_SYMBOL(ath11k_core_free); 1774 1775 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1776 enum ath11k_bus bus) 1777 { 1778 struct ath11k_base *ab; 1779 1780 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 1781 if (!ab) 1782 return NULL; 1783 1784 init_completion(&ab->driver_recovery); 1785 1786 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 1787 if (!ab->workqueue) 1788 goto err_sc_free; 1789 1790 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 1791 if (!ab->workqueue_aux) 1792 goto err_free_wq; 1793 1794 mutex_init(&ab->core_lock); 1795 mutex_init(&ab->tbl_mtx_lock); 1796 spin_lock_init(&ab->base_lock); 1797 mutex_init(&ab->vdev_id_11d_lock); 1798 init_completion(&ab->reset_complete); 1799 init_completion(&ab->reconfigure_complete); 1800 init_completion(&ab->recovery_start); 1801 1802 INIT_LIST_HEAD(&ab->peers); 1803 init_waitqueue_head(&ab->peer_mapping_wq); 1804 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 1805 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 1806 INIT_WORK(&ab->restart_work, ath11k_core_restart); 1807 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 1808 INIT_WORK(&ab->reset_work, ath11k_core_reset); 1809 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 1810 init_completion(&ab->htc_suspend); 1811 init_completion(&ab->wow.wakeup_completed); 1812 1813 ab->dev = dev; 1814 ab->hif.bus = bus; 1815 1816 return ab; 1817 1818 err_free_wq: 1819 destroy_workqueue(ab->workqueue); 1820 err_sc_free: 1821 kfree(ab); 1822 return NULL; 1823 } 1824 EXPORT_SYMBOL(ath11k_core_alloc); 1825 1826 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 1827 MODULE_LICENSE("Dual BSD/GPL"); 1828