1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 static const struct ath11k_hw_params ath11k_hw_params[] = { 36 { 37 .hw_rev = ATH11K_HW_IPQ8074, 38 .name = "ipq8074 hw2.0", 39 .fw = { 40 .dir = "IPQ8074/hw2.0", 41 .board_size = 256 * 1024, 42 .cal_offset = 128 * 1024, 43 }, 44 .max_radios = 3, 45 .bdf_addr = 0x4B0C0000, 46 .hw_ops = &ipq8074_ops, 47 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 48 .internal_sleep_clock = false, 49 .regs = &ipq8074_regs, 50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 51 .host_ce_config = ath11k_host_ce_config_ipq8074, 52 .ce_count = 12, 53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 54 .target_ce_count = 11, 55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 56 .svc_to_ce_map_len = 21, 57 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 58 .single_pdev_only = false, 59 .rxdma1_enable = true, 60 .num_rxmda_per_pdev = 1, 61 .rx_mac_buf_ring = false, 62 .vdev_start_delay = false, 63 .htt_peer_map_v2 = true, 64 65 .spectral = { 66 .fft_sz = 2, 67 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 68 * so added pad size as 2 bytes to compensate the BIN size 69 */ 70 .fft_pad_sz = 2, 71 .summary_pad_sz = 0, 72 .fft_hdr_len = 16, 73 .max_fft_bins = 512, 74 .fragment_160mhz = true, 75 }, 76 77 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 78 BIT(NL80211_IFTYPE_AP) | 79 BIT(NL80211_IFTYPE_MESH_POINT), 80 .supports_monitor = true, 81 .full_monitor_mode = false, 82 .supports_shadow_regs = false, 83 .idle_ps = false, 84 .supports_sta_ps = false, 85 .cold_boot_calib = true, 86 .cbcal_restart_fw = true, 87 .fw_mem_mode = 0, 88 .num_vdevs = 16 + 1, 89 .num_peers = 512, 90 .supports_suspend = false, 91 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 92 .supports_regdb = false, 93 .fix_l1ss = true, 94 .credit_flow = false, 95 .max_tx_ring = DP_TCL_NUM_RING_MAX, 96 .hal_params = &ath11k_hw_hal_params_ipq8074, 97 .supports_dynamic_smps_6ghz = false, 98 .alloc_cacheable_memory = true, 99 .supports_rssi_stats = false, 100 .fw_wmi_diag_event = false, 101 .current_cc_support = false, 102 .dbr_debug_support = true, 103 .global_reset = false, 104 .bios_sar_capa = NULL, 105 .m3_fw_support = false, 106 .fixed_bdf_addr = true, 107 .fixed_mem_region = true, 108 .static_window_map = false, 109 .hybrid_bus_type = false, 110 .fixed_fw_mem = false, 111 .support_off_channel_tx = false, 112 .supports_multi_bssid = false, 113 114 .sram_dump = {}, 115 116 .tcl_ring_retry = true, 117 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 118 .smp2p_wow_exit = false, 119 }, 120 { 121 .hw_rev = ATH11K_HW_IPQ6018_HW10, 122 .name = "ipq6018 hw1.0", 123 .fw = { 124 .dir = "IPQ6018/hw1.0", 125 .board_size = 256 * 1024, 126 .cal_offset = 128 * 1024, 127 }, 128 .max_radios = 2, 129 .bdf_addr = 0x4ABC0000, 130 .hw_ops = &ipq6018_ops, 131 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 132 .internal_sleep_clock = false, 133 .regs = &ipq8074_regs, 134 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 135 .host_ce_config = ath11k_host_ce_config_ipq8074, 136 .ce_count = 12, 137 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 138 .target_ce_count = 11, 139 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 140 .svc_to_ce_map_len = 19, 141 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 142 .single_pdev_only = false, 143 .rxdma1_enable = true, 144 .num_rxmda_per_pdev = 1, 145 .rx_mac_buf_ring = false, 146 .vdev_start_delay = false, 147 .htt_peer_map_v2 = true, 148 149 .spectral = { 150 .fft_sz = 4, 151 .fft_pad_sz = 0, 152 .summary_pad_sz = 0, 153 .fft_hdr_len = 16, 154 .max_fft_bins = 512, 155 .fragment_160mhz = true, 156 }, 157 158 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 159 BIT(NL80211_IFTYPE_AP) | 160 BIT(NL80211_IFTYPE_MESH_POINT), 161 .supports_monitor = true, 162 .full_monitor_mode = false, 163 .supports_shadow_regs = false, 164 .idle_ps = false, 165 .supports_sta_ps = false, 166 .cold_boot_calib = true, 167 .cbcal_restart_fw = true, 168 .fw_mem_mode = 0, 169 .num_vdevs = 16 + 1, 170 .num_peers = 512, 171 .supports_suspend = false, 172 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 173 .supports_regdb = false, 174 .fix_l1ss = true, 175 .credit_flow = false, 176 .max_tx_ring = DP_TCL_NUM_RING_MAX, 177 .hal_params = &ath11k_hw_hal_params_ipq8074, 178 .supports_dynamic_smps_6ghz = false, 179 .alloc_cacheable_memory = true, 180 .supports_rssi_stats = false, 181 .fw_wmi_diag_event = false, 182 .current_cc_support = false, 183 .dbr_debug_support = true, 184 .global_reset = false, 185 .bios_sar_capa = NULL, 186 .m3_fw_support = false, 187 .fixed_bdf_addr = true, 188 .fixed_mem_region = true, 189 .static_window_map = false, 190 .hybrid_bus_type = false, 191 .fixed_fw_mem = false, 192 .support_off_channel_tx = false, 193 .supports_multi_bssid = false, 194 195 .sram_dump = {}, 196 197 .tcl_ring_retry = true, 198 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 199 .smp2p_wow_exit = false, 200 .support_fw_mac_sequence = false, 201 }, 202 { 203 .name = "qca6390 hw2.0", 204 .hw_rev = ATH11K_HW_QCA6390_HW20, 205 .fw = { 206 .dir = "QCA6390/hw2.0", 207 .board_size = 256 * 1024, 208 .cal_offset = 128 * 1024, 209 }, 210 .max_radios = 3, 211 .bdf_addr = 0x4B0C0000, 212 .hw_ops = &qca6390_ops, 213 .ring_mask = &ath11k_hw_ring_mask_qca6390, 214 .internal_sleep_clock = true, 215 .regs = &qca6390_regs, 216 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 217 .host_ce_config = ath11k_host_ce_config_qca6390, 218 .ce_count = 9, 219 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 220 .target_ce_count = 9, 221 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 222 .svc_to_ce_map_len = 14, 223 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 224 .single_pdev_only = true, 225 .rxdma1_enable = false, 226 .num_rxmda_per_pdev = 2, 227 .rx_mac_buf_ring = true, 228 .vdev_start_delay = true, 229 .htt_peer_map_v2 = false, 230 231 .spectral = { 232 .fft_sz = 0, 233 .fft_pad_sz = 0, 234 .summary_pad_sz = 0, 235 .fft_hdr_len = 0, 236 .max_fft_bins = 0, 237 .fragment_160mhz = false, 238 }, 239 240 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 241 BIT(NL80211_IFTYPE_AP), 242 .supports_monitor = false, 243 .full_monitor_mode = false, 244 .supports_shadow_regs = true, 245 .idle_ps = true, 246 .supports_sta_ps = true, 247 .cold_boot_calib = false, 248 .cbcal_restart_fw = false, 249 .fw_mem_mode = 0, 250 .num_vdevs = 16 + 1, 251 .num_peers = 512, 252 .supports_suspend = true, 253 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 254 .supports_regdb = false, 255 .fix_l1ss = true, 256 .credit_flow = true, 257 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 258 .hal_params = &ath11k_hw_hal_params_qca6390, 259 .supports_dynamic_smps_6ghz = false, 260 .alloc_cacheable_memory = false, 261 .supports_rssi_stats = true, 262 .fw_wmi_diag_event = true, 263 .current_cc_support = true, 264 .dbr_debug_support = false, 265 .global_reset = true, 266 .bios_sar_capa = NULL, 267 .m3_fw_support = true, 268 .fixed_bdf_addr = false, 269 .fixed_mem_region = false, 270 .static_window_map = false, 271 .hybrid_bus_type = false, 272 .fixed_fw_mem = false, 273 .support_off_channel_tx = true, 274 .supports_multi_bssid = true, 275 276 .sram_dump = { 277 .start = 0x01400000, 278 .end = 0x0171ffff, 279 }, 280 281 .tcl_ring_retry = true, 282 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 283 .smp2p_wow_exit = false, 284 .support_fw_mac_sequence = true, 285 }, 286 { 287 .name = "qcn9074 hw1.0", 288 .hw_rev = ATH11K_HW_QCN9074_HW10, 289 .fw = { 290 .dir = "QCN9074/hw1.0", 291 .board_size = 256 * 1024, 292 .cal_offset = 128 * 1024, 293 }, 294 .max_radios = 1, 295 .single_pdev_only = false, 296 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 297 .hw_ops = &qcn9074_ops, 298 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 299 .internal_sleep_clock = false, 300 .regs = &qcn9074_regs, 301 .host_ce_config = ath11k_host_ce_config_qcn9074, 302 .ce_count = 6, 303 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 304 .target_ce_count = 9, 305 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 306 .svc_to_ce_map_len = 18, 307 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 308 .rxdma1_enable = true, 309 .num_rxmda_per_pdev = 1, 310 .rx_mac_buf_ring = false, 311 .vdev_start_delay = false, 312 .htt_peer_map_v2 = true, 313 314 .spectral = { 315 .fft_sz = 2, 316 .fft_pad_sz = 0, 317 .summary_pad_sz = 16, 318 .fft_hdr_len = 24, 319 .max_fft_bins = 1024, 320 .fragment_160mhz = false, 321 }, 322 323 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 324 BIT(NL80211_IFTYPE_AP) | 325 BIT(NL80211_IFTYPE_MESH_POINT), 326 .supports_monitor = true, 327 .full_monitor_mode = true, 328 .supports_shadow_regs = false, 329 .idle_ps = false, 330 .supports_sta_ps = false, 331 .cold_boot_calib = false, 332 .cbcal_restart_fw = false, 333 .fw_mem_mode = 2, 334 .num_vdevs = 8, 335 .num_peers = 128, 336 .supports_suspend = false, 337 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 338 .supports_regdb = false, 339 .fix_l1ss = true, 340 .credit_flow = false, 341 .max_tx_ring = DP_TCL_NUM_RING_MAX, 342 .hal_params = &ath11k_hw_hal_params_ipq8074, 343 .supports_dynamic_smps_6ghz = true, 344 .alloc_cacheable_memory = true, 345 .supports_rssi_stats = false, 346 .fw_wmi_diag_event = false, 347 .current_cc_support = false, 348 .dbr_debug_support = true, 349 .global_reset = false, 350 .bios_sar_capa = NULL, 351 .m3_fw_support = true, 352 .fixed_bdf_addr = false, 353 .fixed_mem_region = false, 354 .static_window_map = true, 355 .hybrid_bus_type = false, 356 .fixed_fw_mem = false, 357 .support_off_channel_tx = false, 358 .supports_multi_bssid = false, 359 360 .sram_dump = {}, 361 362 .tcl_ring_retry = true, 363 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 364 .smp2p_wow_exit = false, 365 .support_fw_mac_sequence = false, 366 }, 367 { 368 .name = "wcn6855 hw2.0", 369 .hw_rev = ATH11K_HW_WCN6855_HW20, 370 .fw = { 371 .dir = "WCN6855/hw2.0", 372 .board_size = 256 * 1024, 373 .cal_offset = 128 * 1024, 374 }, 375 .max_radios = 3, 376 .bdf_addr = 0x4B0C0000, 377 .hw_ops = &wcn6855_ops, 378 .ring_mask = &ath11k_hw_ring_mask_qca6390, 379 .internal_sleep_clock = true, 380 .regs = &wcn6855_regs, 381 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 382 .host_ce_config = ath11k_host_ce_config_qca6390, 383 .ce_count = 9, 384 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 385 .target_ce_count = 9, 386 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 387 .svc_to_ce_map_len = 14, 388 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 389 .single_pdev_only = true, 390 .rxdma1_enable = false, 391 .num_rxmda_per_pdev = 2, 392 .rx_mac_buf_ring = true, 393 .vdev_start_delay = true, 394 .htt_peer_map_v2 = false, 395 396 .spectral = { 397 .fft_sz = 0, 398 .fft_pad_sz = 0, 399 .summary_pad_sz = 0, 400 .fft_hdr_len = 0, 401 .max_fft_bins = 0, 402 .fragment_160mhz = false, 403 }, 404 405 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 406 BIT(NL80211_IFTYPE_AP), 407 .supports_monitor = false, 408 .full_monitor_mode = false, 409 .supports_shadow_regs = true, 410 .idle_ps = true, 411 .supports_sta_ps = true, 412 .cold_boot_calib = false, 413 .cbcal_restart_fw = false, 414 .fw_mem_mode = 0, 415 .num_vdevs = 16 + 1, 416 .num_peers = 512, 417 .supports_suspend = true, 418 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 419 .supports_regdb = true, 420 .fix_l1ss = false, 421 .credit_flow = true, 422 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 423 .hal_params = &ath11k_hw_hal_params_qca6390, 424 .supports_dynamic_smps_6ghz = false, 425 .alloc_cacheable_memory = false, 426 .supports_rssi_stats = true, 427 .fw_wmi_diag_event = true, 428 .current_cc_support = true, 429 .dbr_debug_support = false, 430 .global_reset = true, 431 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 432 .m3_fw_support = true, 433 .fixed_bdf_addr = false, 434 .fixed_mem_region = false, 435 .static_window_map = false, 436 .hybrid_bus_type = false, 437 .fixed_fw_mem = false, 438 .support_off_channel_tx = true, 439 .supports_multi_bssid = true, 440 441 .sram_dump = { 442 .start = 0x01400000, 443 .end = 0x0177ffff, 444 }, 445 446 .tcl_ring_retry = true, 447 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 448 .smp2p_wow_exit = false, 449 .support_fw_mac_sequence = true, 450 }, 451 { 452 .name = "wcn6855 hw2.1", 453 .hw_rev = ATH11K_HW_WCN6855_HW21, 454 .fw = { 455 .dir = "WCN6855/hw2.1", 456 .board_size = 256 * 1024, 457 .cal_offset = 128 * 1024, 458 }, 459 .max_radios = 3, 460 .bdf_addr = 0x4B0C0000, 461 .hw_ops = &wcn6855_ops, 462 .ring_mask = &ath11k_hw_ring_mask_qca6390, 463 .internal_sleep_clock = true, 464 .regs = &wcn6855_regs, 465 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 466 .host_ce_config = ath11k_host_ce_config_qca6390, 467 .ce_count = 9, 468 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 469 .target_ce_count = 9, 470 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 471 .svc_to_ce_map_len = 14, 472 .single_pdev_only = true, 473 .rxdma1_enable = false, 474 .num_rxmda_per_pdev = 2, 475 .rx_mac_buf_ring = true, 476 .vdev_start_delay = true, 477 .htt_peer_map_v2 = false, 478 479 .spectral = { 480 .fft_sz = 0, 481 .fft_pad_sz = 0, 482 .summary_pad_sz = 0, 483 .fft_hdr_len = 0, 484 .max_fft_bins = 0, 485 .fragment_160mhz = false, 486 }, 487 488 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 489 BIT(NL80211_IFTYPE_AP), 490 .supports_monitor = false, 491 .supports_shadow_regs = true, 492 .idle_ps = true, 493 .supports_sta_ps = true, 494 .cold_boot_calib = false, 495 .cbcal_restart_fw = false, 496 .fw_mem_mode = 0, 497 .num_vdevs = 16 + 1, 498 .num_peers = 512, 499 .supports_suspend = true, 500 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 501 .supports_regdb = true, 502 .fix_l1ss = false, 503 .credit_flow = true, 504 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 505 .hal_params = &ath11k_hw_hal_params_qca6390, 506 .supports_dynamic_smps_6ghz = false, 507 .alloc_cacheable_memory = false, 508 .supports_rssi_stats = true, 509 .fw_wmi_diag_event = true, 510 .current_cc_support = true, 511 .dbr_debug_support = false, 512 .global_reset = true, 513 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 514 .m3_fw_support = true, 515 .fixed_bdf_addr = false, 516 .fixed_mem_region = false, 517 .static_window_map = false, 518 .hybrid_bus_type = false, 519 .fixed_fw_mem = false, 520 .support_off_channel_tx = true, 521 .supports_multi_bssid = true, 522 523 .sram_dump = { 524 .start = 0x01400000, 525 .end = 0x0177ffff, 526 }, 527 528 .tcl_ring_retry = true, 529 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 530 .smp2p_wow_exit = false, 531 .support_fw_mac_sequence = true, 532 }, 533 { 534 .name = "wcn6750 hw1.0", 535 .hw_rev = ATH11K_HW_WCN6750_HW10, 536 .fw = { 537 .dir = "WCN6750/hw1.0", 538 .board_size = 256 * 1024, 539 .cal_offset = 128 * 1024, 540 }, 541 .max_radios = 1, 542 .bdf_addr = 0x4B0C0000, 543 .hw_ops = &wcn6750_ops, 544 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 545 .internal_sleep_clock = false, 546 .regs = &wcn6750_regs, 547 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 548 .host_ce_config = ath11k_host_ce_config_qca6390, 549 .ce_count = 9, 550 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 551 .target_ce_count = 9, 552 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 553 .svc_to_ce_map_len = 14, 554 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 555 .single_pdev_only = true, 556 .rxdma1_enable = false, 557 .num_rxmda_per_pdev = 1, 558 .rx_mac_buf_ring = true, 559 .vdev_start_delay = true, 560 .htt_peer_map_v2 = false, 561 562 .spectral = { 563 .fft_sz = 0, 564 .fft_pad_sz = 0, 565 .summary_pad_sz = 0, 566 .fft_hdr_len = 0, 567 .max_fft_bins = 0, 568 .fragment_160mhz = false, 569 }, 570 571 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 572 BIT(NL80211_IFTYPE_AP), 573 .supports_monitor = false, 574 .supports_shadow_regs = true, 575 .idle_ps = true, 576 .supports_sta_ps = true, 577 .cold_boot_calib = true, 578 .cbcal_restart_fw = false, 579 .fw_mem_mode = 0, 580 .num_vdevs = 16 + 1, 581 .num_peers = 512, 582 .supports_suspend = false, 583 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 584 .supports_regdb = true, 585 .fix_l1ss = false, 586 .credit_flow = true, 587 .max_tx_ring = DP_TCL_NUM_RING_MAX, 588 .hal_params = &ath11k_hw_hal_params_wcn6750, 589 .supports_dynamic_smps_6ghz = false, 590 .alloc_cacheable_memory = false, 591 .supports_rssi_stats = true, 592 .fw_wmi_diag_event = false, 593 .current_cc_support = true, 594 .dbr_debug_support = false, 595 .global_reset = false, 596 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 597 .m3_fw_support = false, 598 .fixed_bdf_addr = false, 599 .fixed_mem_region = false, 600 .static_window_map = true, 601 .hybrid_bus_type = true, 602 .fixed_fw_mem = true, 603 .support_off_channel_tx = true, 604 .supports_multi_bssid = true, 605 606 .sram_dump = {}, 607 608 .tcl_ring_retry = false, 609 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 610 .smp2p_wow_exit = true, 611 .support_fw_mac_sequence = true, 612 }, 613 { 614 .hw_rev = ATH11K_HW_IPQ5018_HW10, 615 .name = "ipq5018 hw1.0", 616 .fw = { 617 .dir = "IPQ5018/hw1.0", 618 .board_size = 256 * 1024, 619 .cal_offset = 128 * 1024, 620 }, 621 .max_radios = MAX_RADIOS_5018, 622 .bdf_addr = 0x4BA00000, 623 /* hal_desc_sz and hw ops are similar to qcn9074 */ 624 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 625 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 626 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 627 .credit_flow = false, 628 .max_tx_ring = 1, 629 .spectral = { 630 .fft_sz = 2, 631 .fft_pad_sz = 0, 632 .summary_pad_sz = 16, 633 .fft_hdr_len = 24, 634 .max_fft_bins = 1024, 635 }, 636 .internal_sleep_clock = false, 637 .regs = &ipq5018_regs, 638 .hw_ops = &ipq5018_ops, 639 .host_ce_config = ath11k_host_ce_config_qcn9074, 640 .ce_count = CE_CNT_5018, 641 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 642 .target_ce_count = TARGET_CE_CNT_5018, 643 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 644 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 645 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 646 .ce_remap = &ath11k_ce_remap_ipq5018, 647 .rxdma1_enable = true, 648 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, 649 .rx_mac_buf_ring = false, 650 .vdev_start_delay = false, 651 .htt_peer_map_v2 = true, 652 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 653 BIT(NL80211_IFTYPE_AP) | 654 BIT(NL80211_IFTYPE_MESH_POINT), 655 .supports_monitor = false, 656 .supports_sta_ps = false, 657 .supports_shadow_regs = false, 658 .fw_mem_mode = 0, 659 .num_vdevs = 16 + 1, 660 .num_peers = 512, 661 .supports_regdb = false, 662 .idle_ps = false, 663 .supports_suspend = false, 664 .hal_params = &ath11k_hw_hal_params_ipq8074, 665 .single_pdev_only = false, 666 .cold_boot_calib = true, 667 .fix_l1ss = true, 668 .supports_dynamic_smps_6ghz = false, 669 .alloc_cacheable_memory = true, 670 .supports_rssi_stats = false, 671 .fw_wmi_diag_event = false, 672 .current_cc_support = false, 673 .dbr_debug_support = true, 674 .global_reset = false, 675 .bios_sar_capa = NULL, 676 .m3_fw_support = false, 677 .fixed_bdf_addr = true, 678 .fixed_mem_region = true, 679 .static_window_map = false, 680 .hybrid_bus_type = false, 681 .fixed_fw_mem = false, 682 .support_off_channel_tx = false, 683 .supports_multi_bssid = false, 684 685 .sram_dump = {}, 686 687 .tcl_ring_retry = true, 688 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 689 .smp2p_wow_exit = false, 690 .support_fw_mac_sequence = false, 691 }, 692 }; 693 694 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 695 { 696 WARN_ON(!ab->hw_params.single_pdev_only); 697 698 return &ab->pdevs[0]; 699 } 700 701 void ath11k_fw_stats_pdevs_free(struct list_head *head) 702 { 703 struct ath11k_fw_stats_pdev *i, *tmp; 704 705 list_for_each_entry_safe(i, tmp, head, list) { 706 list_del(&i->list); 707 kfree(i); 708 } 709 } 710 711 void ath11k_fw_stats_vdevs_free(struct list_head *head) 712 { 713 struct ath11k_fw_stats_vdev *i, *tmp; 714 715 list_for_each_entry_safe(i, tmp, head, list) { 716 list_del(&i->list); 717 kfree(i); 718 } 719 } 720 721 void ath11k_fw_stats_bcn_free(struct list_head *head) 722 { 723 struct ath11k_fw_stats_bcn *i, *tmp; 724 725 list_for_each_entry_safe(i, tmp, head, list) { 726 list_del(&i->list); 727 kfree(i); 728 } 729 } 730 731 void ath11k_fw_stats_init(struct ath11k *ar) 732 { 733 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 734 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 735 INIT_LIST_HEAD(&ar->fw_stats.bcn); 736 737 init_completion(&ar->fw_stats_complete); 738 } 739 740 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 741 { 742 ath11k_fw_stats_pdevs_free(&stats->pdevs); 743 ath11k_fw_stats_vdevs_free(&stats->vdevs); 744 ath11k_fw_stats_bcn_free(&stats->bcn); 745 } 746 747 int ath11k_core_suspend(struct ath11k_base *ab) 748 { 749 int ret; 750 struct ath11k_pdev *pdev; 751 struct ath11k *ar; 752 753 if (!ab->hw_params.supports_suspend) 754 return -EOPNOTSUPP; 755 756 /* so far single_pdev_only chips have supports_suspend as true 757 * and only the first pdev is valid. 758 */ 759 pdev = ath11k_core_get_single_pdev(ab); 760 ar = pdev->ar; 761 if (!ar || ar->state != ATH11K_STATE_OFF) 762 return 0; 763 764 ret = ath11k_dp_rx_pktlog_stop(ab, true); 765 if (ret) { 766 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 767 ret); 768 return ret; 769 } 770 771 ret = ath11k_mac_wait_tx_complete(ar); 772 if (ret) { 773 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 774 return ret; 775 } 776 777 ret = ath11k_wow_enable(ab); 778 if (ret) { 779 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 780 return ret; 781 } 782 783 ret = ath11k_dp_rx_pktlog_stop(ab, false); 784 if (ret) { 785 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 786 ret); 787 return ret; 788 } 789 790 ath11k_ce_stop_shadow_timers(ab); 791 ath11k_dp_stop_shadow_timers(ab); 792 793 ath11k_hif_irq_disable(ab); 794 ath11k_hif_ce_irq_disable(ab); 795 796 ret = ath11k_hif_suspend(ab); 797 if (ret) { 798 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 799 return ret; 800 } 801 802 return 0; 803 } 804 EXPORT_SYMBOL(ath11k_core_suspend); 805 806 int ath11k_core_resume(struct ath11k_base *ab) 807 { 808 int ret; 809 struct ath11k_pdev *pdev; 810 struct ath11k *ar; 811 812 if (!ab->hw_params.supports_suspend) 813 return -EOPNOTSUPP; 814 815 /* so far signle_pdev_only chips have supports_suspend as true 816 * and only the first pdev is valid. 817 */ 818 pdev = ath11k_core_get_single_pdev(ab); 819 ar = pdev->ar; 820 if (!ar || ar->state != ATH11K_STATE_OFF) 821 return 0; 822 823 ret = ath11k_hif_resume(ab); 824 if (ret) { 825 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 826 return ret; 827 } 828 829 ath11k_hif_ce_irq_enable(ab); 830 ath11k_hif_irq_enable(ab); 831 832 ret = ath11k_dp_rx_pktlog_start(ab); 833 if (ret) { 834 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 835 ret); 836 return ret; 837 } 838 839 ret = ath11k_wow_wakeup(ab); 840 if (ret) { 841 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 842 return ret; 843 } 844 845 return 0; 846 } 847 EXPORT_SYMBOL(ath11k_core_resume); 848 849 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 850 { 851 struct ath11k_base *ab = data; 852 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 853 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 854 ssize_t copied; 855 size_t len; 856 int i; 857 858 if (ab->qmi.target.bdf_ext[0] != '\0') 859 return; 860 861 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 862 return; 863 864 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 865 ath11k_dbg(ab, ATH11K_DBG_BOOT, 866 "wrong smbios bdf ext type length (%d).\n", 867 hdr->length); 868 return; 869 } 870 871 spin_lock_bh(&ab->base_lock); 872 873 switch (smbios->country_code_flag) { 874 case ATH11K_SMBIOS_CC_ISO: 875 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 876 ab->new_alpha2[1] = smbios->cc_code & 0xff; 877 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n", 878 ab->new_alpha2[0], ab->new_alpha2[1]); 879 break; 880 case ATH11K_SMBIOS_CC_WW: 881 ab->new_alpha2[0] = '0'; 882 ab->new_alpha2[1] = '0'; 883 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n"); 884 break; 885 default: 886 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n", 887 smbios->country_code_flag); 888 break; 889 } 890 891 spin_unlock_bh(&ab->base_lock); 892 893 if (!smbios->bdf_enabled) { 894 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 895 return; 896 } 897 898 /* Only one string exists (per spec) */ 899 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 900 ath11k_dbg(ab, ATH11K_DBG_BOOT, 901 "bdf variant magic does not match.\n"); 902 return; 903 } 904 905 len = min_t(size_t, 906 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 907 for (i = 0; i < len; i++) { 908 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 909 ath11k_dbg(ab, ATH11K_DBG_BOOT, 910 "bdf variant name contains non ascii chars.\n"); 911 return; 912 } 913 } 914 915 /* Copy extension name without magic prefix */ 916 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 917 sizeof(ab->qmi.target.bdf_ext)); 918 if (copied < 0) { 919 ath11k_dbg(ab, ATH11K_DBG_BOOT, 920 "bdf variant string is longer than the buffer can accommodate\n"); 921 return; 922 } 923 924 ath11k_dbg(ab, ATH11K_DBG_BOOT, 925 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 926 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 927 } 928 929 int ath11k_core_check_smbios(struct ath11k_base *ab) 930 { 931 ab->qmi.target.bdf_ext[0] = '\0'; 932 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 933 934 if (ab->qmi.target.bdf_ext[0] == '\0') 935 return -ENODATA; 936 937 return 0; 938 } 939 940 int ath11k_core_check_dt(struct ath11k_base *ab) 941 { 942 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 943 const char *variant = NULL; 944 struct device_node *node; 945 946 node = ab->dev->of_node; 947 if (!node) 948 return -ENOENT; 949 950 of_property_read_string(node, "qcom,ath11k-calibration-variant", 951 &variant); 952 if (!variant) 953 return -ENODATA; 954 955 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 956 ath11k_dbg(ab, ATH11K_DBG_BOOT, 957 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 958 variant); 959 960 return 0; 961 } 962 963 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 964 size_t name_len, bool with_variant) 965 { 966 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 967 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 968 969 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 970 scnprintf(variant, sizeof(variant), ",variant=%s", 971 ab->qmi.target.bdf_ext); 972 973 switch (ab->id.bdf_search) { 974 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 975 scnprintf(name, name_len, 976 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 977 ath11k_bus_str(ab->hif.bus), 978 ab->id.vendor, ab->id.device, 979 ab->id.subsystem_vendor, 980 ab->id.subsystem_device, 981 ab->qmi.target.chip_id, 982 ab->qmi.target.board_id, 983 variant); 984 break; 985 default: 986 scnprintf(name, name_len, 987 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 988 ath11k_bus_str(ab->hif.bus), 989 ab->qmi.target.chip_id, 990 ab->qmi.target.board_id, variant); 991 break; 992 } 993 994 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name); 995 996 return 0; 997 } 998 999 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1000 size_t name_len) 1001 { 1002 return __ath11k_core_create_board_name(ab, name, name_len, true); 1003 } 1004 1005 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1006 size_t name_len) 1007 { 1008 return __ath11k_core_create_board_name(ab, name, name_len, false); 1009 } 1010 1011 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1012 const char *file) 1013 { 1014 const struct firmware *fw; 1015 char path[100]; 1016 int ret; 1017 1018 if (file == NULL) 1019 return ERR_PTR(-ENOENT); 1020 1021 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1022 1023 ret = firmware_request_nowarn(&fw, path, ab->dev); 1024 if (ret) 1025 return ERR_PTR(ret); 1026 1027 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n", 1028 path, fw->size); 1029 1030 return fw; 1031 } 1032 1033 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1034 { 1035 if (!IS_ERR(bd->fw)) 1036 release_firmware(bd->fw); 1037 1038 memset(bd, 0, sizeof(*bd)); 1039 } 1040 1041 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1042 struct ath11k_board_data *bd, 1043 const void *buf, size_t buf_len, 1044 const char *boardname, 1045 int ie_id, 1046 int name_id, 1047 int data_id) 1048 { 1049 const struct ath11k_fw_ie *hdr; 1050 bool name_match_found; 1051 int ret, board_ie_id; 1052 size_t board_ie_len; 1053 const void *board_ie_data; 1054 1055 name_match_found = false; 1056 1057 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1058 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1059 hdr = buf; 1060 board_ie_id = le32_to_cpu(hdr->id); 1061 board_ie_len = le32_to_cpu(hdr->len); 1062 board_ie_data = hdr->data; 1063 1064 buf_len -= sizeof(*hdr); 1065 buf += sizeof(*hdr); 1066 1067 if (buf_len < ALIGN(board_ie_len, 4)) { 1068 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1069 ath11k_bd_ie_type_str(ie_id), 1070 buf_len, ALIGN(board_ie_len, 4)); 1071 ret = -EINVAL; 1072 goto out; 1073 } 1074 1075 if (board_ie_id == name_id) { 1076 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1077 board_ie_data, board_ie_len); 1078 1079 if (board_ie_len != strlen(boardname)) 1080 goto next; 1081 1082 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1083 if (ret) 1084 goto next; 1085 1086 name_match_found = true; 1087 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1088 "boot found match %s for name '%s'", 1089 ath11k_bd_ie_type_str(ie_id), 1090 boardname); 1091 } else if (board_ie_id == data_id) { 1092 if (!name_match_found) 1093 /* no match found */ 1094 goto next; 1095 1096 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1097 "boot found %s for '%s'", 1098 ath11k_bd_ie_type_str(ie_id), 1099 boardname); 1100 1101 bd->data = board_ie_data; 1102 bd->len = board_ie_len; 1103 1104 ret = 0; 1105 goto out; 1106 } else { 1107 ath11k_warn(ab, "unknown %s id found: %d\n", 1108 ath11k_bd_ie_type_str(ie_id), 1109 board_ie_id); 1110 } 1111 next: 1112 /* jump over the padding */ 1113 board_ie_len = ALIGN(board_ie_len, 4); 1114 1115 buf_len -= board_ie_len; 1116 buf += board_ie_len; 1117 } 1118 1119 /* no match found */ 1120 ret = -ENOENT; 1121 1122 out: 1123 return ret; 1124 } 1125 1126 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1127 struct ath11k_board_data *bd, 1128 const char *boardname, 1129 int ie_id_match, 1130 int name_id, 1131 int data_id) 1132 { 1133 size_t len, magic_len; 1134 const u8 *data; 1135 char *filename, filepath[100]; 1136 size_t ie_len; 1137 struct ath11k_fw_ie *hdr; 1138 int ret, ie_id; 1139 1140 filename = ATH11K_BOARD_API2_FILE; 1141 1142 if (!bd->fw) 1143 bd->fw = ath11k_core_firmware_request(ab, filename); 1144 1145 if (IS_ERR(bd->fw)) 1146 return PTR_ERR(bd->fw); 1147 1148 data = bd->fw->data; 1149 len = bd->fw->size; 1150 1151 ath11k_core_create_firmware_path(ab, filename, 1152 filepath, sizeof(filepath)); 1153 1154 /* magic has extra null byte padded */ 1155 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1156 if (len < magic_len) { 1157 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1158 filepath, len); 1159 ret = -EINVAL; 1160 goto err; 1161 } 1162 1163 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1164 ath11k_err(ab, "found invalid board magic\n"); 1165 ret = -EINVAL; 1166 goto err; 1167 } 1168 1169 /* magic is padded to 4 bytes */ 1170 magic_len = ALIGN(magic_len, 4); 1171 if (len < magic_len) { 1172 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1173 filepath, len); 1174 ret = -EINVAL; 1175 goto err; 1176 } 1177 1178 data += magic_len; 1179 len -= magic_len; 1180 1181 while (len > sizeof(struct ath11k_fw_ie)) { 1182 hdr = (struct ath11k_fw_ie *)data; 1183 ie_id = le32_to_cpu(hdr->id); 1184 ie_len = le32_to_cpu(hdr->len); 1185 1186 len -= sizeof(*hdr); 1187 data = hdr->data; 1188 1189 if (len < ALIGN(ie_len, 4)) { 1190 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1191 ie_id, ie_len, len); 1192 ret = -EINVAL; 1193 goto err; 1194 } 1195 1196 if (ie_id == ie_id_match) { 1197 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1198 ie_len, 1199 boardname, 1200 ie_id_match, 1201 name_id, 1202 data_id); 1203 if (ret == -ENOENT) 1204 /* no match found, continue */ 1205 goto next; 1206 else if (ret) 1207 /* there was an error, bail out */ 1208 goto err; 1209 /* either found or error, so stop searching */ 1210 goto out; 1211 } 1212 next: 1213 /* jump over the padding */ 1214 ie_len = ALIGN(ie_len, 4); 1215 1216 len -= ie_len; 1217 data += ie_len; 1218 } 1219 1220 out: 1221 if (!bd->data || !bd->len) { 1222 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1223 "failed to fetch %s for %s from %s\n", 1224 ath11k_bd_ie_type_str(ie_id_match), 1225 boardname, filepath); 1226 ret = -ENODATA; 1227 goto err; 1228 } 1229 1230 return 0; 1231 1232 err: 1233 ath11k_core_free_bdf(ab, bd); 1234 return ret; 1235 } 1236 1237 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1238 struct ath11k_board_data *bd, 1239 const char *name) 1240 { 1241 bd->fw = ath11k_core_firmware_request(ab, name); 1242 1243 if (IS_ERR(bd->fw)) 1244 return PTR_ERR(bd->fw); 1245 1246 bd->data = bd->fw->data; 1247 bd->len = bd->fw->size; 1248 1249 return 0; 1250 } 1251 1252 #define BOARD_NAME_SIZE 200 1253 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1254 { 1255 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1256 char *filename, filepath[100]; 1257 int ret; 1258 1259 filename = ATH11K_BOARD_API2_FILE; 1260 1261 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1262 if (ret) { 1263 ath11k_err(ab, "failed to create board name: %d", ret); 1264 return ret; 1265 } 1266 1267 ab->bd_api = 2; 1268 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1269 ATH11K_BD_IE_BOARD, 1270 ATH11K_BD_IE_BOARD_NAME, 1271 ATH11K_BD_IE_BOARD_DATA); 1272 if (!ret) 1273 goto success; 1274 1275 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1276 sizeof(fallback_boardname)); 1277 if (ret) { 1278 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1279 return ret; 1280 } 1281 1282 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1283 ATH11K_BD_IE_BOARD, 1284 ATH11K_BD_IE_BOARD_NAME, 1285 ATH11K_BD_IE_BOARD_DATA); 1286 if (!ret) 1287 goto success; 1288 1289 ab->bd_api = 1; 1290 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1291 if (ret) { 1292 ath11k_core_create_firmware_path(ab, filename, 1293 filepath, sizeof(filepath)); 1294 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1295 boardname, filepath); 1296 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1297 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1298 fallback_boardname, filepath); 1299 1300 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1301 ab->hw_params.fw.dir); 1302 return ret; 1303 } 1304 1305 success: 1306 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1307 return 0; 1308 } 1309 1310 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1311 { 1312 char boardname[BOARD_NAME_SIZE]; 1313 int ret; 1314 1315 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1316 if (ret) { 1317 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1318 "failed to create board name for regdb: %d", ret); 1319 goto exit; 1320 } 1321 1322 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1323 ATH11K_BD_IE_REGDB, 1324 ATH11K_BD_IE_REGDB_NAME, 1325 ATH11K_BD_IE_REGDB_DATA); 1326 if (!ret) 1327 goto exit; 1328 1329 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1330 if (ret) 1331 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1332 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1333 1334 exit: 1335 if (!ret) 1336 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1337 1338 return ret; 1339 } 1340 1341 static void ath11k_core_stop(struct ath11k_base *ab) 1342 { 1343 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1344 ath11k_qmi_firmware_stop(ab); 1345 1346 ath11k_hif_stop(ab); 1347 ath11k_wmi_detach(ab); 1348 ath11k_dp_pdev_reo_cleanup(ab); 1349 1350 /* De-Init of components as needed */ 1351 } 1352 1353 static int ath11k_core_soc_create(struct ath11k_base *ab) 1354 { 1355 int ret; 1356 1357 ret = ath11k_qmi_init_service(ab); 1358 if (ret) { 1359 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1360 return ret; 1361 } 1362 1363 ret = ath11k_debugfs_soc_create(ab); 1364 if (ret) { 1365 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1366 goto err_qmi_deinit; 1367 } 1368 1369 ret = ath11k_hif_power_up(ab); 1370 if (ret) { 1371 ath11k_err(ab, "failed to power up :%d\n", ret); 1372 goto err_debugfs_reg; 1373 } 1374 1375 return 0; 1376 1377 err_debugfs_reg: 1378 ath11k_debugfs_soc_destroy(ab); 1379 err_qmi_deinit: 1380 ath11k_qmi_deinit_service(ab); 1381 return ret; 1382 } 1383 1384 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1385 { 1386 ath11k_debugfs_soc_destroy(ab); 1387 ath11k_dp_free(ab); 1388 ath11k_reg_free(ab); 1389 ath11k_qmi_deinit_service(ab); 1390 } 1391 1392 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1393 { 1394 int ret; 1395 1396 ret = ath11k_debugfs_pdev_create(ab); 1397 if (ret) { 1398 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1399 return ret; 1400 } 1401 1402 ret = ath11k_dp_pdev_alloc(ab); 1403 if (ret) { 1404 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1405 goto err_pdev_debug; 1406 } 1407 1408 ret = ath11k_mac_register(ab); 1409 if (ret) { 1410 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1411 goto err_dp_pdev_free; 1412 } 1413 1414 ret = ath11k_thermal_register(ab); 1415 if (ret) { 1416 ath11k_err(ab, "could not register thermal device: %d\n", 1417 ret); 1418 goto err_mac_unregister; 1419 } 1420 1421 ret = ath11k_spectral_init(ab); 1422 if (ret) { 1423 ath11k_err(ab, "failed to init spectral %d\n", ret); 1424 goto err_thermal_unregister; 1425 } 1426 1427 return 0; 1428 1429 err_thermal_unregister: 1430 ath11k_thermal_unregister(ab); 1431 err_mac_unregister: 1432 ath11k_mac_unregister(ab); 1433 err_dp_pdev_free: 1434 ath11k_dp_pdev_free(ab); 1435 err_pdev_debug: 1436 ath11k_debugfs_pdev_destroy(ab); 1437 1438 return ret; 1439 } 1440 1441 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1442 { 1443 ath11k_spectral_deinit(ab); 1444 ath11k_thermal_unregister(ab); 1445 ath11k_mac_unregister(ab); 1446 ath11k_hif_irq_disable(ab); 1447 ath11k_dp_pdev_free(ab); 1448 ath11k_debugfs_pdev_destroy(ab); 1449 } 1450 1451 static int ath11k_core_start(struct ath11k_base *ab) 1452 { 1453 int ret; 1454 1455 ret = ath11k_wmi_attach(ab); 1456 if (ret) { 1457 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1458 return ret; 1459 } 1460 1461 ret = ath11k_htc_init(ab); 1462 if (ret) { 1463 ath11k_err(ab, "failed to init htc: %d\n", ret); 1464 goto err_wmi_detach; 1465 } 1466 1467 ret = ath11k_hif_start(ab); 1468 if (ret) { 1469 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1470 goto err_wmi_detach; 1471 } 1472 1473 ret = ath11k_htc_wait_target(&ab->htc); 1474 if (ret) { 1475 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1476 goto err_hif_stop; 1477 } 1478 1479 ret = ath11k_dp_htt_connect(&ab->dp); 1480 if (ret) { 1481 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1482 goto err_hif_stop; 1483 } 1484 1485 ret = ath11k_wmi_connect(ab); 1486 if (ret) { 1487 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1488 goto err_hif_stop; 1489 } 1490 1491 ret = ath11k_htc_start(&ab->htc); 1492 if (ret) { 1493 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1494 goto err_hif_stop; 1495 } 1496 1497 ret = ath11k_wmi_wait_for_service_ready(ab); 1498 if (ret) { 1499 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1500 ret); 1501 goto err_hif_stop; 1502 } 1503 1504 ret = ath11k_mac_allocate(ab); 1505 if (ret) { 1506 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1507 ret); 1508 goto err_hif_stop; 1509 } 1510 1511 ath11k_dp_pdev_pre_alloc(ab); 1512 1513 ret = ath11k_dp_pdev_reo_setup(ab); 1514 if (ret) { 1515 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1516 goto err_mac_destroy; 1517 } 1518 1519 ret = ath11k_wmi_cmd_init(ab); 1520 if (ret) { 1521 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1522 goto err_reo_cleanup; 1523 } 1524 1525 ret = ath11k_wmi_wait_for_unified_ready(ab); 1526 if (ret) { 1527 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1528 ret); 1529 goto err_reo_cleanup; 1530 } 1531 1532 /* put hardware to DBS mode */ 1533 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1534 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1535 if (ret) { 1536 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1537 goto err_hif_stop; 1538 } 1539 } 1540 1541 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1542 if (ret) { 1543 ath11k_err(ab, "failed to send htt version request message: %d\n", 1544 ret); 1545 goto err_reo_cleanup; 1546 } 1547 1548 return 0; 1549 1550 err_reo_cleanup: 1551 ath11k_dp_pdev_reo_cleanup(ab); 1552 err_mac_destroy: 1553 ath11k_mac_destroy(ab); 1554 err_hif_stop: 1555 ath11k_hif_stop(ab); 1556 err_wmi_detach: 1557 ath11k_wmi_detach(ab); 1558 1559 return ret; 1560 } 1561 1562 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1563 enum ath11k_firmware_mode mode) 1564 { 1565 int ret; 1566 1567 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1568 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1569 1570 ret = ath11k_qmi_firmware_start(ab, mode); 1571 if (ret) { 1572 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1573 return ret; 1574 } 1575 1576 return ret; 1577 } 1578 1579 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1580 { 1581 int ret; 1582 1583 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); 1584 if (ret) { 1585 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1586 return ret; 1587 } 1588 1589 ret = ath11k_ce_init_pipes(ab); 1590 if (ret) { 1591 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1592 goto err_firmware_stop; 1593 } 1594 1595 ret = ath11k_dp_alloc(ab); 1596 if (ret) { 1597 ath11k_err(ab, "failed to init DP: %d\n", ret); 1598 goto err_firmware_stop; 1599 } 1600 1601 switch (ath11k_crypto_mode) { 1602 case ATH11K_CRYPT_MODE_SW: 1603 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1604 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1605 break; 1606 case ATH11K_CRYPT_MODE_HW: 1607 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1608 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1609 break; 1610 default: 1611 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1612 return -EINVAL; 1613 } 1614 1615 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1616 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1617 1618 mutex_lock(&ab->core_lock); 1619 ret = ath11k_core_start(ab); 1620 if (ret) { 1621 ath11k_err(ab, "failed to start core: %d\n", ret); 1622 goto err_dp_free; 1623 } 1624 1625 ret = ath11k_core_pdev_create(ab); 1626 if (ret) { 1627 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1628 goto err_core_stop; 1629 } 1630 ath11k_hif_irq_enable(ab); 1631 mutex_unlock(&ab->core_lock); 1632 1633 return 0; 1634 1635 err_core_stop: 1636 ath11k_core_stop(ab); 1637 ath11k_mac_destroy(ab); 1638 err_dp_free: 1639 ath11k_dp_free(ab); 1640 mutex_unlock(&ab->core_lock); 1641 err_firmware_stop: 1642 ath11k_qmi_firmware_stop(ab); 1643 1644 return ret; 1645 } 1646 1647 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1648 { 1649 int ret; 1650 1651 mutex_lock(&ab->core_lock); 1652 ath11k_thermal_unregister(ab); 1653 ath11k_hif_irq_disable(ab); 1654 ath11k_dp_pdev_free(ab); 1655 ath11k_spectral_deinit(ab); 1656 ath11k_hif_stop(ab); 1657 ath11k_wmi_detach(ab); 1658 ath11k_dp_pdev_reo_cleanup(ab); 1659 mutex_unlock(&ab->core_lock); 1660 1661 ath11k_dp_free(ab); 1662 ath11k_hal_srng_deinit(ab); 1663 1664 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1665 1666 ret = ath11k_hal_srng_init(ab); 1667 if (ret) 1668 return ret; 1669 1670 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1671 1672 ret = ath11k_core_qmi_firmware_ready(ab); 1673 if (ret) 1674 goto err_hal_srng_deinit; 1675 1676 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1677 1678 return 0; 1679 1680 err_hal_srng_deinit: 1681 ath11k_hal_srng_deinit(ab); 1682 return ret; 1683 } 1684 1685 void ath11k_core_halt(struct ath11k *ar) 1686 { 1687 struct ath11k_base *ab = ar->ab; 1688 1689 lockdep_assert_held(&ar->conf_mutex); 1690 1691 ar->num_created_vdevs = 0; 1692 ar->allocated_vdev_map = 0; 1693 1694 ath11k_mac_scan_finish(ar); 1695 ath11k_mac_peer_cleanup_all(ar); 1696 cancel_delayed_work_sync(&ar->scan.timeout); 1697 cancel_work_sync(&ar->regd_update_work); 1698 cancel_work_sync(&ab->update_11d_work); 1699 1700 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1701 synchronize_rcu(); 1702 INIT_LIST_HEAD(&ar->arvifs); 1703 idr_init(&ar->txmgmt_idr); 1704 } 1705 1706 static void ath11k_update_11d(struct work_struct *work) 1707 { 1708 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1709 struct ath11k *ar; 1710 struct ath11k_pdev *pdev; 1711 struct wmi_set_current_country_params set_current_param = {}; 1712 int ret, i; 1713 1714 spin_lock_bh(&ab->base_lock); 1715 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1716 spin_unlock_bh(&ab->base_lock); 1717 1718 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1719 set_current_param.alpha2[0], 1720 set_current_param.alpha2[1]); 1721 1722 for (i = 0; i < ab->num_radios; i++) { 1723 pdev = &ab->pdevs[i]; 1724 ar = pdev->ar; 1725 1726 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1727 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1728 if (ret) 1729 ath11k_warn(ar->ab, 1730 "pdev id %d failed set current country code: %d\n", 1731 i, ret); 1732 } 1733 } 1734 1735 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1736 { 1737 struct ath11k *ar; 1738 struct ath11k_pdev *pdev; 1739 int i; 1740 1741 spin_lock_bh(&ab->base_lock); 1742 ab->stats.fw_crash_counter++; 1743 spin_unlock_bh(&ab->base_lock); 1744 1745 for (i = 0; i < ab->num_radios; i++) { 1746 pdev = &ab->pdevs[i]; 1747 ar = pdev->ar; 1748 if (!ar || ar->state == ATH11K_STATE_OFF) 1749 continue; 1750 1751 ieee80211_stop_queues(ar->hw); 1752 ath11k_mac_drain_tx(ar); 1753 ar->state_11d = ATH11K_11D_IDLE; 1754 complete(&ar->completed_11d_scan); 1755 complete(&ar->scan.started); 1756 complete_all(&ar->scan.completed); 1757 complete(&ar->scan.on_channel); 1758 complete(&ar->peer_assoc_done); 1759 complete(&ar->peer_delete_done); 1760 complete(&ar->install_key_done); 1761 complete(&ar->vdev_setup_done); 1762 complete(&ar->vdev_delete_done); 1763 complete(&ar->bss_survey_done); 1764 complete(&ar->thermal.wmi_sync); 1765 1766 wake_up(&ar->dp.tx_empty_waitq); 1767 idr_for_each(&ar->txmgmt_idr, 1768 ath11k_mac_tx_mgmt_pending_free, ar); 1769 idr_destroy(&ar->txmgmt_idr); 1770 wake_up(&ar->txmgmt_empty_waitq); 1771 1772 ar->monitor_vdev_id = -1; 1773 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 1774 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 1775 } 1776 1777 wake_up(&ab->wmi_ab.tx_credits_wq); 1778 wake_up(&ab->peer_mapping_wq); 1779 1780 reinit_completion(&ab->driver_recovery); 1781 } 1782 1783 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1784 { 1785 struct ath11k *ar; 1786 struct ath11k_pdev *pdev; 1787 int i; 1788 1789 for (i = 0; i < ab->num_radios; i++) { 1790 pdev = &ab->pdevs[i]; 1791 ar = pdev->ar; 1792 if (!ar || ar->state == ATH11K_STATE_OFF) 1793 continue; 1794 1795 mutex_lock(&ar->conf_mutex); 1796 1797 switch (ar->state) { 1798 case ATH11K_STATE_ON: 1799 ar->state = ATH11K_STATE_RESTARTING; 1800 ath11k_core_halt(ar); 1801 ieee80211_restart_hw(ar->hw); 1802 break; 1803 case ATH11K_STATE_OFF: 1804 ath11k_warn(ab, 1805 "cannot restart radio %d that hasn't been started\n", 1806 i); 1807 break; 1808 case ATH11K_STATE_RESTARTING: 1809 break; 1810 case ATH11K_STATE_RESTARTED: 1811 ar->state = ATH11K_STATE_WEDGED; 1812 fallthrough; 1813 case ATH11K_STATE_WEDGED: 1814 ath11k_warn(ab, 1815 "device is wedged, will not restart radio %d\n", i); 1816 break; 1817 } 1818 mutex_unlock(&ar->conf_mutex); 1819 } 1820 complete(&ab->driver_recovery); 1821 } 1822 1823 static void ath11k_core_restart(struct work_struct *work) 1824 { 1825 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1826 int ret; 1827 1828 ret = ath11k_core_reconfigure_on_crash(ab); 1829 if (ret) { 1830 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1831 return; 1832 } 1833 1834 if (ab->is_reset) 1835 complete_all(&ab->reconfigure_complete); 1836 1837 if (!ab->is_reset) 1838 ath11k_core_post_reconfigure_recovery(ab); 1839 } 1840 1841 static void ath11k_core_reset(struct work_struct *work) 1842 { 1843 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1844 int reset_count, fail_cont_count; 1845 long time_left; 1846 1847 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1848 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1849 return; 1850 } 1851 1852 /* Sometimes the recovery will fail and then the next all recovery fail, 1853 * this is to avoid infinite recovery since it can not recovery success. 1854 */ 1855 fail_cont_count = atomic_read(&ab->fail_cont_count); 1856 1857 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1858 return; 1859 1860 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1861 time_before(jiffies, ab->reset_fail_timeout)) 1862 return; 1863 1864 reset_count = atomic_inc_return(&ab->reset_count); 1865 1866 if (reset_count > 1) { 1867 /* Sometimes it happened another reset worker before the previous one 1868 * completed, then the second reset worker will destroy the previous one, 1869 * thus below is to avoid that. 1870 */ 1871 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1872 1873 reinit_completion(&ab->reset_complete); 1874 time_left = wait_for_completion_timeout(&ab->reset_complete, 1875 ATH11K_RESET_TIMEOUT_HZ); 1876 1877 if (time_left) { 1878 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1879 atomic_dec(&ab->reset_count); 1880 return; 1881 } 1882 1883 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1884 /* Record the continuous recovery fail count when recovery failed*/ 1885 atomic_inc(&ab->fail_cont_count); 1886 } 1887 1888 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1889 1890 ab->is_reset = true; 1891 atomic_set(&ab->recovery_count, 0); 1892 reinit_completion(&ab->recovery_start); 1893 atomic_set(&ab->recovery_start_count, 0); 1894 1895 ath11k_core_pre_reconfigure_recovery(ab); 1896 1897 reinit_completion(&ab->reconfigure_complete); 1898 ath11k_core_post_reconfigure_recovery(ab); 1899 1900 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1901 1902 time_left = wait_for_completion_timeout(&ab->recovery_start, 1903 ATH11K_RECOVER_START_TIMEOUT_HZ); 1904 1905 ath11k_hif_power_down(ab); 1906 ath11k_hif_power_up(ab); 1907 1908 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1909 } 1910 1911 static int ath11k_init_hw_params(struct ath11k_base *ab) 1912 { 1913 const struct ath11k_hw_params *hw_params = NULL; 1914 int i; 1915 1916 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1917 hw_params = &ath11k_hw_params[i]; 1918 1919 if (hw_params->hw_rev == ab->hw_rev) 1920 break; 1921 } 1922 1923 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1924 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1925 return -EINVAL; 1926 } 1927 1928 ab->hw_params = *hw_params; 1929 1930 ath11k_info(ab, "%s\n", ab->hw_params.name); 1931 1932 return 0; 1933 } 1934 1935 int ath11k_core_pre_init(struct ath11k_base *ab) 1936 { 1937 int ret; 1938 1939 ret = ath11k_init_hw_params(ab); 1940 if (ret) { 1941 ath11k_err(ab, "failed to get hw params: %d\n", ret); 1942 return ret; 1943 } 1944 1945 return 0; 1946 } 1947 EXPORT_SYMBOL(ath11k_core_pre_init); 1948 1949 int ath11k_core_init(struct ath11k_base *ab) 1950 { 1951 int ret; 1952 1953 ret = ath11k_core_soc_create(ab); 1954 if (ret) { 1955 ath11k_err(ab, "failed to create soc core: %d\n", ret); 1956 return ret; 1957 } 1958 1959 return 0; 1960 } 1961 EXPORT_SYMBOL(ath11k_core_init); 1962 1963 void ath11k_core_deinit(struct ath11k_base *ab) 1964 { 1965 mutex_lock(&ab->core_lock); 1966 1967 ath11k_core_pdev_destroy(ab); 1968 ath11k_core_stop(ab); 1969 1970 mutex_unlock(&ab->core_lock); 1971 1972 ath11k_hif_power_down(ab); 1973 ath11k_mac_destroy(ab); 1974 ath11k_core_soc_destroy(ab); 1975 } 1976 EXPORT_SYMBOL(ath11k_core_deinit); 1977 1978 void ath11k_core_free(struct ath11k_base *ab) 1979 { 1980 destroy_workqueue(ab->workqueue_aux); 1981 destroy_workqueue(ab->workqueue); 1982 1983 kfree(ab); 1984 } 1985 EXPORT_SYMBOL(ath11k_core_free); 1986 1987 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1988 enum ath11k_bus bus) 1989 { 1990 struct ath11k_base *ab; 1991 1992 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 1993 if (!ab) 1994 return NULL; 1995 1996 init_completion(&ab->driver_recovery); 1997 1998 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 1999 if (!ab->workqueue) 2000 goto err_sc_free; 2001 2002 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2003 if (!ab->workqueue_aux) 2004 goto err_free_wq; 2005 2006 mutex_init(&ab->core_lock); 2007 mutex_init(&ab->tbl_mtx_lock); 2008 spin_lock_init(&ab->base_lock); 2009 mutex_init(&ab->vdev_id_11d_lock); 2010 init_completion(&ab->reset_complete); 2011 init_completion(&ab->reconfigure_complete); 2012 init_completion(&ab->recovery_start); 2013 2014 INIT_LIST_HEAD(&ab->peers); 2015 init_waitqueue_head(&ab->peer_mapping_wq); 2016 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2017 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2018 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2019 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2020 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2021 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2022 init_completion(&ab->htc_suspend); 2023 init_completion(&ab->wow.wakeup_completed); 2024 2025 ab->dev = dev; 2026 ab->hif.bus = bus; 2027 2028 return ab; 2029 2030 err_free_wq: 2031 destroy_workqueue(ab->workqueue); 2032 err_sc_free: 2033 kfree(ab); 2034 return NULL; 2035 } 2036 EXPORT_SYMBOL(ath11k_core_alloc); 2037 2038 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2039 MODULE_LICENSE("Dual BSD/GPL"); 2040