1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 bool ath11k_ftm_mode; 36 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 37 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 38 39 static const struct ath11k_hw_params ath11k_hw_params[] = { 40 { 41 .hw_rev = ATH11K_HW_IPQ8074, 42 .name = "ipq8074 hw2.0", 43 .fw = { 44 .dir = "IPQ8074/hw2.0", 45 .board_size = 256 * 1024, 46 .cal_offset = 128 * 1024, 47 }, 48 .max_radios = 3, 49 .bdf_addr = 0x4B0C0000, 50 .hw_ops = &ipq8074_ops, 51 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 52 .internal_sleep_clock = false, 53 .regs = &ipq8074_regs, 54 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 55 .host_ce_config = ath11k_host_ce_config_ipq8074, 56 .ce_count = 12, 57 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 58 .target_ce_count = 11, 59 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 60 .svc_to_ce_map_len = 21, 61 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 62 .single_pdev_only = false, 63 .rxdma1_enable = true, 64 .num_rxmda_per_pdev = 1, 65 .rx_mac_buf_ring = false, 66 .vdev_start_delay = false, 67 .htt_peer_map_v2 = true, 68 69 .spectral = { 70 .fft_sz = 2, 71 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 72 * so added pad size as 2 bytes to compensate the BIN size 73 */ 74 .fft_pad_sz = 2, 75 .summary_pad_sz = 0, 76 .fft_hdr_len = 16, 77 .max_fft_bins = 512, 78 .fragment_160mhz = true, 79 }, 80 81 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 82 BIT(NL80211_IFTYPE_AP) | 83 BIT(NL80211_IFTYPE_MESH_POINT), 84 .supports_monitor = true, 85 .full_monitor_mode = false, 86 .supports_shadow_regs = false, 87 .idle_ps = false, 88 .supports_sta_ps = false, 89 .cold_boot_calib = true, 90 .cbcal_restart_fw = true, 91 .fw_mem_mode = 0, 92 .num_vdevs = 16 + 1, 93 .num_peers = 512, 94 .supports_suspend = false, 95 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 96 .supports_regdb = false, 97 .fix_l1ss = true, 98 .credit_flow = false, 99 .max_tx_ring = DP_TCL_NUM_RING_MAX, 100 .hal_params = &ath11k_hw_hal_params_ipq8074, 101 .supports_dynamic_smps_6ghz = false, 102 .alloc_cacheable_memory = true, 103 .supports_rssi_stats = false, 104 .fw_wmi_diag_event = false, 105 .current_cc_support = false, 106 .dbr_debug_support = true, 107 .global_reset = false, 108 .bios_sar_capa = NULL, 109 .m3_fw_support = false, 110 .fixed_bdf_addr = true, 111 .fixed_mem_region = true, 112 .static_window_map = false, 113 .hybrid_bus_type = false, 114 .fixed_fw_mem = false, 115 .support_off_channel_tx = false, 116 .supports_multi_bssid = false, 117 118 .sram_dump = {}, 119 120 .tcl_ring_retry = true, 121 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 122 .smp2p_wow_exit = false, 123 }, 124 { 125 .hw_rev = ATH11K_HW_IPQ6018_HW10, 126 .name = "ipq6018 hw1.0", 127 .fw = { 128 .dir = "IPQ6018/hw1.0", 129 .board_size = 256 * 1024, 130 .cal_offset = 128 * 1024, 131 }, 132 .max_radios = 2, 133 .bdf_addr = 0x4ABC0000, 134 .hw_ops = &ipq6018_ops, 135 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 136 .internal_sleep_clock = false, 137 .regs = &ipq8074_regs, 138 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 139 .host_ce_config = ath11k_host_ce_config_ipq8074, 140 .ce_count = 12, 141 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 142 .target_ce_count = 11, 143 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 144 .svc_to_ce_map_len = 19, 145 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 146 .single_pdev_only = false, 147 .rxdma1_enable = true, 148 .num_rxmda_per_pdev = 1, 149 .rx_mac_buf_ring = false, 150 .vdev_start_delay = false, 151 .htt_peer_map_v2 = true, 152 153 .spectral = { 154 .fft_sz = 4, 155 .fft_pad_sz = 0, 156 .summary_pad_sz = 0, 157 .fft_hdr_len = 16, 158 .max_fft_bins = 512, 159 .fragment_160mhz = true, 160 }, 161 162 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 163 BIT(NL80211_IFTYPE_AP) | 164 BIT(NL80211_IFTYPE_MESH_POINT), 165 .supports_monitor = true, 166 .full_monitor_mode = false, 167 .supports_shadow_regs = false, 168 .idle_ps = false, 169 .supports_sta_ps = false, 170 .cold_boot_calib = true, 171 .cbcal_restart_fw = true, 172 .fw_mem_mode = 0, 173 .num_vdevs = 16 + 1, 174 .num_peers = 512, 175 .supports_suspend = false, 176 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 177 .supports_regdb = false, 178 .fix_l1ss = true, 179 .credit_flow = false, 180 .max_tx_ring = DP_TCL_NUM_RING_MAX, 181 .hal_params = &ath11k_hw_hal_params_ipq8074, 182 .supports_dynamic_smps_6ghz = false, 183 .alloc_cacheable_memory = true, 184 .supports_rssi_stats = false, 185 .fw_wmi_diag_event = false, 186 .current_cc_support = false, 187 .dbr_debug_support = true, 188 .global_reset = false, 189 .bios_sar_capa = NULL, 190 .m3_fw_support = false, 191 .fixed_bdf_addr = true, 192 .fixed_mem_region = true, 193 .static_window_map = false, 194 .hybrid_bus_type = false, 195 .fixed_fw_mem = false, 196 .support_off_channel_tx = false, 197 .supports_multi_bssid = false, 198 199 .sram_dump = {}, 200 201 .tcl_ring_retry = true, 202 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 203 .smp2p_wow_exit = false, 204 .support_fw_mac_sequence = false, 205 }, 206 { 207 .name = "qca6390 hw2.0", 208 .hw_rev = ATH11K_HW_QCA6390_HW20, 209 .fw = { 210 .dir = "QCA6390/hw2.0", 211 .board_size = 256 * 1024, 212 .cal_offset = 128 * 1024, 213 }, 214 .max_radios = 3, 215 .bdf_addr = 0x4B0C0000, 216 .hw_ops = &qca6390_ops, 217 .ring_mask = &ath11k_hw_ring_mask_qca6390, 218 .internal_sleep_clock = true, 219 .regs = &qca6390_regs, 220 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 221 .host_ce_config = ath11k_host_ce_config_qca6390, 222 .ce_count = 9, 223 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 224 .target_ce_count = 9, 225 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 226 .svc_to_ce_map_len = 14, 227 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 228 .single_pdev_only = true, 229 .rxdma1_enable = false, 230 .num_rxmda_per_pdev = 2, 231 .rx_mac_buf_ring = true, 232 .vdev_start_delay = true, 233 .htt_peer_map_v2 = false, 234 235 .spectral = { 236 .fft_sz = 0, 237 .fft_pad_sz = 0, 238 .summary_pad_sz = 0, 239 .fft_hdr_len = 0, 240 .max_fft_bins = 0, 241 .fragment_160mhz = false, 242 }, 243 244 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 245 BIT(NL80211_IFTYPE_AP), 246 .supports_monitor = false, 247 .full_monitor_mode = false, 248 .supports_shadow_regs = true, 249 .idle_ps = true, 250 .supports_sta_ps = true, 251 .cold_boot_calib = false, 252 .cbcal_restart_fw = false, 253 .fw_mem_mode = 0, 254 .num_vdevs = 16 + 1, 255 .num_peers = 512, 256 .supports_suspend = true, 257 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 258 .supports_regdb = false, 259 .fix_l1ss = true, 260 .credit_flow = true, 261 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 262 .hal_params = &ath11k_hw_hal_params_qca6390, 263 .supports_dynamic_smps_6ghz = false, 264 .alloc_cacheable_memory = false, 265 .supports_rssi_stats = true, 266 .fw_wmi_diag_event = true, 267 .current_cc_support = true, 268 .dbr_debug_support = false, 269 .global_reset = true, 270 .bios_sar_capa = NULL, 271 .m3_fw_support = true, 272 .fixed_bdf_addr = false, 273 .fixed_mem_region = false, 274 .static_window_map = false, 275 .hybrid_bus_type = false, 276 .fixed_fw_mem = false, 277 .support_off_channel_tx = true, 278 .supports_multi_bssid = true, 279 280 .sram_dump = { 281 .start = 0x01400000, 282 .end = 0x0171ffff, 283 }, 284 285 .tcl_ring_retry = true, 286 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 287 .smp2p_wow_exit = false, 288 .support_fw_mac_sequence = true, 289 }, 290 { 291 .name = "qcn9074 hw1.0", 292 .hw_rev = ATH11K_HW_QCN9074_HW10, 293 .fw = { 294 .dir = "QCN9074/hw1.0", 295 .board_size = 256 * 1024, 296 .cal_offset = 128 * 1024, 297 }, 298 .max_radios = 1, 299 .single_pdev_only = false, 300 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 301 .hw_ops = &qcn9074_ops, 302 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 303 .internal_sleep_clock = false, 304 .regs = &qcn9074_regs, 305 .host_ce_config = ath11k_host_ce_config_qcn9074, 306 .ce_count = 6, 307 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 308 .target_ce_count = 9, 309 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 310 .svc_to_ce_map_len = 18, 311 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 312 .rxdma1_enable = true, 313 .num_rxmda_per_pdev = 1, 314 .rx_mac_buf_ring = false, 315 .vdev_start_delay = false, 316 .htt_peer_map_v2 = true, 317 318 .spectral = { 319 .fft_sz = 2, 320 .fft_pad_sz = 0, 321 .summary_pad_sz = 16, 322 .fft_hdr_len = 24, 323 .max_fft_bins = 1024, 324 .fragment_160mhz = false, 325 }, 326 327 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 328 BIT(NL80211_IFTYPE_AP) | 329 BIT(NL80211_IFTYPE_MESH_POINT), 330 .supports_monitor = true, 331 .full_monitor_mode = true, 332 .supports_shadow_regs = false, 333 .idle_ps = false, 334 .supports_sta_ps = false, 335 .cold_boot_calib = false, 336 .cbcal_restart_fw = false, 337 .fw_mem_mode = 2, 338 .num_vdevs = 8, 339 .num_peers = 128, 340 .supports_suspend = false, 341 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 342 .supports_regdb = false, 343 .fix_l1ss = true, 344 .credit_flow = false, 345 .max_tx_ring = DP_TCL_NUM_RING_MAX, 346 .hal_params = &ath11k_hw_hal_params_ipq8074, 347 .supports_dynamic_smps_6ghz = true, 348 .alloc_cacheable_memory = true, 349 .supports_rssi_stats = false, 350 .fw_wmi_diag_event = false, 351 .current_cc_support = false, 352 .dbr_debug_support = true, 353 .global_reset = false, 354 .bios_sar_capa = NULL, 355 .m3_fw_support = true, 356 .fixed_bdf_addr = false, 357 .fixed_mem_region = false, 358 .static_window_map = true, 359 .hybrid_bus_type = false, 360 .fixed_fw_mem = false, 361 .support_off_channel_tx = false, 362 .supports_multi_bssid = false, 363 364 .sram_dump = {}, 365 366 .tcl_ring_retry = true, 367 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 368 .smp2p_wow_exit = false, 369 .support_fw_mac_sequence = false, 370 }, 371 { 372 .name = "wcn6855 hw2.0", 373 .hw_rev = ATH11K_HW_WCN6855_HW20, 374 .fw = { 375 .dir = "WCN6855/hw2.0", 376 .board_size = 256 * 1024, 377 .cal_offset = 128 * 1024, 378 }, 379 .max_radios = 3, 380 .bdf_addr = 0x4B0C0000, 381 .hw_ops = &wcn6855_ops, 382 .ring_mask = &ath11k_hw_ring_mask_qca6390, 383 .internal_sleep_clock = true, 384 .regs = &wcn6855_regs, 385 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 386 .host_ce_config = ath11k_host_ce_config_qca6390, 387 .ce_count = 9, 388 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 389 .target_ce_count = 9, 390 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 391 .svc_to_ce_map_len = 14, 392 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 393 .single_pdev_only = true, 394 .rxdma1_enable = false, 395 .num_rxmda_per_pdev = 2, 396 .rx_mac_buf_ring = true, 397 .vdev_start_delay = true, 398 .htt_peer_map_v2 = false, 399 400 .spectral = { 401 .fft_sz = 0, 402 .fft_pad_sz = 0, 403 .summary_pad_sz = 0, 404 .fft_hdr_len = 0, 405 .max_fft_bins = 0, 406 .fragment_160mhz = false, 407 }, 408 409 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 410 BIT(NL80211_IFTYPE_AP), 411 .supports_monitor = false, 412 .full_monitor_mode = false, 413 .supports_shadow_regs = true, 414 .idle_ps = true, 415 .supports_sta_ps = true, 416 .cold_boot_calib = false, 417 .cbcal_restart_fw = false, 418 .fw_mem_mode = 0, 419 .num_vdevs = 16 + 1, 420 .num_peers = 512, 421 .supports_suspend = true, 422 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 423 .supports_regdb = true, 424 .fix_l1ss = false, 425 .credit_flow = true, 426 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 427 .hal_params = &ath11k_hw_hal_params_qca6390, 428 .supports_dynamic_smps_6ghz = false, 429 .alloc_cacheable_memory = false, 430 .supports_rssi_stats = true, 431 .fw_wmi_diag_event = true, 432 .current_cc_support = true, 433 .dbr_debug_support = false, 434 .global_reset = true, 435 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 436 .m3_fw_support = true, 437 .fixed_bdf_addr = false, 438 .fixed_mem_region = false, 439 .static_window_map = false, 440 .hybrid_bus_type = false, 441 .fixed_fw_mem = false, 442 .support_off_channel_tx = true, 443 .supports_multi_bssid = true, 444 445 .sram_dump = { 446 .start = 0x01400000, 447 .end = 0x0177ffff, 448 }, 449 450 .tcl_ring_retry = true, 451 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 452 .smp2p_wow_exit = false, 453 .support_fw_mac_sequence = true, 454 }, 455 { 456 .name = "wcn6855 hw2.1", 457 .hw_rev = ATH11K_HW_WCN6855_HW21, 458 .fw = { 459 .dir = "WCN6855/hw2.1", 460 .board_size = 256 * 1024, 461 .cal_offset = 128 * 1024, 462 }, 463 .max_radios = 3, 464 .bdf_addr = 0x4B0C0000, 465 .hw_ops = &wcn6855_ops, 466 .ring_mask = &ath11k_hw_ring_mask_qca6390, 467 .internal_sleep_clock = true, 468 .regs = &wcn6855_regs, 469 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 470 .host_ce_config = ath11k_host_ce_config_qca6390, 471 .ce_count = 9, 472 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 473 .target_ce_count = 9, 474 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 475 .svc_to_ce_map_len = 14, 476 .single_pdev_only = true, 477 .rxdma1_enable = false, 478 .num_rxmda_per_pdev = 2, 479 .rx_mac_buf_ring = true, 480 .vdev_start_delay = true, 481 .htt_peer_map_v2 = false, 482 483 .spectral = { 484 .fft_sz = 0, 485 .fft_pad_sz = 0, 486 .summary_pad_sz = 0, 487 .fft_hdr_len = 0, 488 .max_fft_bins = 0, 489 .fragment_160mhz = false, 490 }, 491 492 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 493 BIT(NL80211_IFTYPE_AP), 494 .supports_monitor = false, 495 .supports_shadow_regs = true, 496 .idle_ps = true, 497 .supports_sta_ps = true, 498 .cold_boot_calib = false, 499 .cbcal_restart_fw = false, 500 .fw_mem_mode = 0, 501 .num_vdevs = 16 + 1, 502 .num_peers = 512, 503 .supports_suspend = true, 504 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 505 .supports_regdb = true, 506 .fix_l1ss = false, 507 .credit_flow = true, 508 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 509 .hal_params = &ath11k_hw_hal_params_qca6390, 510 .supports_dynamic_smps_6ghz = false, 511 .alloc_cacheable_memory = false, 512 .supports_rssi_stats = true, 513 .fw_wmi_diag_event = true, 514 .current_cc_support = true, 515 .dbr_debug_support = false, 516 .global_reset = true, 517 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 518 .m3_fw_support = true, 519 .fixed_bdf_addr = false, 520 .fixed_mem_region = false, 521 .static_window_map = false, 522 .hybrid_bus_type = false, 523 .fixed_fw_mem = false, 524 .support_off_channel_tx = true, 525 .supports_multi_bssid = true, 526 527 .sram_dump = { 528 .start = 0x01400000, 529 .end = 0x0177ffff, 530 }, 531 532 .tcl_ring_retry = true, 533 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 534 .smp2p_wow_exit = false, 535 .support_fw_mac_sequence = true, 536 }, 537 { 538 .name = "wcn6750 hw1.0", 539 .hw_rev = ATH11K_HW_WCN6750_HW10, 540 .fw = { 541 .dir = "WCN6750/hw1.0", 542 .board_size = 256 * 1024, 543 .cal_offset = 128 * 1024, 544 }, 545 .max_radios = 1, 546 .bdf_addr = 0x4B0C0000, 547 .hw_ops = &wcn6750_ops, 548 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 549 .internal_sleep_clock = false, 550 .regs = &wcn6750_regs, 551 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 552 .host_ce_config = ath11k_host_ce_config_qca6390, 553 .ce_count = 9, 554 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 555 .target_ce_count = 9, 556 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 557 .svc_to_ce_map_len = 14, 558 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 559 .single_pdev_only = true, 560 .rxdma1_enable = false, 561 .num_rxmda_per_pdev = 1, 562 .rx_mac_buf_ring = true, 563 .vdev_start_delay = true, 564 .htt_peer_map_v2 = false, 565 566 .spectral = { 567 .fft_sz = 0, 568 .fft_pad_sz = 0, 569 .summary_pad_sz = 0, 570 .fft_hdr_len = 0, 571 .max_fft_bins = 0, 572 .fragment_160mhz = false, 573 }, 574 575 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 576 BIT(NL80211_IFTYPE_AP), 577 .supports_monitor = false, 578 .supports_shadow_regs = true, 579 .idle_ps = true, 580 .supports_sta_ps = true, 581 .cold_boot_calib = true, 582 .cbcal_restart_fw = false, 583 .fw_mem_mode = 0, 584 .num_vdevs = 16 + 1, 585 .num_peers = 512, 586 .supports_suspend = false, 587 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 588 .supports_regdb = true, 589 .fix_l1ss = false, 590 .credit_flow = true, 591 .max_tx_ring = DP_TCL_NUM_RING_MAX, 592 .hal_params = &ath11k_hw_hal_params_wcn6750, 593 .supports_dynamic_smps_6ghz = false, 594 .alloc_cacheable_memory = false, 595 .supports_rssi_stats = true, 596 .fw_wmi_diag_event = false, 597 .current_cc_support = true, 598 .dbr_debug_support = false, 599 .global_reset = false, 600 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 601 .m3_fw_support = false, 602 .fixed_bdf_addr = false, 603 .fixed_mem_region = false, 604 .static_window_map = true, 605 .hybrid_bus_type = true, 606 .fixed_fw_mem = true, 607 .support_off_channel_tx = true, 608 .supports_multi_bssid = true, 609 610 .sram_dump = {}, 611 612 .tcl_ring_retry = false, 613 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 614 .smp2p_wow_exit = true, 615 .support_fw_mac_sequence = true, 616 }, 617 { 618 .hw_rev = ATH11K_HW_IPQ5018_HW10, 619 .name = "ipq5018 hw1.0", 620 .fw = { 621 .dir = "IPQ5018/hw1.0", 622 .board_size = 256 * 1024, 623 .cal_offset = 128 * 1024, 624 }, 625 .max_radios = MAX_RADIOS_5018, 626 .bdf_addr = 0x4BA00000, 627 /* hal_desc_sz and hw ops are similar to qcn9074 */ 628 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 629 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 630 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 631 .credit_flow = false, 632 .max_tx_ring = 1, 633 .spectral = { 634 .fft_sz = 2, 635 .fft_pad_sz = 0, 636 .summary_pad_sz = 16, 637 .fft_hdr_len = 24, 638 .max_fft_bins = 1024, 639 }, 640 .internal_sleep_clock = false, 641 .regs = &ipq5018_regs, 642 .hw_ops = &ipq5018_ops, 643 .host_ce_config = ath11k_host_ce_config_qcn9074, 644 .ce_count = CE_CNT_5018, 645 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 646 .target_ce_count = TARGET_CE_CNT_5018, 647 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 648 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 649 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 650 .ce_remap = &ath11k_ce_remap_ipq5018, 651 .rxdma1_enable = true, 652 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, 653 .rx_mac_buf_ring = false, 654 .vdev_start_delay = false, 655 .htt_peer_map_v2 = true, 656 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 657 BIT(NL80211_IFTYPE_AP) | 658 BIT(NL80211_IFTYPE_MESH_POINT), 659 .supports_monitor = false, 660 .supports_sta_ps = false, 661 .supports_shadow_regs = false, 662 .fw_mem_mode = 0, 663 .num_vdevs = 16 + 1, 664 .num_peers = 512, 665 .supports_regdb = false, 666 .idle_ps = false, 667 .supports_suspend = false, 668 .hal_params = &ath11k_hw_hal_params_ipq8074, 669 .single_pdev_only = false, 670 .cold_boot_calib = true, 671 .cbcal_restart_fw = true, 672 .fix_l1ss = true, 673 .supports_dynamic_smps_6ghz = false, 674 .alloc_cacheable_memory = true, 675 .supports_rssi_stats = false, 676 .fw_wmi_diag_event = false, 677 .current_cc_support = false, 678 .dbr_debug_support = true, 679 .global_reset = false, 680 .bios_sar_capa = NULL, 681 .m3_fw_support = false, 682 .fixed_bdf_addr = true, 683 .fixed_mem_region = true, 684 .static_window_map = false, 685 .hybrid_bus_type = false, 686 .fixed_fw_mem = false, 687 .support_off_channel_tx = false, 688 .supports_multi_bssid = false, 689 690 .sram_dump = {}, 691 692 .tcl_ring_retry = true, 693 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 694 .smp2p_wow_exit = false, 695 .support_fw_mac_sequence = false, 696 }, 697 }; 698 699 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 700 { 701 WARN_ON(!ab->hw_params.single_pdev_only); 702 703 return &ab->pdevs[0]; 704 } 705 706 void ath11k_fw_stats_pdevs_free(struct list_head *head) 707 { 708 struct ath11k_fw_stats_pdev *i, *tmp; 709 710 list_for_each_entry_safe(i, tmp, head, list) { 711 list_del(&i->list); 712 kfree(i); 713 } 714 } 715 716 void ath11k_fw_stats_vdevs_free(struct list_head *head) 717 { 718 struct ath11k_fw_stats_vdev *i, *tmp; 719 720 list_for_each_entry_safe(i, tmp, head, list) { 721 list_del(&i->list); 722 kfree(i); 723 } 724 } 725 726 void ath11k_fw_stats_bcn_free(struct list_head *head) 727 { 728 struct ath11k_fw_stats_bcn *i, *tmp; 729 730 list_for_each_entry_safe(i, tmp, head, list) { 731 list_del(&i->list); 732 kfree(i); 733 } 734 } 735 736 void ath11k_fw_stats_init(struct ath11k *ar) 737 { 738 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 739 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 740 INIT_LIST_HEAD(&ar->fw_stats.bcn); 741 742 init_completion(&ar->fw_stats_complete); 743 } 744 745 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 746 { 747 ath11k_fw_stats_pdevs_free(&stats->pdevs); 748 ath11k_fw_stats_vdevs_free(&stats->vdevs); 749 ath11k_fw_stats_bcn_free(&stats->bcn); 750 } 751 752 int ath11k_core_suspend(struct ath11k_base *ab) 753 { 754 int ret; 755 struct ath11k_pdev *pdev; 756 struct ath11k *ar; 757 758 if (!ab->hw_params.supports_suspend) 759 return -EOPNOTSUPP; 760 761 /* so far single_pdev_only chips have supports_suspend as true 762 * and only the first pdev is valid. 763 */ 764 pdev = ath11k_core_get_single_pdev(ab); 765 ar = pdev->ar; 766 if (!ar || ar->state != ATH11K_STATE_OFF) 767 return 0; 768 769 ret = ath11k_dp_rx_pktlog_stop(ab, true); 770 if (ret) { 771 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 772 ret); 773 return ret; 774 } 775 776 ret = ath11k_mac_wait_tx_complete(ar); 777 if (ret) { 778 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 779 return ret; 780 } 781 782 ret = ath11k_wow_enable(ab); 783 if (ret) { 784 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 785 return ret; 786 } 787 788 ret = ath11k_dp_rx_pktlog_stop(ab, false); 789 if (ret) { 790 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 791 ret); 792 return ret; 793 } 794 795 ath11k_ce_stop_shadow_timers(ab); 796 ath11k_dp_stop_shadow_timers(ab); 797 798 ath11k_hif_irq_disable(ab); 799 ath11k_hif_ce_irq_disable(ab); 800 801 ret = ath11k_hif_suspend(ab); 802 if (ret) { 803 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 804 return ret; 805 } 806 807 return 0; 808 } 809 EXPORT_SYMBOL(ath11k_core_suspend); 810 811 int ath11k_core_resume(struct ath11k_base *ab) 812 { 813 int ret; 814 struct ath11k_pdev *pdev; 815 struct ath11k *ar; 816 817 if (!ab->hw_params.supports_suspend) 818 return -EOPNOTSUPP; 819 820 /* so far signle_pdev_only chips have supports_suspend as true 821 * and only the first pdev is valid. 822 */ 823 pdev = ath11k_core_get_single_pdev(ab); 824 ar = pdev->ar; 825 if (!ar || ar->state != ATH11K_STATE_OFF) 826 return 0; 827 828 ret = ath11k_hif_resume(ab); 829 if (ret) { 830 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 831 return ret; 832 } 833 834 ath11k_hif_ce_irq_enable(ab); 835 ath11k_hif_irq_enable(ab); 836 837 ret = ath11k_dp_rx_pktlog_start(ab); 838 if (ret) { 839 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 840 ret); 841 return ret; 842 } 843 844 ret = ath11k_wow_wakeup(ab); 845 if (ret) { 846 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 847 return ret; 848 } 849 850 return 0; 851 } 852 EXPORT_SYMBOL(ath11k_core_resume); 853 854 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 855 { 856 struct ath11k_base *ab = data; 857 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 858 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 859 ssize_t copied; 860 size_t len; 861 int i; 862 863 if (ab->qmi.target.bdf_ext[0] != '\0') 864 return; 865 866 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 867 return; 868 869 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 870 ath11k_dbg(ab, ATH11K_DBG_BOOT, 871 "wrong smbios bdf ext type length (%d).\n", 872 hdr->length); 873 return; 874 } 875 876 spin_lock_bh(&ab->base_lock); 877 878 switch (smbios->country_code_flag) { 879 case ATH11K_SMBIOS_CC_ISO: 880 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 881 ab->new_alpha2[1] = smbios->cc_code & 0xff; 882 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 883 ab->new_alpha2[0], ab->new_alpha2[1]); 884 break; 885 case ATH11K_SMBIOS_CC_WW: 886 ab->new_alpha2[0] = '0'; 887 ab->new_alpha2[1] = '0'; 888 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 889 break; 890 default: 891 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 892 smbios->country_code_flag); 893 break; 894 } 895 896 spin_unlock_bh(&ab->base_lock); 897 898 if (!smbios->bdf_enabled) { 899 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 900 return; 901 } 902 903 /* Only one string exists (per spec) */ 904 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 905 ath11k_dbg(ab, ATH11K_DBG_BOOT, 906 "bdf variant magic does not match.\n"); 907 return; 908 } 909 910 len = min_t(size_t, 911 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 912 for (i = 0; i < len; i++) { 913 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 914 ath11k_dbg(ab, ATH11K_DBG_BOOT, 915 "bdf variant name contains non ascii chars.\n"); 916 return; 917 } 918 } 919 920 /* Copy extension name without magic prefix */ 921 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 922 sizeof(ab->qmi.target.bdf_ext)); 923 if (copied < 0) { 924 ath11k_dbg(ab, ATH11K_DBG_BOOT, 925 "bdf variant string is longer than the buffer can accommodate\n"); 926 return; 927 } 928 929 ath11k_dbg(ab, ATH11K_DBG_BOOT, 930 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 931 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 932 } 933 934 int ath11k_core_check_smbios(struct ath11k_base *ab) 935 { 936 ab->qmi.target.bdf_ext[0] = '\0'; 937 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 938 939 if (ab->qmi.target.bdf_ext[0] == '\0') 940 return -ENODATA; 941 942 return 0; 943 } 944 945 int ath11k_core_check_dt(struct ath11k_base *ab) 946 { 947 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 948 const char *variant = NULL; 949 struct device_node *node; 950 951 node = ab->dev->of_node; 952 if (!node) 953 return -ENOENT; 954 955 of_property_read_string(node, "qcom,ath11k-calibration-variant", 956 &variant); 957 if (!variant) 958 return -ENODATA; 959 960 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 961 ath11k_dbg(ab, ATH11K_DBG_BOOT, 962 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 963 variant); 964 965 return 0; 966 } 967 968 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 969 size_t name_len, bool with_variant, 970 bool bus_type_mode) 971 { 972 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 973 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 974 975 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 976 scnprintf(variant, sizeof(variant), ",variant=%s", 977 ab->qmi.target.bdf_ext); 978 979 switch (ab->id.bdf_search) { 980 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 981 if (bus_type_mode) 982 scnprintf(name, name_len, 983 "bus=%s", 984 ath11k_bus_str(ab->hif.bus)); 985 else 986 scnprintf(name, name_len, 987 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 988 ath11k_bus_str(ab->hif.bus), 989 ab->id.vendor, ab->id.device, 990 ab->id.subsystem_vendor, 991 ab->id.subsystem_device, 992 ab->qmi.target.chip_id, 993 ab->qmi.target.board_id, 994 variant); 995 break; 996 default: 997 scnprintf(name, name_len, 998 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 999 ath11k_bus_str(ab->hif.bus), 1000 ab->qmi.target.chip_id, 1001 ab->qmi.target.board_id, variant); 1002 break; 1003 } 1004 1005 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1006 1007 return 0; 1008 } 1009 1010 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1011 size_t name_len) 1012 { 1013 return __ath11k_core_create_board_name(ab, name, name_len, true, false); 1014 } 1015 1016 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1017 size_t name_len) 1018 { 1019 return __ath11k_core_create_board_name(ab, name, name_len, false, false); 1020 } 1021 1022 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1023 size_t name_len) 1024 { 1025 return __ath11k_core_create_board_name(ab, name, name_len, false, true); 1026 } 1027 1028 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1029 const char *file) 1030 { 1031 const struct firmware *fw; 1032 char path[100]; 1033 int ret; 1034 1035 if (file == NULL) 1036 return ERR_PTR(-ENOENT); 1037 1038 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1039 1040 ret = firmware_request_nowarn(&fw, path, ab->dev); 1041 if (ret) 1042 return ERR_PTR(ret); 1043 1044 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1045 path, fw->size); 1046 1047 return fw; 1048 } 1049 1050 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1051 { 1052 if (!IS_ERR(bd->fw)) 1053 release_firmware(bd->fw); 1054 1055 memset(bd, 0, sizeof(*bd)); 1056 } 1057 1058 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1059 struct ath11k_board_data *bd, 1060 const void *buf, size_t buf_len, 1061 const char *boardname, 1062 int ie_id, 1063 int name_id, 1064 int data_id) 1065 { 1066 const struct ath11k_fw_ie *hdr; 1067 bool name_match_found; 1068 int ret, board_ie_id; 1069 size_t board_ie_len; 1070 const void *board_ie_data; 1071 1072 name_match_found = false; 1073 1074 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1075 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1076 hdr = buf; 1077 board_ie_id = le32_to_cpu(hdr->id); 1078 board_ie_len = le32_to_cpu(hdr->len); 1079 board_ie_data = hdr->data; 1080 1081 buf_len -= sizeof(*hdr); 1082 buf += sizeof(*hdr); 1083 1084 if (buf_len < ALIGN(board_ie_len, 4)) { 1085 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1086 ath11k_bd_ie_type_str(ie_id), 1087 buf_len, ALIGN(board_ie_len, 4)); 1088 ret = -EINVAL; 1089 goto out; 1090 } 1091 1092 if (board_ie_id == name_id) { 1093 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1094 board_ie_data, board_ie_len); 1095 1096 if (board_ie_len != strlen(boardname)) 1097 goto next; 1098 1099 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1100 if (ret) 1101 goto next; 1102 1103 name_match_found = true; 1104 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1105 "found match %s for name '%s'", 1106 ath11k_bd_ie_type_str(ie_id), 1107 boardname); 1108 } else if (board_ie_id == data_id) { 1109 if (!name_match_found) 1110 /* no match found */ 1111 goto next; 1112 1113 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1114 "found %s for '%s'", 1115 ath11k_bd_ie_type_str(ie_id), 1116 boardname); 1117 1118 bd->data = board_ie_data; 1119 bd->len = board_ie_len; 1120 1121 ret = 0; 1122 goto out; 1123 } else { 1124 ath11k_warn(ab, "unknown %s id found: %d\n", 1125 ath11k_bd_ie_type_str(ie_id), 1126 board_ie_id); 1127 } 1128 next: 1129 /* jump over the padding */ 1130 board_ie_len = ALIGN(board_ie_len, 4); 1131 1132 buf_len -= board_ie_len; 1133 buf += board_ie_len; 1134 } 1135 1136 /* no match found */ 1137 ret = -ENOENT; 1138 1139 out: 1140 return ret; 1141 } 1142 1143 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1144 struct ath11k_board_data *bd, 1145 const char *boardname, 1146 int ie_id_match, 1147 int name_id, 1148 int data_id) 1149 { 1150 size_t len, magic_len; 1151 const u8 *data; 1152 char *filename, filepath[100]; 1153 size_t ie_len; 1154 struct ath11k_fw_ie *hdr; 1155 int ret, ie_id; 1156 1157 filename = ATH11K_BOARD_API2_FILE; 1158 1159 if (!bd->fw) 1160 bd->fw = ath11k_core_firmware_request(ab, filename); 1161 1162 if (IS_ERR(bd->fw)) 1163 return PTR_ERR(bd->fw); 1164 1165 data = bd->fw->data; 1166 len = bd->fw->size; 1167 1168 ath11k_core_create_firmware_path(ab, filename, 1169 filepath, sizeof(filepath)); 1170 1171 /* magic has extra null byte padded */ 1172 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1173 if (len < magic_len) { 1174 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1175 filepath, len); 1176 ret = -EINVAL; 1177 goto err; 1178 } 1179 1180 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1181 ath11k_err(ab, "found invalid board magic\n"); 1182 ret = -EINVAL; 1183 goto err; 1184 } 1185 1186 /* magic is padded to 4 bytes */ 1187 magic_len = ALIGN(magic_len, 4); 1188 if (len < magic_len) { 1189 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1190 filepath, len); 1191 ret = -EINVAL; 1192 goto err; 1193 } 1194 1195 data += magic_len; 1196 len -= magic_len; 1197 1198 while (len > sizeof(struct ath11k_fw_ie)) { 1199 hdr = (struct ath11k_fw_ie *)data; 1200 ie_id = le32_to_cpu(hdr->id); 1201 ie_len = le32_to_cpu(hdr->len); 1202 1203 len -= sizeof(*hdr); 1204 data = hdr->data; 1205 1206 if (len < ALIGN(ie_len, 4)) { 1207 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1208 ie_id, ie_len, len); 1209 ret = -EINVAL; 1210 goto err; 1211 } 1212 1213 if (ie_id == ie_id_match) { 1214 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1215 ie_len, 1216 boardname, 1217 ie_id_match, 1218 name_id, 1219 data_id); 1220 if (ret == -ENOENT) 1221 /* no match found, continue */ 1222 goto next; 1223 else if (ret) 1224 /* there was an error, bail out */ 1225 goto err; 1226 /* either found or error, so stop searching */ 1227 goto out; 1228 } 1229 next: 1230 /* jump over the padding */ 1231 ie_len = ALIGN(ie_len, 4); 1232 1233 len -= ie_len; 1234 data += ie_len; 1235 } 1236 1237 out: 1238 if (!bd->data || !bd->len) { 1239 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1240 "failed to fetch %s for %s from %s\n", 1241 ath11k_bd_ie_type_str(ie_id_match), 1242 boardname, filepath); 1243 ret = -ENODATA; 1244 goto err; 1245 } 1246 1247 return 0; 1248 1249 err: 1250 ath11k_core_free_bdf(ab, bd); 1251 return ret; 1252 } 1253 1254 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1255 struct ath11k_board_data *bd, 1256 const char *name) 1257 { 1258 bd->fw = ath11k_core_firmware_request(ab, name); 1259 1260 if (IS_ERR(bd->fw)) 1261 return PTR_ERR(bd->fw); 1262 1263 bd->data = bd->fw->data; 1264 bd->len = bd->fw->size; 1265 1266 return 0; 1267 } 1268 1269 #define BOARD_NAME_SIZE 200 1270 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1271 { 1272 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1273 char *filename, filepath[100]; 1274 int ret; 1275 1276 filename = ATH11K_BOARD_API2_FILE; 1277 1278 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1279 if (ret) { 1280 ath11k_err(ab, "failed to create board name: %d", ret); 1281 return ret; 1282 } 1283 1284 ab->bd_api = 2; 1285 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1286 ATH11K_BD_IE_BOARD, 1287 ATH11K_BD_IE_BOARD_NAME, 1288 ATH11K_BD_IE_BOARD_DATA); 1289 if (!ret) 1290 goto success; 1291 1292 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1293 sizeof(fallback_boardname)); 1294 if (ret) { 1295 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1296 return ret; 1297 } 1298 1299 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1300 ATH11K_BD_IE_BOARD, 1301 ATH11K_BD_IE_BOARD_NAME, 1302 ATH11K_BD_IE_BOARD_DATA); 1303 if (!ret) 1304 goto success; 1305 1306 ab->bd_api = 1; 1307 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1308 if (ret) { 1309 ath11k_core_create_firmware_path(ab, filename, 1310 filepath, sizeof(filepath)); 1311 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1312 boardname, filepath); 1313 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1314 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1315 fallback_boardname, filepath); 1316 1317 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1318 ab->hw_params.fw.dir); 1319 return ret; 1320 } 1321 1322 success: 1323 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1324 return 0; 1325 } 1326 1327 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1328 { 1329 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1330 int ret; 1331 1332 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1333 if (ret) { 1334 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1335 "failed to create board name for regdb: %d", ret); 1336 goto exit; 1337 } 1338 1339 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1340 ATH11K_BD_IE_REGDB, 1341 ATH11K_BD_IE_REGDB_NAME, 1342 ATH11K_BD_IE_REGDB_DATA); 1343 if (!ret) 1344 goto exit; 1345 1346 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1347 BOARD_NAME_SIZE); 1348 if (ret) { 1349 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1350 "failed to create default board name for regdb: %d", ret); 1351 goto exit; 1352 } 1353 1354 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1355 ATH11K_BD_IE_REGDB, 1356 ATH11K_BD_IE_REGDB_NAME, 1357 ATH11K_BD_IE_REGDB_DATA); 1358 if (!ret) 1359 goto exit; 1360 1361 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1362 if (ret) 1363 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1364 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1365 1366 exit: 1367 if (!ret) 1368 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1369 1370 return ret; 1371 } 1372 1373 static void ath11k_core_stop(struct ath11k_base *ab) 1374 { 1375 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1376 ath11k_qmi_firmware_stop(ab); 1377 1378 ath11k_hif_stop(ab); 1379 ath11k_wmi_detach(ab); 1380 ath11k_dp_pdev_reo_cleanup(ab); 1381 1382 /* De-Init of components as needed */ 1383 } 1384 1385 static int ath11k_core_soc_create(struct ath11k_base *ab) 1386 { 1387 int ret; 1388 1389 if (ath11k_ftm_mode) { 1390 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1391 ath11k_info(ab, "Booting in factory test mode\n"); 1392 } 1393 1394 ret = ath11k_qmi_init_service(ab); 1395 if (ret) { 1396 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1397 return ret; 1398 } 1399 1400 ret = ath11k_debugfs_soc_create(ab); 1401 if (ret) { 1402 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1403 goto err_qmi_deinit; 1404 } 1405 1406 ret = ath11k_hif_power_up(ab); 1407 if (ret) { 1408 ath11k_err(ab, "failed to power up :%d\n", ret); 1409 goto err_debugfs_reg; 1410 } 1411 1412 return 0; 1413 1414 err_debugfs_reg: 1415 ath11k_debugfs_soc_destroy(ab); 1416 err_qmi_deinit: 1417 ath11k_qmi_deinit_service(ab); 1418 return ret; 1419 } 1420 1421 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1422 { 1423 ath11k_debugfs_soc_destroy(ab); 1424 ath11k_dp_free(ab); 1425 ath11k_reg_free(ab); 1426 ath11k_qmi_deinit_service(ab); 1427 } 1428 1429 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1430 { 1431 int ret; 1432 1433 ret = ath11k_debugfs_pdev_create(ab); 1434 if (ret) { 1435 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1436 return ret; 1437 } 1438 1439 ret = ath11k_dp_pdev_alloc(ab); 1440 if (ret) { 1441 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1442 goto err_pdev_debug; 1443 } 1444 1445 ret = ath11k_mac_register(ab); 1446 if (ret) { 1447 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1448 goto err_dp_pdev_free; 1449 } 1450 1451 ret = ath11k_thermal_register(ab); 1452 if (ret) { 1453 ath11k_err(ab, "could not register thermal device: %d\n", 1454 ret); 1455 goto err_mac_unregister; 1456 } 1457 1458 ret = ath11k_spectral_init(ab); 1459 if (ret) { 1460 ath11k_err(ab, "failed to init spectral %d\n", ret); 1461 goto err_thermal_unregister; 1462 } 1463 1464 return 0; 1465 1466 err_thermal_unregister: 1467 ath11k_thermal_unregister(ab); 1468 err_mac_unregister: 1469 ath11k_mac_unregister(ab); 1470 err_dp_pdev_free: 1471 ath11k_dp_pdev_free(ab); 1472 err_pdev_debug: 1473 ath11k_debugfs_pdev_destroy(ab); 1474 1475 return ret; 1476 } 1477 1478 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1479 { 1480 ath11k_spectral_deinit(ab); 1481 ath11k_thermal_unregister(ab); 1482 ath11k_mac_unregister(ab); 1483 ath11k_hif_irq_disable(ab); 1484 ath11k_dp_pdev_free(ab); 1485 ath11k_debugfs_pdev_destroy(ab); 1486 } 1487 1488 static int ath11k_core_start(struct ath11k_base *ab) 1489 { 1490 int ret; 1491 1492 ret = ath11k_wmi_attach(ab); 1493 if (ret) { 1494 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1495 return ret; 1496 } 1497 1498 ret = ath11k_htc_init(ab); 1499 if (ret) { 1500 ath11k_err(ab, "failed to init htc: %d\n", ret); 1501 goto err_wmi_detach; 1502 } 1503 1504 ret = ath11k_hif_start(ab); 1505 if (ret) { 1506 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1507 goto err_wmi_detach; 1508 } 1509 1510 ret = ath11k_htc_wait_target(&ab->htc); 1511 if (ret) { 1512 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1513 goto err_hif_stop; 1514 } 1515 1516 ret = ath11k_dp_htt_connect(&ab->dp); 1517 if (ret) { 1518 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1519 goto err_hif_stop; 1520 } 1521 1522 ret = ath11k_wmi_connect(ab); 1523 if (ret) { 1524 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1525 goto err_hif_stop; 1526 } 1527 1528 ret = ath11k_htc_start(&ab->htc); 1529 if (ret) { 1530 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1531 goto err_hif_stop; 1532 } 1533 1534 ret = ath11k_wmi_wait_for_service_ready(ab); 1535 if (ret) { 1536 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1537 ret); 1538 goto err_hif_stop; 1539 } 1540 1541 ret = ath11k_mac_allocate(ab); 1542 if (ret) { 1543 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1544 ret); 1545 goto err_hif_stop; 1546 } 1547 1548 ath11k_dp_pdev_pre_alloc(ab); 1549 1550 ret = ath11k_dp_pdev_reo_setup(ab); 1551 if (ret) { 1552 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1553 goto err_mac_destroy; 1554 } 1555 1556 ret = ath11k_wmi_cmd_init(ab); 1557 if (ret) { 1558 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1559 goto err_reo_cleanup; 1560 } 1561 1562 ret = ath11k_wmi_wait_for_unified_ready(ab); 1563 if (ret) { 1564 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1565 ret); 1566 goto err_reo_cleanup; 1567 } 1568 1569 /* put hardware to DBS mode */ 1570 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1571 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1572 if (ret) { 1573 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1574 goto err_hif_stop; 1575 } 1576 } 1577 1578 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1579 if (ret) { 1580 ath11k_err(ab, "failed to send htt version request message: %d\n", 1581 ret); 1582 goto err_reo_cleanup; 1583 } 1584 1585 return 0; 1586 1587 err_reo_cleanup: 1588 ath11k_dp_pdev_reo_cleanup(ab); 1589 err_mac_destroy: 1590 ath11k_mac_destroy(ab); 1591 err_hif_stop: 1592 ath11k_hif_stop(ab); 1593 err_wmi_detach: 1594 ath11k_wmi_detach(ab); 1595 1596 return ret; 1597 } 1598 1599 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1600 enum ath11k_firmware_mode mode) 1601 { 1602 int ret; 1603 1604 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1605 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1606 1607 ret = ath11k_qmi_firmware_start(ab, mode); 1608 if (ret) { 1609 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1610 return ret; 1611 } 1612 1613 return ret; 1614 } 1615 1616 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1617 { 1618 int ret; 1619 1620 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 1621 if (ret) { 1622 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1623 return ret; 1624 } 1625 1626 ret = ath11k_ce_init_pipes(ab); 1627 if (ret) { 1628 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1629 goto err_firmware_stop; 1630 } 1631 1632 ret = ath11k_dp_alloc(ab); 1633 if (ret) { 1634 ath11k_err(ab, "failed to init DP: %d\n", ret); 1635 goto err_firmware_stop; 1636 } 1637 1638 switch (ath11k_crypto_mode) { 1639 case ATH11K_CRYPT_MODE_SW: 1640 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1641 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1642 break; 1643 case ATH11K_CRYPT_MODE_HW: 1644 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1645 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1646 break; 1647 default: 1648 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1649 return -EINVAL; 1650 } 1651 1652 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1653 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1654 1655 mutex_lock(&ab->core_lock); 1656 ret = ath11k_core_start(ab); 1657 if (ret) { 1658 ath11k_err(ab, "failed to start core: %d\n", ret); 1659 goto err_dp_free; 1660 } 1661 1662 ret = ath11k_core_pdev_create(ab); 1663 if (ret) { 1664 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1665 goto err_core_stop; 1666 } 1667 ath11k_hif_irq_enable(ab); 1668 mutex_unlock(&ab->core_lock); 1669 1670 return 0; 1671 1672 err_core_stop: 1673 ath11k_core_stop(ab); 1674 ath11k_mac_destroy(ab); 1675 err_dp_free: 1676 ath11k_dp_free(ab); 1677 mutex_unlock(&ab->core_lock); 1678 err_firmware_stop: 1679 ath11k_qmi_firmware_stop(ab); 1680 1681 return ret; 1682 } 1683 1684 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1685 { 1686 int ret; 1687 1688 mutex_lock(&ab->core_lock); 1689 ath11k_thermal_unregister(ab); 1690 ath11k_hif_irq_disable(ab); 1691 ath11k_dp_pdev_free(ab); 1692 ath11k_spectral_deinit(ab); 1693 ath11k_hif_stop(ab); 1694 ath11k_wmi_detach(ab); 1695 ath11k_dp_pdev_reo_cleanup(ab); 1696 mutex_unlock(&ab->core_lock); 1697 1698 ath11k_dp_free(ab); 1699 ath11k_hal_srng_deinit(ab); 1700 1701 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1702 1703 ret = ath11k_hal_srng_init(ab); 1704 if (ret) 1705 return ret; 1706 1707 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1708 1709 ret = ath11k_core_qmi_firmware_ready(ab); 1710 if (ret) 1711 goto err_hal_srng_deinit; 1712 1713 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1714 1715 return 0; 1716 1717 err_hal_srng_deinit: 1718 ath11k_hal_srng_deinit(ab); 1719 return ret; 1720 } 1721 1722 void ath11k_core_halt(struct ath11k *ar) 1723 { 1724 struct ath11k_base *ab = ar->ab; 1725 1726 lockdep_assert_held(&ar->conf_mutex); 1727 1728 ar->num_created_vdevs = 0; 1729 ar->allocated_vdev_map = 0; 1730 1731 ath11k_mac_scan_finish(ar); 1732 ath11k_mac_peer_cleanup_all(ar); 1733 cancel_delayed_work_sync(&ar->scan.timeout); 1734 cancel_work_sync(&ar->regd_update_work); 1735 cancel_work_sync(&ab->update_11d_work); 1736 1737 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1738 synchronize_rcu(); 1739 INIT_LIST_HEAD(&ar->arvifs); 1740 idr_init(&ar->txmgmt_idr); 1741 } 1742 1743 static void ath11k_update_11d(struct work_struct *work) 1744 { 1745 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1746 struct ath11k *ar; 1747 struct ath11k_pdev *pdev; 1748 struct wmi_set_current_country_params set_current_param = {}; 1749 int ret, i; 1750 1751 spin_lock_bh(&ab->base_lock); 1752 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1753 spin_unlock_bh(&ab->base_lock); 1754 1755 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1756 set_current_param.alpha2[0], 1757 set_current_param.alpha2[1]); 1758 1759 for (i = 0; i < ab->num_radios; i++) { 1760 pdev = &ab->pdevs[i]; 1761 ar = pdev->ar; 1762 1763 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1764 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1765 if (ret) 1766 ath11k_warn(ar->ab, 1767 "pdev id %d failed set current country code: %d\n", 1768 i, ret); 1769 } 1770 } 1771 1772 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1773 { 1774 struct ath11k *ar; 1775 struct ath11k_pdev *pdev; 1776 int i; 1777 1778 spin_lock_bh(&ab->base_lock); 1779 ab->stats.fw_crash_counter++; 1780 spin_unlock_bh(&ab->base_lock); 1781 1782 for (i = 0; i < ab->num_radios; i++) { 1783 pdev = &ab->pdevs[i]; 1784 ar = pdev->ar; 1785 if (!ar || ar->state == ATH11K_STATE_OFF || 1786 ar->state == ATH11K_STATE_FTM) 1787 continue; 1788 1789 ieee80211_stop_queues(ar->hw); 1790 ath11k_mac_drain_tx(ar); 1791 ar->state_11d = ATH11K_11D_IDLE; 1792 complete(&ar->completed_11d_scan); 1793 complete(&ar->scan.started); 1794 complete_all(&ar->scan.completed); 1795 complete(&ar->scan.on_channel); 1796 complete(&ar->peer_assoc_done); 1797 complete(&ar->peer_delete_done); 1798 complete(&ar->install_key_done); 1799 complete(&ar->vdev_setup_done); 1800 complete(&ar->vdev_delete_done); 1801 complete(&ar->bss_survey_done); 1802 complete(&ar->thermal.wmi_sync); 1803 1804 wake_up(&ar->dp.tx_empty_waitq); 1805 idr_for_each(&ar->txmgmt_idr, 1806 ath11k_mac_tx_mgmt_pending_free, ar); 1807 idr_destroy(&ar->txmgmt_idr); 1808 wake_up(&ar->txmgmt_empty_waitq); 1809 1810 ar->monitor_vdev_id = -1; 1811 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 1812 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 1813 } 1814 1815 wake_up(&ab->wmi_ab.tx_credits_wq); 1816 wake_up(&ab->peer_mapping_wq); 1817 1818 reinit_completion(&ab->driver_recovery); 1819 } 1820 1821 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1822 { 1823 struct ath11k *ar; 1824 struct ath11k_pdev *pdev; 1825 int i; 1826 1827 for (i = 0; i < ab->num_radios; i++) { 1828 pdev = &ab->pdevs[i]; 1829 ar = pdev->ar; 1830 if (!ar || ar->state == ATH11K_STATE_OFF) 1831 continue; 1832 1833 mutex_lock(&ar->conf_mutex); 1834 1835 switch (ar->state) { 1836 case ATH11K_STATE_ON: 1837 ar->state = ATH11K_STATE_RESTARTING; 1838 ath11k_core_halt(ar); 1839 ieee80211_restart_hw(ar->hw); 1840 break; 1841 case ATH11K_STATE_OFF: 1842 ath11k_warn(ab, 1843 "cannot restart radio %d that hasn't been started\n", 1844 i); 1845 break; 1846 case ATH11K_STATE_RESTARTING: 1847 break; 1848 case ATH11K_STATE_RESTARTED: 1849 ar->state = ATH11K_STATE_WEDGED; 1850 fallthrough; 1851 case ATH11K_STATE_WEDGED: 1852 ath11k_warn(ab, 1853 "device is wedged, will not restart radio %d\n", i); 1854 break; 1855 case ATH11K_STATE_FTM: 1856 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 1857 "fw mode reset done radio %d\n", i); 1858 break; 1859 } 1860 1861 mutex_unlock(&ar->conf_mutex); 1862 } 1863 complete(&ab->driver_recovery); 1864 } 1865 1866 static void ath11k_core_restart(struct work_struct *work) 1867 { 1868 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1869 int ret; 1870 1871 ret = ath11k_core_reconfigure_on_crash(ab); 1872 if (ret) { 1873 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1874 return; 1875 } 1876 1877 if (ab->is_reset) 1878 complete_all(&ab->reconfigure_complete); 1879 1880 if (!ab->is_reset) 1881 ath11k_core_post_reconfigure_recovery(ab); 1882 } 1883 1884 static void ath11k_core_reset(struct work_struct *work) 1885 { 1886 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1887 int reset_count, fail_cont_count; 1888 long time_left; 1889 1890 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1891 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1892 return; 1893 } 1894 1895 /* Sometimes the recovery will fail and then the next all recovery fail, 1896 * this is to avoid infinite recovery since it can not recovery success. 1897 */ 1898 fail_cont_count = atomic_read(&ab->fail_cont_count); 1899 1900 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1901 return; 1902 1903 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1904 time_before(jiffies, ab->reset_fail_timeout)) 1905 return; 1906 1907 reset_count = atomic_inc_return(&ab->reset_count); 1908 1909 if (reset_count > 1) { 1910 /* Sometimes it happened another reset worker before the previous one 1911 * completed, then the second reset worker will destroy the previous one, 1912 * thus below is to avoid that. 1913 */ 1914 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1915 1916 reinit_completion(&ab->reset_complete); 1917 time_left = wait_for_completion_timeout(&ab->reset_complete, 1918 ATH11K_RESET_TIMEOUT_HZ); 1919 1920 if (time_left) { 1921 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1922 atomic_dec(&ab->reset_count); 1923 return; 1924 } 1925 1926 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1927 /* Record the continuous recovery fail count when recovery failed*/ 1928 atomic_inc(&ab->fail_cont_count); 1929 } 1930 1931 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1932 1933 ab->is_reset = true; 1934 atomic_set(&ab->recovery_count, 0); 1935 reinit_completion(&ab->recovery_start); 1936 atomic_set(&ab->recovery_start_count, 0); 1937 1938 ath11k_core_pre_reconfigure_recovery(ab); 1939 1940 reinit_completion(&ab->reconfigure_complete); 1941 ath11k_core_post_reconfigure_recovery(ab); 1942 1943 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1944 1945 time_left = wait_for_completion_timeout(&ab->recovery_start, 1946 ATH11K_RECOVER_START_TIMEOUT_HZ); 1947 1948 ath11k_hif_power_down(ab); 1949 ath11k_hif_power_up(ab); 1950 1951 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1952 } 1953 1954 static int ath11k_init_hw_params(struct ath11k_base *ab) 1955 { 1956 const struct ath11k_hw_params *hw_params = NULL; 1957 int i; 1958 1959 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1960 hw_params = &ath11k_hw_params[i]; 1961 1962 if (hw_params->hw_rev == ab->hw_rev) 1963 break; 1964 } 1965 1966 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1967 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1968 return -EINVAL; 1969 } 1970 1971 ab->hw_params = *hw_params; 1972 1973 ath11k_info(ab, "%s\n", ab->hw_params.name); 1974 1975 return 0; 1976 } 1977 1978 int ath11k_core_pre_init(struct ath11k_base *ab) 1979 { 1980 int ret; 1981 1982 ret = ath11k_init_hw_params(ab); 1983 if (ret) { 1984 ath11k_err(ab, "failed to get hw params: %d\n", ret); 1985 return ret; 1986 } 1987 1988 return 0; 1989 } 1990 EXPORT_SYMBOL(ath11k_core_pre_init); 1991 1992 int ath11k_core_init(struct ath11k_base *ab) 1993 { 1994 int ret; 1995 1996 ret = ath11k_core_soc_create(ab); 1997 if (ret) { 1998 ath11k_err(ab, "failed to create soc core: %d\n", ret); 1999 return ret; 2000 } 2001 2002 return 0; 2003 } 2004 EXPORT_SYMBOL(ath11k_core_init); 2005 2006 void ath11k_core_deinit(struct ath11k_base *ab) 2007 { 2008 mutex_lock(&ab->core_lock); 2009 2010 ath11k_core_pdev_destroy(ab); 2011 ath11k_core_stop(ab); 2012 2013 mutex_unlock(&ab->core_lock); 2014 2015 ath11k_hif_power_down(ab); 2016 ath11k_mac_destroy(ab); 2017 ath11k_core_soc_destroy(ab); 2018 } 2019 EXPORT_SYMBOL(ath11k_core_deinit); 2020 2021 void ath11k_core_free(struct ath11k_base *ab) 2022 { 2023 destroy_workqueue(ab->workqueue_aux); 2024 destroy_workqueue(ab->workqueue); 2025 2026 kfree(ab); 2027 } 2028 EXPORT_SYMBOL(ath11k_core_free); 2029 2030 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2031 enum ath11k_bus bus) 2032 { 2033 struct ath11k_base *ab; 2034 2035 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2036 if (!ab) 2037 return NULL; 2038 2039 init_completion(&ab->driver_recovery); 2040 2041 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2042 if (!ab->workqueue) 2043 goto err_sc_free; 2044 2045 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2046 if (!ab->workqueue_aux) 2047 goto err_free_wq; 2048 2049 mutex_init(&ab->core_lock); 2050 mutex_init(&ab->tbl_mtx_lock); 2051 spin_lock_init(&ab->base_lock); 2052 mutex_init(&ab->vdev_id_11d_lock); 2053 init_completion(&ab->reset_complete); 2054 init_completion(&ab->reconfigure_complete); 2055 init_completion(&ab->recovery_start); 2056 2057 INIT_LIST_HEAD(&ab->peers); 2058 init_waitqueue_head(&ab->peer_mapping_wq); 2059 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2060 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2061 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2062 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2063 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2064 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2065 init_completion(&ab->htc_suspend); 2066 init_completion(&ab->wow.wakeup_completed); 2067 2068 ab->dev = dev; 2069 ab->hif.bus = bus; 2070 2071 return ab; 2072 2073 err_free_wq: 2074 destroy_workqueue(ab->workqueue); 2075 err_sc_free: 2076 kfree(ab); 2077 return NULL; 2078 } 2079 EXPORT_SYMBOL(ath11k_core_alloc); 2080 2081 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2082 MODULE_LICENSE("Dual BSD/GPL"); 2083