1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 static const struct ath11k_hw_params ath11k_hw_params[] = { 36 { 37 .hw_rev = ATH11K_HW_IPQ8074, 38 .name = "ipq8074 hw2.0", 39 .fw = { 40 .dir = "IPQ8074/hw2.0", 41 .board_size = 256 * 1024, 42 .cal_offset = 128 * 1024, 43 }, 44 .max_radios = 3, 45 .bdf_addr = 0x4B0C0000, 46 .hw_ops = &ipq8074_ops, 47 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 48 .internal_sleep_clock = false, 49 .regs = &ipq8074_regs, 50 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 51 .host_ce_config = ath11k_host_ce_config_ipq8074, 52 .ce_count = 12, 53 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 54 .target_ce_count = 11, 55 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 56 .svc_to_ce_map_len = 21, 57 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 58 .single_pdev_only = false, 59 .rxdma1_enable = true, 60 .num_rxmda_per_pdev = 1, 61 .rx_mac_buf_ring = false, 62 .vdev_start_delay = false, 63 .htt_peer_map_v2 = true, 64 65 .spectral = { 66 .fft_sz = 2, 67 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 68 * so added pad size as 2 bytes to compensate the BIN size 69 */ 70 .fft_pad_sz = 2, 71 .summary_pad_sz = 0, 72 .fft_hdr_len = 16, 73 .max_fft_bins = 512, 74 .fragment_160mhz = true, 75 }, 76 77 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 78 BIT(NL80211_IFTYPE_AP) | 79 BIT(NL80211_IFTYPE_MESH_POINT), 80 .supports_monitor = true, 81 .full_monitor_mode = false, 82 .supports_shadow_regs = false, 83 .idle_ps = false, 84 .supports_sta_ps = false, 85 .cold_boot_calib = true, 86 .cbcal_restart_fw = true, 87 .fw_mem_mode = 0, 88 .num_vdevs = 16 + 1, 89 .num_peers = 512, 90 .supports_suspend = false, 91 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 92 .supports_regdb = false, 93 .fix_l1ss = true, 94 .credit_flow = false, 95 .max_tx_ring = DP_TCL_NUM_RING_MAX, 96 .hal_params = &ath11k_hw_hal_params_ipq8074, 97 .supports_dynamic_smps_6ghz = false, 98 .alloc_cacheable_memory = true, 99 .supports_rssi_stats = false, 100 .fw_wmi_diag_event = false, 101 .current_cc_support = false, 102 .dbr_debug_support = true, 103 .global_reset = false, 104 .bios_sar_capa = NULL, 105 .m3_fw_support = false, 106 .fixed_bdf_addr = true, 107 .fixed_mem_region = true, 108 .static_window_map = false, 109 .hybrid_bus_type = false, 110 .fixed_fw_mem = false, 111 .support_off_channel_tx = false, 112 .supports_multi_bssid = false, 113 114 .sram_dump = {}, 115 116 .tcl_ring_retry = true, 117 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 118 .smp2p_wow_exit = false, 119 .ftm_responder = true, 120 }, 121 { 122 .hw_rev = ATH11K_HW_IPQ6018_HW10, 123 .name = "ipq6018 hw1.0", 124 .fw = { 125 .dir = "IPQ6018/hw1.0", 126 .board_size = 256 * 1024, 127 .cal_offset = 128 * 1024, 128 }, 129 .max_radios = 2, 130 .bdf_addr = 0x4ABC0000, 131 .hw_ops = &ipq6018_ops, 132 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 133 .internal_sleep_clock = false, 134 .regs = &ipq8074_regs, 135 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 136 .host_ce_config = ath11k_host_ce_config_ipq8074, 137 .ce_count = 12, 138 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 139 .target_ce_count = 11, 140 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 141 .svc_to_ce_map_len = 19, 142 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 143 .single_pdev_only = false, 144 .rxdma1_enable = true, 145 .num_rxmda_per_pdev = 1, 146 .rx_mac_buf_ring = false, 147 .vdev_start_delay = false, 148 .htt_peer_map_v2 = true, 149 150 .spectral = { 151 .fft_sz = 4, 152 .fft_pad_sz = 0, 153 .summary_pad_sz = 0, 154 .fft_hdr_len = 16, 155 .max_fft_bins = 512, 156 .fragment_160mhz = true, 157 }, 158 159 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 160 BIT(NL80211_IFTYPE_AP) | 161 BIT(NL80211_IFTYPE_MESH_POINT), 162 .supports_monitor = true, 163 .full_monitor_mode = false, 164 .supports_shadow_regs = false, 165 .idle_ps = false, 166 .supports_sta_ps = false, 167 .cold_boot_calib = true, 168 .cbcal_restart_fw = true, 169 .fw_mem_mode = 0, 170 .num_vdevs = 16 + 1, 171 .num_peers = 512, 172 .supports_suspend = false, 173 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 174 .supports_regdb = false, 175 .fix_l1ss = true, 176 .credit_flow = false, 177 .max_tx_ring = DP_TCL_NUM_RING_MAX, 178 .hal_params = &ath11k_hw_hal_params_ipq8074, 179 .supports_dynamic_smps_6ghz = false, 180 .alloc_cacheable_memory = true, 181 .supports_rssi_stats = false, 182 .fw_wmi_diag_event = false, 183 .current_cc_support = false, 184 .dbr_debug_support = true, 185 .global_reset = false, 186 .bios_sar_capa = NULL, 187 .m3_fw_support = false, 188 .fixed_bdf_addr = true, 189 .fixed_mem_region = true, 190 .static_window_map = false, 191 .hybrid_bus_type = false, 192 .fixed_fw_mem = false, 193 .support_off_channel_tx = false, 194 .supports_multi_bssid = false, 195 196 .sram_dump = {}, 197 198 .tcl_ring_retry = true, 199 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 200 .smp2p_wow_exit = false, 201 .support_fw_mac_sequence = false, 202 .ftm_responder = true, 203 }, 204 { 205 .name = "qca6390 hw2.0", 206 .hw_rev = ATH11K_HW_QCA6390_HW20, 207 .fw = { 208 .dir = "QCA6390/hw2.0", 209 .board_size = 256 * 1024, 210 .cal_offset = 128 * 1024, 211 }, 212 .max_radios = 3, 213 .bdf_addr = 0x4B0C0000, 214 .hw_ops = &qca6390_ops, 215 .ring_mask = &ath11k_hw_ring_mask_qca6390, 216 .internal_sleep_clock = true, 217 .regs = &qca6390_regs, 218 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 219 .host_ce_config = ath11k_host_ce_config_qca6390, 220 .ce_count = 9, 221 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 222 .target_ce_count = 9, 223 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 224 .svc_to_ce_map_len = 14, 225 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 226 .single_pdev_only = true, 227 .rxdma1_enable = false, 228 .num_rxmda_per_pdev = 2, 229 .rx_mac_buf_ring = true, 230 .vdev_start_delay = true, 231 .htt_peer_map_v2 = false, 232 233 .spectral = { 234 .fft_sz = 0, 235 .fft_pad_sz = 0, 236 .summary_pad_sz = 0, 237 .fft_hdr_len = 0, 238 .max_fft_bins = 0, 239 .fragment_160mhz = false, 240 }, 241 242 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 243 BIT(NL80211_IFTYPE_AP), 244 .supports_monitor = false, 245 .full_monitor_mode = false, 246 .supports_shadow_regs = true, 247 .idle_ps = true, 248 .supports_sta_ps = true, 249 .cold_boot_calib = false, 250 .cbcal_restart_fw = false, 251 .fw_mem_mode = 0, 252 .num_vdevs = 16 + 1, 253 .num_peers = 512, 254 .supports_suspend = true, 255 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 256 .supports_regdb = false, 257 .fix_l1ss = true, 258 .credit_flow = true, 259 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 260 .hal_params = &ath11k_hw_hal_params_qca6390, 261 .supports_dynamic_smps_6ghz = false, 262 .alloc_cacheable_memory = false, 263 .supports_rssi_stats = true, 264 .fw_wmi_diag_event = true, 265 .current_cc_support = true, 266 .dbr_debug_support = false, 267 .global_reset = true, 268 .bios_sar_capa = NULL, 269 .m3_fw_support = true, 270 .fixed_bdf_addr = false, 271 .fixed_mem_region = false, 272 .static_window_map = false, 273 .hybrid_bus_type = false, 274 .fixed_fw_mem = false, 275 .support_off_channel_tx = true, 276 .supports_multi_bssid = true, 277 278 .sram_dump = { 279 .start = 0x01400000, 280 .end = 0x0171ffff, 281 }, 282 283 .tcl_ring_retry = true, 284 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 285 .smp2p_wow_exit = false, 286 .support_fw_mac_sequence = true, 287 .ftm_responder = false, 288 }, 289 { 290 .name = "qcn9074 hw1.0", 291 .hw_rev = ATH11K_HW_QCN9074_HW10, 292 .fw = { 293 .dir = "QCN9074/hw1.0", 294 .board_size = 256 * 1024, 295 .cal_offset = 128 * 1024, 296 }, 297 .max_radios = 1, 298 .single_pdev_only = false, 299 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 300 .hw_ops = &qcn9074_ops, 301 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 302 .internal_sleep_clock = false, 303 .regs = &qcn9074_regs, 304 .host_ce_config = ath11k_host_ce_config_qcn9074, 305 .ce_count = 6, 306 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 307 .target_ce_count = 9, 308 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 309 .svc_to_ce_map_len = 18, 310 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 311 .rxdma1_enable = true, 312 .num_rxmda_per_pdev = 1, 313 .rx_mac_buf_ring = false, 314 .vdev_start_delay = false, 315 .htt_peer_map_v2 = true, 316 317 .spectral = { 318 .fft_sz = 2, 319 .fft_pad_sz = 0, 320 .summary_pad_sz = 16, 321 .fft_hdr_len = 24, 322 .max_fft_bins = 1024, 323 .fragment_160mhz = false, 324 }, 325 326 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 327 BIT(NL80211_IFTYPE_AP) | 328 BIT(NL80211_IFTYPE_MESH_POINT), 329 .supports_monitor = true, 330 .full_monitor_mode = true, 331 .supports_shadow_regs = false, 332 .idle_ps = false, 333 .supports_sta_ps = false, 334 .cold_boot_calib = false, 335 .cbcal_restart_fw = false, 336 .fw_mem_mode = 2, 337 .num_vdevs = 8, 338 .num_peers = 128, 339 .supports_suspend = false, 340 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 341 .supports_regdb = false, 342 .fix_l1ss = true, 343 .credit_flow = false, 344 .max_tx_ring = DP_TCL_NUM_RING_MAX, 345 .hal_params = &ath11k_hw_hal_params_ipq8074, 346 .supports_dynamic_smps_6ghz = true, 347 .alloc_cacheable_memory = true, 348 .supports_rssi_stats = false, 349 .fw_wmi_diag_event = false, 350 .current_cc_support = false, 351 .dbr_debug_support = true, 352 .global_reset = false, 353 .bios_sar_capa = NULL, 354 .m3_fw_support = true, 355 .fixed_bdf_addr = false, 356 .fixed_mem_region = false, 357 .static_window_map = true, 358 .hybrid_bus_type = false, 359 .fixed_fw_mem = false, 360 .support_off_channel_tx = false, 361 .supports_multi_bssid = false, 362 363 .sram_dump = {}, 364 365 .tcl_ring_retry = true, 366 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 367 .smp2p_wow_exit = false, 368 .support_fw_mac_sequence = false, 369 .ftm_responder = true, 370 }, 371 { 372 .name = "wcn6855 hw2.0", 373 .hw_rev = ATH11K_HW_WCN6855_HW20, 374 .fw = { 375 .dir = "WCN6855/hw2.0", 376 .board_size = 256 * 1024, 377 .cal_offset = 128 * 1024, 378 }, 379 .max_radios = 3, 380 .bdf_addr = 0x4B0C0000, 381 .hw_ops = &wcn6855_ops, 382 .ring_mask = &ath11k_hw_ring_mask_qca6390, 383 .internal_sleep_clock = true, 384 .regs = &wcn6855_regs, 385 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 386 .host_ce_config = ath11k_host_ce_config_qca6390, 387 .ce_count = 9, 388 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 389 .target_ce_count = 9, 390 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 391 .svc_to_ce_map_len = 14, 392 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 393 .single_pdev_only = true, 394 .rxdma1_enable = false, 395 .num_rxmda_per_pdev = 2, 396 .rx_mac_buf_ring = true, 397 .vdev_start_delay = true, 398 .htt_peer_map_v2 = false, 399 400 .spectral = { 401 .fft_sz = 0, 402 .fft_pad_sz = 0, 403 .summary_pad_sz = 0, 404 .fft_hdr_len = 0, 405 .max_fft_bins = 0, 406 .fragment_160mhz = false, 407 }, 408 409 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 410 BIT(NL80211_IFTYPE_AP), 411 .supports_monitor = false, 412 .full_monitor_mode = false, 413 .supports_shadow_regs = true, 414 .idle_ps = true, 415 .supports_sta_ps = true, 416 .cold_boot_calib = false, 417 .cbcal_restart_fw = false, 418 .fw_mem_mode = 0, 419 .num_vdevs = 16 + 1, 420 .num_peers = 512, 421 .supports_suspend = true, 422 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 423 .supports_regdb = true, 424 .fix_l1ss = false, 425 .credit_flow = true, 426 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 427 .hal_params = &ath11k_hw_hal_params_qca6390, 428 .supports_dynamic_smps_6ghz = false, 429 .alloc_cacheable_memory = false, 430 .supports_rssi_stats = true, 431 .fw_wmi_diag_event = true, 432 .current_cc_support = true, 433 .dbr_debug_support = false, 434 .global_reset = true, 435 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 436 .m3_fw_support = true, 437 .fixed_bdf_addr = false, 438 .fixed_mem_region = false, 439 .static_window_map = false, 440 .hybrid_bus_type = false, 441 .fixed_fw_mem = false, 442 .support_off_channel_tx = true, 443 .supports_multi_bssid = true, 444 445 .sram_dump = { 446 .start = 0x01400000, 447 .end = 0x0177ffff, 448 }, 449 450 .tcl_ring_retry = true, 451 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 452 .smp2p_wow_exit = false, 453 .support_fw_mac_sequence = true, 454 .ftm_responder = false, 455 }, 456 { 457 .name = "wcn6855 hw2.1", 458 .hw_rev = ATH11K_HW_WCN6855_HW21, 459 .fw = { 460 .dir = "WCN6855/hw2.1", 461 .board_size = 256 * 1024, 462 .cal_offset = 128 * 1024, 463 }, 464 .max_radios = 3, 465 .bdf_addr = 0x4B0C0000, 466 .hw_ops = &wcn6855_ops, 467 .ring_mask = &ath11k_hw_ring_mask_qca6390, 468 .internal_sleep_clock = true, 469 .regs = &wcn6855_regs, 470 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 471 .host_ce_config = ath11k_host_ce_config_qca6390, 472 .ce_count = 9, 473 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 474 .target_ce_count = 9, 475 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 476 .svc_to_ce_map_len = 14, 477 .single_pdev_only = true, 478 .rxdma1_enable = false, 479 .num_rxmda_per_pdev = 2, 480 .rx_mac_buf_ring = true, 481 .vdev_start_delay = true, 482 .htt_peer_map_v2 = false, 483 484 .spectral = { 485 .fft_sz = 0, 486 .fft_pad_sz = 0, 487 .summary_pad_sz = 0, 488 .fft_hdr_len = 0, 489 .max_fft_bins = 0, 490 .fragment_160mhz = false, 491 }, 492 493 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 494 BIT(NL80211_IFTYPE_AP), 495 .supports_monitor = false, 496 .supports_shadow_regs = true, 497 .idle_ps = true, 498 .supports_sta_ps = true, 499 .cold_boot_calib = false, 500 .cbcal_restart_fw = false, 501 .fw_mem_mode = 0, 502 .num_vdevs = 16 + 1, 503 .num_peers = 512, 504 .supports_suspend = true, 505 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 506 .supports_regdb = true, 507 .fix_l1ss = false, 508 .credit_flow = true, 509 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 510 .hal_params = &ath11k_hw_hal_params_qca6390, 511 .supports_dynamic_smps_6ghz = false, 512 .alloc_cacheable_memory = false, 513 .supports_rssi_stats = true, 514 .fw_wmi_diag_event = true, 515 .current_cc_support = true, 516 .dbr_debug_support = false, 517 .global_reset = true, 518 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 519 .m3_fw_support = true, 520 .fixed_bdf_addr = false, 521 .fixed_mem_region = false, 522 .static_window_map = false, 523 .hybrid_bus_type = false, 524 .fixed_fw_mem = false, 525 .support_off_channel_tx = true, 526 .supports_multi_bssid = true, 527 528 .sram_dump = { 529 .start = 0x01400000, 530 .end = 0x0177ffff, 531 }, 532 533 .tcl_ring_retry = true, 534 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 535 .smp2p_wow_exit = false, 536 .support_fw_mac_sequence = true, 537 .ftm_responder = false, 538 }, 539 { 540 .name = "wcn6750 hw1.0", 541 .hw_rev = ATH11K_HW_WCN6750_HW10, 542 .fw = { 543 .dir = "WCN6750/hw1.0", 544 .board_size = 256 * 1024, 545 .cal_offset = 128 * 1024, 546 }, 547 .max_radios = 1, 548 .bdf_addr = 0x4B0C0000, 549 .hw_ops = &wcn6750_ops, 550 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 551 .internal_sleep_clock = false, 552 .regs = &wcn6750_regs, 553 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 554 .host_ce_config = ath11k_host_ce_config_qca6390, 555 .ce_count = 9, 556 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 557 .target_ce_count = 9, 558 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 559 .svc_to_ce_map_len = 14, 560 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 561 .single_pdev_only = true, 562 .rxdma1_enable = false, 563 .num_rxmda_per_pdev = 1, 564 .rx_mac_buf_ring = true, 565 .vdev_start_delay = true, 566 .htt_peer_map_v2 = false, 567 568 .spectral = { 569 .fft_sz = 0, 570 .fft_pad_sz = 0, 571 .summary_pad_sz = 0, 572 .fft_hdr_len = 0, 573 .max_fft_bins = 0, 574 .fragment_160mhz = false, 575 }, 576 577 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 578 BIT(NL80211_IFTYPE_AP), 579 .supports_monitor = false, 580 .supports_shadow_regs = true, 581 .idle_ps = true, 582 .supports_sta_ps = true, 583 .cold_boot_calib = true, 584 .cbcal_restart_fw = false, 585 .fw_mem_mode = 0, 586 .num_vdevs = 16 + 1, 587 .num_peers = 512, 588 .supports_suspend = false, 589 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 590 .supports_regdb = true, 591 .fix_l1ss = false, 592 .credit_flow = true, 593 .max_tx_ring = DP_TCL_NUM_RING_MAX, 594 .hal_params = &ath11k_hw_hal_params_wcn6750, 595 .supports_dynamic_smps_6ghz = false, 596 .alloc_cacheable_memory = false, 597 .supports_rssi_stats = true, 598 .fw_wmi_diag_event = false, 599 .current_cc_support = true, 600 .dbr_debug_support = false, 601 .global_reset = false, 602 .bios_sar_capa = NULL, 603 .m3_fw_support = false, 604 .fixed_bdf_addr = false, 605 .fixed_mem_region = false, 606 .static_window_map = true, 607 .hybrid_bus_type = true, 608 .fixed_fw_mem = true, 609 .support_off_channel_tx = true, 610 .supports_multi_bssid = true, 611 612 .sram_dump = {}, 613 614 .tcl_ring_retry = false, 615 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 616 .smp2p_wow_exit = true, 617 .support_fw_mac_sequence = true, 618 .ftm_responder = false, 619 }, 620 { 621 .hw_rev = ATH11K_HW_IPQ5018_HW10, 622 .name = "ipq5018 hw1.0", 623 .fw = { 624 .dir = "IPQ5018/hw1.0", 625 .board_size = 256 * 1024, 626 .cal_offset = 128 * 1024, 627 }, 628 .max_radios = MAX_RADIOS_5018, 629 .bdf_addr = 0x4BA00000, 630 /* hal_desc_sz and hw ops are similar to qcn9074 */ 631 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 632 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 633 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 634 .credit_flow = false, 635 .max_tx_ring = 1, 636 .spectral = { 637 .fft_sz = 2, 638 .fft_pad_sz = 0, 639 .summary_pad_sz = 16, 640 .fft_hdr_len = 24, 641 .max_fft_bins = 1024, 642 }, 643 .internal_sleep_clock = false, 644 .regs = &ipq5018_regs, 645 .hw_ops = &ipq5018_ops, 646 .host_ce_config = ath11k_host_ce_config_qcn9074, 647 .ce_count = CE_CNT_5018, 648 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 649 .target_ce_count = TARGET_CE_CNT_5018, 650 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 651 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 652 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 653 .ce_remap = &ath11k_ce_remap_ipq5018, 654 .rxdma1_enable = true, 655 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, 656 .rx_mac_buf_ring = false, 657 .vdev_start_delay = false, 658 .htt_peer_map_v2 = true, 659 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 660 BIT(NL80211_IFTYPE_AP) | 661 BIT(NL80211_IFTYPE_MESH_POINT), 662 .supports_monitor = false, 663 .supports_sta_ps = false, 664 .supports_shadow_regs = false, 665 .fw_mem_mode = 0, 666 .num_vdevs = 16 + 1, 667 .num_peers = 512, 668 .supports_regdb = false, 669 .idle_ps = false, 670 .supports_suspend = false, 671 .hal_params = &ath11k_hw_hal_params_ipq8074, 672 .single_pdev_only = false, 673 .cold_boot_calib = true, 674 .fix_l1ss = true, 675 .supports_dynamic_smps_6ghz = false, 676 .alloc_cacheable_memory = true, 677 .supports_rssi_stats = false, 678 .fw_wmi_diag_event = false, 679 .current_cc_support = false, 680 .dbr_debug_support = true, 681 .global_reset = false, 682 .bios_sar_capa = NULL, 683 .m3_fw_support = false, 684 .fixed_bdf_addr = true, 685 .fixed_mem_region = true, 686 .static_window_map = false, 687 .hybrid_bus_type = false, 688 .fixed_fw_mem = false, 689 .support_off_channel_tx = false, 690 .supports_multi_bssid = false, 691 692 .sram_dump = {}, 693 694 .tcl_ring_retry = true, 695 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 696 .smp2p_wow_exit = false, 697 .support_fw_mac_sequence = false, 698 .ftm_responder = true, 699 }, 700 }; 701 702 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 703 { 704 WARN_ON(!ab->hw_params.single_pdev_only); 705 706 return &ab->pdevs[0]; 707 } 708 709 void ath11k_fw_stats_pdevs_free(struct list_head *head) 710 { 711 struct ath11k_fw_stats_pdev *i, *tmp; 712 713 list_for_each_entry_safe(i, tmp, head, list) { 714 list_del(&i->list); 715 kfree(i); 716 } 717 } 718 719 void ath11k_fw_stats_vdevs_free(struct list_head *head) 720 { 721 struct ath11k_fw_stats_vdev *i, *tmp; 722 723 list_for_each_entry_safe(i, tmp, head, list) { 724 list_del(&i->list); 725 kfree(i); 726 } 727 } 728 729 void ath11k_fw_stats_bcn_free(struct list_head *head) 730 { 731 struct ath11k_fw_stats_bcn *i, *tmp; 732 733 list_for_each_entry_safe(i, tmp, head, list) { 734 list_del(&i->list); 735 kfree(i); 736 } 737 } 738 739 void ath11k_fw_stats_init(struct ath11k *ar) 740 { 741 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 742 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 743 INIT_LIST_HEAD(&ar->fw_stats.bcn); 744 745 init_completion(&ar->fw_stats_complete); 746 } 747 748 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 749 { 750 ath11k_fw_stats_pdevs_free(&stats->pdevs); 751 ath11k_fw_stats_vdevs_free(&stats->vdevs); 752 ath11k_fw_stats_bcn_free(&stats->bcn); 753 } 754 755 int ath11k_core_suspend(struct ath11k_base *ab) 756 { 757 int ret; 758 struct ath11k_pdev *pdev; 759 struct ath11k *ar; 760 761 if (!ab->hw_params.supports_suspend) 762 return -EOPNOTSUPP; 763 764 /* so far single_pdev_only chips have supports_suspend as true 765 * and only the first pdev is valid. 766 */ 767 pdev = ath11k_core_get_single_pdev(ab); 768 ar = pdev->ar; 769 if (!ar || ar->state != ATH11K_STATE_OFF) 770 return 0; 771 772 ret = ath11k_dp_rx_pktlog_stop(ab, true); 773 if (ret) { 774 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 775 ret); 776 return ret; 777 } 778 779 ret = ath11k_mac_wait_tx_complete(ar); 780 if (ret) { 781 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 782 return ret; 783 } 784 785 ret = ath11k_wow_enable(ab); 786 if (ret) { 787 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 788 return ret; 789 } 790 791 ret = ath11k_dp_rx_pktlog_stop(ab, false); 792 if (ret) { 793 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 794 ret); 795 return ret; 796 } 797 798 ath11k_ce_stop_shadow_timers(ab); 799 ath11k_dp_stop_shadow_timers(ab); 800 801 ath11k_hif_irq_disable(ab); 802 ath11k_hif_ce_irq_disable(ab); 803 804 ret = ath11k_hif_suspend(ab); 805 if (ret) { 806 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 807 return ret; 808 } 809 810 return 0; 811 } 812 EXPORT_SYMBOL(ath11k_core_suspend); 813 814 int ath11k_core_resume(struct ath11k_base *ab) 815 { 816 int ret; 817 struct ath11k_pdev *pdev; 818 struct ath11k *ar; 819 820 if (!ab->hw_params.supports_suspend) 821 return -EOPNOTSUPP; 822 823 /* so far signle_pdev_only chips have supports_suspend as true 824 * and only the first pdev is valid. 825 */ 826 pdev = ath11k_core_get_single_pdev(ab); 827 ar = pdev->ar; 828 if (!ar || ar->state != ATH11K_STATE_OFF) 829 return 0; 830 831 ret = ath11k_hif_resume(ab); 832 if (ret) { 833 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 834 return ret; 835 } 836 837 ath11k_hif_ce_irq_enable(ab); 838 ath11k_hif_irq_enable(ab); 839 840 ret = ath11k_dp_rx_pktlog_start(ab); 841 if (ret) { 842 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 843 ret); 844 return ret; 845 } 846 847 ret = ath11k_wow_wakeup(ab); 848 if (ret) { 849 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 850 return ret; 851 } 852 853 return 0; 854 } 855 EXPORT_SYMBOL(ath11k_core_resume); 856 857 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 858 { 859 struct ath11k_base *ab = data; 860 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 861 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 862 ssize_t copied; 863 size_t len; 864 int i; 865 866 if (ab->qmi.target.bdf_ext[0] != '\0') 867 return; 868 869 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 870 return; 871 872 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 873 ath11k_dbg(ab, ATH11K_DBG_BOOT, 874 "wrong smbios bdf ext type length (%d).\n", 875 hdr->length); 876 return; 877 } 878 879 spin_lock_bh(&ab->base_lock); 880 881 switch (smbios->country_code_flag) { 882 case ATH11K_SMBIOS_CC_ISO: 883 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 884 ab->new_alpha2[1] = smbios->cc_code & 0xff; 885 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios cc_code %c%c\n", 886 ab->new_alpha2[0], ab->new_alpha2[1]); 887 break; 888 case ATH11K_SMBIOS_CC_WW: 889 ab->new_alpha2[0] = '0'; 890 ab->new_alpha2[1] = '0'; 891 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot smbios worldwide regdomain\n"); 892 break; 893 default: 894 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot ignore smbios country code setting %d\n", 895 smbios->country_code_flag); 896 break; 897 } 898 899 spin_unlock_bh(&ab->base_lock); 900 901 if (!smbios->bdf_enabled) { 902 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 903 return; 904 } 905 906 /* Only one string exists (per spec) */ 907 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 908 ath11k_dbg(ab, ATH11K_DBG_BOOT, 909 "bdf variant magic does not match.\n"); 910 return; 911 } 912 913 len = min_t(size_t, 914 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 915 for (i = 0; i < len; i++) { 916 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 917 ath11k_dbg(ab, ATH11K_DBG_BOOT, 918 "bdf variant name contains non ascii chars.\n"); 919 return; 920 } 921 } 922 923 /* Copy extension name without magic prefix */ 924 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 925 sizeof(ab->qmi.target.bdf_ext)); 926 if (copied < 0) { 927 ath11k_dbg(ab, ATH11K_DBG_BOOT, 928 "bdf variant string is longer than the buffer can accommodate\n"); 929 return; 930 } 931 932 ath11k_dbg(ab, ATH11K_DBG_BOOT, 933 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 934 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 935 } 936 937 int ath11k_core_check_smbios(struct ath11k_base *ab) 938 { 939 ab->qmi.target.bdf_ext[0] = '\0'; 940 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 941 942 if (ab->qmi.target.bdf_ext[0] == '\0') 943 return -ENODATA; 944 945 return 0; 946 } 947 948 int ath11k_core_check_dt(struct ath11k_base *ab) 949 { 950 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 951 const char *variant = NULL; 952 struct device_node *node; 953 954 node = ab->dev->of_node; 955 if (!node) 956 return -ENOENT; 957 958 of_property_read_string(node, "qcom,ath11k-calibration-variant", 959 &variant); 960 if (!variant) 961 return -ENODATA; 962 963 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 964 ath11k_dbg(ab, ATH11K_DBG_BOOT, 965 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 966 variant); 967 968 return 0; 969 } 970 971 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 972 size_t name_len, bool with_variant) 973 { 974 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 975 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 976 977 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 978 scnprintf(variant, sizeof(variant), ",variant=%s", 979 ab->qmi.target.bdf_ext); 980 981 switch (ab->id.bdf_search) { 982 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 983 scnprintf(name, name_len, 984 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 985 ath11k_bus_str(ab->hif.bus), 986 ab->id.vendor, ab->id.device, 987 ab->id.subsystem_vendor, 988 ab->id.subsystem_device, 989 ab->qmi.target.chip_id, 990 ab->qmi.target.board_id, 991 variant); 992 break; 993 default: 994 scnprintf(name, name_len, 995 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 996 ath11k_bus_str(ab->hif.bus), 997 ab->qmi.target.chip_id, 998 ab->qmi.target.board_id, variant); 999 break; 1000 } 1001 1002 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot using board name '%s'\n", name); 1003 1004 return 0; 1005 } 1006 1007 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1008 size_t name_len) 1009 { 1010 return __ath11k_core_create_board_name(ab, name, name_len, true); 1011 } 1012 1013 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1014 size_t name_len) 1015 { 1016 return __ath11k_core_create_board_name(ab, name, name_len, false); 1017 } 1018 1019 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1020 const char *file) 1021 { 1022 const struct firmware *fw; 1023 char path[100]; 1024 int ret; 1025 1026 if (file == NULL) 1027 return ERR_PTR(-ENOENT); 1028 1029 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1030 1031 ret = firmware_request_nowarn(&fw, path, ab->dev); 1032 if (ret) 1033 return ERR_PTR(ret); 1034 1035 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot firmware request %s size %zu\n", 1036 path, fw->size); 1037 1038 return fw; 1039 } 1040 1041 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1042 { 1043 if (!IS_ERR(bd->fw)) 1044 release_firmware(bd->fw); 1045 1046 memset(bd, 0, sizeof(*bd)); 1047 } 1048 1049 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1050 struct ath11k_board_data *bd, 1051 const void *buf, size_t buf_len, 1052 const char *boardname, 1053 int ie_id, 1054 int name_id, 1055 int data_id) 1056 { 1057 const struct ath11k_fw_ie *hdr; 1058 bool name_match_found; 1059 int ret, board_ie_id; 1060 size_t board_ie_len; 1061 const void *board_ie_data; 1062 1063 name_match_found = false; 1064 1065 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1066 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1067 hdr = buf; 1068 board_ie_id = le32_to_cpu(hdr->id); 1069 board_ie_len = le32_to_cpu(hdr->len); 1070 board_ie_data = hdr->data; 1071 1072 buf_len -= sizeof(*hdr); 1073 buf += sizeof(*hdr); 1074 1075 if (buf_len < ALIGN(board_ie_len, 4)) { 1076 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1077 ath11k_bd_ie_type_str(ie_id), 1078 buf_len, ALIGN(board_ie_len, 4)); 1079 ret = -EINVAL; 1080 goto out; 1081 } 1082 1083 if (board_ie_id == name_id) { 1084 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1085 board_ie_data, board_ie_len); 1086 1087 if (board_ie_len != strlen(boardname)) 1088 goto next; 1089 1090 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1091 if (ret) 1092 goto next; 1093 1094 name_match_found = true; 1095 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1096 "boot found match %s for name '%s'", 1097 ath11k_bd_ie_type_str(ie_id), 1098 boardname); 1099 } else if (board_ie_id == data_id) { 1100 if (!name_match_found) 1101 /* no match found */ 1102 goto next; 1103 1104 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1105 "boot found %s for '%s'", 1106 ath11k_bd_ie_type_str(ie_id), 1107 boardname); 1108 1109 bd->data = board_ie_data; 1110 bd->len = board_ie_len; 1111 1112 ret = 0; 1113 goto out; 1114 } else { 1115 ath11k_warn(ab, "unknown %s id found: %d\n", 1116 ath11k_bd_ie_type_str(ie_id), 1117 board_ie_id); 1118 } 1119 next: 1120 /* jump over the padding */ 1121 board_ie_len = ALIGN(board_ie_len, 4); 1122 1123 buf_len -= board_ie_len; 1124 buf += board_ie_len; 1125 } 1126 1127 /* no match found */ 1128 ret = -ENOENT; 1129 1130 out: 1131 return ret; 1132 } 1133 1134 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1135 struct ath11k_board_data *bd, 1136 const char *boardname, 1137 int ie_id_match, 1138 int name_id, 1139 int data_id) 1140 { 1141 size_t len, magic_len; 1142 const u8 *data; 1143 char *filename, filepath[100]; 1144 size_t ie_len; 1145 struct ath11k_fw_ie *hdr; 1146 int ret, ie_id; 1147 1148 filename = ATH11K_BOARD_API2_FILE; 1149 1150 if (!bd->fw) 1151 bd->fw = ath11k_core_firmware_request(ab, filename); 1152 1153 if (IS_ERR(bd->fw)) 1154 return PTR_ERR(bd->fw); 1155 1156 data = bd->fw->data; 1157 len = bd->fw->size; 1158 1159 ath11k_core_create_firmware_path(ab, filename, 1160 filepath, sizeof(filepath)); 1161 1162 /* magic has extra null byte padded */ 1163 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1164 if (len < magic_len) { 1165 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1166 filepath, len); 1167 ret = -EINVAL; 1168 goto err; 1169 } 1170 1171 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1172 ath11k_err(ab, "found invalid board magic\n"); 1173 ret = -EINVAL; 1174 goto err; 1175 } 1176 1177 /* magic is padded to 4 bytes */ 1178 magic_len = ALIGN(magic_len, 4); 1179 if (len < magic_len) { 1180 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1181 filepath, len); 1182 ret = -EINVAL; 1183 goto err; 1184 } 1185 1186 data += magic_len; 1187 len -= magic_len; 1188 1189 while (len > sizeof(struct ath11k_fw_ie)) { 1190 hdr = (struct ath11k_fw_ie *)data; 1191 ie_id = le32_to_cpu(hdr->id); 1192 ie_len = le32_to_cpu(hdr->len); 1193 1194 len -= sizeof(*hdr); 1195 data = hdr->data; 1196 1197 if (len < ALIGN(ie_len, 4)) { 1198 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1199 ie_id, ie_len, len); 1200 ret = -EINVAL; 1201 goto err; 1202 } 1203 1204 if (ie_id == ie_id_match) { 1205 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1206 ie_len, 1207 boardname, 1208 ie_id_match, 1209 name_id, 1210 data_id); 1211 if (ret == -ENOENT) 1212 /* no match found, continue */ 1213 goto next; 1214 else if (ret) 1215 /* there was an error, bail out */ 1216 goto err; 1217 /* either found or error, so stop searching */ 1218 goto out; 1219 } 1220 next: 1221 /* jump over the padding */ 1222 ie_len = ALIGN(ie_len, 4); 1223 1224 len -= ie_len; 1225 data += ie_len; 1226 } 1227 1228 out: 1229 if (!bd->data || !bd->len) { 1230 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1231 "failed to fetch %s for %s from %s\n", 1232 ath11k_bd_ie_type_str(ie_id_match), 1233 boardname, filepath); 1234 ret = -ENODATA; 1235 goto err; 1236 } 1237 1238 return 0; 1239 1240 err: 1241 ath11k_core_free_bdf(ab, bd); 1242 return ret; 1243 } 1244 1245 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1246 struct ath11k_board_data *bd, 1247 const char *name) 1248 { 1249 bd->fw = ath11k_core_firmware_request(ab, name); 1250 1251 if (IS_ERR(bd->fw)) 1252 return PTR_ERR(bd->fw); 1253 1254 bd->data = bd->fw->data; 1255 bd->len = bd->fw->size; 1256 1257 return 0; 1258 } 1259 1260 #define BOARD_NAME_SIZE 200 1261 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1262 { 1263 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1264 char *filename, filepath[100]; 1265 int ret; 1266 1267 filename = ATH11K_BOARD_API2_FILE; 1268 1269 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1270 if (ret) { 1271 ath11k_err(ab, "failed to create board name: %d", ret); 1272 return ret; 1273 } 1274 1275 ab->bd_api = 2; 1276 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1277 ATH11K_BD_IE_BOARD, 1278 ATH11K_BD_IE_BOARD_NAME, 1279 ATH11K_BD_IE_BOARD_DATA); 1280 if (!ret) 1281 goto success; 1282 1283 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1284 sizeof(fallback_boardname)); 1285 if (ret) { 1286 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1287 return ret; 1288 } 1289 1290 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1291 ATH11K_BD_IE_BOARD, 1292 ATH11K_BD_IE_BOARD_NAME, 1293 ATH11K_BD_IE_BOARD_DATA); 1294 if (!ret) 1295 goto success; 1296 1297 ab->bd_api = 1; 1298 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1299 if (ret) { 1300 ath11k_core_create_firmware_path(ab, filename, 1301 filepath, sizeof(filepath)); 1302 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1303 boardname, filepath); 1304 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1305 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1306 fallback_boardname, filepath); 1307 1308 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1309 ab->hw_params.fw.dir); 1310 return ret; 1311 } 1312 1313 success: 1314 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1315 return 0; 1316 } 1317 1318 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1319 { 1320 char boardname[BOARD_NAME_SIZE]; 1321 int ret; 1322 1323 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1324 if (ret) { 1325 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1326 "failed to create board name for regdb: %d", ret); 1327 goto exit; 1328 } 1329 1330 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1331 ATH11K_BD_IE_REGDB, 1332 ATH11K_BD_IE_REGDB_NAME, 1333 ATH11K_BD_IE_REGDB_DATA); 1334 if (!ret) 1335 goto exit; 1336 1337 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1338 if (ret) 1339 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1340 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1341 1342 exit: 1343 if (!ret) 1344 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1345 1346 return ret; 1347 } 1348 1349 static void ath11k_core_stop(struct ath11k_base *ab) 1350 { 1351 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1352 ath11k_qmi_firmware_stop(ab); 1353 1354 ath11k_hif_stop(ab); 1355 ath11k_wmi_detach(ab); 1356 ath11k_dp_pdev_reo_cleanup(ab); 1357 1358 /* De-Init of components as needed */ 1359 } 1360 1361 static int ath11k_core_soc_create(struct ath11k_base *ab) 1362 { 1363 int ret; 1364 1365 ret = ath11k_qmi_init_service(ab); 1366 if (ret) { 1367 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1368 return ret; 1369 } 1370 1371 ret = ath11k_debugfs_soc_create(ab); 1372 if (ret) { 1373 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1374 goto err_qmi_deinit; 1375 } 1376 1377 ret = ath11k_hif_power_up(ab); 1378 if (ret) { 1379 ath11k_err(ab, "failed to power up :%d\n", ret); 1380 goto err_debugfs_reg; 1381 } 1382 1383 return 0; 1384 1385 err_debugfs_reg: 1386 ath11k_debugfs_soc_destroy(ab); 1387 err_qmi_deinit: 1388 ath11k_qmi_deinit_service(ab); 1389 return ret; 1390 } 1391 1392 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1393 { 1394 ath11k_debugfs_soc_destroy(ab); 1395 ath11k_dp_free(ab); 1396 ath11k_reg_free(ab); 1397 ath11k_qmi_deinit_service(ab); 1398 } 1399 1400 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1401 { 1402 int ret; 1403 1404 ret = ath11k_debugfs_pdev_create(ab); 1405 if (ret) { 1406 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1407 return ret; 1408 } 1409 1410 ret = ath11k_dp_pdev_alloc(ab); 1411 if (ret) { 1412 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1413 goto err_pdev_debug; 1414 } 1415 1416 ret = ath11k_mac_register(ab); 1417 if (ret) { 1418 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1419 goto err_dp_pdev_free; 1420 } 1421 1422 ret = ath11k_thermal_register(ab); 1423 if (ret) { 1424 ath11k_err(ab, "could not register thermal device: %d\n", 1425 ret); 1426 goto err_mac_unregister; 1427 } 1428 1429 ret = ath11k_spectral_init(ab); 1430 if (ret) { 1431 ath11k_err(ab, "failed to init spectral %d\n", ret); 1432 goto err_thermal_unregister; 1433 } 1434 1435 return 0; 1436 1437 err_thermal_unregister: 1438 ath11k_thermal_unregister(ab); 1439 err_mac_unregister: 1440 ath11k_mac_unregister(ab); 1441 err_dp_pdev_free: 1442 ath11k_dp_pdev_free(ab); 1443 err_pdev_debug: 1444 ath11k_debugfs_pdev_destroy(ab); 1445 1446 return ret; 1447 } 1448 1449 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1450 { 1451 ath11k_spectral_deinit(ab); 1452 ath11k_thermal_unregister(ab); 1453 ath11k_mac_unregister(ab); 1454 ath11k_hif_irq_disable(ab); 1455 ath11k_dp_pdev_free(ab); 1456 ath11k_debugfs_pdev_destroy(ab); 1457 } 1458 1459 static int ath11k_core_start(struct ath11k_base *ab) 1460 { 1461 int ret; 1462 1463 ret = ath11k_wmi_attach(ab); 1464 if (ret) { 1465 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1466 return ret; 1467 } 1468 1469 ret = ath11k_htc_init(ab); 1470 if (ret) { 1471 ath11k_err(ab, "failed to init htc: %d\n", ret); 1472 goto err_wmi_detach; 1473 } 1474 1475 ret = ath11k_hif_start(ab); 1476 if (ret) { 1477 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1478 goto err_wmi_detach; 1479 } 1480 1481 ret = ath11k_htc_wait_target(&ab->htc); 1482 if (ret) { 1483 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1484 goto err_hif_stop; 1485 } 1486 1487 ret = ath11k_dp_htt_connect(&ab->dp); 1488 if (ret) { 1489 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1490 goto err_hif_stop; 1491 } 1492 1493 ret = ath11k_wmi_connect(ab); 1494 if (ret) { 1495 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1496 goto err_hif_stop; 1497 } 1498 1499 ret = ath11k_htc_start(&ab->htc); 1500 if (ret) { 1501 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1502 goto err_hif_stop; 1503 } 1504 1505 ret = ath11k_wmi_wait_for_service_ready(ab); 1506 if (ret) { 1507 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1508 ret); 1509 goto err_hif_stop; 1510 } 1511 1512 ret = ath11k_mac_allocate(ab); 1513 if (ret) { 1514 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1515 ret); 1516 goto err_hif_stop; 1517 } 1518 1519 ath11k_dp_pdev_pre_alloc(ab); 1520 1521 ret = ath11k_dp_pdev_reo_setup(ab); 1522 if (ret) { 1523 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1524 goto err_mac_destroy; 1525 } 1526 1527 ret = ath11k_wmi_cmd_init(ab); 1528 if (ret) { 1529 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1530 goto err_reo_cleanup; 1531 } 1532 1533 ret = ath11k_wmi_wait_for_unified_ready(ab); 1534 if (ret) { 1535 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1536 ret); 1537 goto err_reo_cleanup; 1538 } 1539 1540 /* put hardware to DBS mode */ 1541 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1542 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1543 if (ret) { 1544 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1545 goto err_hif_stop; 1546 } 1547 } 1548 1549 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1550 if (ret) { 1551 ath11k_err(ab, "failed to send htt version request message: %d\n", 1552 ret); 1553 goto err_reo_cleanup; 1554 } 1555 1556 return 0; 1557 1558 err_reo_cleanup: 1559 ath11k_dp_pdev_reo_cleanup(ab); 1560 err_mac_destroy: 1561 ath11k_mac_destroy(ab); 1562 err_hif_stop: 1563 ath11k_hif_stop(ab); 1564 err_wmi_detach: 1565 ath11k_wmi_detach(ab); 1566 1567 return ret; 1568 } 1569 1570 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1571 enum ath11k_firmware_mode mode) 1572 { 1573 int ret; 1574 1575 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1576 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1577 1578 ret = ath11k_qmi_firmware_start(ab, mode); 1579 if (ret) { 1580 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1581 return ret; 1582 } 1583 1584 return ret; 1585 } 1586 1587 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1588 { 1589 int ret; 1590 1591 ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); 1592 if (ret) { 1593 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1594 return ret; 1595 } 1596 1597 ret = ath11k_ce_init_pipes(ab); 1598 if (ret) { 1599 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1600 goto err_firmware_stop; 1601 } 1602 1603 ret = ath11k_dp_alloc(ab); 1604 if (ret) { 1605 ath11k_err(ab, "failed to init DP: %d\n", ret); 1606 goto err_firmware_stop; 1607 } 1608 1609 switch (ath11k_crypto_mode) { 1610 case ATH11K_CRYPT_MODE_SW: 1611 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1612 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1613 break; 1614 case ATH11K_CRYPT_MODE_HW: 1615 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1616 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1617 break; 1618 default: 1619 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1620 return -EINVAL; 1621 } 1622 1623 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1624 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1625 1626 mutex_lock(&ab->core_lock); 1627 ret = ath11k_core_start(ab); 1628 if (ret) { 1629 ath11k_err(ab, "failed to start core: %d\n", ret); 1630 goto err_dp_free; 1631 } 1632 1633 ret = ath11k_core_pdev_create(ab); 1634 if (ret) { 1635 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1636 goto err_core_stop; 1637 } 1638 ath11k_hif_irq_enable(ab); 1639 mutex_unlock(&ab->core_lock); 1640 1641 return 0; 1642 1643 err_core_stop: 1644 ath11k_core_stop(ab); 1645 ath11k_mac_destroy(ab); 1646 err_dp_free: 1647 ath11k_dp_free(ab); 1648 mutex_unlock(&ab->core_lock); 1649 err_firmware_stop: 1650 ath11k_qmi_firmware_stop(ab); 1651 1652 return ret; 1653 } 1654 1655 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1656 { 1657 int ret; 1658 1659 mutex_lock(&ab->core_lock); 1660 ath11k_thermal_unregister(ab); 1661 ath11k_hif_irq_disable(ab); 1662 ath11k_dp_pdev_free(ab); 1663 ath11k_spectral_deinit(ab); 1664 ath11k_hif_stop(ab); 1665 ath11k_wmi_detach(ab); 1666 ath11k_dp_pdev_reo_cleanup(ab); 1667 mutex_unlock(&ab->core_lock); 1668 1669 ath11k_dp_free(ab); 1670 ath11k_hal_srng_deinit(ab); 1671 1672 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1673 1674 ret = ath11k_hal_srng_init(ab); 1675 if (ret) 1676 return ret; 1677 1678 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1679 1680 ret = ath11k_core_qmi_firmware_ready(ab); 1681 if (ret) 1682 goto err_hal_srng_deinit; 1683 1684 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1685 1686 return 0; 1687 1688 err_hal_srng_deinit: 1689 ath11k_hal_srng_deinit(ab); 1690 return ret; 1691 } 1692 1693 void ath11k_core_halt(struct ath11k *ar) 1694 { 1695 struct ath11k_base *ab = ar->ab; 1696 1697 lockdep_assert_held(&ar->conf_mutex); 1698 1699 ar->num_created_vdevs = 0; 1700 ar->allocated_vdev_map = 0; 1701 1702 ath11k_mac_scan_finish(ar); 1703 ath11k_mac_peer_cleanup_all(ar); 1704 cancel_delayed_work_sync(&ar->scan.timeout); 1705 cancel_work_sync(&ar->regd_update_work); 1706 cancel_work_sync(&ab->update_11d_work); 1707 1708 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1709 synchronize_rcu(); 1710 INIT_LIST_HEAD(&ar->arvifs); 1711 idr_init(&ar->txmgmt_idr); 1712 } 1713 1714 static void ath11k_update_11d(struct work_struct *work) 1715 { 1716 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1717 struct ath11k *ar; 1718 struct ath11k_pdev *pdev; 1719 struct wmi_set_current_country_params set_current_param = {}; 1720 int ret, i; 1721 1722 spin_lock_bh(&ab->base_lock); 1723 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1724 spin_unlock_bh(&ab->base_lock); 1725 1726 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1727 set_current_param.alpha2[0], 1728 set_current_param.alpha2[1]); 1729 1730 for (i = 0; i < ab->num_radios; i++) { 1731 pdev = &ab->pdevs[i]; 1732 ar = pdev->ar; 1733 1734 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1735 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1736 if (ret) 1737 ath11k_warn(ar->ab, 1738 "pdev id %d failed set current country code: %d\n", 1739 i, ret); 1740 } 1741 } 1742 1743 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1744 { 1745 struct ath11k *ar; 1746 struct ath11k_pdev *pdev; 1747 int i; 1748 1749 spin_lock_bh(&ab->base_lock); 1750 ab->stats.fw_crash_counter++; 1751 spin_unlock_bh(&ab->base_lock); 1752 1753 for (i = 0; i < ab->num_radios; i++) { 1754 pdev = &ab->pdevs[i]; 1755 ar = pdev->ar; 1756 if (!ar || ar->state == ATH11K_STATE_OFF) 1757 continue; 1758 1759 ieee80211_stop_queues(ar->hw); 1760 ath11k_mac_drain_tx(ar); 1761 ar->state_11d = ATH11K_11D_IDLE; 1762 complete(&ar->completed_11d_scan); 1763 complete(&ar->scan.started); 1764 complete_all(&ar->scan.completed); 1765 complete(&ar->scan.on_channel); 1766 complete(&ar->peer_assoc_done); 1767 complete(&ar->peer_delete_done); 1768 complete(&ar->install_key_done); 1769 complete(&ar->vdev_setup_done); 1770 complete(&ar->vdev_delete_done); 1771 complete(&ar->bss_survey_done); 1772 complete(&ar->thermal.wmi_sync); 1773 1774 wake_up(&ar->dp.tx_empty_waitq); 1775 idr_for_each(&ar->txmgmt_idr, 1776 ath11k_mac_tx_mgmt_pending_free, ar); 1777 idr_destroy(&ar->txmgmt_idr); 1778 wake_up(&ar->txmgmt_empty_waitq); 1779 1780 ar->monitor_vdev_id = -1; 1781 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 1782 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 1783 } 1784 1785 wake_up(&ab->wmi_ab.tx_credits_wq); 1786 wake_up(&ab->peer_mapping_wq); 1787 1788 reinit_completion(&ab->driver_recovery); 1789 } 1790 1791 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1792 { 1793 struct ath11k *ar; 1794 struct ath11k_pdev *pdev; 1795 int i; 1796 1797 for (i = 0; i < ab->num_radios; i++) { 1798 pdev = &ab->pdevs[i]; 1799 ar = pdev->ar; 1800 if (!ar || ar->state == ATH11K_STATE_OFF) 1801 continue; 1802 1803 mutex_lock(&ar->conf_mutex); 1804 1805 switch (ar->state) { 1806 case ATH11K_STATE_ON: 1807 ar->state = ATH11K_STATE_RESTARTING; 1808 ath11k_core_halt(ar); 1809 ieee80211_restart_hw(ar->hw); 1810 break; 1811 case ATH11K_STATE_OFF: 1812 ath11k_warn(ab, 1813 "cannot restart radio %d that hasn't been started\n", 1814 i); 1815 break; 1816 case ATH11K_STATE_RESTARTING: 1817 break; 1818 case ATH11K_STATE_RESTARTED: 1819 ar->state = ATH11K_STATE_WEDGED; 1820 fallthrough; 1821 case ATH11K_STATE_WEDGED: 1822 ath11k_warn(ab, 1823 "device is wedged, will not restart radio %d\n", i); 1824 break; 1825 } 1826 mutex_unlock(&ar->conf_mutex); 1827 } 1828 complete(&ab->driver_recovery); 1829 } 1830 1831 static void ath11k_core_restart(struct work_struct *work) 1832 { 1833 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1834 int ret; 1835 1836 ret = ath11k_core_reconfigure_on_crash(ab); 1837 if (ret) { 1838 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1839 return; 1840 } 1841 1842 if (ab->is_reset) 1843 complete_all(&ab->reconfigure_complete); 1844 1845 if (!ab->is_reset) 1846 ath11k_core_post_reconfigure_recovery(ab); 1847 } 1848 1849 static void ath11k_core_reset(struct work_struct *work) 1850 { 1851 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1852 int reset_count, fail_cont_count; 1853 long time_left; 1854 1855 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1856 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1857 return; 1858 } 1859 1860 /* Sometimes the recovery will fail and then the next all recovery fail, 1861 * this is to avoid infinite recovery since it can not recovery success. 1862 */ 1863 fail_cont_count = atomic_read(&ab->fail_cont_count); 1864 1865 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1866 return; 1867 1868 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1869 time_before(jiffies, ab->reset_fail_timeout)) 1870 return; 1871 1872 reset_count = atomic_inc_return(&ab->reset_count); 1873 1874 if (reset_count > 1) { 1875 /* Sometimes it happened another reset worker before the previous one 1876 * completed, then the second reset worker will destroy the previous one, 1877 * thus below is to avoid that. 1878 */ 1879 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1880 1881 reinit_completion(&ab->reset_complete); 1882 time_left = wait_for_completion_timeout(&ab->reset_complete, 1883 ATH11K_RESET_TIMEOUT_HZ); 1884 1885 if (time_left) { 1886 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1887 atomic_dec(&ab->reset_count); 1888 return; 1889 } 1890 1891 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1892 /* Record the continuous recovery fail count when recovery failed*/ 1893 atomic_inc(&ab->fail_cont_count); 1894 } 1895 1896 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1897 1898 ab->is_reset = true; 1899 atomic_set(&ab->recovery_count, 0); 1900 reinit_completion(&ab->recovery_start); 1901 atomic_set(&ab->recovery_start_count, 0); 1902 1903 ath11k_core_pre_reconfigure_recovery(ab); 1904 1905 reinit_completion(&ab->reconfigure_complete); 1906 ath11k_core_post_reconfigure_recovery(ab); 1907 1908 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1909 1910 time_left = wait_for_completion_timeout(&ab->recovery_start, 1911 ATH11K_RECOVER_START_TIMEOUT_HZ); 1912 1913 ath11k_hif_power_down(ab); 1914 ath11k_hif_power_up(ab); 1915 1916 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1917 } 1918 1919 static int ath11k_init_hw_params(struct ath11k_base *ab) 1920 { 1921 const struct ath11k_hw_params *hw_params = NULL; 1922 int i; 1923 1924 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1925 hw_params = &ath11k_hw_params[i]; 1926 1927 if (hw_params->hw_rev == ab->hw_rev) 1928 break; 1929 } 1930 1931 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1932 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1933 return -EINVAL; 1934 } 1935 1936 ab->hw_params = *hw_params; 1937 1938 ath11k_info(ab, "%s\n", ab->hw_params.name); 1939 1940 return 0; 1941 } 1942 1943 int ath11k_core_pre_init(struct ath11k_base *ab) 1944 { 1945 int ret; 1946 1947 ret = ath11k_init_hw_params(ab); 1948 if (ret) { 1949 ath11k_err(ab, "failed to get hw params: %d\n", ret); 1950 return ret; 1951 } 1952 1953 return 0; 1954 } 1955 EXPORT_SYMBOL(ath11k_core_pre_init); 1956 1957 int ath11k_core_init(struct ath11k_base *ab) 1958 { 1959 int ret; 1960 1961 ret = ath11k_core_soc_create(ab); 1962 if (ret) { 1963 ath11k_err(ab, "failed to create soc core: %d\n", ret); 1964 return ret; 1965 } 1966 1967 return 0; 1968 } 1969 EXPORT_SYMBOL(ath11k_core_init); 1970 1971 void ath11k_core_deinit(struct ath11k_base *ab) 1972 { 1973 mutex_lock(&ab->core_lock); 1974 1975 ath11k_core_pdev_destroy(ab); 1976 ath11k_core_stop(ab); 1977 1978 mutex_unlock(&ab->core_lock); 1979 1980 ath11k_hif_power_down(ab); 1981 ath11k_mac_destroy(ab); 1982 ath11k_core_soc_destroy(ab); 1983 } 1984 EXPORT_SYMBOL(ath11k_core_deinit); 1985 1986 void ath11k_core_free(struct ath11k_base *ab) 1987 { 1988 destroy_workqueue(ab->workqueue_aux); 1989 destroy_workqueue(ab->workqueue); 1990 1991 kfree(ab); 1992 } 1993 EXPORT_SYMBOL(ath11k_core_free); 1994 1995 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 1996 enum ath11k_bus bus) 1997 { 1998 struct ath11k_base *ab; 1999 2000 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2001 if (!ab) 2002 return NULL; 2003 2004 init_completion(&ab->driver_recovery); 2005 2006 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2007 if (!ab->workqueue) 2008 goto err_sc_free; 2009 2010 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2011 if (!ab->workqueue_aux) 2012 goto err_free_wq; 2013 2014 mutex_init(&ab->core_lock); 2015 mutex_init(&ab->tbl_mtx_lock); 2016 spin_lock_init(&ab->base_lock); 2017 mutex_init(&ab->vdev_id_11d_lock); 2018 init_completion(&ab->reset_complete); 2019 init_completion(&ab->reconfigure_complete); 2020 init_completion(&ab->recovery_start); 2021 2022 INIT_LIST_HEAD(&ab->peers); 2023 init_waitqueue_head(&ab->peer_mapping_wq); 2024 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2025 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2026 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2027 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2028 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2029 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2030 init_completion(&ab->htc_suspend); 2031 init_completion(&ab->wow.wakeup_completed); 2032 2033 ab->dev = dev; 2034 ab->hif.bus = bus; 2035 2036 return ab; 2037 2038 err_free_wq: 2039 destroy_workqueue(ab->workqueue); 2040 err_sc_free: 2041 kfree(ab); 2042 return NULL; 2043 } 2044 EXPORT_SYMBOL(ath11k_core_alloc); 2045 2046 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2047 MODULE_LICENSE("Dual BSD/GPL"); 2048