1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/slab.h> 9 #include <linux/remoteproc.h> 10 #include <linux/firmware.h> 11 #include <linux/of.h> 12 13 #include "core.h" 14 #include "dp_tx.h" 15 #include "dp_rx.h" 16 #include "debug.h" 17 #include "hif.h" 18 #include "wow.h" 19 20 unsigned int ath11k_debug_mask; 21 EXPORT_SYMBOL(ath11k_debug_mask); 22 module_param_named(debug_mask, ath11k_debug_mask, uint, 0644); 23 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 24 25 static unsigned int ath11k_crypto_mode; 26 module_param_named(crypto_mode, ath11k_crypto_mode, uint, 0644); 27 MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); 28 29 /* frame mode values are mapped as per enum ath11k_hw_txrx_mode */ 30 unsigned int ath11k_frame_mode = ATH11K_HW_TXRX_NATIVE_WIFI; 31 module_param_named(frame_mode, ath11k_frame_mode, uint, 0644); 32 MODULE_PARM_DESC(frame_mode, 33 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); 34 35 bool ath11k_ftm_mode; 36 module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0444); 37 MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); 38 39 static const struct ath11k_hw_params ath11k_hw_params[] = { 40 { 41 .hw_rev = ATH11K_HW_IPQ8074, 42 .name = "ipq8074 hw2.0", 43 .fw = { 44 .dir = "IPQ8074/hw2.0", 45 .board_size = 256 * 1024, 46 .cal_offset = 128 * 1024, 47 }, 48 .max_radios = 3, 49 .bdf_addr = 0x4B0C0000, 50 .hw_ops = &ipq8074_ops, 51 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 52 .internal_sleep_clock = false, 53 .regs = &ipq8074_regs, 54 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 55 .host_ce_config = ath11k_host_ce_config_ipq8074, 56 .ce_count = 12, 57 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 58 .target_ce_count = 11, 59 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, 60 .svc_to_ce_map_len = 21, 61 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 62 .single_pdev_only = false, 63 .rxdma1_enable = true, 64 .num_rxmda_per_pdev = 1, 65 .rx_mac_buf_ring = false, 66 .vdev_start_delay = false, 67 .htt_peer_map_v2 = true, 68 69 .spectral = { 70 .fft_sz = 2, 71 /* HW bug, expected BIN size is 2 bytes but HW report as 4 bytes. 72 * so added pad size as 2 bytes to compensate the BIN size 73 */ 74 .fft_pad_sz = 2, 75 .summary_pad_sz = 0, 76 .fft_hdr_len = 16, 77 .max_fft_bins = 512, 78 .fragment_160mhz = true, 79 }, 80 81 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 82 BIT(NL80211_IFTYPE_AP) | 83 BIT(NL80211_IFTYPE_MESH_POINT), 84 .supports_monitor = true, 85 .full_monitor_mode = false, 86 .supports_shadow_regs = false, 87 .idle_ps = false, 88 .supports_sta_ps = false, 89 .coldboot_cal_mm = true, 90 .coldboot_cal_ftm = true, 91 .cbcal_restart_fw = true, 92 .fw_mem_mode = 0, 93 .num_vdevs = 16 + 1, 94 .num_peers = 512, 95 .supports_suspend = false, 96 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 97 .supports_regdb = false, 98 .fix_l1ss = true, 99 .credit_flow = false, 100 .max_tx_ring = DP_TCL_NUM_RING_MAX, 101 .hal_params = &ath11k_hw_hal_params_ipq8074, 102 .supports_dynamic_smps_6ghz = false, 103 .alloc_cacheable_memory = true, 104 .supports_rssi_stats = false, 105 .fw_wmi_diag_event = false, 106 .current_cc_support = false, 107 .dbr_debug_support = true, 108 .global_reset = false, 109 .bios_sar_capa = NULL, 110 .m3_fw_support = false, 111 .fixed_bdf_addr = true, 112 .fixed_mem_region = true, 113 .static_window_map = false, 114 .hybrid_bus_type = false, 115 .fixed_fw_mem = false, 116 .support_off_channel_tx = false, 117 .supports_multi_bssid = false, 118 119 .sram_dump = {}, 120 121 .tcl_ring_retry = true, 122 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 123 .smp2p_wow_exit = false, 124 }, 125 { 126 .hw_rev = ATH11K_HW_IPQ6018_HW10, 127 .name = "ipq6018 hw1.0", 128 .fw = { 129 .dir = "IPQ6018/hw1.0", 130 .board_size = 256 * 1024, 131 .cal_offset = 128 * 1024, 132 }, 133 .max_radios = 2, 134 .bdf_addr = 0x4ABC0000, 135 .hw_ops = &ipq6018_ops, 136 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 137 .internal_sleep_clock = false, 138 .regs = &ipq8074_regs, 139 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 140 .host_ce_config = ath11k_host_ce_config_ipq8074, 141 .ce_count = 12, 142 .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, 143 .target_ce_count = 11, 144 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, 145 .svc_to_ce_map_len = 19, 146 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 147 .single_pdev_only = false, 148 .rxdma1_enable = true, 149 .num_rxmda_per_pdev = 1, 150 .rx_mac_buf_ring = false, 151 .vdev_start_delay = false, 152 .htt_peer_map_v2 = true, 153 154 .spectral = { 155 .fft_sz = 4, 156 .fft_pad_sz = 0, 157 .summary_pad_sz = 0, 158 .fft_hdr_len = 16, 159 .max_fft_bins = 512, 160 .fragment_160mhz = true, 161 }, 162 163 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 164 BIT(NL80211_IFTYPE_AP) | 165 BIT(NL80211_IFTYPE_MESH_POINT), 166 .supports_monitor = true, 167 .full_monitor_mode = false, 168 .supports_shadow_regs = false, 169 .idle_ps = false, 170 .supports_sta_ps = false, 171 .coldboot_cal_mm = true, 172 .coldboot_cal_ftm = true, 173 .cbcal_restart_fw = true, 174 .fw_mem_mode = 0, 175 .num_vdevs = 16 + 1, 176 .num_peers = 512, 177 .supports_suspend = false, 178 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 179 .supports_regdb = false, 180 .fix_l1ss = true, 181 .credit_flow = false, 182 .max_tx_ring = DP_TCL_NUM_RING_MAX, 183 .hal_params = &ath11k_hw_hal_params_ipq8074, 184 .supports_dynamic_smps_6ghz = false, 185 .alloc_cacheable_memory = true, 186 .supports_rssi_stats = false, 187 .fw_wmi_diag_event = false, 188 .current_cc_support = false, 189 .dbr_debug_support = true, 190 .global_reset = false, 191 .bios_sar_capa = NULL, 192 .m3_fw_support = false, 193 .fixed_bdf_addr = true, 194 .fixed_mem_region = true, 195 .static_window_map = false, 196 .hybrid_bus_type = false, 197 .fixed_fw_mem = false, 198 .support_off_channel_tx = false, 199 .supports_multi_bssid = false, 200 201 .sram_dump = {}, 202 203 .tcl_ring_retry = true, 204 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 205 .smp2p_wow_exit = false, 206 .support_fw_mac_sequence = false, 207 }, 208 { 209 .name = "qca6390 hw2.0", 210 .hw_rev = ATH11K_HW_QCA6390_HW20, 211 .fw = { 212 .dir = "QCA6390/hw2.0", 213 .board_size = 256 * 1024, 214 .cal_offset = 128 * 1024, 215 }, 216 .max_radios = 3, 217 .bdf_addr = 0x4B0C0000, 218 .hw_ops = &qca6390_ops, 219 .ring_mask = &ath11k_hw_ring_mask_qca6390, 220 .internal_sleep_clock = true, 221 .regs = &qca6390_regs, 222 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 223 .host_ce_config = ath11k_host_ce_config_qca6390, 224 .ce_count = 9, 225 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 226 .target_ce_count = 9, 227 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 228 .svc_to_ce_map_len = 14, 229 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 230 .single_pdev_only = true, 231 .rxdma1_enable = false, 232 .num_rxmda_per_pdev = 2, 233 .rx_mac_buf_ring = true, 234 .vdev_start_delay = true, 235 .htt_peer_map_v2 = false, 236 237 .spectral = { 238 .fft_sz = 0, 239 .fft_pad_sz = 0, 240 .summary_pad_sz = 0, 241 .fft_hdr_len = 0, 242 .max_fft_bins = 0, 243 .fragment_160mhz = false, 244 }, 245 246 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 247 BIT(NL80211_IFTYPE_AP), 248 .supports_monitor = false, 249 .full_monitor_mode = false, 250 .supports_shadow_regs = true, 251 .idle_ps = true, 252 .supports_sta_ps = true, 253 .coldboot_cal_mm = false, 254 .coldboot_cal_ftm = false, 255 .cbcal_restart_fw = false, 256 .fw_mem_mode = 0, 257 .num_vdevs = 16 + 1, 258 .num_peers = 512, 259 .supports_suspend = true, 260 .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), 261 .supports_regdb = false, 262 .fix_l1ss = true, 263 .credit_flow = true, 264 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 265 .hal_params = &ath11k_hw_hal_params_qca6390, 266 .supports_dynamic_smps_6ghz = false, 267 .alloc_cacheable_memory = false, 268 .supports_rssi_stats = true, 269 .fw_wmi_diag_event = true, 270 .current_cc_support = true, 271 .dbr_debug_support = false, 272 .global_reset = true, 273 .bios_sar_capa = NULL, 274 .m3_fw_support = true, 275 .fixed_bdf_addr = false, 276 .fixed_mem_region = false, 277 .static_window_map = false, 278 .hybrid_bus_type = false, 279 .fixed_fw_mem = false, 280 .support_off_channel_tx = true, 281 .supports_multi_bssid = true, 282 283 .sram_dump = { 284 .start = 0x01400000, 285 .end = 0x0171ffff, 286 }, 287 288 .tcl_ring_retry = true, 289 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 290 .smp2p_wow_exit = false, 291 .support_fw_mac_sequence = true, 292 }, 293 { 294 .name = "qcn9074 hw1.0", 295 .hw_rev = ATH11K_HW_QCN9074_HW10, 296 .fw = { 297 .dir = "QCN9074/hw1.0", 298 .board_size = 256 * 1024, 299 .cal_offset = 128 * 1024, 300 }, 301 .max_radios = 1, 302 .single_pdev_only = false, 303 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074, 304 .hw_ops = &qcn9074_ops, 305 .ring_mask = &ath11k_hw_ring_mask_qcn9074, 306 .internal_sleep_clock = false, 307 .regs = &qcn9074_regs, 308 .host_ce_config = ath11k_host_ce_config_qcn9074, 309 .ce_count = 6, 310 .target_ce_config = ath11k_target_ce_config_wlan_qcn9074, 311 .target_ce_count = 9, 312 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074, 313 .svc_to_ce_map_len = 18, 314 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 315 .rxdma1_enable = true, 316 .num_rxmda_per_pdev = 1, 317 .rx_mac_buf_ring = false, 318 .vdev_start_delay = false, 319 .htt_peer_map_v2 = true, 320 321 .spectral = { 322 .fft_sz = 2, 323 .fft_pad_sz = 0, 324 .summary_pad_sz = 16, 325 .fft_hdr_len = 24, 326 .max_fft_bins = 1024, 327 .fragment_160mhz = false, 328 }, 329 330 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 331 BIT(NL80211_IFTYPE_AP) | 332 BIT(NL80211_IFTYPE_MESH_POINT), 333 .supports_monitor = true, 334 .full_monitor_mode = true, 335 .supports_shadow_regs = false, 336 .idle_ps = false, 337 .supports_sta_ps = false, 338 .coldboot_cal_mm = false, 339 .coldboot_cal_ftm = true, 340 .cbcal_restart_fw = true, 341 .fw_mem_mode = 2, 342 .num_vdevs = 8, 343 .num_peers = 128, 344 .supports_suspend = false, 345 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 346 .supports_regdb = false, 347 .fix_l1ss = true, 348 .credit_flow = false, 349 .max_tx_ring = DP_TCL_NUM_RING_MAX, 350 .hal_params = &ath11k_hw_hal_params_ipq8074, 351 .supports_dynamic_smps_6ghz = true, 352 .alloc_cacheable_memory = true, 353 .supports_rssi_stats = false, 354 .fw_wmi_diag_event = false, 355 .current_cc_support = false, 356 .dbr_debug_support = true, 357 .global_reset = false, 358 .bios_sar_capa = NULL, 359 .m3_fw_support = true, 360 .fixed_bdf_addr = false, 361 .fixed_mem_region = false, 362 .static_window_map = true, 363 .hybrid_bus_type = false, 364 .fixed_fw_mem = false, 365 .support_off_channel_tx = false, 366 .supports_multi_bssid = false, 367 368 .sram_dump = {}, 369 370 .tcl_ring_retry = true, 371 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 372 .smp2p_wow_exit = false, 373 .support_fw_mac_sequence = false, 374 }, 375 { 376 .name = "wcn6855 hw2.0", 377 .hw_rev = ATH11K_HW_WCN6855_HW20, 378 .fw = { 379 .dir = "WCN6855/hw2.0", 380 .board_size = 256 * 1024, 381 .cal_offset = 128 * 1024, 382 }, 383 .max_radios = 3, 384 .bdf_addr = 0x4B0C0000, 385 .hw_ops = &wcn6855_ops, 386 .ring_mask = &ath11k_hw_ring_mask_qca6390, 387 .internal_sleep_clock = true, 388 .regs = &wcn6855_regs, 389 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 390 .host_ce_config = ath11k_host_ce_config_qca6390, 391 .ce_count = 9, 392 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 393 .target_ce_count = 9, 394 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 395 .svc_to_ce_map_len = 14, 396 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 397 .single_pdev_only = true, 398 .rxdma1_enable = false, 399 .num_rxmda_per_pdev = 2, 400 .rx_mac_buf_ring = true, 401 .vdev_start_delay = true, 402 .htt_peer_map_v2 = false, 403 404 .spectral = { 405 .fft_sz = 0, 406 .fft_pad_sz = 0, 407 .summary_pad_sz = 0, 408 .fft_hdr_len = 0, 409 .max_fft_bins = 0, 410 .fragment_160mhz = false, 411 }, 412 413 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 414 BIT(NL80211_IFTYPE_AP), 415 .supports_monitor = false, 416 .full_monitor_mode = false, 417 .supports_shadow_regs = true, 418 .idle_ps = true, 419 .supports_sta_ps = true, 420 .coldboot_cal_mm = false, 421 .coldboot_cal_ftm = false, 422 .cbcal_restart_fw = false, 423 .fw_mem_mode = 0, 424 .num_vdevs = 16 + 1, 425 .num_peers = 512, 426 .supports_suspend = true, 427 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 428 .supports_regdb = true, 429 .fix_l1ss = false, 430 .credit_flow = true, 431 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 432 .hal_params = &ath11k_hw_hal_params_qca6390, 433 .supports_dynamic_smps_6ghz = false, 434 .alloc_cacheable_memory = false, 435 .supports_rssi_stats = true, 436 .fw_wmi_diag_event = true, 437 .current_cc_support = true, 438 .dbr_debug_support = false, 439 .global_reset = true, 440 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 441 .m3_fw_support = true, 442 .fixed_bdf_addr = false, 443 .fixed_mem_region = false, 444 .static_window_map = false, 445 .hybrid_bus_type = false, 446 .fixed_fw_mem = false, 447 .support_off_channel_tx = true, 448 .supports_multi_bssid = true, 449 450 .sram_dump = { 451 .start = 0x01400000, 452 .end = 0x0177ffff, 453 }, 454 455 .tcl_ring_retry = true, 456 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 457 .smp2p_wow_exit = false, 458 .support_fw_mac_sequence = true, 459 }, 460 { 461 .name = "wcn6855 hw2.1", 462 .hw_rev = ATH11K_HW_WCN6855_HW21, 463 .fw = { 464 .dir = "WCN6855/hw2.1", 465 .board_size = 256 * 1024, 466 .cal_offset = 128 * 1024, 467 }, 468 .max_radios = 3, 469 .bdf_addr = 0x4B0C0000, 470 .hw_ops = &wcn6855_ops, 471 .ring_mask = &ath11k_hw_ring_mask_qca6390, 472 .internal_sleep_clock = true, 473 .regs = &wcn6855_regs, 474 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390, 475 .host_ce_config = ath11k_host_ce_config_qca6390, 476 .ce_count = 9, 477 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 478 .target_ce_count = 9, 479 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 480 .svc_to_ce_map_len = 14, 481 .single_pdev_only = true, 482 .rxdma1_enable = false, 483 .num_rxmda_per_pdev = 2, 484 .rx_mac_buf_ring = true, 485 .vdev_start_delay = true, 486 .htt_peer_map_v2 = false, 487 488 .spectral = { 489 .fft_sz = 0, 490 .fft_pad_sz = 0, 491 .summary_pad_sz = 0, 492 .fft_hdr_len = 0, 493 .max_fft_bins = 0, 494 .fragment_160mhz = false, 495 }, 496 497 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 498 BIT(NL80211_IFTYPE_AP), 499 .supports_monitor = false, 500 .supports_shadow_regs = true, 501 .idle_ps = true, 502 .supports_sta_ps = true, 503 .coldboot_cal_mm = false, 504 .coldboot_cal_ftm = false, 505 .cbcal_restart_fw = false, 506 .fw_mem_mode = 0, 507 .num_vdevs = 16 + 1, 508 .num_peers = 512, 509 .supports_suspend = true, 510 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), 511 .supports_regdb = true, 512 .fix_l1ss = false, 513 .credit_flow = true, 514 .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390, 515 .hal_params = &ath11k_hw_hal_params_qca6390, 516 .supports_dynamic_smps_6ghz = false, 517 .alloc_cacheable_memory = false, 518 .supports_rssi_stats = true, 519 .fw_wmi_diag_event = true, 520 .current_cc_support = true, 521 .dbr_debug_support = false, 522 .global_reset = true, 523 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 524 .m3_fw_support = true, 525 .fixed_bdf_addr = false, 526 .fixed_mem_region = false, 527 .static_window_map = false, 528 .hybrid_bus_type = false, 529 .fixed_fw_mem = false, 530 .support_off_channel_tx = true, 531 .supports_multi_bssid = true, 532 533 .sram_dump = { 534 .start = 0x01400000, 535 .end = 0x0177ffff, 536 }, 537 538 .tcl_ring_retry = true, 539 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 540 .smp2p_wow_exit = false, 541 .support_fw_mac_sequence = true, 542 }, 543 { 544 .name = "wcn6750 hw1.0", 545 .hw_rev = ATH11K_HW_WCN6750_HW10, 546 .fw = { 547 .dir = "WCN6750/hw1.0", 548 .board_size = 256 * 1024, 549 .cal_offset = 128 * 1024, 550 }, 551 .max_radios = 1, 552 .bdf_addr = 0x4B0C0000, 553 .hw_ops = &wcn6750_ops, 554 .ring_mask = &ath11k_hw_ring_mask_wcn6750, 555 .internal_sleep_clock = false, 556 .regs = &wcn6750_regs, 557 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750, 558 .host_ce_config = ath11k_host_ce_config_qca6390, 559 .ce_count = 9, 560 .target_ce_config = ath11k_target_ce_config_wlan_qca6390, 561 .target_ce_count = 9, 562 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390, 563 .svc_to_ce_map_len = 14, 564 .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, 565 .single_pdev_only = true, 566 .rxdma1_enable = false, 567 .num_rxmda_per_pdev = 1, 568 .rx_mac_buf_ring = true, 569 .vdev_start_delay = true, 570 .htt_peer_map_v2 = false, 571 572 .spectral = { 573 .fft_sz = 0, 574 .fft_pad_sz = 0, 575 .summary_pad_sz = 0, 576 .fft_hdr_len = 0, 577 .max_fft_bins = 0, 578 .fragment_160mhz = false, 579 }, 580 581 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 582 BIT(NL80211_IFTYPE_AP), 583 .supports_monitor = false, 584 .supports_shadow_regs = true, 585 .idle_ps = true, 586 .supports_sta_ps = true, 587 .coldboot_cal_mm = true, 588 .coldboot_cal_ftm = true, 589 .cbcal_restart_fw = false, 590 .fw_mem_mode = 0, 591 .num_vdevs = 16 + 1, 592 .num_peers = 512, 593 .supports_suspend = false, 594 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 595 .supports_regdb = true, 596 .fix_l1ss = false, 597 .credit_flow = true, 598 .max_tx_ring = DP_TCL_NUM_RING_MAX, 599 .hal_params = &ath11k_hw_hal_params_wcn6750, 600 .supports_dynamic_smps_6ghz = false, 601 .alloc_cacheable_memory = false, 602 .supports_rssi_stats = true, 603 .fw_wmi_diag_event = false, 604 .current_cc_support = true, 605 .dbr_debug_support = false, 606 .global_reset = false, 607 .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855, 608 .m3_fw_support = false, 609 .fixed_bdf_addr = false, 610 .fixed_mem_region = false, 611 .static_window_map = true, 612 .hybrid_bus_type = true, 613 .fixed_fw_mem = true, 614 .support_off_channel_tx = true, 615 .supports_multi_bssid = true, 616 617 .sram_dump = {}, 618 619 .tcl_ring_retry = false, 620 .tx_ring_size = DP_TCL_DATA_RING_SIZE_WCN6750, 621 .smp2p_wow_exit = true, 622 .support_fw_mac_sequence = true, 623 }, 624 { 625 .hw_rev = ATH11K_HW_IPQ5018_HW10, 626 .name = "ipq5018 hw1.0", 627 .fw = { 628 .dir = "IPQ5018/hw1.0", 629 .board_size = 256 * 1024, 630 .cal_offset = 128 * 1024, 631 }, 632 .max_radios = MAX_RADIOS_5018, 633 .bdf_addr = 0x4BA00000, 634 /* hal_desc_sz and hw ops are similar to qcn9074 */ 635 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), 636 .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, 637 .ring_mask = &ath11k_hw_ring_mask_ipq8074, 638 .credit_flow = false, 639 .max_tx_ring = 1, 640 .spectral = { 641 .fft_sz = 2, 642 .fft_pad_sz = 0, 643 .summary_pad_sz = 16, 644 .fft_hdr_len = 24, 645 .max_fft_bins = 1024, 646 }, 647 .internal_sleep_clock = false, 648 .regs = &ipq5018_regs, 649 .hw_ops = &ipq5018_ops, 650 .host_ce_config = ath11k_host_ce_config_qcn9074, 651 .ce_count = CE_CNT_5018, 652 .target_ce_config = ath11k_target_ce_config_wlan_ipq5018, 653 .target_ce_count = TARGET_CE_CNT_5018, 654 .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq5018, 655 .svc_to_ce_map_len = SVC_CE_MAP_LEN_5018, 656 .ce_ie_addr = &ath11k_ce_ie_addr_ipq5018, 657 .ce_remap = &ath11k_ce_remap_ipq5018, 658 .rxdma1_enable = true, 659 .num_rxmda_per_pdev = RXDMA_PER_PDEV_5018, 660 .rx_mac_buf_ring = false, 661 .vdev_start_delay = false, 662 .htt_peer_map_v2 = true, 663 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 664 BIT(NL80211_IFTYPE_AP) | 665 BIT(NL80211_IFTYPE_MESH_POINT), 666 .supports_monitor = false, 667 .supports_sta_ps = false, 668 .supports_shadow_regs = false, 669 .fw_mem_mode = 0, 670 .num_vdevs = 16 + 1, 671 .num_peers = 512, 672 .supports_regdb = false, 673 .idle_ps = false, 674 .supports_suspend = false, 675 .hal_params = &ath11k_hw_hal_params_ipq8074, 676 .single_pdev_only = false, 677 .coldboot_cal_mm = true, 678 .coldboot_cal_ftm = true, 679 .cbcal_restart_fw = true, 680 .fix_l1ss = true, 681 .supports_dynamic_smps_6ghz = false, 682 .alloc_cacheable_memory = true, 683 .supports_rssi_stats = false, 684 .fw_wmi_diag_event = false, 685 .current_cc_support = false, 686 .dbr_debug_support = true, 687 .global_reset = false, 688 .bios_sar_capa = NULL, 689 .m3_fw_support = false, 690 .fixed_bdf_addr = true, 691 .fixed_mem_region = true, 692 .static_window_map = false, 693 .hybrid_bus_type = false, 694 .fixed_fw_mem = false, 695 .support_off_channel_tx = false, 696 .supports_multi_bssid = false, 697 698 .sram_dump = {}, 699 700 .tcl_ring_retry = true, 701 .tx_ring_size = DP_TCL_DATA_RING_SIZE, 702 .smp2p_wow_exit = false, 703 .support_fw_mac_sequence = false, 704 }, 705 }; 706 707 static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab) 708 { 709 WARN_ON(!ab->hw_params.single_pdev_only); 710 711 return &ab->pdevs[0]; 712 } 713 714 void ath11k_fw_stats_pdevs_free(struct list_head *head) 715 { 716 struct ath11k_fw_stats_pdev *i, *tmp; 717 718 list_for_each_entry_safe(i, tmp, head, list) { 719 list_del(&i->list); 720 kfree(i); 721 } 722 } 723 724 void ath11k_fw_stats_vdevs_free(struct list_head *head) 725 { 726 struct ath11k_fw_stats_vdev *i, *tmp; 727 728 list_for_each_entry_safe(i, tmp, head, list) { 729 list_del(&i->list); 730 kfree(i); 731 } 732 } 733 734 void ath11k_fw_stats_bcn_free(struct list_head *head) 735 { 736 struct ath11k_fw_stats_bcn *i, *tmp; 737 738 list_for_each_entry_safe(i, tmp, head, list) { 739 list_del(&i->list); 740 kfree(i); 741 } 742 } 743 744 void ath11k_fw_stats_init(struct ath11k *ar) 745 { 746 INIT_LIST_HEAD(&ar->fw_stats.pdevs); 747 INIT_LIST_HEAD(&ar->fw_stats.vdevs); 748 INIT_LIST_HEAD(&ar->fw_stats.bcn); 749 750 init_completion(&ar->fw_stats_complete); 751 } 752 753 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats) 754 { 755 ath11k_fw_stats_pdevs_free(&stats->pdevs); 756 ath11k_fw_stats_vdevs_free(&stats->vdevs); 757 ath11k_fw_stats_bcn_free(&stats->bcn); 758 } 759 760 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) 761 { 762 if (!ath11k_cold_boot_cal) 763 return false; 764 765 if (ath11k_ftm_mode) 766 return ab->hw_params.coldboot_cal_ftm; 767 768 else 769 return ab->hw_params.coldboot_cal_mm; 770 } 771 772 int ath11k_core_suspend(struct ath11k_base *ab) 773 { 774 int ret; 775 struct ath11k_pdev *pdev; 776 struct ath11k *ar; 777 778 if (!ab->hw_params.supports_suspend) 779 return -EOPNOTSUPP; 780 781 /* so far single_pdev_only chips have supports_suspend as true 782 * and only the first pdev is valid. 783 */ 784 pdev = ath11k_core_get_single_pdev(ab); 785 ar = pdev->ar; 786 if (!ar || ar->state != ATH11K_STATE_OFF) 787 return 0; 788 789 ret = ath11k_dp_rx_pktlog_stop(ab, true); 790 if (ret) { 791 ath11k_warn(ab, "failed to stop dp rx (and timer) pktlog during suspend: %d\n", 792 ret); 793 return ret; 794 } 795 796 ret = ath11k_mac_wait_tx_complete(ar); 797 if (ret) { 798 ath11k_warn(ab, "failed to wait tx complete: %d\n", ret); 799 return ret; 800 } 801 802 ret = ath11k_wow_enable(ab); 803 if (ret) { 804 ath11k_warn(ab, "failed to enable wow during suspend: %d\n", ret); 805 return ret; 806 } 807 808 ret = ath11k_dp_rx_pktlog_stop(ab, false); 809 if (ret) { 810 ath11k_warn(ab, "failed to stop dp rx pktlog during suspend: %d\n", 811 ret); 812 return ret; 813 } 814 815 ath11k_ce_stop_shadow_timers(ab); 816 ath11k_dp_stop_shadow_timers(ab); 817 818 ath11k_hif_irq_disable(ab); 819 ath11k_hif_ce_irq_disable(ab); 820 821 ret = ath11k_hif_suspend(ab); 822 if (ret) { 823 ath11k_warn(ab, "failed to suspend hif: %d\n", ret); 824 return ret; 825 } 826 827 return 0; 828 } 829 EXPORT_SYMBOL(ath11k_core_suspend); 830 831 int ath11k_core_resume(struct ath11k_base *ab) 832 { 833 int ret; 834 struct ath11k_pdev *pdev; 835 struct ath11k *ar; 836 837 if (!ab->hw_params.supports_suspend) 838 return -EOPNOTSUPP; 839 840 /* so far signle_pdev_only chips have supports_suspend as true 841 * and only the first pdev is valid. 842 */ 843 pdev = ath11k_core_get_single_pdev(ab); 844 ar = pdev->ar; 845 if (!ar || ar->state != ATH11K_STATE_OFF) 846 return 0; 847 848 ret = ath11k_hif_resume(ab); 849 if (ret) { 850 ath11k_warn(ab, "failed to resume hif during resume: %d\n", ret); 851 return ret; 852 } 853 854 ath11k_hif_ce_irq_enable(ab); 855 ath11k_hif_irq_enable(ab); 856 857 ret = ath11k_dp_rx_pktlog_start(ab); 858 if (ret) { 859 ath11k_warn(ab, "failed to start rx pktlog during resume: %d\n", 860 ret); 861 return ret; 862 } 863 864 ret = ath11k_wow_wakeup(ab); 865 if (ret) { 866 ath11k_warn(ab, "failed to wakeup wow during resume: %d\n", ret); 867 return ret; 868 } 869 870 return 0; 871 } 872 EXPORT_SYMBOL(ath11k_core_resume); 873 874 static void ath11k_core_check_cc_code_bdfext(const struct dmi_header *hdr, void *data) 875 { 876 struct ath11k_base *ab = data; 877 const char *magic = ATH11K_SMBIOS_BDF_EXT_MAGIC; 878 struct ath11k_smbios_bdf *smbios = (struct ath11k_smbios_bdf *)hdr; 879 ssize_t copied; 880 size_t len; 881 int i; 882 883 if (ab->qmi.target.bdf_ext[0] != '\0') 884 return; 885 886 if (hdr->type != ATH11K_SMBIOS_BDF_EXT_TYPE) 887 return; 888 889 if (hdr->length != ATH11K_SMBIOS_BDF_EXT_LENGTH) { 890 ath11k_dbg(ab, ATH11K_DBG_BOOT, 891 "wrong smbios bdf ext type length (%d).\n", 892 hdr->length); 893 return; 894 } 895 896 spin_lock_bh(&ab->base_lock); 897 898 switch (smbios->country_code_flag) { 899 case ATH11K_SMBIOS_CC_ISO: 900 ab->new_alpha2[0] = (smbios->cc_code >> 8) & 0xff; 901 ab->new_alpha2[1] = smbios->cc_code & 0xff; 902 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios cc_code %c%c\n", 903 ab->new_alpha2[0], ab->new_alpha2[1]); 904 break; 905 case ATH11K_SMBIOS_CC_WW: 906 ab->new_alpha2[0] = '0'; 907 ab->new_alpha2[1] = '0'; 908 ath11k_dbg(ab, ATH11K_DBG_BOOT, "smbios worldwide regdomain\n"); 909 break; 910 default: 911 ath11k_dbg(ab, ATH11K_DBG_BOOT, "ignore smbios country code setting %d\n", 912 smbios->country_code_flag); 913 break; 914 } 915 916 spin_unlock_bh(&ab->base_lock); 917 918 if (!smbios->bdf_enabled) { 919 ath11k_dbg(ab, ATH11K_DBG_BOOT, "bdf variant name not found.\n"); 920 return; 921 } 922 923 /* Only one string exists (per spec) */ 924 if (memcmp(smbios->bdf_ext, magic, strlen(magic)) != 0) { 925 ath11k_dbg(ab, ATH11K_DBG_BOOT, 926 "bdf variant magic does not match.\n"); 927 return; 928 } 929 930 len = min_t(size_t, 931 strlen(smbios->bdf_ext), sizeof(ab->qmi.target.bdf_ext)); 932 for (i = 0; i < len; i++) { 933 if (!isascii(smbios->bdf_ext[i]) || !isprint(smbios->bdf_ext[i])) { 934 ath11k_dbg(ab, ATH11K_DBG_BOOT, 935 "bdf variant name contains non ascii chars.\n"); 936 return; 937 } 938 } 939 940 /* Copy extension name without magic prefix */ 941 copied = strscpy(ab->qmi.target.bdf_ext, smbios->bdf_ext + strlen(magic), 942 sizeof(ab->qmi.target.bdf_ext)); 943 if (copied < 0) { 944 ath11k_dbg(ab, ATH11K_DBG_BOOT, 945 "bdf variant string is longer than the buffer can accommodate\n"); 946 return; 947 } 948 949 ath11k_dbg(ab, ATH11K_DBG_BOOT, 950 "found and validated bdf variant smbios_type 0x%x bdf %s\n", 951 ATH11K_SMBIOS_BDF_EXT_TYPE, ab->qmi.target.bdf_ext); 952 } 953 954 int ath11k_core_check_smbios(struct ath11k_base *ab) 955 { 956 ab->qmi.target.bdf_ext[0] = '\0'; 957 dmi_walk(ath11k_core_check_cc_code_bdfext, ab); 958 959 if (ab->qmi.target.bdf_ext[0] == '\0') 960 return -ENODATA; 961 962 return 0; 963 } 964 965 int ath11k_core_check_dt(struct ath11k_base *ab) 966 { 967 size_t max_len = sizeof(ab->qmi.target.bdf_ext); 968 const char *variant = NULL; 969 struct device_node *node; 970 971 node = ab->dev->of_node; 972 if (!node) 973 return -ENOENT; 974 975 of_property_read_string(node, "qcom,ath11k-calibration-variant", 976 &variant); 977 if (!variant) 978 return -ENODATA; 979 980 if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) 981 ath11k_dbg(ab, ATH11K_DBG_BOOT, 982 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", 983 variant); 984 985 return 0; 986 } 987 988 static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 989 size_t name_len, bool with_variant, 990 bool bus_type_mode) 991 { 992 /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ 993 char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; 994 995 if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') 996 scnprintf(variant, sizeof(variant), ",variant=%s", 997 ab->qmi.target.bdf_ext); 998 999 switch (ab->id.bdf_search) { 1000 case ATH11K_BDF_SEARCH_BUS_AND_BOARD: 1001 if (bus_type_mode) 1002 scnprintf(name, name_len, 1003 "bus=%s", 1004 ath11k_bus_str(ab->hif.bus)); 1005 else 1006 scnprintf(name, name_len, 1007 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", 1008 ath11k_bus_str(ab->hif.bus), 1009 ab->id.vendor, ab->id.device, 1010 ab->id.subsystem_vendor, 1011 ab->id.subsystem_device, 1012 ab->qmi.target.chip_id, 1013 ab->qmi.target.board_id, 1014 variant); 1015 break; 1016 default: 1017 scnprintf(name, name_len, 1018 "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", 1019 ath11k_bus_str(ab->hif.bus), 1020 ab->qmi.target.chip_id, 1021 ab->qmi.target.board_id, variant); 1022 break; 1023 } 1024 1025 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board name '%s'\n", name); 1026 1027 return 0; 1028 } 1029 1030 static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, 1031 size_t name_len) 1032 { 1033 return __ath11k_core_create_board_name(ab, name, name_len, true, false); 1034 } 1035 1036 static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, 1037 size_t name_len) 1038 { 1039 return __ath11k_core_create_board_name(ab, name, name_len, false, false); 1040 } 1041 1042 static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, 1043 size_t name_len) 1044 { 1045 return __ath11k_core_create_board_name(ab, name, name_len, false, true); 1046 } 1047 1048 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, 1049 const char *file) 1050 { 1051 const struct firmware *fw; 1052 char path[100]; 1053 int ret; 1054 1055 if (file == NULL) 1056 return ERR_PTR(-ENOENT); 1057 1058 ath11k_core_create_firmware_path(ab, file, path, sizeof(path)); 1059 1060 ret = firmware_request_nowarn(&fw, path, ab->dev); 1061 if (ret) 1062 return ERR_PTR(ret); 1063 1064 ath11k_dbg(ab, ATH11K_DBG_BOOT, "firmware request %s size %zu\n", 1065 path, fw->size); 1066 1067 return fw; 1068 } 1069 1070 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1071 { 1072 if (!IS_ERR(bd->fw)) 1073 release_firmware(bd->fw); 1074 1075 memset(bd, 0, sizeof(*bd)); 1076 } 1077 1078 static int ath11k_core_parse_bd_ie_board(struct ath11k_base *ab, 1079 struct ath11k_board_data *bd, 1080 const void *buf, size_t buf_len, 1081 const char *boardname, 1082 int ie_id, 1083 int name_id, 1084 int data_id) 1085 { 1086 const struct ath11k_fw_ie *hdr; 1087 bool name_match_found; 1088 int ret, board_ie_id; 1089 size_t board_ie_len; 1090 const void *board_ie_data; 1091 1092 name_match_found = false; 1093 1094 /* go through ATH11K_BD_IE_BOARD_/ATH11K_BD_IE_REGDB_ elements */ 1095 while (buf_len > sizeof(struct ath11k_fw_ie)) { 1096 hdr = buf; 1097 board_ie_id = le32_to_cpu(hdr->id); 1098 board_ie_len = le32_to_cpu(hdr->len); 1099 board_ie_data = hdr->data; 1100 1101 buf_len -= sizeof(*hdr); 1102 buf += sizeof(*hdr); 1103 1104 if (buf_len < ALIGN(board_ie_len, 4)) { 1105 ath11k_err(ab, "invalid %s length: %zu < %zu\n", 1106 ath11k_bd_ie_type_str(ie_id), 1107 buf_len, ALIGN(board_ie_len, 4)); 1108 ret = -EINVAL; 1109 goto out; 1110 } 1111 1112 if (board_ie_id == name_id) { 1113 ath11k_dbg_dump(ab, ATH11K_DBG_BOOT, "board name", "", 1114 board_ie_data, board_ie_len); 1115 1116 if (board_ie_len != strlen(boardname)) 1117 goto next; 1118 1119 ret = memcmp(board_ie_data, boardname, strlen(boardname)); 1120 if (ret) 1121 goto next; 1122 1123 name_match_found = true; 1124 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1125 "found match %s for name '%s'", 1126 ath11k_bd_ie_type_str(ie_id), 1127 boardname); 1128 } else if (board_ie_id == data_id) { 1129 if (!name_match_found) 1130 /* no match found */ 1131 goto next; 1132 1133 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1134 "found %s for '%s'", 1135 ath11k_bd_ie_type_str(ie_id), 1136 boardname); 1137 1138 bd->data = board_ie_data; 1139 bd->len = board_ie_len; 1140 1141 ret = 0; 1142 goto out; 1143 } else { 1144 ath11k_warn(ab, "unknown %s id found: %d\n", 1145 ath11k_bd_ie_type_str(ie_id), 1146 board_ie_id); 1147 } 1148 next: 1149 /* jump over the padding */ 1150 board_ie_len = ALIGN(board_ie_len, 4); 1151 1152 buf_len -= board_ie_len; 1153 buf += board_ie_len; 1154 } 1155 1156 /* no match found */ 1157 ret = -ENOENT; 1158 1159 out: 1160 return ret; 1161 } 1162 1163 static int ath11k_core_fetch_board_data_api_n(struct ath11k_base *ab, 1164 struct ath11k_board_data *bd, 1165 const char *boardname, 1166 int ie_id_match, 1167 int name_id, 1168 int data_id) 1169 { 1170 size_t len, magic_len; 1171 const u8 *data; 1172 char *filename, filepath[100]; 1173 size_t ie_len; 1174 struct ath11k_fw_ie *hdr; 1175 int ret, ie_id; 1176 1177 filename = ATH11K_BOARD_API2_FILE; 1178 1179 if (!bd->fw) 1180 bd->fw = ath11k_core_firmware_request(ab, filename); 1181 1182 if (IS_ERR(bd->fw)) 1183 return PTR_ERR(bd->fw); 1184 1185 data = bd->fw->data; 1186 len = bd->fw->size; 1187 1188 ath11k_core_create_firmware_path(ab, filename, 1189 filepath, sizeof(filepath)); 1190 1191 /* magic has extra null byte padded */ 1192 magic_len = strlen(ATH11K_BOARD_MAGIC) + 1; 1193 if (len < magic_len) { 1194 ath11k_err(ab, "failed to find magic value in %s, file too short: %zu\n", 1195 filepath, len); 1196 ret = -EINVAL; 1197 goto err; 1198 } 1199 1200 if (memcmp(data, ATH11K_BOARD_MAGIC, magic_len)) { 1201 ath11k_err(ab, "found invalid board magic\n"); 1202 ret = -EINVAL; 1203 goto err; 1204 } 1205 1206 /* magic is padded to 4 bytes */ 1207 magic_len = ALIGN(magic_len, 4); 1208 if (len < magic_len) { 1209 ath11k_err(ab, "failed: %s too small to contain board data, len: %zu\n", 1210 filepath, len); 1211 ret = -EINVAL; 1212 goto err; 1213 } 1214 1215 data += magic_len; 1216 len -= magic_len; 1217 1218 while (len > sizeof(struct ath11k_fw_ie)) { 1219 hdr = (struct ath11k_fw_ie *)data; 1220 ie_id = le32_to_cpu(hdr->id); 1221 ie_len = le32_to_cpu(hdr->len); 1222 1223 len -= sizeof(*hdr); 1224 data = hdr->data; 1225 1226 if (len < ALIGN(ie_len, 4)) { 1227 ath11k_err(ab, "invalid length for board ie_id %d ie_len %zu len %zu\n", 1228 ie_id, ie_len, len); 1229 ret = -EINVAL; 1230 goto err; 1231 } 1232 1233 if (ie_id == ie_id_match) { 1234 ret = ath11k_core_parse_bd_ie_board(ab, bd, data, 1235 ie_len, 1236 boardname, 1237 ie_id_match, 1238 name_id, 1239 data_id); 1240 if (ret == -ENOENT) 1241 /* no match found, continue */ 1242 goto next; 1243 else if (ret) 1244 /* there was an error, bail out */ 1245 goto err; 1246 /* either found or error, so stop searching */ 1247 goto out; 1248 } 1249 next: 1250 /* jump over the padding */ 1251 ie_len = ALIGN(ie_len, 4); 1252 1253 len -= ie_len; 1254 data += ie_len; 1255 } 1256 1257 out: 1258 if (!bd->data || !bd->len) { 1259 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1260 "failed to fetch %s for %s from %s\n", 1261 ath11k_bd_ie_type_str(ie_id_match), 1262 boardname, filepath); 1263 ret = -ENODATA; 1264 goto err; 1265 } 1266 1267 return 0; 1268 1269 err: 1270 ath11k_core_free_bdf(ab, bd); 1271 return ret; 1272 } 1273 1274 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab, 1275 struct ath11k_board_data *bd, 1276 const char *name) 1277 { 1278 bd->fw = ath11k_core_firmware_request(ab, name); 1279 1280 if (IS_ERR(bd->fw)) 1281 return PTR_ERR(bd->fw); 1282 1283 bd->data = bd->fw->data; 1284 bd->len = bd->fw->size; 1285 1286 return 0; 1287 } 1288 1289 #define BOARD_NAME_SIZE 200 1290 int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) 1291 { 1292 char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; 1293 char *filename, filepath[100]; 1294 int ret; 1295 1296 filename = ATH11K_BOARD_API2_FILE; 1297 1298 ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); 1299 if (ret) { 1300 ath11k_err(ab, "failed to create board name: %d", ret); 1301 return ret; 1302 } 1303 1304 ab->bd_api = 2; 1305 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1306 ATH11K_BD_IE_BOARD, 1307 ATH11K_BD_IE_BOARD_NAME, 1308 ATH11K_BD_IE_BOARD_DATA); 1309 if (!ret) 1310 goto success; 1311 1312 ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, 1313 sizeof(fallback_boardname)); 1314 if (ret) { 1315 ath11k_err(ab, "failed to create fallback board name: %d", ret); 1316 return ret; 1317 } 1318 1319 ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, 1320 ATH11K_BD_IE_BOARD, 1321 ATH11K_BD_IE_BOARD_NAME, 1322 ATH11K_BD_IE_BOARD_DATA); 1323 if (!ret) 1324 goto success; 1325 1326 ab->bd_api = 1; 1327 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); 1328 if (ret) { 1329 ath11k_core_create_firmware_path(ab, filename, 1330 filepath, sizeof(filepath)); 1331 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1332 boardname, filepath); 1333 if (memcmp(boardname, fallback_boardname, strlen(boardname))) 1334 ath11k_err(ab, "failed to fetch board data for %s from %s\n", 1335 fallback_boardname, filepath); 1336 1337 ath11k_err(ab, "failed to fetch board.bin from %s\n", 1338 ab->hw_params.fw.dir); 1339 return ret; 1340 } 1341 1342 success: 1343 ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); 1344 return 0; 1345 } 1346 1347 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) 1348 { 1349 char boardname[BOARD_NAME_SIZE], default_boardname[BOARD_NAME_SIZE]; 1350 int ret; 1351 1352 ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); 1353 if (ret) { 1354 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1355 "failed to create board name for regdb: %d", ret); 1356 goto exit; 1357 } 1358 1359 ret = ath11k_core_fetch_board_data_api_n(ab, bd, boardname, 1360 ATH11K_BD_IE_REGDB, 1361 ATH11K_BD_IE_REGDB_NAME, 1362 ATH11K_BD_IE_REGDB_DATA); 1363 if (!ret) 1364 goto exit; 1365 1366 ret = ath11k_core_create_bus_type_board_name(ab, default_boardname, 1367 BOARD_NAME_SIZE); 1368 if (ret) { 1369 ath11k_dbg(ab, ATH11K_DBG_BOOT, 1370 "failed to create default board name for regdb: %d", ret); 1371 goto exit; 1372 } 1373 1374 ret = ath11k_core_fetch_board_data_api_n(ab, bd, default_boardname, 1375 ATH11K_BD_IE_REGDB, 1376 ATH11K_BD_IE_REGDB_NAME, 1377 ATH11K_BD_IE_REGDB_DATA); 1378 if (!ret) 1379 goto exit; 1380 1381 ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_REGDB_FILE_NAME); 1382 if (ret) 1383 ath11k_dbg(ab, ATH11K_DBG_BOOT, "failed to fetch %s from %s\n", 1384 ATH11K_REGDB_FILE_NAME, ab->hw_params.fw.dir); 1385 1386 exit: 1387 if (!ret) 1388 ath11k_dbg(ab, ATH11K_DBG_BOOT, "fetched regdb\n"); 1389 1390 return ret; 1391 } 1392 1393 static void ath11k_core_stop(struct ath11k_base *ab) 1394 { 1395 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 1396 ath11k_qmi_firmware_stop(ab); 1397 1398 ath11k_hif_stop(ab); 1399 ath11k_wmi_detach(ab); 1400 ath11k_dp_pdev_reo_cleanup(ab); 1401 1402 /* De-Init of components as needed */ 1403 } 1404 1405 static int ath11k_core_soc_create(struct ath11k_base *ab) 1406 { 1407 int ret; 1408 1409 if (ath11k_ftm_mode) { 1410 ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; 1411 ath11k_info(ab, "Booting in factory test mode\n"); 1412 } 1413 1414 ret = ath11k_qmi_init_service(ab); 1415 if (ret) { 1416 ath11k_err(ab, "failed to initialize qmi :%d\n", ret); 1417 return ret; 1418 } 1419 1420 ret = ath11k_debugfs_soc_create(ab); 1421 if (ret) { 1422 ath11k_err(ab, "failed to create ath11k debugfs\n"); 1423 goto err_qmi_deinit; 1424 } 1425 1426 ret = ath11k_hif_power_up(ab); 1427 if (ret) { 1428 ath11k_err(ab, "failed to power up :%d\n", ret); 1429 goto err_debugfs_reg; 1430 } 1431 1432 return 0; 1433 1434 err_debugfs_reg: 1435 ath11k_debugfs_soc_destroy(ab); 1436 err_qmi_deinit: 1437 ath11k_qmi_deinit_service(ab); 1438 return ret; 1439 } 1440 1441 static void ath11k_core_soc_destroy(struct ath11k_base *ab) 1442 { 1443 ath11k_debugfs_soc_destroy(ab); 1444 ath11k_dp_free(ab); 1445 ath11k_reg_free(ab); 1446 ath11k_qmi_deinit_service(ab); 1447 } 1448 1449 static int ath11k_core_pdev_create(struct ath11k_base *ab) 1450 { 1451 int ret; 1452 1453 ret = ath11k_debugfs_pdev_create(ab); 1454 if (ret) { 1455 ath11k_err(ab, "failed to create core pdev debugfs: %d\n", ret); 1456 return ret; 1457 } 1458 1459 ret = ath11k_dp_pdev_alloc(ab); 1460 if (ret) { 1461 ath11k_err(ab, "failed to attach DP pdev: %d\n", ret); 1462 goto err_pdev_debug; 1463 } 1464 1465 ret = ath11k_mac_register(ab); 1466 if (ret) { 1467 ath11k_err(ab, "failed register the radio with mac80211: %d\n", ret); 1468 goto err_dp_pdev_free; 1469 } 1470 1471 ret = ath11k_thermal_register(ab); 1472 if (ret) { 1473 ath11k_err(ab, "could not register thermal device: %d\n", 1474 ret); 1475 goto err_mac_unregister; 1476 } 1477 1478 ret = ath11k_spectral_init(ab); 1479 if (ret) { 1480 ath11k_err(ab, "failed to init spectral %d\n", ret); 1481 goto err_thermal_unregister; 1482 } 1483 1484 return 0; 1485 1486 err_thermal_unregister: 1487 ath11k_thermal_unregister(ab); 1488 err_mac_unregister: 1489 ath11k_mac_unregister(ab); 1490 err_dp_pdev_free: 1491 ath11k_dp_pdev_free(ab); 1492 err_pdev_debug: 1493 ath11k_debugfs_pdev_destroy(ab); 1494 1495 return ret; 1496 } 1497 1498 static void ath11k_core_pdev_destroy(struct ath11k_base *ab) 1499 { 1500 ath11k_spectral_deinit(ab); 1501 ath11k_thermal_unregister(ab); 1502 ath11k_mac_unregister(ab); 1503 ath11k_hif_irq_disable(ab); 1504 ath11k_dp_pdev_free(ab); 1505 ath11k_debugfs_pdev_destroy(ab); 1506 } 1507 1508 static int ath11k_core_start(struct ath11k_base *ab) 1509 { 1510 int ret; 1511 1512 ret = ath11k_wmi_attach(ab); 1513 if (ret) { 1514 ath11k_err(ab, "failed to attach wmi: %d\n", ret); 1515 return ret; 1516 } 1517 1518 ret = ath11k_htc_init(ab); 1519 if (ret) { 1520 ath11k_err(ab, "failed to init htc: %d\n", ret); 1521 goto err_wmi_detach; 1522 } 1523 1524 ret = ath11k_hif_start(ab); 1525 if (ret) { 1526 ath11k_err(ab, "failed to start HIF: %d\n", ret); 1527 goto err_wmi_detach; 1528 } 1529 1530 ret = ath11k_htc_wait_target(&ab->htc); 1531 if (ret) { 1532 ath11k_err(ab, "failed to connect to HTC: %d\n", ret); 1533 goto err_hif_stop; 1534 } 1535 1536 ret = ath11k_dp_htt_connect(&ab->dp); 1537 if (ret) { 1538 ath11k_err(ab, "failed to connect to HTT: %d\n", ret); 1539 goto err_hif_stop; 1540 } 1541 1542 ret = ath11k_wmi_connect(ab); 1543 if (ret) { 1544 ath11k_err(ab, "failed to connect wmi: %d\n", ret); 1545 goto err_hif_stop; 1546 } 1547 1548 ret = ath11k_htc_start(&ab->htc); 1549 if (ret) { 1550 ath11k_err(ab, "failed to start HTC: %d\n", ret); 1551 goto err_hif_stop; 1552 } 1553 1554 ret = ath11k_wmi_wait_for_service_ready(ab); 1555 if (ret) { 1556 ath11k_err(ab, "failed to receive wmi service ready event: %d\n", 1557 ret); 1558 goto err_hif_stop; 1559 } 1560 1561 ret = ath11k_mac_allocate(ab); 1562 if (ret) { 1563 ath11k_err(ab, "failed to create new hw device with mac80211 :%d\n", 1564 ret); 1565 goto err_hif_stop; 1566 } 1567 1568 ath11k_dp_pdev_pre_alloc(ab); 1569 1570 ret = ath11k_dp_pdev_reo_setup(ab); 1571 if (ret) { 1572 ath11k_err(ab, "failed to initialize reo destination rings: %d\n", ret); 1573 goto err_mac_destroy; 1574 } 1575 1576 ret = ath11k_wmi_cmd_init(ab); 1577 if (ret) { 1578 ath11k_err(ab, "failed to send wmi init cmd: %d\n", ret); 1579 goto err_reo_cleanup; 1580 } 1581 1582 ret = ath11k_wmi_wait_for_unified_ready(ab); 1583 if (ret) { 1584 ath11k_err(ab, "failed to receive wmi unified ready event: %d\n", 1585 ret); 1586 goto err_reo_cleanup; 1587 } 1588 1589 /* put hardware to DBS mode */ 1590 if (ab->hw_params.single_pdev_only && ab->hw_params.num_rxmda_per_pdev > 1) { 1591 ret = ath11k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); 1592 if (ret) { 1593 ath11k_err(ab, "failed to send dbs mode: %d\n", ret); 1594 goto err_hif_stop; 1595 } 1596 } 1597 1598 ret = ath11k_dp_tx_htt_h2t_ver_req_msg(ab); 1599 if (ret) { 1600 ath11k_err(ab, "failed to send htt version request message: %d\n", 1601 ret); 1602 goto err_reo_cleanup; 1603 } 1604 1605 return 0; 1606 1607 err_reo_cleanup: 1608 ath11k_dp_pdev_reo_cleanup(ab); 1609 err_mac_destroy: 1610 ath11k_mac_destroy(ab); 1611 err_hif_stop: 1612 ath11k_hif_stop(ab); 1613 err_wmi_detach: 1614 ath11k_wmi_detach(ab); 1615 1616 return ret; 1617 } 1618 1619 static int ath11k_core_start_firmware(struct ath11k_base *ab, 1620 enum ath11k_firmware_mode mode) 1621 { 1622 int ret; 1623 1624 ath11k_ce_get_shadow_config(ab, &ab->qmi.ce_cfg.shadow_reg_v2, 1625 &ab->qmi.ce_cfg.shadow_reg_v2_len); 1626 1627 ret = ath11k_qmi_firmware_start(ab, mode); 1628 if (ret) { 1629 ath11k_err(ab, "failed to send firmware start: %d\n", ret); 1630 return ret; 1631 } 1632 1633 return ret; 1634 } 1635 1636 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) 1637 { 1638 int ret; 1639 1640 ret = ath11k_core_start_firmware(ab, ab->fw_mode); 1641 if (ret) { 1642 ath11k_err(ab, "failed to start firmware: %d\n", ret); 1643 return ret; 1644 } 1645 1646 ret = ath11k_ce_init_pipes(ab); 1647 if (ret) { 1648 ath11k_err(ab, "failed to initialize CE: %d\n", ret); 1649 goto err_firmware_stop; 1650 } 1651 1652 ret = ath11k_dp_alloc(ab); 1653 if (ret) { 1654 ath11k_err(ab, "failed to init DP: %d\n", ret); 1655 goto err_firmware_stop; 1656 } 1657 1658 switch (ath11k_crypto_mode) { 1659 case ATH11K_CRYPT_MODE_SW: 1660 set_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1661 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1662 break; 1663 case ATH11K_CRYPT_MODE_HW: 1664 clear_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags); 1665 clear_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1666 break; 1667 default: 1668 ath11k_info(ab, "invalid crypto_mode: %d\n", ath11k_crypto_mode); 1669 return -EINVAL; 1670 } 1671 1672 if (ath11k_frame_mode == ATH11K_HW_TXRX_RAW) 1673 set_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags); 1674 1675 mutex_lock(&ab->core_lock); 1676 ret = ath11k_core_start(ab); 1677 if (ret) { 1678 ath11k_err(ab, "failed to start core: %d\n", ret); 1679 goto err_dp_free; 1680 } 1681 1682 ret = ath11k_core_pdev_create(ab); 1683 if (ret) { 1684 ath11k_err(ab, "failed to create pdev core: %d\n", ret); 1685 goto err_core_stop; 1686 } 1687 ath11k_hif_irq_enable(ab); 1688 mutex_unlock(&ab->core_lock); 1689 1690 return 0; 1691 1692 err_core_stop: 1693 ath11k_core_stop(ab); 1694 ath11k_mac_destroy(ab); 1695 err_dp_free: 1696 ath11k_dp_free(ab); 1697 mutex_unlock(&ab->core_lock); 1698 err_firmware_stop: 1699 ath11k_qmi_firmware_stop(ab); 1700 1701 return ret; 1702 } 1703 1704 static int ath11k_core_reconfigure_on_crash(struct ath11k_base *ab) 1705 { 1706 int ret; 1707 1708 mutex_lock(&ab->core_lock); 1709 ath11k_thermal_unregister(ab); 1710 ath11k_hif_irq_disable(ab); 1711 ath11k_dp_pdev_free(ab); 1712 ath11k_spectral_deinit(ab); 1713 ath11k_hif_stop(ab); 1714 ath11k_wmi_detach(ab); 1715 ath11k_dp_pdev_reo_cleanup(ab); 1716 mutex_unlock(&ab->core_lock); 1717 1718 ath11k_dp_free(ab); 1719 ath11k_hal_srng_deinit(ab); 1720 1721 ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS(ab))) - 1; 1722 1723 ret = ath11k_hal_srng_init(ab); 1724 if (ret) 1725 return ret; 1726 1727 clear_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags); 1728 1729 ret = ath11k_core_qmi_firmware_ready(ab); 1730 if (ret) 1731 goto err_hal_srng_deinit; 1732 1733 clear_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags); 1734 1735 return 0; 1736 1737 err_hal_srng_deinit: 1738 ath11k_hal_srng_deinit(ab); 1739 return ret; 1740 } 1741 1742 void ath11k_core_halt(struct ath11k *ar) 1743 { 1744 struct ath11k_base *ab = ar->ab; 1745 1746 lockdep_assert_held(&ar->conf_mutex); 1747 1748 ar->num_created_vdevs = 0; 1749 ar->allocated_vdev_map = 0; 1750 1751 ath11k_mac_scan_finish(ar); 1752 ath11k_mac_peer_cleanup_all(ar); 1753 cancel_delayed_work_sync(&ar->scan.timeout); 1754 cancel_work_sync(&ar->regd_update_work); 1755 cancel_work_sync(&ab->update_11d_work); 1756 1757 rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); 1758 synchronize_rcu(); 1759 INIT_LIST_HEAD(&ar->arvifs); 1760 idr_init(&ar->txmgmt_idr); 1761 } 1762 1763 static void ath11k_update_11d(struct work_struct *work) 1764 { 1765 struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work); 1766 struct ath11k *ar; 1767 struct ath11k_pdev *pdev; 1768 struct wmi_set_current_country_params set_current_param = {}; 1769 int ret, i; 1770 1771 spin_lock_bh(&ab->base_lock); 1772 memcpy(&set_current_param.alpha2, &ab->new_alpha2, 2); 1773 spin_unlock_bh(&ab->base_lock); 1774 1775 ath11k_dbg(ab, ATH11K_DBG_WMI, "update 11d new cc %c%c\n", 1776 set_current_param.alpha2[0], 1777 set_current_param.alpha2[1]); 1778 1779 for (i = 0; i < ab->num_radios; i++) { 1780 pdev = &ab->pdevs[i]; 1781 ar = pdev->ar; 1782 1783 memcpy(&ar->alpha2, &set_current_param.alpha2, 2); 1784 ret = ath11k_wmi_send_set_current_country_cmd(ar, &set_current_param); 1785 if (ret) 1786 ath11k_warn(ar->ab, 1787 "pdev id %d failed set current country code: %d\n", 1788 i, ret); 1789 } 1790 } 1791 1792 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab) 1793 { 1794 struct ath11k *ar; 1795 struct ath11k_pdev *pdev; 1796 int i; 1797 1798 spin_lock_bh(&ab->base_lock); 1799 ab->stats.fw_crash_counter++; 1800 spin_unlock_bh(&ab->base_lock); 1801 1802 for (i = 0; i < ab->num_radios; i++) { 1803 pdev = &ab->pdevs[i]; 1804 ar = pdev->ar; 1805 if (!ar || ar->state == ATH11K_STATE_OFF || 1806 ar->state == ATH11K_STATE_FTM) 1807 continue; 1808 1809 ieee80211_stop_queues(ar->hw); 1810 ath11k_mac_drain_tx(ar); 1811 ar->state_11d = ATH11K_11D_IDLE; 1812 complete(&ar->completed_11d_scan); 1813 complete(&ar->scan.started); 1814 complete_all(&ar->scan.completed); 1815 complete(&ar->scan.on_channel); 1816 complete(&ar->peer_assoc_done); 1817 complete(&ar->peer_delete_done); 1818 complete(&ar->install_key_done); 1819 complete(&ar->vdev_setup_done); 1820 complete(&ar->vdev_delete_done); 1821 complete(&ar->bss_survey_done); 1822 complete(&ar->thermal.wmi_sync); 1823 1824 wake_up(&ar->dp.tx_empty_waitq); 1825 idr_for_each(&ar->txmgmt_idr, 1826 ath11k_mac_tx_mgmt_pending_free, ar); 1827 idr_destroy(&ar->txmgmt_idr); 1828 wake_up(&ar->txmgmt_empty_waitq); 1829 1830 ar->monitor_vdev_id = -1; 1831 clear_bit(ATH11K_FLAG_MONITOR_STARTED, &ar->monitor_flags); 1832 clear_bit(ATH11K_FLAG_MONITOR_VDEV_CREATED, &ar->monitor_flags); 1833 } 1834 1835 wake_up(&ab->wmi_ab.tx_credits_wq); 1836 wake_up(&ab->peer_mapping_wq); 1837 1838 reinit_completion(&ab->driver_recovery); 1839 } 1840 1841 static void ath11k_core_post_reconfigure_recovery(struct ath11k_base *ab) 1842 { 1843 struct ath11k *ar; 1844 struct ath11k_pdev *pdev; 1845 int i; 1846 1847 for (i = 0; i < ab->num_radios; i++) { 1848 pdev = &ab->pdevs[i]; 1849 ar = pdev->ar; 1850 if (!ar || ar->state == ATH11K_STATE_OFF) 1851 continue; 1852 1853 mutex_lock(&ar->conf_mutex); 1854 1855 switch (ar->state) { 1856 case ATH11K_STATE_ON: 1857 ar->state = ATH11K_STATE_RESTARTING; 1858 ath11k_core_halt(ar); 1859 ieee80211_restart_hw(ar->hw); 1860 break; 1861 case ATH11K_STATE_OFF: 1862 ath11k_warn(ab, 1863 "cannot restart radio %d that hasn't been started\n", 1864 i); 1865 break; 1866 case ATH11K_STATE_RESTARTING: 1867 break; 1868 case ATH11K_STATE_RESTARTED: 1869 ar->state = ATH11K_STATE_WEDGED; 1870 fallthrough; 1871 case ATH11K_STATE_WEDGED: 1872 ath11k_warn(ab, 1873 "device is wedged, will not restart radio %d\n", i); 1874 break; 1875 case ATH11K_STATE_FTM: 1876 ath11k_dbg(ab, ATH11K_DBG_TESTMODE, 1877 "fw mode reset done radio %d\n", i); 1878 break; 1879 } 1880 1881 mutex_unlock(&ar->conf_mutex); 1882 } 1883 complete(&ab->driver_recovery); 1884 } 1885 1886 static void ath11k_core_restart(struct work_struct *work) 1887 { 1888 struct ath11k_base *ab = container_of(work, struct ath11k_base, restart_work); 1889 int ret; 1890 1891 ret = ath11k_core_reconfigure_on_crash(ab); 1892 if (ret) { 1893 ath11k_err(ab, "failed to reconfigure driver on crash recovery\n"); 1894 return; 1895 } 1896 1897 if (ab->is_reset) 1898 complete_all(&ab->reconfigure_complete); 1899 1900 if (!ab->is_reset) 1901 ath11k_core_post_reconfigure_recovery(ab); 1902 } 1903 1904 static void ath11k_core_reset(struct work_struct *work) 1905 { 1906 struct ath11k_base *ab = container_of(work, struct ath11k_base, reset_work); 1907 int reset_count, fail_cont_count; 1908 long time_left; 1909 1910 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags))) { 1911 ath11k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); 1912 return; 1913 } 1914 1915 /* Sometimes the recovery will fail and then the next all recovery fail, 1916 * this is to avoid infinite recovery since it can not recovery success. 1917 */ 1918 fail_cont_count = atomic_read(&ab->fail_cont_count); 1919 1920 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FINAL) 1921 return; 1922 1923 if (fail_cont_count >= ATH11K_RESET_MAX_FAIL_COUNT_FIRST && 1924 time_before(jiffies, ab->reset_fail_timeout)) 1925 return; 1926 1927 reset_count = atomic_inc_return(&ab->reset_count); 1928 1929 if (reset_count > 1) { 1930 /* Sometimes it happened another reset worker before the previous one 1931 * completed, then the second reset worker will destroy the previous one, 1932 * thus below is to avoid that. 1933 */ 1934 ath11k_warn(ab, "already resetting count %d\n", reset_count); 1935 1936 reinit_completion(&ab->reset_complete); 1937 time_left = wait_for_completion_timeout(&ab->reset_complete, 1938 ATH11K_RESET_TIMEOUT_HZ); 1939 1940 if (time_left) { 1941 ath11k_dbg(ab, ATH11K_DBG_BOOT, "to skip reset\n"); 1942 atomic_dec(&ab->reset_count); 1943 return; 1944 } 1945 1946 ab->reset_fail_timeout = jiffies + ATH11K_RESET_FAIL_TIMEOUT_HZ; 1947 /* Record the continuous recovery fail count when recovery failed*/ 1948 atomic_inc(&ab->fail_cont_count); 1949 } 1950 1951 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset starting\n"); 1952 1953 ab->is_reset = true; 1954 atomic_set(&ab->recovery_count, 0); 1955 reinit_completion(&ab->recovery_start); 1956 atomic_set(&ab->recovery_start_count, 0); 1957 1958 ath11k_core_pre_reconfigure_recovery(ab); 1959 1960 reinit_completion(&ab->reconfigure_complete); 1961 ath11k_core_post_reconfigure_recovery(ab); 1962 1963 ath11k_dbg(ab, ATH11K_DBG_BOOT, "waiting recovery start...\n"); 1964 1965 time_left = wait_for_completion_timeout(&ab->recovery_start, 1966 ATH11K_RECOVER_START_TIMEOUT_HZ); 1967 1968 ath11k_hif_power_down(ab); 1969 ath11k_hif_power_up(ab); 1970 1971 ath11k_dbg(ab, ATH11K_DBG_BOOT, "reset started\n"); 1972 } 1973 1974 static int ath11k_init_hw_params(struct ath11k_base *ab) 1975 { 1976 const struct ath11k_hw_params *hw_params = NULL; 1977 int i; 1978 1979 for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { 1980 hw_params = &ath11k_hw_params[i]; 1981 1982 if (hw_params->hw_rev == ab->hw_rev) 1983 break; 1984 } 1985 1986 if (i == ARRAY_SIZE(ath11k_hw_params)) { 1987 ath11k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1988 return -EINVAL; 1989 } 1990 1991 ab->hw_params = *hw_params; 1992 1993 ath11k_info(ab, "%s\n", ab->hw_params.name); 1994 1995 return 0; 1996 } 1997 1998 int ath11k_core_pre_init(struct ath11k_base *ab) 1999 { 2000 int ret; 2001 2002 ret = ath11k_init_hw_params(ab); 2003 if (ret) { 2004 ath11k_err(ab, "failed to get hw params: %d\n", ret); 2005 return ret; 2006 } 2007 2008 return 0; 2009 } 2010 EXPORT_SYMBOL(ath11k_core_pre_init); 2011 2012 int ath11k_core_init(struct ath11k_base *ab) 2013 { 2014 int ret; 2015 2016 ret = ath11k_core_soc_create(ab); 2017 if (ret) { 2018 ath11k_err(ab, "failed to create soc core: %d\n", ret); 2019 return ret; 2020 } 2021 2022 return 0; 2023 } 2024 EXPORT_SYMBOL(ath11k_core_init); 2025 2026 void ath11k_core_deinit(struct ath11k_base *ab) 2027 { 2028 mutex_lock(&ab->core_lock); 2029 2030 ath11k_core_pdev_destroy(ab); 2031 ath11k_core_stop(ab); 2032 2033 mutex_unlock(&ab->core_lock); 2034 2035 ath11k_hif_power_down(ab); 2036 ath11k_mac_destroy(ab); 2037 ath11k_core_soc_destroy(ab); 2038 } 2039 EXPORT_SYMBOL(ath11k_core_deinit); 2040 2041 void ath11k_core_free(struct ath11k_base *ab) 2042 { 2043 destroy_workqueue(ab->workqueue_aux); 2044 destroy_workqueue(ab->workqueue); 2045 2046 kfree(ab); 2047 } 2048 EXPORT_SYMBOL(ath11k_core_free); 2049 2050 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size, 2051 enum ath11k_bus bus) 2052 { 2053 struct ath11k_base *ab; 2054 2055 ab = kzalloc(sizeof(*ab) + priv_size, GFP_KERNEL); 2056 if (!ab) 2057 return NULL; 2058 2059 init_completion(&ab->driver_recovery); 2060 2061 ab->workqueue = create_singlethread_workqueue("ath11k_wq"); 2062 if (!ab->workqueue) 2063 goto err_sc_free; 2064 2065 ab->workqueue_aux = create_singlethread_workqueue("ath11k_aux_wq"); 2066 if (!ab->workqueue_aux) 2067 goto err_free_wq; 2068 2069 mutex_init(&ab->core_lock); 2070 mutex_init(&ab->tbl_mtx_lock); 2071 spin_lock_init(&ab->base_lock); 2072 mutex_init(&ab->vdev_id_11d_lock); 2073 init_completion(&ab->reset_complete); 2074 init_completion(&ab->reconfigure_complete); 2075 init_completion(&ab->recovery_start); 2076 2077 INIT_LIST_HEAD(&ab->peers); 2078 init_waitqueue_head(&ab->peer_mapping_wq); 2079 init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); 2080 init_waitqueue_head(&ab->qmi.cold_boot_waitq); 2081 INIT_WORK(&ab->restart_work, ath11k_core_restart); 2082 INIT_WORK(&ab->update_11d_work, ath11k_update_11d); 2083 INIT_WORK(&ab->reset_work, ath11k_core_reset); 2084 timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0); 2085 init_completion(&ab->htc_suspend); 2086 init_completion(&ab->wow.wakeup_completed); 2087 2088 ab->dev = dev; 2089 ab->hif.bus = bus; 2090 2091 return ab; 2092 2093 err_free_wq: 2094 destroy_workqueue(ab->workqueue); 2095 err_sc_free: 2096 kfree(ab); 2097 return NULL; 2098 } 2099 EXPORT_SYMBOL(ath11k_core_alloc); 2100 2101 MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ax wireless LAN cards."); 2102 MODULE_LICENSE("Dual BSD/GPL"); 2103