1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_CE_H 7 #define ATH11K_CE_H 8 9 #define CE_COUNT 12 10 11 /* Byte swap data words */ 12 #define CE_ATTR_BYTE_SWAP_DATA 2 13 14 /* no interrupt on copy completion */ 15 #define CE_ATTR_DIS_INTR 8 16 17 /* Host software's Copy Engine configuration. */ 18 #ifdef __BIG_ENDIAN 19 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA 20 #else 21 #define CE_ATTR_FLAGS 0 22 #endif 23 24 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 25 #define ATH11K_CE_USAGE_THRESHOLD 32 26 27 void ath11k_ce_byte_swap(void *mem, u32 len); 28 29 /* 30 * Directions for interconnect pipe configuration. 31 * These definitions may be used during configuration and are shared 32 * between Host and Target. 33 * 34 * Pipe Directions are relative to the Host, so PIPEDIR_IN means 35 * "coming IN over air through Target to Host" as with a WiFi Rx operation. 36 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 37 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 38 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 39 * over the interconnect. 40 */ 41 #define PIPEDIR_NONE 0 42 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 43 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 44 #define PIPEDIR_INOUT 3 /* bidirectional */ 45 #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 46 47 /* CE address/mask */ 48 #define CE_HOST_IE_ADDRESS 0x00A1803C 49 #define CE_HOST_IE_2_ADDRESS 0x00A18040 50 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS 51 52 #define CE_HOST_IE_3_SHIFT 0xC 53 54 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 55 56 #define ATH11K_CE_RX_POST_RETRY_JIFFIES 50 57 58 struct ath11k_base; 59 60 /* 61 * Establish a mapping between a service/direction and a pipe. 62 * Configuration information for a Copy Engine pipe and services. 63 * Passed from Host to Target through QMI message and must be in 64 * little endian format. 65 */ 66 struct service_to_pipe { 67 __le32 service_id; 68 __le32 pipedir; 69 __le32 pipenum; 70 }; 71 72 /* 73 * Configuration information for a Copy Engine pipe. 74 * Passed from Host to Target through QMI message during startup (one per CE). 75 * 76 * NOTE: Structure is shared between Host software and Target firmware! 77 */ 78 struct ce_pipe_config { 79 __le32 pipenum; 80 __le32 pipedir; 81 __le32 nentries; 82 __le32 nbytes_max; 83 __le32 flags; 84 __le32 reserved; 85 }; 86 87 struct ce_attr { 88 /* CE_ATTR_* values */ 89 unsigned int flags; 90 91 /* #entries in source ring - Must be a power of 2 */ 92 unsigned int src_nentries; 93 94 /* 95 * Max source send size for this CE. 96 * This is also the minimum size of a destination buffer. 97 */ 98 unsigned int src_sz_max; 99 100 /* #entries in destination ring - Must be a power of 2 */ 101 unsigned int dest_nentries; 102 103 void (*recv_cb)(struct ath11k_base *, struct sk_buff *); 104 }; 105 106 #define CE_DESC_RING_ALIGN 8 107 108 struct ath11k_ce_ring { 109 /* Number of entries in this ring; must be power of 2 */ 110 unsigned int nentries; 111 unsigned int nentries_mask; 112 113 /* For dest ring, this is the next index to be processed 114 * by software after it was/is received into. 115 * 116 * For src ring, this is the last descriptor that was sent 117 * and completion processed by software. 118 * 119 * Regardless of src or dest ring, this is an invariant 120 * (modulo ring size): 121 * write index >= read index >= sw_index 122 */ 123 unsigned int sw_index; 124 /* cached copy */ 125 unsigned int write_index; 126 127 /* Start of DMA-coherent area reserved for descriptors */ 128 /* Host address space */ 129 void *base_addr_owner_space_unaligned; 130 /* CE address space */ 131 u32 base_addr_ce_space_unaligned; 132 133 /* Actual start of descriptors. 134 * Aligned to descriptor-size boundary. 135 * Points into reserved DMA-coherent area, above. 136 */ 137 /* Host address space */ 138 void *base_addr_owner_space; 139 140 /* CE address space */ 141 u32 base_addr_ce_space; 142 143 /* HAL ring id */ 144 u32 hal_ring_id; 145 146 /* keep last */ 147 struct sk_buff *skb[0]; 148 }; 149 150 struct ath11k_ce_pipe { 151 struct ath11k_base *ab; 152 u16 pipe_num; 153 unsigned int attr_flags; 154 unsigned int buf_sz; 155 unsigned int rx_buf_needed; 156 157 void (*send_cb)(struct ath11k_ce_pipe *); 158 void (*recv_cb)(struct ath11k_base *, struct sk_buff *); 159 160 struct tasklet_struct intr_tq; 161 struct ath11k_ce_ring *src_ring; 162 struct ath11k_ce_ring *dest_ring; 163 struct ath11k_ce_ring *status_ring; 164 }; 165 166 struct ath11k_ce { 167 struct ath11k_ce_pipe ce_pipe[CE_COUNT]; 168 /* Protects rings of all ce pipes */ 169 spinlock_t ce_lock; 170 }; 171 172 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab); 173 void ath11k_ce_rx_replenish_retry(struct timer_list *t); 174 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id); 175 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, 176 u16 transfer_id); 177 void ath11k_ce_rx_post_buf(struct ath11k_base *ab); 178 int ath11k_ce_init_pipes(struct ath11k_base *ab); 179 int ath11k_ce_alloc_pipes(struct ath11k_base *ab); 180 void ath11k_ce_free_pipes(struct ath11k_base *ab); 181 int ath11k_ce_get_attr_flags(int ce_id); 182 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id); 183 #endif 184