1d5c65159SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4d5c65159SKalle Valo */ 5d5c65159SKalle Valo 6d5c65159SKalle Valo #ifndef ATH11K_CE_H 7d5c65159SKalle Valo #define ATH11K_CE_H 8d5c65159SKalle Valo 9e3396b8bSCarl Huang #define CE_COUNT_MAX 12 10d5c65159SKalle Valo 11d5c65159SKalle Valo /* Byte swap data words */ 12d5c65159SKalle Valo #define CE_ATTR_BYTE_SWAP_DATA 2 13d5c65159SKalle Valo 14d5c65159SKalle Valo /* no interrupt on copy completion */ 15d5c65159SKalle Valo #define CE_ATTR_DIS_INTR 8 16d5c65159SKalle Valo 17d5c65159SKalle Valo /* Host software's Copy Engine configuration. */ 18d5c65159SKalle Valo #ifdef __BIG_ENDIAN 19d5c65159SKalle Valo #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA 20d5c65159SKalle Valo #else 21d5c65159SKalle Valo #define CE_ATTR_FLAGS 0 22d5c65159SKalle Valo #endif 23d5c65159SKalle Valo 24d5c65159SKalle Valo /* Threshold to poll for tx completion in case of Interrupt disabled CE's */ 25d5c65159SKalle Valo #define ATH11K_CE_USAGE_THRESHOLD 32 26d5c65159SKalle Valo 27d5c65159SKalle Valo void ath11k_ce_byte_swap(void *mem, u32 len); 28d5c65159SKalle Valo 29d5c65159SKalle Valo /* 30d5c65159SKalle Valo * Directions for interconnect pipe configuration. 31d5c65159SKalle Valo * These definitions may be used during configuration and are shared 32d5c65159SKalle Valo * between Host and Target. 33d5c65159SKalle Valo * 34d5c65159SKalle Valo * Pipe Directions are relative to the Host, so PIPEDIR_IN means 35d5c65159SKalle Valo * "coming IN over air through Target to Host" as with a WiFi Rx operation. 36d5c65159SKalle Valo * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" 37d5c65159SKalle Valo * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" 38d5c65159SKalle Valo * Target since things that are "PIPEDIR_OUT" are coming IN to the Target 39d5c65159SKalle Valo * over the interconnect. 40d5c65159SKalle Valo */ 41d5c65159SKalle Valo #define PIPEDIR_NONE 0 42d5c65159SKalle Valo #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ 43d5c65159SKalle Valo #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ 44d5c65159SKalle Valo #define PIPEDIR_INOUT 3 /* bidirectional */ 45d5c65159SKalle Valo #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ 46d5c65159SKalle Valo 47d5c65159SKalle Valo /* CE address/mask */ 48d5c65159SKalle Valo #define CE_HOST_IE_ADDRESS 0x00A1803C 49d5c65159SKalle Valo #define CE_HOST_IE_2_ADDRESS 0x00A18040 50d5c65159SKalle Valo #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS 51d5c65159SKalle Valo 52*b42b3678SSriram R /* CE IE registers are different for IPQ5018 */ 53*b42b3678SSriram R #define CE_HOST_IPQ5018_IE_ADDRESS 0x0841804C 54*b42b3678SSriram R #define CE_HOST_IPQ5018_IE_2_ADDRESS 0x08418050 55*b42b3678SSriram R #define CE_HOST_IPQ5018_IE_3_ADDRESS CE_HOST_IPQ5018_IE_ADDRESS 56*b42b3678SSriram R 57d5c65159SKalle Valo #define CE_HOST_IE_3_SHIFT 0xC 58d5c65159SKalle Valo 59d5c65159SKalle Valo #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask)) 60d5c65159SKalle Valo 61d5c65159SKalle Valo #define ATH11K_CE_RX_POST_RETRY_JIFFIES 50 62d5c65159SKalle Valo 63d5c65159SKalle Valo struct ath11k_base; 64d5c65159SKalle Valo 650c408515SAnilkumar Kolli /* 660c408515SAnilkumar Kolli * Establish a mapping between a service/direction and a pipe. 670c408515SAnilkumar Kolli * Configuration information for a Copy Engine pipe and services. 680c408515SAnilkumar Kolli * Passed from Host to Target through QMI message and must be in 690c408515SAnilkumar Kolli * little endian format. 700c408515SAnilkumar Kolli */ 71d5c65159SKalle Valo struct service_to_pipe { 72d5c65159SKalle Valo __le32 service_id; 73d5c65159SKalle Valo __le32 pipedir; 74d5c65159SKalle Valo __le32 pipenum; 75d5c65159SKalle Valo }; 76d5c65159SKalle Valo 77d5c65159SKalle Valo /* 78d5c65159SKalle Valo * Configuration information for a Copy Engine pipe. 790c408515SAnilkumar Kolli * Passed from Host to Target through QMI message during startup (one per CE). 80d5c65159SKalle Valo * 81d5c65159SKalle Valo * NOTE: Structure is shared between Host software and Target firmware! 82d5c65159SKalle Valo */ 83d5c65159SKalle Valo struct ce_pipe_config { 84d5c65159SKalle Valo __le32 pipenum; 85d5c65159SKalle Valo __le32 pipedir; 86d5c65159SKalle Valo __le32 nentries; 87d5c65159SKalle Valo __le32 nbytes_max; 88d5c65159SKalle Valo __le32 flags; 89d5c65159SKalle Valo __le32 reserved; 90d5c65159SKalle Valo }; 91d5c65159SKalle Valo 92*b42b3678SSriram R struct ce_ie_addr { 93*b42b3678SSriram R u32 ie1_reg_addr; 94*b42b3678SSriram R u32 ie2_reg_addr; 95*b42b3678SSriram R u32 ie3_reg_addr; 96*b42b3678SSriram R }; 97*b42b3678SSriram R 98*b42b3678SSriram R struct ce_remap { 99*b42b3678SSriram R u32 base; 100*b42b3678SSriram R u32 size; 101*b42b3678SSriram R }; 102*b42b3678SSriram R 103d5c65159SKalle Valo struct ce_attr { 104d5c65159SKalle Valo /* CE_ATTR_* values */ 105d5c65159SKalle Valo unsigned int flags; 106d5c65159SKalle Valo 107d5c65159SKalle Valo /* #entries in source ring - Must be a power of 2 */ 108d5c65159SKalle Valo unsigned int src_nentries; 109d5c65159SKalle Valo 110d5c65159SKalle Valo /* 111d5c65159SKalle Valo * Max source send size for this CE. 112d5c65159SKalle Valo * This is also the minimum size of a destination buffer. 113d5c65159SKalle Valo */ 114d5c65159SKalle Valo unsigned int src_sz_max; 115d5c65159SKalle Valo 116d5c65159SKalle Valo /* #entries in destination ring - Must be a power of 2 */ 117d5c65159SKalle Valo unsigned int dest_nentries; 118d5c65159SKalle Valo 119d5c65159SKalle Valo void (*recv_cb)(struct ath11k_base *, struct sk_buff *); 120f951380aSP Praneesh void (*send_cb)(struct ath11k_base *, struct sk_buff *); 121d5c65159SKalle Valo }; 122d5c65159SKalle Valo 123d5c65159SKalle Valo #define CE_DESC_RING_ALIGN 8 124d5c65159SKalle Valo 125d5c65159SKalle Valo struct ath11k_ce_ring { 126d5c65159SKalle Valo /* Number of entries in this ring; must be power of 2 */ 127d5c65159SKalle Valo unsigned int nentries; 128d5c65159SKalle Valo unsigned int nentries_mask; 129d5c65159SKalle Valo 130d5c65159SKalle Valo /* For dest ring, this is the next index to be processed 131d5c65159SKalle Valo * by software after it was/is received into. 132d5c65159SKalle Valo * 133d5c65159SKalle Valo * For src ring, this is the last descriptor that was sent 134d5c65159SKalle Valo * and completion processed by software. 135d5c65159SKalle Valo * 136d5c65159SKalle Valo * Regardless of src or dest ring, this is an invariant 137d5c65159SKalle Valo * (modulo ring size): 138d5c65159SKalle Valo * write index >= read index >= sw_index 139d5c65159SKalle Valo */ 140d5c65159SKalle Valo unsigned int sw_index; 141d5c65159SKalle Valo /* cached copy */ 142d5c65159SKalle Valo unsigned int write_index; 143d5c65159SKalle Valo 144d5c65159SKalle Valo /* Start of DMA-coherent area reserved for descriptors */ 145d5c65159SKalle Valo /* Host address space */ 146d5c65159SKalle Valo void *base_addr_owner_space_unaligned; 147d5c65159SKalle Valo /* CE address space */ 148d5c65159SKalle Valo u32 base_addr_ce_space_unaligned; 149d5c65159SKalle Valo 150d5c65159SKalle Valo /* Actual start of descriptors. 151d5c65159SKalle Valo * Aligned to descriptor-size boundary. 152d5c65159SKalle Valo * Points into reserved DMA-coherent area, above. 153d5c65159SKalle Valo */ 154d5c65159SKalle Valo /* Host address space */ 155d5c65159SKalle Valo void *base_addr_owner_space; 156d5c65159SKalle Valo 157d5c65159SKalle Valo /* CE address space */ 158d5c65159SKalle Valo u32 base_addr_ce_space; 159d5c65159SKalle Valo 160d5c65159SKalle Valo /* HAL ring id */ 161d5c65159SKalle Valo u32 hal_ring_id; 162d5c65159SKalle Valo 163d5c65159SKalle Valo /* keep last */ 164e9e59168SGustavo A. R. Silva struct sk_buff *skb[]; 165d5c65159SKalle Valo }; 166d5c65159SKalle Valo 167d5c65159SKalle Valo struct ath11k_ce_pipe { 168d5c65159SKalle Valo struct ath11k_base *ab; 169d5c65159SKalle Valo u16 pipe_num; 170d5c65159SKalle Valo unsigned int attr_flags; 171d5c65159SKalle Valo unsigned int buf_sz; 172d5c65159SKalle Valo unsigned int rx_buf_needed; 173d5c65159SKalle Valo 174f951380aSP Praneesh void (*send_cb)(struct ath11k_base *, struct sk_buff *); 175d5c65159SKalle Valo void (*recv_cb)(struct ath11k_base *, struct sk_buff *); 176d5c65159SKalle Valo 177d5c65159SKalle Valo struct tasklet_struct intr_tq; 178d5c65159SKalle Valo struct ath11k_ce_ring *src_ring; 179d5c65159SKalle Valo struct ath11k_ce_ring *dest_ring; 180d5c65159SKalle Valo struct ath11k_ce_ring *status_ring; 1815118935bSManikanta Pubbisetty u64 timestamp; 182d5c65159SKalle Valo }; 183d5c65159SKalle Valo 184d5c65159SKalle Valo struct ath11k_ce { 185e3396b8bSCarl Huang struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX]; 186d5c65159SKalle Valo /* Protects rings of all ce pipes */ 187d5c65159SKalle Valo spinlock_t ce_lock; 1889b309970SCarl Huang struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX]; 189d5c65159SKalle Valo }; 190d5c65159SKalle Valo 191e3396b8bSCarl Huang extern const struct ce_attr ath11k_host_ce_config_ipq8074[]; 192e3396b8bSCarl Huang extern const struct ce_attr ath11k_host_ce_config_qca6390[]; 1936289ac2bSKarthikeyan Periyasamy extern const struct ce_attr ath11k_host_ce_config_qcn9074[]; 194e3396b8bSCarl Huang 195d5c65159SKalle Valo void ath11k_ce_cleanup_pipes(struct ath11k_base *ab); 196d5c65159SKalle Valo void ath11k_ce_rx_replenish_retry(struct timer_list *t); 197d5c65159SKalle Valo void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id); 198d5c65159SKalle Valo int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id, 199d5c65159SKalle Valo u16 transfer_id); 200d5c65159SKalle Valo void ath11k_ce_rx_post_buf(struct ath11k_base *ab); 201d5c65159SKalle Valo int ath11k_ce_init_pipes(struct ath11k_base *ab); 202d5c65159SKalle Valo int ath11k_ce_alloc_pipes(struct ath11k_base *ab); 203d5c65159SKalle Valo void ath11k_ce_free_pipes(struct ath11k_base *ab); 204e3396b8bSCarl Huang int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id); 205d5c65159SKalle Valo void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id); 206e838c14aSCarl Huang void ath11k_ce_get_shadow_config(struct ath11k_base *ab, 207e838c14aSCarl Huang u32 **shadow_cfg, u32 *shadow_cfg_len); 208d1b0c338SCarl Huang void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab); 209d1b0c338SCarl Huang 210d5c65159SKalle Valo #endif 211