1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/platform_device.h> 8 #include <linux/of_device.h> 9 #include <linux/of.h> 10 #include <linux/dma-mapping.h> 11 #include "ahb.h" 12 #include "debug.h" 13 #include "hif.h" 14 #include <linux/remoteproc.h> 15 16 static const struct of_device_id ath11k_ahb_of_match[] = { 17 /* TODO: Should we change the compatible string to something similar 18 * to one that ath10k uses? 19 */ 20 { .compatible = "qcom,ipq8074-wifi", 21 .data = (void *)ATH11K_HW_IPQ8074, 22 }, 23 { .compatible = "qcom,ipq6018-wifi", 24 .data = (void *)ATH11K_HW_IPQ6018_HW10, 25 }, 26 { } 27 }; 28 29 MODULE_DEVICE_TABLE(of, ath11k_ahb_of_match); 30 31 static const struct ath11k_bus_params ath11k_ahb_bus_params = { 32 .mhi_support = false, 33 .m3_fw_support = false, 34 .fixed_bdf_addr = true, 35 .fixed_mem_region = true, 36 }; 37 38 #define ATH11K_IRQ_CE0_OFFSET 4 39 40 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 41 "misc-pulse1", 42 "misc-latch", 43 "sw-exception", 44 "watchdog", 45 "ce0", 46 "ce1", 47 "ce2", 48 "ce3", 49 "ce4", 50 "ce5", 51 "ce6", 52 "ce7", 53 "ce8", 54 "ce9", 55 "ce10", 56 "ce11", 57 "host2wbm-desc-feed", 58 "host2reo-re-injection", 59 "host2reo-command", 60 "host2rxdma-monitor-ring3", 61 "host2rxdma-monitor-ring2", 62 "host2rxdma-monitor-ring1", 63 "reo2ost-exception", 64 "wbm2host-rx-release", 65 "reo2host-status", 66 "reo2host-destination-ring4", 67 "reo2host-destination-ring3", 68 "reo2host-destination-ring2", 69 "reo2host-destination-ring1", 70 "rxdma2host-monitor-destination-mac3", 71 "rxdma2host-monitor-destination-mac2", 72 "rxdma2host-monitor-destination-mac1", 73 "ppdu-end-interrupts-mac3", 74 "ppdu-end-interrupts-mac2", 75 "ppdu-end-interrupts-mac1", 76 "rxdma2host-monitor-status-ring-mac3", 77 "rxdma2host-monitor-status-ring-mac2", 78 "rxdma2host-monitor-status-ring-mac1", 79 "host2rxdma-host-buf-ring-mac3", 80 "host2rxdma-host-buf-ring-mac2", 81 "host2rxdma-host-buf-ring-mac1", 82 "rxdma2host-destination-ring-mac3", 83 "rxdma2host-destination-ring-mac2", 84 "rxdma2host-destination-ring-mac1", 85 "host2tcl-input-ring4", 86 "host2tcl-input-ring3", 87 "host2tcl-input-ring2", 88 "host2tcl-input-ring1", 89 "wbm2host-tx-completions-ring3", 90 "wbm2host-tx-completions-ring2", 91 "wbm2host-tx-completions-ring1", 92 "tcl2host-status-ring", 93 }; 94 95 /* enum ext_irq_num - irq numbers that can be used by external modules 96 * like datapath 97 */ 98 enum ext_irq_num { 99 host2wbm_desc_feed = 16, 100 host2reo_re_injection, 101 host2reo_command, 102 host2rxdma_monitor_ring3, 103 host2rxdma_monitor_ring2, 104 host2rxdma_monitor_ring1, 105 reo2host_exception, 106 wbm2host_rx_release, 107 reo2host_status, 108 reo2host_destination_ring4, 109 reo2host_destination_ring3, 110 reo2host_destination_ring2, 111 reo2host_destination_ring1, 112 rxdma2host_monitor_destination_mac3, 113 rxdma2host_monitor_destination_mac2, 114 rxdma2host_monitor_destination_mac1, 115 ppdu_end_interrupts_mac3, 116 ppdu_end_interrupts_mac2, 117 ppdu_end_interrupts_mac1, 118 rxdma2host_monitor_status_ring_mac3, 119 rxdma2host_monitor_status_ring_mac2, 120 rxdma2host_monitor_status_ring_mac1, 121 host2rxdma_host_buf_ring_mac3, 122 host2rxdma_host_buf_ring_mac2, 123 host2rxdma_host_buf_ring_mac1, 124 rxdma2host_destination_ring_mac3, 125 rxdma2host_destination_ring_mac2, 126 rxdma2host_destination_ring_mac1, 127 host2tcl_input_ring4, 128 host2tcl_input_ring3, 129 host2tcl_input_ring2, 130 host2tcl_input_ring1, 131 wbm2host_tx_completions_ring3, 132 wbm2host_tx_completions_ring2, 133 wbm2host_tx_completions_ring1, 134 tcl2host_status_ring, 135 }; 136 137 static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset) 138 { 139 return ioread32(ab->mem + offset); 140 } 141 142 static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value) 143 { 144 iowrite32(value, ab->mem + offset); 145 } 146 147 static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab) 148 { 149 int i; 150 151 for (i = 0; i < ab->hw_params.ce_count; i++) { 152 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 153 154 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 155 continue; 156 157 tasklet_kill(&ce_pipe->intr_tq); 158 } 159 } 160 161 static void ath11k_ahb_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 162 { 163 int i; 164 165 for (i = 0; i < irq_grp->num_irq; i++) 166 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 167 } 168 169 static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) 170 { 171 int i; 172 173 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 174 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 175 176 ath11k_ahb_ext_grp_disable(irq_grp); 177 178 napi_synchronize(&irq_grp->napi); 179 napi_disable(&irq_grp->napi); 180 } 181 } 182 183 static void ath11k_ahb_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 184 { 185 int i; 186 187 for (i = 0; i < irq_grp->num_irq; i++) 188 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 189 } 190 191 static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset) 192 { 193 u32 val; 194 195 val = ath11k_ahb_read32(ab, offset); 196 ath11k_ahb_write32(ab, offset, val | BIT(bit)); 197 } 198 199 static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset) 200 { 201 u32 val; 202 203 val = ath11k_ahb_read32(ab, offset); 204 ath11k_ahb_write32(ab, offset, val & ~BIT(bit)); 205 } 206 207 static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 208 { 209 const struct ce_pipe_config *ce_config; 210 211 ce_config = &ab->hw_params.target_ce_config[ce_id]; 212 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT) 213 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_ADDRESS); 214 215 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) { 216 ath11k_ahb_setbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); 217 ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, 218 CE_HOST_IE_3_ADDRESS); 219 } 220 } 221 222 static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 223 { 224 const struct ce_pipe_config *ce_config; 225 226 ce_config = &ab->hw_params.target_ce_config[ce_id]; 227 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_OUT) 228 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_ADDRESS); 229 230 if (__le32_to_cpu(ce_config->pipedir) & PIPEDIR_IN) { 231 ath11k_ahb_clearbit32(ab, ce_id, CE_HOST_IE_2_ADDRESS); 232 ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT, 233 CE_HOST_IE_3_ADDRESS); 234 } 235 } 236 237 static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab) 238 { 239 int i; 240 int irq_idx; 241 242 for (i = 0; i < ab->hw_params.ce_count; i++) { 243 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 244 continue; 245 246 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 247 synchronize_irq(ab->irq_num[irq_idx]); 248 } 249 } 250 251 static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab) 252 { 253 int i, j; 254 int irq_idx; 255 256 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 257 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 258 259 for (j = 0; j < irq_grp->num_irq; j++) { 260 irq_idx = irq_grp->irqs[j]; 261 synchronize_irq(ab->irq_num[irq_idx]); 262 } 263 } 264 } 265 266 static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab) 267 { 268 int i; 269 270 for (i = 0; i < ab->hw_params.ce_count; i++) { 271 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 272 continue; 273 ath11k_ahb_ce_irq_enable(ab, i); 274 } 275 } 276 277 static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab) 278 { 279 int i; 280 281 for (i = 0; i < ab->hw_params.ce_count; i++) { 282 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 283 continue; 284 ath11k_ahb_ce_irq_disable(ab, i); 285 } 286 } 287 288 static int ath11k_ahb_start(struct ath11k_base *ab) 289 { 290 ath11k_ahb_ce_irqs_enable(ab); 291 ath11k_ce_rx_post_buf(ab); 292 293 return 0; 294 } 295 296 static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab) 297 { 298 int i; 299 300 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 301 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 302 303 napi_enable(&irq_grp->napi); 304 ath11k_ahb_ext_grp_enable(irq_grp); 305 } 306 } 307 308 static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab) 309 { 310 __ath11k_ahb_ext_irq_disable(ab); 311 ath11k_ahb_sync_ext_irqs(ab); 312 } 313 314 static void ath11k_ahb_stop(struct ath11k_base *ab) 315 { 316 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags)) 317 ath11k_ahb_ce_irqs_disable(ab); 318 ath11k_ahb_sync_ce_irqs(ab); 319 ath11k_ahb_kill_tasklets(ab); 320 del_timer_sync(&ab->rx_replenish_retry); 321 ath11k_ce_cleanup_pipes(ab); 322 } 323 324 static int ath11k_ahb_power_up(struct ath11k_base *ab) 325 { 326 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 327 int ret; 328 329 ret = rproc_boot(ab_ahb->tgt_rproc); 330 if (ret) 331 ath11k_err(ab, "failed to boot the remote processor Q6\n"); 332 333 return ret; 334 } 335 336 static void ath11k_ahb_power_down(struct ath11k_base *ab) 337 { 338 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 339 340 rproc_shutdown(ab_ahb->tgt_rproc); 341 } 342 343 static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab) 344 { 345 int timeout; 346 347 if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done || 348 ab->hw_params.cold_boot_calib == 0) 349 return 0; 350 351 ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n"); 352 timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, 353 (ab->qmi.cal_done == 1), 354 ATH11K_COLD_BOOT_FW_RESET_DELAY); 355 if (timeout <= 0) { 356 ath11k_cold_boot_cal = 0; 357 ath11k_warn(ab, "Coldboot Calibration failed timed out\n"); 358 } 359 360 /* reset the firmware */ 361 ath11k_ahb_power_down(ab); 362 ath11k_ahb_power_up(ab); 363 364 ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n"); 365 return 0; 366 } 367 368 static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab) 369 { 370 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 371 372 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 373 cfg->tgt_ce = ab->hw_params.target_ce_config; 374 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 375 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 376 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 377 } 378 379 static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab) 380 { 381 int i, j; 382 383 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 384 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 385 386 for (j = 0; j < irq_grp->num_irq; j++) 387 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 388 } 389 } 390 391 static void ath11k_ahb_free_irq(struct ath11k_base *ab) 392 { 393 int irq_idx; 394 int i; 395 396 for (i = 0; i < ab->hw_params.ce_count; i++) { 397 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 398 continue; 399 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 400 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 401 } 402 403 ath11k_ahb_free_ext_irq(ab); 404 } 405 406 static void ath11k_ahb_ce_tasklet(struct tasklet_struct *t) 407 { 408 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 409 410 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 411 412 ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 413 } 414 415 static irqreturn_t ath11k_ahb_ce_interrupt_handler(int irq, void *arg) 416 { 417 struct ath11k_ce_pipe *ce_pipe = arg; 418 419 /* last interrupt received for this CE */ 420 ce_pipe->timestamp = jiffies; 421 422 ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 423 424 tasklet_schedule(&ce_pipe->intr_tq); 425 426 return IRQ_HANDLED; 427 } 428 429 static int ath11k_ahb_ext_grp_napi_poll(struct napi_struct *napi, int budget) 430 { 431 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 432 struct ath11k_ext_irq_grp, 433 napi); 434 struct ath11k_base *ab = irq_grp->ab; 435 int work_done; 436 437 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 438 if (work_done < budget) { 439 napi_complete_done(napi, work_done); 440 ath11k_ahb_ext_grp_enable(irq_grp); 441 } 442 443 if (work_done > budget) 444 work_done = budget; 445 446 return work_done; 447 } 448 449 static irqreturn_t ath11k_ahb_ext_interrupt_handler(int irq, void *arg) 450 { 451 struct ath11k_ext_irq_grp *irq_grp = arg; 452 453 /* last interrupt received for this group */ 454 irq_grp->timestamp = jiffies; 455 456 ath11k_ahb_ext_grp_disable(irq_grp); 457 458 napi_schedule(&irq_grp->napi); 459 460 return IRQ_HANDLED; 461 } 462 463 static int ath11k_ahb_ext_irq_config(struct ath11k_base *ab) 464 { 465 struct ath11k_hw_params *hw = &ab->hw_params; 466 int i, j; 467 int irq; 468 int ret; 469 470 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 471 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 472 u32 num_irq = 0; 473 474 irq_grp->ab = ab; 475 irq_grp->grp_id = i; 476 init_dummy_netdev(&irq_grp->napi_ndev); 477 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 478 ath11k_ahb_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 479 480 for (j = 0; j < ATH11K_EXT_IRQ_NUM_MAX; j++) { 481 if (ab->hw_params.ring_mask->tx[i] & BIT(j)) { 482 irq_grp->irqs[num_irq++] = 483 wbm2host_tx_completions_ring1 - j; 484 } 485 486 if (ab->hw_params.ring_mask->rx[i] & BIT(j)) { 487 irq_grp->irqs[num_irq++] = 488 reo2host_destination_ring1 - j; 489 } 490 491 if (ab->hw_params.ring_mask->rx_err[i] & BIT(j)) 492 irq_grp->irqs[num_irq++] = reo2host_exception; 493 494 if (ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j)) 495 irq_grp->irqs[num_irq++] = wbm2host_rx_release; 496 497 if (ab->hw_params.ring_mask->reo_status[i] & BIT(j)) 498 irq_grp->irqs[num_irq++] = reo2host_status; 499 500 if (j < ab->hw_params.max_radios) { 501 if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) { 502 irq_grp->irqs[num_irq++] = 503 rxdma2host_destination_ring_mac1 - 504 ath11k_hw_get_mac_from_pdev_id(hw, j); 505 } 506 507 if (ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) { 508 irq_grp->irqs[num_irq++] = 509 host2rxdma_host_buf_ring_mac1 - 510 ath11k_hw_get_mac_from_pdev_id(hw, j); 511 } 512 513 if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) { 514 irq_grp->irqs[num_irq++] = 515 ppdu_end_interrupts_mac1 - 516 ath11k_hw_get_mac_from_pdev_id(hw, j); 517 irq_grp->irqs[num_irq++] = 518 rxdma2host_monitor_status_ring_mac1 - 519 ath11k_hw_get_mac_from_pdev_id(hw, j); 520 } 521 } 522 } 523 irq_grp->num_irq = num_irq; 524 525 for (j = 0; j < irq_grp->num_irq; j++) { 526 int irq_idx = irq_grp->irqs[j]; 527 528 irq = platform_get_irq_byname(ab->pdev, 529 irq_name[irq_idx]); 530 ab->irq_num[irq_idx] = irq; 531 irq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_DISABLE_UNLAZY); 532 ret = request_irq(irq, ath11k_ahb_ext_interrupt_handler, 533 IRQF_TRIGGER_RISING, 534 irq_name[irq_idx], irq_grp); 535 if (ret) { 536 ath11k_err(ab, "failed request_irq for %d\n", 537 irq); 538 } 539 } 540 } 541 542 return 0; 543 } 544 545 static int ath11k_ahb_config_irq(struct ath11k_base *ab) 546 { 547 int irq, irq_idx, i; 548 int ret; 549 550 /* Configure CE irqs */ 551 for (i = 0; i < ab->hw_params.ce_count; i++) { 552 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 553 554 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 555 continue; 556 557 irq_idx = ATH11K_IRQ_CE0_OFFSET + i; 558 559 tasklet_setup(&ce_pipe->intr_tq, ath11k_ahb_ce_tasklet); 560 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]); 561 ret = request_irq(irq, ath11k_ahb_ce_interrupt_handler, 562 IRQF_TRIGGER_RISING, irq_name[irq_idx], 563 ce_pipe); 564 if (ret) 565 return ret; 566 567 ab->irq_num[irq_idx] = irq; 568 } 569 570 /* Configure external interrupts */ 571 ret = ath11k_ahb_ext_irq_config(ab); 572 573 return ret; 574 } 575 576 static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 577 u8 *ul_pipe, u8 *dl_pipe) 578 { 579 const struct service_to_pipe *entry; 580 bool ul_set = false, dl_set = false; 581 int i; 582 583 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 584 entry = &ab->hw_params.svc_to_ce_map[i]; 585 586 if (__le32_to_cpu(entry->service_id) != service_id) 587 continue; 588 589 switch (__le32_to_cpu(entry->pipedir)) { 590 case PIPEDIR_NONE: 591 break; 592 case PIPEDIR_IN: 593 WARN_ON(dl_set); 594 *dl_pipe = __le32_to_cpu(entry->pipenum); 595 dl_set = true; 596 break; 597 case PIPEDIR_OUT: 598 WARN_ON(ul_set); 599 *ul_pipe = __le32_to_cpu(entry->pipenum); 600 ul_set = true; 601 break; 602 case PIPEDIR_INOUT: 603 WARN_ON(dl_set); 604 WARN_ON(ul_set); 605 *dl_pipe = __le32_to_cpu(entry->pipenum); 606 *ul_pipe = __le32_to_cpu(entry->pipenum); 607 dl_set = true; 608 ul_set = true; 609 break; 610 } 611 } 612 613 if (WARN_ON(!ul_set || !dl_set)) 614 return -ENOENT; 615 616 return 0; 617 } 618 619 static const struct ath11k_hif_ops ath11k_ahb_hif_ops = { 620 .start = ath11k_ahb_start, 621 .stop = ath11k_ahb_stop, 622 .read32 = ath11k_ahb_read32, 623 .write32 = ath11k_ahb_write32, 624 .irq_enable = ath11k_ahb_ext_irq_enable, 625 .irq_disable = ath11k_ahb_ext_irq_disable, 626 .map_service_to_pipe = ath11k_ahb_map_service_to_pipe, 627 .power_down = ath11k_ahb_power_down, 628 .power_up = ath11k_ahb_power_up, 629 }; 630 631 static int ath11k_core_get_rproc(struct ath11k_base *ab) 632 { 633 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab); 634 struct device *dev = ab->dev; 635 struct rproc *prproc; 636 phandle rproc_phandle; 637 638 if (of_property_read_u32(dev->of_node, "qcom,rproc", &rproc_phandle)) { 639 ath11k_err(ab, "failed to get q6_rproc handle\n"); 640 return -ENOENT; 641 } 642 643 prproc = rproc_get_by_phandle(rproc_phandle); 644 if (!prproc) { 645 ath11k_err(ab, "failed to get rproc\n"); 646 return -EINVAL; 647 } 648 ab_ahb->tgt_rproc = prproc; 649 650 return 0; 651 } 652 653 static int ath11k_ahb_probe(struct platform_device *pdev) 654 { 655 struct ath11k_base *ab; 656 const struct of_device_id *of_id; 657 struct resource *mem_res; 658 void __iomem *mem; 659 int ret; 660 661 of_id = of_match_device(ath11k_ahb_of_match, &pdev->dev); 662 if (!of_id) { 663 dev_err(&pdev->dev, "failed to find matching device tree id\n"); 664 return -EINVAL; 665 } 666 667 mem = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 668 if (IS_ERR(mem)) { 669 dev_err(&pdev->dev, "ioremap error\n"); 670 return PTR_ERR(mem); 671 } 672 673 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 674 if (ret) { 675 dev_err(&pdev->dev, "failed to set 32-bit consistent dma\n"); 676 return ret; 677 } 678 679 ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb), 680 ATH11K_BUS_AHB, 681 &ath11k_ahb_bus_params); 682 if (!ab) { 683 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 684 return -ENOMEM; 685 } 686 687 ab->hif.ops = &ath11k_ahb_hif_ops; 688 ab->pdev = pdev; 689 ab->hw_rev = (enum ath11k_hw_rev)of_id->data; 690 ab->mem = mem; 691 ab->mem_len = resource_size(mem_res); 692 platform_set_drvdata(pdev, ab); 693 694 ret = ath11k_core_pre_init(ab); 695 if (ret) 696 goto err_core_free; 697 698 ret = ath11k_hal_srng_init(ab); 699 if (ret) 700 goto err_core_free; 701 702 ret = ath11k_ce_alloc_pipes(ab); 703 if (ret) { 704 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 705 goto err_hal_srng_deinit; 706 } 707 708 ath11k_ahb_init_qmi_ce_config(ab); 709 710 ret = ath11k_core_get_rproc(ab); 711 if (ret) { 712 ath11k_err(ab, "failed to get rproc: %d\n", ret); 713 goto err_ce_free; 714 } 715 716 ret = ath11k_core_init(ab); 717 if (ret) { 718 ath11k_err(ab, "failed to init core: %d\n", ret); 719 goto err_ce_free; 720 } 721 722 ret = ath11k_ahb_config_irq(ab); 723 if (ret) { 724 ath11k_err(ab, "failed to configure irq: %d\n", ret); 725 goto err_ce_free; 726 } 727 728 ath11k_ahb_fwreset_from_cold_boot(ab); 729 730 return 0; 731 732 err_ce_free: 733 ath11k_ce_free_pipes(ab); 734 735 err_hal_srng_deinit: 736 ath11k_hal_srng_deinit(ab); 737 738 err_core_free: 739 ath11k_core_free(ab); 740 platform_set_drvdata(pdev, NULL); 741 742 return ret; 743 } 744 745 static int ath11k_ahb_remove(struct platform_device *pdev) 746 { 747 struct ath11k_base *ab = platform_get_drvdata(pdev); 748 unsigned long left; 749 750 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 751 ath11k_ahb_power_down(ab); 752 ath11k_debugfs_soc_destroy(ab); 753 ath11k_qmi_deinit_service(ab); 754 goto qmi_fail; 755 } 756 757 reinit_completion(&ab->driver_recovery); 758 759 if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) { 760 left = wait_for_completion_timeout(&ab->driver_recovery, 761 ATH11K_AHB_RECOVERY_TIMEOUT); 762 if (!left) 763 ath11k_warn(ab, "failed to receive recovery response completion\n"); 764 } 765 766 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 767 cancel_work_sync(&ab->restart_work); 768 769 ath11k_core_deinit(ab); 770 qmi_fail: 771 ath11k_ahb_free_irq(ab); 772 ath11k_hal_srng_deinit(ab); 773 ath11k_ce_free_pipes(ab); 774 ath11k_core_free(ab); 775 platform_set_drvdata(pdev, NULL); 776 777 return 0; 778 } 779 780 static struct platform_driver ath11k_ahb_driver = { 781 .driver = { 782 .name = "ath11k", 783 .of_match_table = ath11k_ahb_of_match, 784 }, 785 .probe = ath11k_ahb_probe, 786 .remove = ath11k_ahb_remove, 787 }; 788 789 static int ath11k_ahb_init(void) 790 { 791 return platform_driver_register(&ath11k_ahb_driver); 792 } 793 module_init(ath11k_ahb_init); 794 795 static void ath11k_ahb_exit(void) 796 { 797 platform_driver_unregister(&ath11k_ahb_driver); 798 } 799 module_exit(ath11k_ahb_exit); 800 801 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN AHB devices"); 802 MODULE_LICENSE("Dual BSD/GPL"); 803