1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __TARGADDRS_H__ 19 #define __TARGADDRS_H__ 20 21 #include "hw.h" 22 23 /* 24 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the 25 * host_interest structure. It must match the address of the _host_interest 26 * symbol (see linker script). 27 * 28 * Host Interest is shared between Host and Target in order to coordinate 29 * between the two, and is intended to remain constant (with additions only 30 * at the end) across software releases. 31 * 32 * All addresses are available here so that it's possible to 33 * write a single binary that works with all Target Types. 34 * May be used in assembler code as well as C. 35 */ 36 #define QCA988X_HOST_INTEREST_ADDRESS 0x00400800 37 #define HOST_INTEREST_MAX_SIZE 0x200 38 39 /* 40 * These are items that the Host may need to access via BMI or via the 41 * Diagnostic Window. The position of items in this structure must remain 42 * constant across firmware revisions! Types for each item must be fixed 43 * size across target and host platforms. More items may be added at the end. 44 */ 45 struct host_interest { 46 /* 47 * Pointer to application-defined area, if any. 48 * Set by Target application during startup. 49 */ 50 u32 hi_app_host_interest; /* 0x00 */ 51 52 /* Pointer to register dump area, valid after Target crash. */ 53 u32 hi_failure_state; /* 0x04 */ 54 55 /* Pointer to debug logging header */ 56 u32 hi_dbglog_hdr; /* 0x08 */ 57 58 u32 hi_unused0c; /* 0x0c */ 59 60 /* 61 * General-purpose flag bits, similar to SOC_OPTION_* flags. 62 * Can be used by application rather than by OS. 63 */ 64 u32 hi_option_flag; /* 0x10 */ 65 66 /* 67 * Boolean that determines whether or not to 68 * display messages on the serial port. 69 */ 70 u32 hi_serial_enable; /* 0x14 */ 71 72 /* Start address of DataSet index, if any */ 73 u32 hi_dset_list_head; /* 0x18 */ 74 75 /* Override Target application start address */ 76 u32 hi_app_start; /* 0x1c */ 77 78 /* Clock and voltage tuning */ 79 u32 hi_skip_clock_init; /* 0x20 */ 80 u32 hi_core_clock_setting; /* 0x24 */ 81 u32 hi_cpu_clock_setting; /* 0x28 */ 82 u32 hi_system_sleep_setting; /* 0x2c */ 83 u32 hi_xtal_control_setting; /* 0x30 */ 84 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ 85 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ 86 u32 hi_ref_voltage_trim_setting; /* 0x3c */ 87 u32 hi_clock_info; /* 0x40 */ 88 89 /* Host uses BE CPU or not */ 90 u32 hi_be; /* 0x44 */ 91 92 u32 hi_stack; /* normal stack */ /* 0x48 */ 93 u32 hi_err_stack; /* error stack */ /* 0x4c */ 94 u32 hi_desired_cpu_speed_hz; /* 0x50 */ 95 96 /* Pointer to Board Data */ 97 u32 hi_board_data; /* 0x54 */ 98 99 /* 100 * Indication of Board Data state: 101 * 0: board data is not yet initialized. 102 * 1: board data is initialized; unknown size 103 * >1: number of bytes of initialized board data 104 */ 105 u32 hi_board_data_initialized; /* 0x58 */ 106 107 u32 hi_dset_ram_index_table; /* 0x5c */ 108 109 u32 hi_desired_baud_rate; /* 0x60 */ 110 u32 hi_dbglog_config; /* 0x64 */ 111 u32 hi_end_ram_reserve_sz; /* 0x68 */ 112 u32 hi_mbox_io_block_sz; /* 0x6c */ 113 114 u32 hi_num_bpatch_streams; /* 0x70 -- unused */ 115 u32 hi_mbox_isr_yield_limit; /* 0x74 */ 116 117 u32 hi_refclk_hz; /* 0x78 */ 118 u32 hi_ext_clk_detected; /* 0x7c */ 119 u32 hi_dbg_uart_txpin; /* 0x80 */ 120 u32 hi_dbg_uart_rxpin; /* 0x84 */ 121 u32 hi_hci_uart_baud; /* 0x88 */ 122 u32 hi_hci_uart_pin_assignments; /* 0x8C */ 123 124 u32 hi_hci_uart_baud_scale_val; /* 0x90 */ 125 u32 hi_hci_uart_baud_step_val; /* 0x94 */ 126 127 u32 hi_allocram_start; /* 0x98 */ 128 u32 hi_allocram_sz; /* 0x9c */ 129 u32 hi_hci_bridge_flags; /* 0xa0 */ 130 u32 hi_hci_uart_support_pins; /* 0xa4 */ 131 132 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ 133 134 /* 135 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high 136 * [31:16]: wakeup timeout in ms 137 */ 138 /* Pointer to extended board Data */ 139 u32 hi_board_ext_data; /* 0xac */ 140 u32 hi_board_ext_data_config; /* 0xb0 */ 141 /* 142 * Bit [0] : valid 143 * Bit[31:16: size 144 */ 145 /* 146 * hi_reset_flag is used to do some stuff when target reset. 147 * such as restore app_start after warm reset or 148 * preserve host Interest area, or preserve ROM data, literals etc. 149 */ 150 u32 hi_reset_flag; /* 0xb4 */ 151 /* indicate hi_reset_flag is valid */ 152 u32 hi_reset_flag_valid; /* 0xb8 */ 153 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ 154 /* 0xbc - [31:0]: idle timeout in ms */ 155 /* ACS flags */ 156 u32 hi_acs_flags; /* 0xc0 */ 157 u32 hi_console_flags; /* 0xc4 */ 158 u32 hi_nvram_state; /* 0xc8 */ 159 u32 hi_option_flag2; /* 0xcc */ 160 161 /* If non-zero, override values sent to Host in WMI_READY event. */ 162 u32 hi_sw_version_override; /* 0xd0 */ 163 u32 hi_abi_version_override; /* 0xd4 */ 164 165 /* 166 * Percentage of high priority RX traffic to total expected RX traffic 167 * applicable only to ar6004 168 */ 169 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ 170 171 /* test applications flags */ 172 u32 hi_test_apps_related; /* 0xdc */ 173 /* location of test script */ 174 u32 hi_ota_testscript; /* 0xe0 */ 175 /* location of CAL data */ 176 u32 hi_cal_data; /* 0xe4 */ 177 178 /* Number of packet log buffers */ 179 u32 hi_pktlog_num_buffers; /* 0xe8 */ 180 181 /* wow extension configuration */ 182 u32 hi_wow_ext_config; /* 0xec */ 183 u32 hi_pwr_save_flags; /* 0xf0 */ 184 185 /* Spatial Multiplexing Power Save (SMPS) options */ 186 u32 hi_smps_options; /* 0xf4 */ 187 188 /* Interconnect-specific state */ 189 u32 hi_interconnect_state; /* 0xf8 */ 190 191 /* Coex configuration flags */ 192 u32 hi_coex_config; /* 0xfc */ 193 194 /* Early allocation support */ 195 u32 hi_early_alloc; /* 0x100 */ 196 /* FW swap field */ 197 /* 198 * Bits of this 32bit word will be used to pass specific swap 199 * instruction to FW 200 */ 201 /* 202 * Bit 0 -- AP Nart descriptor no swap. When this bit is set 203 * FW will not swap TX descriptor. Meaning packets are formed 204 * on the target processor. 205 */ 206 /* Bit 1 - unused */ 207 u32 hi_fw_swap; /* 0x104 */ 208 } __packed; 209 210 #define HI_ITEM(item) offsetof(struct host_interest, item) 211 212 /* Bits defined in hi_option_flag */ 213 214 /* Enable timer workaround */ 215 #define HI_OPTION_TIMER_WAR 0x01 216 /* Limit BMI command credits */ 217 #define HI_OPTION_BMI_CRED_LIMIT 0x02 218 /* Relay Dot11 hdr to/from host */ 219 #define HI_OPTION_RELAY_DOT11_HDR 0x04 220 /* MAC addr method 0-locally administred 1-globally unique addrs */ 221 #define HI_OPTION_MAC_ADDR_METHOD 0x08 222 /* Firmware Bridging */ 223 #define HI_OPTION_FW_BRIDGE 0x10 224 /* Enable CPU profiling */ 225 #define HI_OPTION_ENABLE_PROFILE 0x20 226 /* Disable debug logging */ 227 #define HI_OPTION_DISABLE_DBGLOG 0x40 228 /* Skip Era Tracking */ 229 #define HI_OPTION_SKIP_ERA_TRACKING 0x80 230 /* Disable PAPRD (debug) */ 231 #define HI_OPTION_PAPRD_DISABLE 0x100 232 #define HI_OPTION_NUM_DEV_LSB 0x200 233 #define HI_OPTION_NUM_DEV_MSB 0x800 234 #define HI_OPTION_DEV_MODE_LSB 0x1000 235 #define HI_OPTION_DEV_MODE_MSB 0x8000000 236 /* Disable LowFreq Timer Stabilization */ 237 #define HI_OPTION_NO_LFT_STBL 0x10000000 238 /* Skip regulatory scan */ 239 #define HI_OPTION_SKIP_REG_SCAN 0x20000000 240 /* 241 * Do regulatory scan during init before 242 * sending WMI ready event to host 243 */ 244 #define HI_OPTION_INIT_REG_SCAN 0x40000000 245 246 /* REV6: Do not adjust memory map */ 247 #define HI_OPTION_SKIP_MEMMAP 0x80000000 248 249 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 250 251 /* 2 bits of hi_option_flag are used to represent 3 modes */ 252 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ 253 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ 254 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ 255 #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ 256 257 /* 2 bits of hi_option flag are usedto represent 4 submodes */ 258 #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ 259 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ 260 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ 261 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ 262 263 /* Num dev Mask */ 264 #define HI_OPTION_NUM_DEV_MASK 0x7 265 #define HI_OPTION_NUM_DEV_SHIFT 0x9 266 267 /* firmware bridging */ 268 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 269 270 /* 271 * Fw Mode/SubMode Mask 272 *----------------------------------------------------------------------------- 273 * SUB | SUB | SUB | SUB | | | | 274 *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] 275 * (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) 276 *----------------------------------------------------------------------------- 277 */ 278 #define HI_OPTION_FW_MODE_BITS 0x2 279 #define HI_OPTION_FW_MODE_MASK 0x3 280 #define HI_OPTION_FW_MODE_SHIFT 0xC 281 #define HI_OPTION_ALL_FW_MODE_MASK 0xFF 282 283 #define HI_OPTION_FW_SUBMODE_BITS 0x2 284 #define HI_OPTION_FW_SUBMODE_MASK 0x3 285 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 286 #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 287 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 288 289 /* hi_option_flag2 options */ 290 #define HI_OPTION_OFFLOAD_AMSDU 0x01 291 #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ 292 #define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ 293 #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ 294 #define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ 295 296 #define HI_OPTION_RF_KILL_SHIFT 0x2 297 #define HI_OPTION_RF_KILL_MASK 0x1 298 299 /* hi_reset_flag */ 300 /* preserve App Start address */ 301 #define HI_RESET_FLAG_PRESERVE_APP_START 0x01 302 /* preserve host interest */ 303 #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 304 /* preserve ROM data */ 305 #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 306 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 307 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 308 #define HI_RESET_FLAG_WARM_RESET 0x20 309 310 /* define hi_fw_swap bits */ 311 #define HI_DESC_IN_FW_BIT 0x01 312 313 /* indicate the reset flag is valid */ 314 #define HI_RESET_FLAG_IS_VALID 0x12345678 315 316 /* ACS is enabled */ 317 #define HI_ACS_FLAGS_ENABLED (1 << 0) 318 /* Use physical WWAN device */ 319 #define HI_ACS_FLAGS_USE_WWAN (1 << 1) 320 /* Use test VAP */ 321 #define HI_ACS_FLAGS_TEST_VAP (1 << 2) 322 323 /* 324 * CONSOLE FLAGS 325 * 326 * Bit Range Meaning 327 * --------- -------------------------------- 328 * 2..0 UART ID (0 = Default) 329 * 3 Baud Select (0 = 9600, 1 = 115200) 330 * 30..4 Reserved 331 * 31 Enable Console 332 * 333 */ 334 335 #define HI_CONSOLE_FLAGS_ENABLE (1 << 31) 336 #define HI_CONSOLE_FLAGS_UART_MASK (0x7) 337 #define HI_CONSOLE_FLAGS_UART_SHIFT 0 338 #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) 339 340 /* SM power save options */ 341 #define HI_SMPS_ALLOW_MASK (0x00000001) 342 #define HI_SMPS_MODE_MASK (0x00000002) 343 #define HI_SMPS_MODE_STATIC (0x00000000) 344 #define HI_SMPS_MODE_DYNAMIC (0x00000002) 345 #define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) 346 #define HI_SMPS_DATA_THRESH_MASK (0x000007f8) 347 #define HI_SMPS_DATA_THRESH_SHIFT (3) 348 #define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) 349 #define HI_SMPS_RSSI_THRESH_SHIFT (11) 350 #define HI_SMPS_LOWPWR_CM_MASK (0x00380000) 351 #define HI_SMPS_LOWPWR_CM_SHIFT (15) 352 #define HI_SMPS_HIPWR_CM_MASK (0x03c00000) 353 #define HI_SMPS_HIPWR_CM_SHIFT (19) 354 355 /* 356 * WOW Extension configuration 357 * 358 * Bit Range Meaning 359 * --------- -------------------------------- 360 * 8..0 Size of each WOW pattern (max 511) 361 * 15..9 Number of patterns per list (max 127) 362 * 17..16 Number of lists (max 4) 363 * 30..18 Reserved 364 * 31 Enabled 365 * 366 * set values (except enable) to zeros for default settings 367 */ 368 369 #define HI_WOW_EXT_ENABLED_MASK (1 << 31) 370 #define HI_WOW_EXT_NUM_LIST_SHIFT 16 371 #define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) 372 #define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 373 #define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) 374 #define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 375 #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) 376 377 #define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \ 378 ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \ 379 HI_WOW_EXT_NUM_LIST_MASK) | \ 380 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \ 381 HI_WOW_EXT_NUM_PATTERNS_MASK) | \ 382 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \ 383 HI_WOW_EXT_PATTERN_SIZE_MASK)) 384 385 #define HI_WOW_EXT_GET_NUM_LISTS(config) \ 386 (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) 387 #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ 388 (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \ 389 HI_WOW_EXT_NUM_PATTERNS_SHIFT) 390 #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ 391 (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \ 392 HI_WOW_EXT_PATTERN_SIZE_SHIFT) 393 394 /* 395 * Early allocation configuration 396 * Support RAM bank configuration before BMI done and this eases the memory 397 * allocation at very early stage 398 * Bit Range Meaning 399 * --------- ---------------------------------- 400 * [0:3] number of bank assigned to be IRAM 401 * [4:15] reserved 402 * [16:31] magic number 403 * 404 * Note: 405 * 1. target firmware would check magic number and if it's a match, firmware 406 * would consider the bits[0:15] are valid and base on that to calculate 407 * the end of DRAM. Early allocation would be located at that area and 408 * may be reclaimed when necessary 409 * 2. if no magic number is found, early allocation would happen at "_end" 410 * symbol of ROM which is located before the app-data and might NOT be 411 * re-claimable. If this is adopted, link script should keep this in 412 * mind to avoid data corruption. 413 */ 414 #define HI_EARLY_ALLOC_MAGIC 0x6d8a 415 #define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000 416 #define HI_EARLY_ALLOC_MAGIC_SHIFT 16 417 #define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f 418 #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 419 420 #define HI_EARLY_ALLOC_VALID() \ 421 ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \ 422 HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC)) 423 #define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ 424 (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \ 425 >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) 426 427 /*power save flag bit definitions*/ 428 #define HI_PWR_SAVE_LPL_ENABLED 0x1 429 /*b1-b3 reserved*/ 430 /*b4-b5 : dev0 LPL type : 0 - none 431 * 1- Reduce Pwr Search 432 * 2- Reduce Pwr Listen 433 */ 434 /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ 435 #define HI_PWR_SAVE_LPL_DEV0_LSB 4 436 #define HI_PWR_SAVE_LPL_DEV_MASK 0x3 437 /*power save related utility macros*/ 438 #define HI_LPL_ENABLED() \ 439 ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) 440 #define HI_DEV_LPL_TYPE_GET(_devix) \ 441 (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \ 442 (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix) * 2))) 443 444 #define HOST_INTEREST_SMPS_IS_ALLOWED() \ 445 ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) 446 447 /* Reserve 1024 bytes for extended board data */ 448 #define QCA988X_BOARD_DATA_SZ 7168 449 #define QCA988X_BOARD_EXT_DATA_SZ 0 450 451 #define QCA9887_BOARD_DATA_SZ 7168 452 #define QCA9887_BOARD_EXT_DATA_SZ 0 453 454 #define QCA6174_BOARD_DATA_SZ 8192 455 #define QCA6174_BOARD_EXT_DATA_SZ 0 456 457 #define QCA9377_BOARD_DATA_SZ QCA6174_BOARD_DATA_SZ 458 #define QCA9377_BOARD_EXT_DATA_SZ 0 459 460 #define QCA99X0_BOARD_DATA_SZ 12288 461 #define QCA99X0_BOARD_EXT_DATA_SZ 0 462 463 #define QCA4019_BOARD_DATA_SZ 12064 464 #define QCA4019_BOARD_EXT_DATA_SZ 0 465 466 #endif /* __TARGADDRS_H__ */ 467