1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SNOC_H_ 18 #define _SNOC_H_ 19 20 #include "hw.h" 21 #include "ce.h" 22 #include "qmi.h" 23 24 struct ath10k_snoc_drv_priv { 25 enum ath10k_hw_rev hw_rev; 26 u64 dma_mask; 27 u32 msa_size; 28 }; 29 30 struct snoc_state { 31 u32 pipe_cfg_addr; 32 u32 svc_to_pipe_map; 33 }; 34 35 struct ath10k_snoc_pipe { 36 struct ath10k_ce_pipe *ce_hdl; 37 u8 pipe_num; 38 struct ath10k *hif_ce_state; 39 size_t buf_sz; 40 /* protect ce info */ 41 spinlock_t pipe_lock; 42 struct ath10k_snoc *ar_snoc; 43 }; 44 45 struct ath10k_snoc_target_info { 46 u32 target_version; 47 u32 target_type; 48 u32 target_revision; 49 u32 soc_version; 50 }; 51 52 struct ath10k_snoc_ce_irq { 53 u32 irq_line; 54 }; 55 56 struct ath10k_wcn3990_vreg_info { 57 struct regulator *reg; 58 const char *name; 59 u32 min_v; 60 u32 max_v; 61 u32 load_ua; 62 unsigned long settle_delay; 63 bool required; 64 }; 65 66 struct ath10k_wcn3990_clk_info { 67 struct clk *handle; 68 const char *name; 69 u32 freq; 70 bool required; 71 }; 72 73 struct ath10k_snoc { 74 struct platform_device *dev; 75 struct ath10k *ar; 76 void __iomem *mem; 77 dma_addr_t mem_pa; 78 struct ath10k_snoc_target_info target_info; 79 size_t mem_len; 80 struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX]; 81 struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX]; 82 struct ath10k_ce ce; 83 struct timer_list rx_post_retry; 84 struct ath10k_wcn3990_vreg_info *vreg; 85 struct ath10k_wcn3990_clk_info *clk; 86 struct ath10k_qmi *qmi; 87 }; 88 89 static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar) 90 { 91 return (struct ath10k_snoc *)ar->drv_priv; 92 } 93 94 void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value); 95 u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset); 96 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type); 97 98 #endif /* _SNOC_H_ */ 99