1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _SNOC_H_ 18 #define _SNOC_H_ 19 20 #include "hw.h" 21 #include "ce.h" 22 #include "pci.h" 23 24 struct ath10k_snoc_drv_priv { 25 enum ath10k_hw_rev hw_rev; 26 u64 dma_mask; 27 }; 28 29 struct snoc_state { 30 u32 pipe_cfg_addr; 31 u32 svc_to_pipe_map; 32 }; 33 34 struct ath10k_snoc_pipe { 35 struct ath10k_ce_pipe *ce_hdl; 36 u8 pipe_num; 37 struct ath10k *hif_ce_state; 38 size_t buf_sz; 39 /* protect ce info */ 40 spinlock_t pipe_lock; 41 struct ath10k_snoc *ar_snoc; 42 }; 43 44 struct ath10k_snoc_target_info { 45 u32 target_version; 46 u32 target_type; 47 u32 target_revision; 48 u32 soc_version; 49 }; 50 51 struct ath10k_snoc_ce_irq { 52 u32 irq_line; 53 }; 54 55 struct ath10k_wcn3990_vreg_info { 56 struct regulator *reg; 57 const char *name; 58 u32 min_v; 59 u32 max_v; 60 u32 load_ua; 61 unsigned long settle_delay; 62 bool required; 63 }; 64 65 struct ath10k_wcn3990_clk_info { 66 struct clk *handle; 67 const char *name; 68 u32 freq; 69 bool required; 70 }; 71 72 struct ath10k_snoc { 73 struct platform_device *dev; 74 struct ath10k *ar; 75 void __iomem *mem; 76 dma_addr_t mem_pa; 77 struct ath10k_snoc_target_info target_info; 78 size_t mem_len; 79 struct ath10k_snoc_pipe pipe_info[CE_COUNT_MAX]; 80 struct ath10k_snoc_ce_irq ce_irqs[CE_COUNT_MAX]; 81 struct ath10k_ce ce; 82 struct timer_list rx_post_retry; 83 struct ath10k_wcn3990_vreg_info *vreg; 84 struct ath10k_wcn3990_clk_info *clk; 85 }; 86 87 static inline struct ath10k_snoc *ath10k_snoc_priv(struct ath10k *ar) 88 { 89 return (struct ath10k_snoc *)ar->drv_priv; 90 } 91 92 void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value); 93 u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset); 94 95 #endif /* _SNOC_H_ */ 96