1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bits.h> 7 #include <linux/clk.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/property.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/of_address.h> 16 #include <linux/iommu.h> 17 18 #include "ce.h" 19 #include "coredump.h" 20 #include "debug.h" 21 #include "hif.h" 22 #include "htc.h" 23 #include "snoc.h" 24 25 #define ATH10K_SNOC_RX_POST_RETRY_MS 50 26 #define CE_POLL_PIPE 4 27 #define ATH10K_SNOC_WAKE_IRQ 2 28 29 static char *const ce_name[] = { 30 "WLAN_CE_0", 31 "WLAN_CE_1", 32 "WLAN_CE_2", 33 "WLAN_CE_3", 34 "WLAN_CE_4", 35 "WLAN_CE_5", 36 "WLAN_CE_6", 37 "WLAN_CE_7", 38 "WLAN_CE_8", 39 "WLAN_CE_9", 40 "WLAN_CE_10", 41 "WLAN_CE_11", 42 }; 43 44 static const char * const ath10k_regulators[] = { 45 "vdd-0.8-cx-mx", 46 "vdd-1.8-xo", 47 "vdd-1.3-rfa", 48 "vdd-3.3-ch0", 49 "vdd-3.3-ch1", 50 }; 51 52 static const char * const ath10k_clocks[] = { 53 "cxo_ref_clk_pin", "qdss", 54 }; 55 56 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 57 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 58 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 59 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 60 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 61 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 62 63 static const struct ath10k_snoc_drv_priv drv_priv = { 64 .hw_rev = ATH10K_HW_WCN3990, 65 .dma_mask = DMA_BIT_MASK(35), 66 .msa_size = 0x100000, 67 }; 68 69 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C 70 #define WCN3990_DST_WR_IDX_OFFSET 0x40 71 72 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = { 73 { 74 .ce_id = __cpu_to_le16(0), 75 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 76 }, 77 78 { 79 .ce_id = __cpu_to_le16(3), 80 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 81 }, 82 83 { 84 .ce_id = __cpu_to_le16(4), 85 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 86 }, 87 88 { 89 .ce_id = __cpu_to_le16(5), 90 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 91 }, 92 93 { 94 .ce_id = __cpu_to_le16(7), 95 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 96 }, 97 98 { 99 .ce_id = __cpu_to_le16(1), 100 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 101 }, 102 103 { 104 .ce_id = __cpu_to_le16(2), 105 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 106 }, 107 108 { 109 .ce_id = __cpu_to_le16(7), 110 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 111 }, 112 113 { 114 .ce_id = __cpu_to_le16(8), 115 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 116 }, 117 118 { 119 .ce_id = __cpu_to_le16(9), 120 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 121 }, 122 123 { 124 .ce_id = __cpu_to_le16(10), 125 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 126 }, 127 128 { 129 .ce_id = __cpu_to_le16(11), 130 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 131 }, 132 }; 133 134 static struct ce_attr host_ce_config_wlan[] = { 135 /* CE0: host->target HTC control streams */ 136 { 137 .flags = CE_ATTR_FLAGS, 138 .src_nentries = 16, 139 .src_sz_max = 2048, 140 .dest_nentries = 0, 141 .send_cb = ath10k_snoc_htc_tx_cb, 142 }, 143 144 /* CE1: target->host HTT + HTC control */ 145 { 146 .flags = CE_ATTR_FLAGS, 147 .src_nentries = 0, 148 .src_sz_max = 2048, 149 .dest_nentries = 512, 150 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 151 }, 152 153 /* CE2: target->host WMI */ 154 { 155 .flags = CE_ATTR_FLAGS, 156 .src_nentries = 0, 157 .src_sz_max = 2048, 158 .dest_nentries = 64, 159 .recv_cb = ath10k_snoc_htc_rx_cb, 160 }, 161 162 /* CE3: host->target WMI */ 163 { 164 .flags = CE_ATTR_FLAGS, 165 .src_nentries = 32, 166 .src_sz_max = 2048, 167 .dest_nentries = 0, 168 .send_cb = ath10k_snoc_htc_tx_cb, 169 }, 170 171 /* CE4: host->target HTT */ 172 { 173 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 174 .src_nentries = 2048, 175 .src_sz_max = 256, 176 .dest_nentries = 0, 177 .send_cb = ath10k_snoc_htt_tx_cb, 178 }, 179 180 /* CE5: target->host HTT (ipa_uc->target ) */ 181 { 182 .flags = CE_ATTR_FLAGS, 183 .src_nentries = 0, 184 .src_sz_max = 512, 185 .dest_nentries = 512, 186 .recv_cb = ath10k_snoc_htt_rx_cb, 187 }, 188 189 /* CE6: target autonomous hif_memcpy */ 190 { 191 .flags = CE_ATTR_FLAGS, 192 .src_nentries = 0, 193 .src_sz_max = 0, 194 .dest_nentries = 0, 195 }, 196 197 /* CE7: ce_diag, the Diagnostic Window */ 198 { 199 .flags = CE_ATTR_FLAGS, 200 .src_nentries = 2, 201 .src_sz_max = 2048, 202 .dest_nentries = 2, 203 }, 204 205 /* CE8: Target to uMC */ 206 { 207 .flags = CE_ATTR_FLAGS, 208 .src_nentries = 0, 209 .src_sz_max = 2048, 210 .dest_nentries = 128, 211 }, 212 213 /* CE9 target->host HTT */ 214 { 215 .flags = CE_ATTR_FLAGS, 216 .src_nentries = 0, 217 .src_sz_max = 2048, 218 .dest_nentries = 512, 219 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 220 }, 221 222 /* CE10: target->host HTT */ 223 { 224 .flags = CE_ATTR_FLAGS, 225 .src_nentries = 0, 226 .src_sz_max = 2048, 227 .dest_nentries = 512, 228 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 229 }, 230 231 /* CE11: target -> host PKTLOG */ 232 { 233 .flags = CE_ATTR_FLAGS, 234 .src_nentries = 0, 235 .src_sz_max = 2048, 236 .dest_nentries = 512, 237 .recv_cb = ath10k_snoc_pktlog_rx_cb, 238 }, 239 }; 240 241 static struct ce_pipe_config target_ce_config_wlan[] = { 242 /* CE0: host->target HTC control and raw streams */ 243 { 244 .pipenum = __cpu_to_le32(0), 245 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 246 .nentries = __cpu_to_le32(32), 247 .nbytes_max = __cpu_to_le32(2048), 248 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 249 .reserved = __cpu_to_le32(0), 250 }, 251 252 /* CE1: target->host HTT + HTC control */ 253 { 254 .pipenum = __cpu_to_le32(1), 255 .pipedir = __cpu_to_le32(PIPEDIR_IN), 256 .nentries = __cpu_to_le32(32), 257 .nbytes_max = __cpu_to_le32(2048), 258 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 259 .reserved = __cpu_to_le32(0), 260 }, 261 262 /* CE2: target->host WMI */ 263 { 264 .pipenum = __cpu_to_le32(2), 265 .pipedir = __cpu_to_le32(PIPEDIR_IN), 266 .nentries = __cpu_to_le32(64), 267 .nbytes_max = __cpu_to_le32(2048), 268 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 269 .reserved = __cpu_to_le32(0), 270 }, 271 272 /* CE3: host->target WMI */ 273 { 274 .pipenum = __cpu_to_le32(3), 275 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 276 .nentries = __cpu_to_le32(32), 277 .nbytes_max = __cpu_to_le32(2048), 278 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 279 .reserved = __cpu_to_le32(0), 280 }, 281 282 /* CE4: host->target HTT */ 283 { 284 .pipenum = __cpu_to_le32(4), 285 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 286 .nentries = __cpu_to_le32(256), 287 .nbytes_max = __cpu_to_le32(256), 288 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 289 .reserved = __cpu_to_le32(0), 290 }, 291 292 /* CE5: target->host HTT (HIF->HTT) */ 293 { 294 .pipenum = __cpu_to_le32(5), 295 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 296 .nentries = __cpu_to_le32(1024), 297 .nbytes_max = __cpu_to_le32(64), 298 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 299 .reserved = __cpu_to_le32(0), 300 }, 301 302 /* CE6: Reserved for target autonomous hif_memcpy */ 303 { 304 .pipenum = __cpu_to_le32(6), 305 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 306 .nentries = __cpu_to_le32(32), 307 .nbytes_max = __cpu_to_le32(16384), 308 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 309 .reserved = __cpu_to_le32(0), 310 }, 311 312 /* CE7 used only by Host */ 313 { 314 .pipenum = __cpu_to_le32(7), 315 .pipedir = __cpu_to_le32(4), 316 .nentries = __cpu_to_le32(0), 317 .nbytes_max = __cpu_to_le32(0), 318 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 319 .reserved = __cpu_to_le32(0), 320 }, 321 322 /* CE8 Target to uMC */ 323 { 324 .pipenum = __cpu_to_le32(8), 325 .pipedir = __cpu_to_le32(PIPEDIR_IN), 326 .nentries = __cpu_to_le32(32), 327 .nbytes_max = __cpu_to_le32(2048), 328 .flags = __cpu_to_le32(0), 329 .reserved = __cpu_to_le32(0), 330 }, 331 332 /* CE9 target->host HTT */ 333 { 334 .pipenum = __cpu_to_le32(9), 335 .pipedir = __cpu_to_le32(PIPEDIR_IN), 336 .nentries = __cpu_to_le32(32), 337 .nbytes_max = __cpu_to_le32(2048), 338 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 339 .reserved = __cpu_to_le32(0), 340 }, 341 342 /* CE10 target->host HTT */ 343 { 344 .pipenum = __cpu_to_le32(10), 345 .pipedir = __cpu_to_le32(PIPEDIR_IN), 346 .nentries = __cpu_to_le32(32), 347 .nbytes_max = __cpu_to_le32(2048), 348 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 349 .reserved = __cpu_to_le32(0), 350 }, 351 352 /* CE11 target autonomous qcache memcpy */ 353 { 354 .pipenum = __cpu_to_le32(11), 355 .pipedir = __cpu_to_le32(PIPEDIR_IN), 356 .nentries = __cpu_to_le32(32), 357 .nbytes_max = __cpu_to_le32(2048), 358 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 359 .reserved = __cpu_to_le32(0), 360 }, 361 }; 362 363 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = { 364 { 365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 366 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 367 __cpu_to_le32(3), 368 }, 369 { 370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 371 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 372 __cpu_to_le32(2), 373 }, 374 { 375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 376 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 377 __cpu_to_le32(3), 378 }, 379 { 380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 381 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 382 __cpu_to_le32(2), 383 }, 384 { 385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 386 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 387 __cpu_to_le32(3), 388 }, 389 { 390 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 391 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 392 __cpu_to_le32(2), 393 }, 394 { 395 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 396 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 397 __cpu_to_le32(3), 398 }, 399 { 400 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 401 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 402 __cpu_to_le32(2), 403 }, 404 { 405 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 406 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 407 __cpu_to_le32(3), 408 }, 409 { 410 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 411 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 412 __cpu_to_le32(2), 413 }, 414 { 415 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 416 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 417 __cpu_to_le32(0), 418 }, 419 { 420 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 421 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 422 __cpu_to_le32(2), 423 }, 424 { /* not used */ 425 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 426 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 427 __cpu_to_le32(0), 428 }, 429 { /* not used */ 430 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 431 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 432 __cpu_to_le32(2), 433 }, 434 { 435 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 436 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 437 __cpu_to_le32(4), 438 }, 439 { 440 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 441 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 442 __cpu_to_le32(1), 443 }, 444 { /* not used */ 445 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 446 __cpu_to_le32(PIPEDIR_OUT), 447 __cpu_to_le32(5), 448 }, 449 { /* in = DL = target -> host */ 450 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG), 451 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 452 __cpu_to_le32(9), 453 }, 454 { /* in = DL = target -> host */ 455 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG), 456 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 457 __cpu_to_le32(10), 458 }, 459 { /* in = DL = target -> host pktlog */ 460 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG), 461 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 462 __cpu_to_le32(11), 463 }, 464 /* (Additions here) */ 465 466 { /* must be last */ 467 __cpu_to_le32(0), 468 __cpu_to_le32(0), 469 __cpu_to_le32(0), 470 }, 471 }; 472 473 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value) 474 { 475 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 476 477 iowrite32(value, ar_snoc->mem + offset); 478 } 479 480 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset) 481 { 482 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 483 u32 val; 484 485 val = ioread32(ar_snoc->mem + offset); 486 487 return val; 488 } 489 490 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe) 491 { 492 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 493 struct ath10k *ar = pipe->hif_ce_state; 494 struct ath10k_ce *ce = ath10k_ce_priv(ar); 495 struct sk_buff *skb; 496 dma_addr_t paddr; 497 int ret; 498 499 skb = dev_alloc_skb(pipe->buf_sz); 500 if (!skb) 501 return -ENOMEM; 502 503 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 504 505 paddr = dma_map_single(ar->dev, skb->data, 506 skb->len + skb_tailroom(skb), 507 DMA_FROM_DEVICE); 508 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 509 ath10k_warn(ar, "failed to dma map snoc rx buf\n"); 510 dev_kfree_skb_any(skb); 511 return -EIO; 512 } 513 514 ATH10K_SKB_RXCB(skb)->paddr = paddr; 515 516 spin_lock_bh(&ce->ce_lock); 517 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 518 spin_unlock_bh(&ce->ce_lock); 519 if (ret) { 520 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 521 DMA_FROM_DEVICE); 522 dev_kfree_skb_any(skb); 523 return ret; 524 } 525 526 return 0; 527 } 528 529 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe) 530 { 531 struct ath10k *ar = pipe->hif_ce_state; 532 struct ath10k_ce *ce = ath10k_ce_priv(ar); 533 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 534 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 535 int ret, num; 536 537 if (pipe->buf_sz == 0) 538 return; 539 540 if (!ce_pipe->dest_ring) 541 return; 542 543 spin_lock_bh(&ce->ce_lock); 544 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 545 spin_unlock_bh(&ce->ce_lock); 546 while (num--) { 547 ret = __ath10k_snoc_rx_post_buf(pipe); 548 if (ret) { 549 if (ret == -ENOSPC) 550 break; 551 ath10k_warn(ar, "failed to post rx buf: %d\n", ret); 552 mod_timer(&ar_snoc->rx_post_retry, jiffies + 553 ATH10K_SNOC_RX_POST_RETRY_MS); 554 break; 555 } 556 } 557 } 558 559 static void ath10k_snoc_rx_post(struct ath10k *ar) 560 { 561 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 562 int i; 563 564 for (i = 0; i < CE_COUNT; i++) 565 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]); 566 } 567 568 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state, 569 void (*callback)(struct ath10k *ar, 570 struct sk_buff *skb)) 571 { 572 struct ath10k *ar = ce_state->ar; 573 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 574 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id]; 575 struct sk_buff *skb; 576 struct sk_buff_head list; 577 void *transfer_context; 578 unsigned int nbytes, max_nbytes; 579 580 __skb_queue_head_init(&list); 581 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 582 &nbytes) == 0) { 583 skb = transfer_context; 584 max_nbytes = skb->len + skb_tailroom(skb); 585 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 586 max_nbytes, DMA_FROM_DEVICE); 587 588 if (unlikely(max_nbytes < nbytes)) { 589 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n", 590 nbytes, max_nbytes); 591 dev_kfree_skb_any(skb); 592 continue; 593 } 594 595 skb_put(skb, nbytes); 596 __skb_queue_tail(&list, skb); 597 } 598 599 while ((skb = __skb_dequeue(&list))) { 600 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n", 601 ce_state->id, skb->len); 602 603 callback(ar, skb); 604 } 605 606 ath10k_snoc_rx_post_pipe(pipe_info); 607 } 608 609 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 610 { 611 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 612 } 613 614 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 615 { 616 /* CE4 polling needs to be done whenever CE pipe which transports 617 * HTT Rx (target->host) is processed. 618 */ 619 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 620 621 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 622 } 623 624 /* Called by lower (CE) layer when data is received from the Target. 625 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data. 626 */ 627 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 628 { 629 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 630 } 631 632 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 633 { 634 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 635 ath10k_htt_t2h_msg_handler(ar, skb); 636 } 637 638 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 639 { 640 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 641 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver); 642 } 643 644 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t) 645 { 646 struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry); 647 struct ath10k *ar = ar_snoc->ar; 648 649 ath10k_snoc_rx_post(ar); 650 } 651 652 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 653 { 654 struct ath10k *ar = ce_state->ar; 655 struct sk_buff_head list; 656 struct sk_buff *skb; 657 658 __skb_queue_head_init(&list); 659 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 660 if (!skb) 661 continue; 662 663 __skb_queue_tail(&list, skb); 664 } 665 666 while ((skb = __skb_dequeue(&list))) 667 ath10k_htc_tx_completion_handler(ar, skb); 668 } 669 670 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 671 { 672 struct ath10k *ar = ce_state->ar; 673 struct sk_buff *skb; 674 675 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 676 if (!skb) 677 continue; 678 679 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 680 skb->len, DMA_TO_DEVICE); 681 ath10k_htt_hif_tx_complete(ar, skb); 682 } 683 } 684 685 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 686 struct ath10k_hif_sg_item *items, int n_items) 687 { 688 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 689 struct ath10k_ce *ce = ath10k_ce_priv(ar); 690 struct ath10k_snoc_pipe *snoc_pipe; 691 struct ath10k_ce_pipe *ce_pipe; 692 int err, i = 0; 693 694 snoc_pipe = &ar_snoc->pipe_info[pipe_id]; 695 ce_pipe = snoc_pipe->ce_hdl; 696 spin_lock_bh(&ce->ce_lock); 697 698 for (i = 0; i < n_items - 1; i++) { 699 ath10k_dbg(ar, ATH10K_DBG_SNOC, 700 "snoc tx item %d paddr %pad len %d n_items %d\n", 701 i, &items[i].paddr, items[i].len, n_items); 702 703 err = ath10k_ce_send_nolock(ce_pipe, 704 items[i].transfer_context, 705 items[i].paddr, 706 items[i].len, 707 items[i].transfer_id, 708 CE_SEND_FLAG_GATHER); 709 if (err) 710 goto err; 711 } 712 713 ath10k_dbg(ar, ATH10K_DBG_SNOC, 714 "snoc tx item %d paddr %pad len %d n_items %d\n", 715 i, &items[i].paddr, items[i].len, n_items); 716 717 err = ath10k_ce_send_nolock(ce_pipe, 718 items[i].transfer_context, 719 items[i].paddr, 720 items[i].len, 721 items[i].transfer_id, 722 0); 723 if (err) 724 goto err; 725 726 spin_unlock_bh(&ce->ce_lock); 727 728 return 0; 729 730 err: 731 for (; i > 0; i--) 732 __ath10k_ce_send_revert(ce_pipe); 733 734 spin_unlock_bh(&ce->ce_lock); 735 return err; 736 } 737 738 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar, 739 struct bmi_target_info *target_info) 740 { 741 target_info->version = ATH10K_HW_WCN3990; 742 target_info->type = ATH10K_HW_WCN3990; 743 744 return 0; 745 } 746 747 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 748 { 749 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 750 751 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n"); 752 753 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl); 754 } 755 756 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe, 757 int force) 758 { 759 int resources; 760 761 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n"); 762 763 if (!force) { 764 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe); 765 766 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 767 return; 768 } 769 ath10k_ce_per_engine_service(ar, pipe); 770 } 771 772 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar, 773 u16 service_id, 774 u8 *ul_pipe, u8 *dl_pipe) 775 { 776 const struct ce_service_to_pipe *entry; 777 bool ul_set = false, dl_set = false; 778 int i; 779 780 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n"); 781 782 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 783 entry = &target_service_to_ce_map_wlan[i]; 784 785 if (__le32_to_cpu(entry->service_id) != service_id) 786 continue; 787 788 switch (__le32_to_cpu(entry->pipedir)) { 789 case PIPEDIR_NONE: 790 break; 791 case PIPEDIR_IN: 792 WARN_ON(dl_set); 793 *dl_pipe = __le32_to_cpu(entry->pipenum); 794 dl_set = true; 795 break; 796 case PIPEDIR_OUT: 797 WARN_ON(ul_set); 798 *ul_pipe = __le32_to_cpu(entry->pipenum); 799 ul_set = true; 800 break; 801 case PIPEDIR_INOUT: 802 WARN_ON(dl_set); 803 WARN_ON(ul_set); 804 *dl_pipe = __le32_to_cpu(entry->pipenum); 805 *ul_pipe = __le32_to_cpu(entry->pipenum); 806 dl_set = true; 807 ul_set = true; 808 break; 809 } 810 } 811 812 if (!ul_set || !dl_set) 813 return -ENOENT; 814 815 return 0; 816 } 817 818 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar, 819 u8 *ul_pipe, u8 *dl_pipe) 820 { 821 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n"); 822 823 (void)ath10k_snoc_hif_map_service_to_pipe(ar, 824 ATH10K_HTC_SVC_ID_RSVD_CTRL, 825 ul_pipe, dl_pipe); 826 } 827 828 static inline void ath10k_snoc_irq_disable(struct ath10k *ar) 829 { 830 ath10k_ce_disable_interrupts(ar); 831 } 832 833 static inline void ath10k_snoc_irq_enable(struct ath10k *ar) 834 { 835 ath10k_ce_enable_interrupts(ar); 836 } 837 838 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 839 { 840 struct ath10k_ce_pipe *ce_pipe; 841 struct ath10k_ce_ring *ce_ring; 842 struct sk_buff *skb; 843 struct ath10k *ar; 844 int i; 845 846 ar = snoc_pipe->hif_ce_state; 847 ce_pipe = snoc_pipe->ce_hdl; 848 ce_ring = ce_pipe->dest_ring; 849 850 if (!ce_ring) 851 return; 852 853 if (!snoc_pipe->buf_sz) 854 return; 855 856 for (i = 0; i < ce_ring->nentries; i++) { 857 skb = ce_ring->per_transfer_context[i]; 858 if (!skb) 859 continue; 860 861 ce_ring->per_transfer_context[i] = NULL; 862 863 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 864 skb->len + skb_tailroom(skb), 865 DMA_FROM_DEVICE); 866 dev_kfree_skb_any(skb); 867 } 868 } 869 870 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 871 { 872 struct ath10k_ce_pipe *ce_pipe; 873 struct ath10k_ce_ring *ce_ring; 874 struct sk_buff *skb; 875 struct ath10k *ar; 876 int i; 877 878 ar = snoc_pipe->hif_ce_state; 879 ce_pipe = snoc_pipe->ce_hdl; 880 ce_ring = ce_pipe->src_ring; 881 882 if (!ce_ring) 883 return; 884 885 if (!snoc_pipe->buf_sz) 886 return; 887 888 for (i = 0; i < ce_ring->nentries; i++) { 889 skb = ce_ring->per_transfer_context[i]; 890 if (!skb) 891 continue; 892 893 ce_ring->per_transfer_context[i] = NULL; 894 895 ath10k_htc_tx_completion_handler(ar, skb); 896 } 897 } 898 899 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar) 900 { 901 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 902 struct ath10k_snoc_pipe *pipe_info; 903 int pipe_num; 904 905 del_timer_sync(&ar_snoc->rx_post_retry); 906 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 907 pipe_info = &ar_snoc->pipe_info[pipe_num]; 908 ath10k_snoc_rx_pipe_cleanup(pipe_info); 909 ath10k_snoc_tx_pipe_cleanup(pipe_info); 910 } 911 } 912 913 static void ath10k_snoc_hif_stop(struct ath10k *ar) 914 { 915 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) 916 ath10k_snoc_irq_disable(ar); 917 918 napi_synchronize(&ar->napi); 919 napi_disable(&ar->napi); 920 ath10k_snoc_buffer_cleanup(ar); 921 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 922 } 923 924 static int ath10k_snoc_hif_start(struct ath10k *ar) 925 { 926 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 927 928 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX); 929 napi_enable(&ar->napi); 930 ath10k_snoc_irq_enable(ar); 931 ath10k_snoc_rx_post(ar); 932 933 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 934 935 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 936 937 return 0; 938 } 939 940 static int ath10k_snoc_init_pipes(struct ath10k *ar) 941 { 942 int i, ret; 943 944 for (i = 0; i < CE_COUNT; i++) { 945 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 946 if (ret) { 947 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 948 i, ret); 949 return ret; 950 } 951 } 952 953 return 0; 954 } 955 956 static int ath10k_snoc_wlan_enable(struct ath10k *ar, 957 enum ath10k_firmware_mode fw_mode) 958 { 959 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX]; 960 struct ath10k_qmi_wlan_enable_cfg cfg; 961 enum wlfw_driver_mode_enum_v01 mode; 962 int pipe_num; 963 964 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) { 965 tgt_cfg[pipe_num].pipe_num = 966 target_ce_config_wlan[pipe_num].pipenum; 967 tgt_cfg[pipe_num].pipe_dir = 968 target_ce_config_wlan[pipe_num].pipedir; 969 tgt_cfg[pipe_num].nentries = 970 target_ce_config_wlan[pipe_num].nentries; 971 tgt_cfg[pipe_num].nbytes_max = 972 target_ce_config_wlan[pipe_num].nbytes_max; 973 tgt_cfg[pipe_num].flags = 974 target_ce_config_wlan[pipe_num].flags; 975 tgt_cfg[pipe_num].reserved = 0; 976 } 977 978 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) / 979 sizeof(struct ath10k_tgt_pipe_cfg); 980 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *) 981 &tgt_cfg; 982 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) / 983 sizeof(struct ath10k_svc_pipe_cfg); 984 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *) 985 &target_service_to_ce_map_wlan; 986 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map); 987 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *) 988 &target_shadow_reg_cfg_map; 989 990 switch (fw_mode) { 991 case ATH10K_FIRMWARE_MODE_NORMAL: 992 mode = QMI_WLFW_MISSION_V01; 993 break; 994 case ATH10K_FIRMWARE_MODE_UTF: 995 mode = QMI_WLFW_FTM_V01; 996 break; 997 default: 998 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode); 999 return -EINVAL; 1000 } 1001 1002 return ath10k_qmi_wlan_enable(ar, &cfg, mode, 1003 NULL); 1004 } 1005 1006 static void ath10k_snoc_wlan_disable(struct ath10k *ar) 1007 { 1008 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1009 1010 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY 1011 * flags are not set, it means that the driver has restarted 1012 * due to a crash inject via debugfs. In this case, the driver 1013 * needs to restart the firmware and hence send qmi wlan disable, 1014 * during the driver restart sequence. 1015 */ 1016 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) || 1017 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1018 ath10k_qmi_wlan_disable(ar); 1019 } 1020 1021 static void ath10k_snoc_hif_power_down(struct ath10k *ar) 1022 { 1023 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 1024 1025 ath10k_snoc_wlan_disable(ar); 1026 ath10k_ce_free_rri(ar); 1027 } 1028 1029 static int ath10k_snoc_hif_power_up(struct ath10k *ar, 1030 enum ath10k_firmware_mode fw_mode) 1031 { 1032 int ret; 1033 1034 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n", 1035 __func__, ar->state); 1036 1037 ret = ath10k_snoc_wlan_enable(ar, fw_mode); 1038 if (ret) { 1039 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret); 1040 return ret; 1041 } 1042 1043 ath10k_ce_alloc_rri(ar); 1044 1045 ret = ath10k_snoc_init_pipes(ar); 1046 if (ret) { 1047 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 1048 goto err_wlan_enable; 1049 } 1050 1051 return 0; 1052 1053 err_wlan_enable: 1054 ath10k_snoc_wlan_disable(ar); 1055 1056 return ret; 1057 } 1058 1059 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar, 1060 u8 fw_log_mode) 1061 { 1062 u8 fw_dbg_mode; 1063 1064 if (fw_log_mode) 1065 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE; 1066 else 1067 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG; 1068 1069 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode); 1070 } 1071 1072 #ifdef CONFIG_PM 1073 static int ath10k_snoc_hif_suspend(struct ath10k *ar) 1074 { 1075 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1076 int ret; 1077 1078 if (!device_may_wakeup(ar->dev)) 1079 return -EPERM; 1080 1081 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1082 if (ret) { 1083 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret); 1084 return ret; 1085 } 1086 1087 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n"); 1088 1089 return ret; 1090 } 1091 1092 static int ath10k_snoc_hif_resume(struct ath10k *ar) 1093 { 1094 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1095 int ret; 1096 1097 if (!device_may_wakeup(ar->dev)) 1098 return -EPERM; 1099 1100 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1101 if (ret) { 1102 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret); 1103 return ret; 1104 } 1105 1106 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n"); 1107 1108 return ret; 1109 } 1110 #endif 1111 1112 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = { 1113 .read32 = ath10k_snoc_read32, 1114 .write32 = ath10k_snoc_write32, 1115 .start = ath10k_snoc_hif_start, 1116 .stop = ath10k_snoc_hif_stop, 1117 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe, 1118 .get_default_pipe = ath10k_snoc_hif_get_default_pipe, 1119 .power_up = ath10k_snoc_hif_power_up, 1120 .power_down = ath10k_snoc_hif_power_down, 1121 .tx_sg = ath10k_snoc_hif_tx_sg, 1122 .send_complete_check = ath10k_snoc_hif_send_complete_check, 1123 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number, 1124 .get_target_info = ath10k_snoc_hif_get_target_info, 1125 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode, 1126 1127 #ifdef CONFIG_PM 1128 .suspend = ath10k_snoc_hif_suspend, 1129 .resume = ath10k_snoc_hif_resume, 1130 #endif 1131 }; 1132 1133 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = { 1134 .read32 = ath10k_snoc_read32, 1135 .write32 = ath10k_snoc_write32, 1136 }; 1137 1138 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq) 1139 { 1140 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1141 int i; 1142 1143 for (i = 0; i < CE_COUNT_MAX; i++) { 1144 if (ar_snoc->ce_irqs[i].irq_line == irq) 1145 return i; 1146 } 1147 ath10k_err(ar, "No matching CE id for irq %d\n", irq); 1148 1149 return -EINVAL; 1150 } 1151 1152 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg) 1153 { 1154 struct ath10k *ar = arg; 1155 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1156 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq); 1157 1158 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) { 1159 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, 1160 ce_id); 1161 return IRQ_HANDLED; 1162 } 1163 1164 ath10k_ce_disable_interrupt(ar, ce_id); 1165 set_bit(ce_id, ar_snoc->pending_ce_irqs); 1166 1167 napi_schedule(&ar->napi); 1168 1169 return IRQ_HANDLED; 1170 } 1171 1172 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget) 1173 { 1174 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 1175 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1176 int done = 0; 1177 int ce_id; 1178 1179 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) { 1180 napi_complete(ctx); 1181 return done; 1182 } 1183 1184 for (ce_id = 0; ce_id < CE_COUNT; ce_id++) 1185 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) { 1186 ath10k_ce_per_engine_service(ar, ce_id); 1187 ath10k_ce_enable_interrupt(ar, ce_id); 1188 } 1189 1190 done = ath10k_htt_txrx_compl_task(ar, budget); 1191 1192 if (done < budget) 1193 napi_complete(ctx); 1194 1195 return done; 1196 } 1197 1198 static void ath10k_snoc_init_napi(struct ath10k *ar) 1199 { 1200 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll, 1201 ATH10K_NAPI_BUDGET); 1202 } 1203 1204 static int ath10k_snoc_request_irq(struct ath10k *ar) 1205 { 1206 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1207 int irqflags = IRQF_TRIGGER_RISING; 1208 int ret, id; 1209 1210 for (id = 0; id < CE_COUNT_MAX; id++) { 1211 ret = request_irq(ar_snoc->ce_irqs[id].irq_line, 1212 ath10k_snoc_per_engine_handler, 1213 irqflags, ce_name[id], ar); 1214 if (ret) { 1215 ath10k_err(ar, 1216 "failed to register IRQ handler for CE %d: %d\n", 1217 id, ret); 1218 goto err_irq; 1219 } 1220 } 1221 1222 return 0; 1223 1224 err_irq: 1225 for (id -= 1; id >= 0; id--) 1226 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1227 1228 return ret; 1229 } 1230 1231 static void ath10k_snoc_free_irq(struct ath10k *ar) 1232 { 1233 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1234 int id; 1235 1236 for (id = 0; id < CE_COUNT_MAX; id++) 1237 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1238 } 1239 1240 static int ath10k_snoc_resource_init(struct ath10k *ar) 1241 { 1242 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1243 struct platform_device *pdev; 1244 struct resource *res; 1245 int i, ret = 0; 1246 1247 pdev = ar_snoc->dev; 1248 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); 1249 if (!res) { 1250 ath10k_err(ar, "Memory base not found in DT\n"); 1251 return -EINVAL; 1252 } 1253 1254 ar_snoc->mem_pa = res->start; 1255 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa, 1256 resource_size(res)); 1257 if (!ar_snoc->mem) { 1258 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n", 1259 &ar_snoc->mem_pa); 1260 return -EINVAL; 1261 } 1262 1263 for (i = 0; i < CE_COUNT; i++) { 1264 res = platform_get_resource(ar_snoc->dev, IORESOURCE_IRQ, i); 1265 if (!res) { 1266 ath10k_err(ar, "failed to get IRQ%d\n", i); 1267 ret = -ENODEV; 1268 goto out; 1269 } 1270 ar_snoc->ce_irqs[i].irq_line = res->start; 1271 } 1272 1273 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data", 1274 &ar_snoc->xo_cal_data); 1275 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret); 1276 if (ret == 0) { 1277 ar_snoc->xo_cal_supported = true; 1278 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n", 1279 ar_snoc->xo_cal_data); 1280 } 1281 ret = 0; 1282 1283 out: 1284 return ret; 1285 } 1286 1287 static void ath10k_snoc_quirks_init(struct ath10k *ar) 1288 { 1289 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1290 struct device *dev = &ar_snoc->dev->dev; 1291 1292 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk")) 1293 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags); 1294 } 1295 1296 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type) 1297 { 1298 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1299 struct ath10k_bus_params bus_params = {}; 1300 int ret; 1301 1302 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags)) 1303 return 0; 1304 1305 switch (type) { 1306 case ATH10K_QMI_EVENT_FW_READY_IND: 1307 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) { 1308 ath10k_core_start_recovery(ar); 1309 break; 1310 } 1311 1312 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 1313 bus_params.chip_id = ar_snoc->target_info.soc_version; 1314 ret = ath10k_core_register(ar, &bus_params); 1315 if (ret) { 1316 ath10k_err(ar, "Failed to register driver core: %d\n", 1317 ret); 1318 return ret; 1319 } 1320 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags); 1321 break; 1322 case ATH10K_QMI_EVENT_FW_DOWN_IND: 1323 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 1324 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 1325 break; 1326 default: 1327 ath10k_err(ar, "invalid fw indication: %llx\n", type); 1328 return -EINVAL; 1329 } 1330 1331 return 0; 1332 } 1333 1334 static int ath10k_snoc_setup_resource(struct ath10k *ar) 1335 { 1336 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1337 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1338 struct ath10k_snoc_pipe *pipe; 1339 int i, ret; 1340 1341 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0); 1342 spin_lock_init(&ce->ce_lock); 1343 for (i = 0; i < CE_COUNT; i++) { 1344 pipe = &ar_snoc->pipe_info[i]; 1345 pipe->ce_hdl = &ce->ce_states[i]; 1346 pipe->pipe_num = i; 1347 pipe->hif_ce_state = ar; 1348 1349 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 1350 if (ret) { 1351 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 1352 i, ret); 1353 return ret; 1354 } 1355 1356 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max; 1357 } 1358 ath10k_snoc_init_napi(ar); 1359 1360 return 0; 1361 } 1362 1363 static void ath10k_snoc_release_resource(struct ath10k *ar) 1364 { 1365 int i; 1366 1367 netif_napi_del(&ar->napi); 1368 for (i = 0; i < CE_COUNT; i++) 1369 ath10k_ce_free_pipe(ar, i); 1370 } 1371 1372 static int ath10k_hw_power_on(struct ath10k *ar) 1373 { 1374 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1375 int ret; 1376 1377 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n"); 1378 1379 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs); 1380 if (ret) 1381 return ret; 1382 1383 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks); 1384 if (ret) 1385 goto vreg_off; 1386 1387 return ret; 1388 1389 vreg_off: 1390 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1391 return ret; 1392 } 1393 1394 static int ath10k_hw_power_off(struct ath10k *ar) 1395 { 1396 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1397 1398 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n"); 1399 1400 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks); 1401 1402 return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1403 } 1404 1405 static void ath10k_msa_dump_memory(struct ath10k *ar, 1406 struct ath10k_fw_crash_data *crash_data) 1407 { 1408 const struct ath10k_hw_mem_layout *mem_layout; 1409 const struct ath10k_mem_region *current_region; 1410 struct ath10k_dump_ram_data_hdr *hdr; 1411 size_t buf_len; 1412 u8 *buf; 1413 1414 if (!crash_data || !crash_data->ramdump_buf) 1415 return; 1416 1417 mem_layout = ath10k_coredump_get_mem_layout(ar); 1418 if (!mem_layout) 1419 return; 1420 1421 current_region = &mem_layout->region_table.regions[0]; 1422 1423 buf = crash_data->ramdump_buf; 1424 buf_len = crash_data->ramdump_buf_len; 1425 memset(buf, 0, buf_len); 1426 1427 /* Reserve space for the header. */ 1428 hdr = (void *)buf; 1429 buf += sizeof(*hdr); 1430 buf_len -= sizeof(*hdr); 1431 1432 hdr->region_type = cpu_to_le32(current_region->type); 1433 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr); 1434 hdr->length = cpu_to_le32(ar->msa.mem_size); 1435 1436 if (current_region->len < ar->msa.mem_size) { 1437 memcpy(buf, ar->msa.vaddr, current_region->len); 1438 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n", 1439 current_region->len, ar->msa.mem_size); 1440 } else { 1441 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size); 1442 } 1443 } 1444 1445 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar) 1446 { 1447 struct ath10k_fw_crash_data *crash_data; 1448 char guid[UUID_STRING_LEN + 1]; 1449 1450 mutex_lock(&ar->dump_mutex); 1451 1452 spin_lock_bh(&ar->data_lock); 1453 ar->stats.fw_crash_counter++; 1454 spin_unlock_bh(&ar->data_lock); 1455 1456 crash_data = ath10k_coredump_new(ar); 1457 1458 if (crash_data) 1459 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1460 else 1461 scnprintf(guid, sizeof(guid), "n/a"); 1462 1463 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1464 ath10k_print_driver_info(ar); 1465 ath10k_msa_dump_memory(ar, crash_data); 1466 mutex_unlock(&ar->dump_mutex); 1467 } 1468 1469 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size) 1470 { 1471 struct device *dev = ar->dev; 1472 struct device_node *node; 1473 struct resource r; 1474 int ret; 1475 1476 node = of_parse_phandle(dev->of_node, "memory-region", 0); 1477 if (node) { 1478 ret = of_address_to_resource(node, 0, &r); 1479 if (ret) { 1480 dev_err(dev, "failed to resolve msa fixed region\n"); 1481 return ret; 1482 } 1483 of_node_put(node); 1484 1485 ar->msa.paddr = r.start; 1486 ar->msa.mem_size = resource_size(&r); 1487 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr, 1488 ar->msa.mem_size, 1489 MEMREMAP_WT); 1490 if (IS_ERR(ar->msa.vaddr)) { 1491 dev_err(dev, "failed to map memory region: %pa\n", 1492 &r.start); 1493 return PTR_ERR(ar->msa.vaddr); 1494 } 1495 } else { 1496 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size, 1497 &ar->msa.paddr, 1498 GFP_KERNEL); 1499 if (!ar->msa.vaddr) { 1500 ath10k_err(ar, "failed to allocate dma memory for msa region\n"); 1501 return -ENOMEM; 1502 } 1503 ar->msa.mem_size = msa_size; 1504 } 1505 1506 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n", 1507 &ar->msa.paddr, 1508 ar->msa.vaddr); 1509 1510 return 0; 1511 } 1512 1513 static int ath10k_fw_init(struct ath10k *ar) 1514 { 1515 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1516 struct device *host_dev = &ar_snoc->dev->dev; 1517 struct platform_device_info info; 1518 struct iommu_domain *iommu_dom; 1519 struct platform_device *pdev; 1520 struct device_node *node; 1521 int ret; 1522 1523 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware"); 1524 if (!node) { 1525 ar_snoc->use_tz = true; 1526 return 0; 1527 } 1528 1529 memset(&info, 0, sizeof(info)); 1530 info.fwnode = &node->fwnode; 1531 info.parent = host_dev; 1532 info.name = node->name; 1533 info.dma_mask = DMA_BIT_MASK(32); 1534 1535 pdev = platform_device_register_full(&info); 1536 if (IS_ERR(pdev)) { 1537 of_node_put(node); 1538 return PTR_ERR(pdev); 1539 } 1540 1541 pdev->dev.of_node = node; 1542 1543 ret = of_dma_configure(&pdev->dev, node, true); 1544 if (ret) { 1545 ath10k_err(ar, "dma configure fail: %d\n", ret); 1546 goto err_unregister; 1547 } 1548 1549 ar_snoc->fw.dev = &pdev->dev; 1550 1551 iommu_dom = iommu_domain_alloc(&platform_bus_type); 1552 if (!iommu_dom) { 1553 ath10k_err(ar, "failed to allocate iommu domain\n"); 1554 ret = -ENOMEM; 1555 goto err_unregister; 1556 } 1557 1558 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev); 1559 if (ret) { 1560 ath10k_err(ar, "could not attach device: %d\n", ret); 1561 goto err_iommu_free; 1562 } 1563 1564 ar_snoc->fw.iommu_domain = iommu_dom; 1565 ar_snoc->fw.fw_start_addr = ar->msa.paddr; 1566 1567 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr, 1568 ar->msa.paddr, ar->msa.mem_size, 1569 IOMMU_READ | IOMMU_WRITE); 1570 if (ret) { 1571 ath10k_err(ar, "failed to map firmware region: %d\n", ret); 1572 goto err_iommu_detach; 1573 } 1574 1575 of_node_put(node); 1576 1577 return 0; 1578 1579 err_iommu_detach: 1580 iommu_detach_device(iommu_dom, ar_snoc->fw.dev); 1581 1582 err_iommu_free: 1583 iommu_domain_free(iommu_dom); 1584 1585 err_unregister: 1586 platform_device_unregister(pdev); 1587 of_node_put(node); 1588 1589 return ret; 1590 } 1591 1592 static int ath10k_fw_deinit(struct ath10k *ar) 1593 { 1594 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1595 const size_t mapped_size = ar_snoc->fw.mapped_mem_size; 1596 struct iommu_domain *iommu; 1597 size_t unmapped_size; 1598 1599 if (ar_snoc->use_tz) 1600 return 0; 1601 1602 iommu = ar_snoc->fw.iommu_domain; 1603 1604 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr, 1605 mapped_size); 1606 if (unmapped_size != mapped_size) 1607 ath10k_err(ar, "failed to unmap firmware: %zu\n", 1608 unmapped_size); 1609 1610 iommu_detach_device(iommu, ar_snoc->fw.dev); 1611 iommu_domain_free(iommu); 1612 1613 platform_device_unregister(to_platform_device(ar_snoc->fw.dev)); 1614 1615 return 0; 1616 } 1617 1618 static const struct of_device_id ath10k_snoc_dt_match[] = { 1619 { .compatible = "qcom,wcn3990-wifi", 1620 .data = &drv_priv, 1621 }, 1622 { } 1623 }; 1624 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match); 1625 1626 static int ath10k_snoc_probe(struct platform_device *pdev) 1627 { 1628 const struct ath10k_snoc_drv_priv *drv_data; 1629 struct ath10k_snoc *ar_snoc; 1630 struct device *dev; 1631 struct ath10k *ar; 1632 u32 msa_size; 1633 int ret; 1634 u32 i; 1635 1636 dev = &pdev->dev; 1637 drv_data = device_get_match_data(dev); 1638 if (!drv_data) { 1639 dev_err(dev, "failed to find matching device tree id\n"); 1640 return -EINVAL; 1641 } 1642 1643 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask); 1644 if (ret) { 1645 dev_err(dev, "failed to set dma mask: %d\n", ret); 1646 return ret; 1647 } 1648 1649 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC, 1650 drv_data->hw_rev, &ath10k_snoc_hif_ops); 1651 if (!ar) { 1652 dev_err(dev, "failed to allocate core\n"); 1653 return -ENOMEM; 1654 } 1655 1656 ar_snoc = ath10k_snoc_priv(ar); 1657 ar_snoc->dev = pdev; 1658 platform_set_drvdata(pdev, ar); 1659 ar_snoc->ar = ar; 1660 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops; 1661 ar->ce_priv = &ar_snoc->ce; 1662 msa_size = drv_data->msa_size; 1663 1664 ath10k_snoc_quirks_init(ar); 1665 1666 ret = ath10k_snoc_resource_init(ar); 1667 if (ret) { 1668 ath10k_warn(ar, "failed to initialize resource: %d\n", ret); 1669 goto err_core_destroy; 1670 } 1671 1672 ret = ath10k_snoc_setup_resource(ar); 1673 if (ret) { 1674 ath10k_warn(ar, "failed to setup resource: %d\n", ret); 1675 goto err_core_destroy; 1676 } 1677 ret = ath10k_snoc_request_irq(ar); 1678 if (ret) { 1679 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 1680 goto err_release_resource; 1681 } 1682 1683 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators); 1684 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs, 1685 sizeof(*ar_snoc->vregs), GFP_KERNEL); 1686 if (!ar_snoc->vregs) { 1687 ret = -ENOMEM; 1688 goto err_free_irq; 1689 } 1690 for (i = 0; i < ar_snoc->num_vregs; i++) 1691 ar_snoc->vregs[i].supply = ath10k_regulators[i]; 1692 1693 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs, 1694 ar_snoc->vregs); 1695 if (ret < 0) 1696 goto err_free_irq; 1697 1698 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks); 1699 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks, 1700 sizeof(*ar_snoc->clks), GFP_KERNEL); 1701 if (!ar_snoc->clks) { 1702 ret = -ENOMEM; 1703 goto err_free_irq; 1704 } 1705 1706 for (i = 0; i < ar_snoc->num_clks; i++) 1707 ar_snoc->clks[i].id = ath10k_clocks[i]; 1708 1709 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks, 1710 ar_snoc->clks); 1711 if (ret) 1712 goto err_free_irq; 1713 1714 ret = ath10k_hw_power_on(ar); 1715 if (ret) { 1716 ath10k_err(ar, "failed to power on device: %d\n", ret); 1717 goto err_free_irq; 1718 } 1719 1720 ret = ath10k_setup_msa_resources(ar, msa_size); 1721 if (ret) { 1722 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret); 1723 goto err_power_off; 1724 } 1725 1726 ret = ath10k_fw_init(ar); 1727 if (ret) { 1728 ath10k_err(ar, "failed to initialize firmware: %d\n", ret); 1729 goto err_power_off; 1730 } 1731 1732 ret = ath10k_qmi_init(ar, msa_size); 1733 if (ret) { 1734 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret); 1735 goto err_fw_deinit; 1736 } 1737 1738 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n"); 1739 1740 return 0; 1741 1742 err_fw_deinit: 1743 ath10k_fw_deinit(ar); 1744 1745 err_power_off: 1746 ath10k_hw_power_off(ar); 1747 1748 err_free_irq: 1749 ath10k_snoc_free_irq(ar); 1750 1751 err_release_resource: 1752 ath10k_snoc_release_resource(ar); 1753 1754 err_core_destroy: 1755 ath10k_core_destroy(ar); 1756 1757 return ret; 1758 } 1759 1760 static int ath10k_snoc_remove(struct platform_device *pdev) 1761 { 1762 struct ath10k *ar = platform_get_drvdata(pdev); 1763 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1764 1765 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n"); 1766 1767 reinit_completion(&ar->driver_recovery); 1768 1769 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1770 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ); 1771 1772 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags); 1773 1774 ath10k_core_unregister(ar); 1775 ath10k_hw_power_off(ar); 1776 ath10k_fw_deinit(ar); 1777 ath10k_snoc_free_irq(ar); 1778 ath10k_snoc_release_resource(ar); 1779 ath10k_qmi_deinit(ar); 1780 ath10k_core_destroy(ar); 1781 1782 return 0; 1783 } 1784 1785 static void ath10k_snoc_shutdown(struct platform_device *pdev) 1786 { 1787 struct ath10k *ar = platform_get_drvdata(pdev); 1788 1789 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n"); 1790 ath10k_snoc_remove(pdev); 1791 } 1792 1793 static struct platform_driver ath10k_snoc_driver = { 1794 .probe = ath10k_snoc_probe, 1795 .remove = ath10k_snoc_remove, 1796 .shutdown = ath10k_snoc_shutdown, 1797 .driver = { 1798 .name = "ath10k_snoc", 1799 .of_match_table = ath10k_snoc_dt_match, 1800 }, 1801 }; 1802 module_platform_driver(ath10k_snoc_driver); 1803 1804 MODULE_AUTHOR("Qualcomm"); 1805 MODULE_LICENSE("Dual BSD/GPL"); 1806 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices"); 1807