1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bits.h> 7 #include <linux/clk.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/property.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/of_address.h> 16 #include <linux/iommu.h> 17 18 #include "ce.h" 19 #include "coredump.h" 20 #include "debug.h" 21 #include "hif.h" 22 #include "htc.h" 23 #include "snoc.h" 24 25 #define ATH10K_SNOC_RX_POST_RETRY_MS 50 26 #define CE_POLL_PIPE 4 27 #define ATH10K_SNOC_WAKE_IRQ 2 28 29 static char *const ce_name[] = { 30 "WLAN_CE_0", 31 "WLAN_CE_1", 32 "WLAN_CE_2", 33 "WLAN_CE_3", 34 "WLAN_CE_4", 35 "WLAN_CE_5", 36 "WLAN_CE_6", 37 "WLAN_CE_7", 38 "WLAN_CE_8", 39 "WLAN_CE_9", 40 "WLAN_CE_10", 41 "WLAN_CE_11", 42 }; 43 44 static const char * const ath10k_regulators[] = { 45 "vdd-0.8-cx-mx", 46 "vdd-1.8-xo", 47 "vdd-1.3-rfa", 48 "vdd-3.3-ch0", 49 "vdd-3.3-ch1", 50 }; 51 52 static const char * const ath10k_clocks[] = { 53 "cxo_ref_clk_pin", "qdss", 54 }; 55 56 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 57 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 58 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 59 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 60 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 61 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 62 63 static const struct ath10k_snoc_drv_priv drv_priv = { 64 .hw_rev = ATH10K_HW_WCN3990, 65 .dma_mask = DMA_BIT_MASK(35), 66 .msa_size = 0x100000, 67 }; 68 69 #define WCN3990_SRC_WR_IDX_OFFSET 0x3C 70 #define WCN3990_DST_WR_IDX_OFFSET 0x40 71 72 static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = { 73 { 74 .ce_id = __cpu_to_le16(0), 75 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 76 }, 77 78 { 79 .ce_id = __cpu_to_le16(3), 80 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 81 }, 82 83 { 84 .ce_id = __cpu_to_le16(4), 85 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 86 }, 87 88 { 89 .ce_id = __cpu_to_le16(5), 90 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 91 }, 92 93 { 94 .ce_id = __cpu_to_le16(7), 95 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET), 96 }, 97 98 { 99 .ce_id = __cpu_to_le16(1), 100 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 101 }, 102 103 { 104 .ce_id = __cpu_to_le16(2), 105 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 106 }, 107 108 { 109 .ce_id = __cpu_to_le16(7), 110 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 111 }, 112 113 { 114 .ce_id = __cpu_to_le16(8), 115 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 116 }, 117 118 { 119 .ce_id = __cpu_to_le16(9), 120 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 121 }, 122 123 { 124 .ce_id = __cpu_to_le16(10), 125 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 126 }, 127 128 { 129 .ce_id = __cpu_to_le16(11), 130 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET), 131 }, 132 }; 133 134 static struct ce_attr host_ce_config_wlan[] = { 135 /* CE0: host->target HTC control streams */ 136 { 137 .flags = CE_ATTR_FLAGS, 138 .src_nentries = 16, 139 .src_sz_max = 2048, 140 .dest_nentries = 0, 141 .send_cb = ath10k_snoc_htc_tx_cb, 142 }, 143 144 /* CE1: target->host HTT + HTC control */ 145 { 146 .flags = CE_ATTR_FLAGS, 147 .src_nentries = 0, 148 .src_sz_max = 2048, 149 .dest_nentries = 512, 150 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 151 }, 152 153 /* CE2: target->host WMI */ 154 { 155 .flags = CE_ATTR_FLAGS, 156 .src_nentries = 0, 157 .src_sz_max = 2048, 158 .dest_nentries = 64, 159 .recv_cb = ath10k_snoc_htc_rx_cb, 160 }, 161 162 /* CE3: host->target WMI */ 163 { 164 .flags = CE_ATTR_FLAGS, 165 .src_nentries = 32, 166 .src_sz_max = 2048, 167 .dest_nentries = 0, 168 .send_cb = ath10k_snoc_htc_tx_cb, 169 }, 170 171 /* CE4: host->target HTT */ 172 { 173 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 174 .src_nentries = 2048, 175 .src_sz_max = 256, 176 .dest_nentries = 0, 177 .send_cb = ath10k_snoc_htt_tx_cb, 178 }, 179 180 /* CE5: target->host HTT (ipa_uc->target ) */ 181 { 182 .flags = CE_ATTR_FLAGS, 183 .src_nentries = 0, 184 .src_sz_max = 512, 185 .dest_nentries = 512, 186 .recv_cb = ath10k_snoc_htt_rx_cb, 187 }, 188 189 /* CE6: target autonomous hif_memcpy */ 190 { 191 .flags = CE_ATTR_FLAGS, 192 .src_nentries = 0, 193 .src_sz_max = 0, 194 .dest_nentries = 0, 195 }, 196 197 /* CE7: ce_diag, the Diagnostic Window */ 198 { 199 .flags = CE_ATTR_FLAGS, 200 .src_nentries = 2, 201 .src_sz_max = 2048, 202 .dest_nentries = 2, 203 }, 204 205 /* CE8: Target to uMC */ 206 { 207 .flags = CE_ATTR_FLAGS, 208 .src_nentries = 0, 209 .src_sz_max = 2048, 210 .dest_nentries = 128, 211 }, 212 213 /* CE9 target->host HTT */ 214 { 215 .flags = CE_ATTR_FLAGS, 216 .src_nentries = 0, 217 .src_sz_max = 2048, 218 .dest_nentries = 512, 219 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 220 }, 221 222 /* CE10: target->host HTT */ 223 { 224 .flags = CE_ATTR_FLAGS, 225 .src_nentries = 0, 226 .src_sz_max = 2048, 227 .dest_nentries = 512, 228 .recv_cb = ath10k_snoc_htt_htc_rx_cb, 229 }, 230 231 /* CE11: target -> host PKTLOG */ 232 { 233 .flags = CE_ATTR_FLAGS, 234 .src_nentries = 0, 235 .src_sz_max = 2048, 236 .dest_nentries = 512, 237 .recv_cb = ath10k_snoc_pktlog_rx_cb, 238 }, 239 }; 240 241 static struct ce_pipe_config target_ce_config_wlan[] = { 242 /* CE0: host->target HTC control and raw streams */ 243 { 244 .pipenum = __cpu_to_le32(0), 245 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 246 .nentries = __cpu_to_le32(32), 247 .nbytes_max = __cpu_to_le32(2048), 248 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 249 .reserved = __cpu_to_le32(0), 250 }, 251 252 /* CE1: target->host HTT + HTC control */ 253 { 254 .pipenum = __cpu_to_le32(1), 255 .pipedir = __cpu_to_le32(PIPEDIR_IN), 256 .nentries = __cpu_to_le32(32), 257 .nbytes_max = __cpu_to_le32(2048), 258 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 259 .reserved = __cpu_to_le32(0), 260 }, 261 262 /* CE2: target->host WMI */ 263 { 264 .pipenum = __cpu_to_le32(2), 265 .pipedir = __cpu_to_le32(PIPEDIR_IN), 266 .nentries = __cpu_to_le32(64), 267 .nbytes_max = __cpu_to_le32(2048), 268 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 269 .reserved = __cpu_to_le32(0), 270 }, 271 272 /* CE3: host->target WMI */ 273 { 274 .pipenum = __cpu_to_le32(3), 275 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 276 .nentries = __cpu_to_le32(32), 277 .nbytes_max = __cpu_to_le32(2048), 278 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 279 .reserved = __cpu_to_le32(0), 280 }, 281 282 /* CE4: host->target HTT */ 283 { 284 .pipenum = __cpu_to_le32(4), 285 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 286 .nentries = __cpu_to_le32(256), 287 .nbytes_max = __cpu_to_le32(256), 288 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 289 .reserved = __cpu_to_le32(0), 290 }, 291 292 /* CE5: target->host HTT (HIF->HTT) */ 293 { 294 .pipenum = __cpu_to_le32(5), 295 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 296 .nentries = __cpu_to_le32(1024), 297 .nbytes_max = __cpu_to_le32(64), 298 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 299 .reserved = __cpu_to_le32(0), 300 }, 301 302 /* CE6: Reserved for target autonomous hif_memcpy */ 303 { 304 .pipenum = __cpu_to_le32(6), 305 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 306 .nentries = __cpu_to_le32(32), 307 .nbytes_max = __cpu_to_le32(16384), 308 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 309 .reserved = __cpu_to_le32(0), 310 }, 311 312 /* CE7 used only by Host */ 313 { 314 .pipenum = __cpu_to_le32(7), 315 .pipedir = __cpu_to_le32(4), 316 .nentries = __cpu_to_le32(0), 317 .nbytes_max = __cpu_to_le32(0), 318 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 319 .reserved = __cpu_to_le32(0), 320 }, 321 322 /* CE8 Target to uMC */ 323 { 324 .pipenum = __cpu_to_le32(8), 325 .pipedir = __cpu_to_le32(PIPEDIR_IN), 326 .nentries = __cpu_to_le32(32), 327 .nbytes_max = __cpu_to_le32(2048), 328 .flags = __cpu_to_le32(0), 329 .reserved = __cpu_to_le32(0), 330 }, 331 332 /* CE9 target->host HTT */ 333 { 334 .pipenum = __cpu_to_le32(9), 335 .pipedir = __cpu_to_le32(PIPEDIR_IN), 336 .nentries = __cpu_to_le32(32), 337 .nbytes_max = __cpu_to_le32(2048), 338 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 339 .reserved = __cpu_to_le32(0), 340 }, 341 342 /* CE10 target->host HTT */ 343 { 344 .pipenum = __cpu_to_le32(10), 345 .pipedir = __cpu_to_le32(PIPEDIR_IN), 346 .nentries = __cpu_to_le32(32), 347 .nbytes_max = __cpu_to_le32(2048), 348 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 349 .reserved = __cpu_to_le32(0), 350 }, 351 352 /* CE11 target autonomous qcache memcpy */ 353 { 354 .pipenum = __cpu_to_le32(11), 355 .pipedir = __cpu_to_le32(PIPEDIR_IN), 356 .nentries = __cpu_to_le32(32), 357 .nbytes_max = __cpu_to_le32(2048), 358 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 359 .reserved = __cpu_to_le32(0), 360 }, 361 }; 362 363 static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = { 364 { 365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 366 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 367 __cpu_to_le32(3), 368 }, 369 { 370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 371 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 372 __cpu_to_le32(2), 373 }, 374 { 375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 376 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 377 __cpu_to_le32(3), 378 }, 379 { 380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 381 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 382 __cpu_to_le32(2), 383 }, 384 { 385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 386 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 387 __cpu_to_le32(3), 388 }, 389 { 390 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 391 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 392 __cpu_to_le32(2), 393 }, 394 { 395 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 396 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 397 __cpu_to_le32(3), 398 }, 399 { 400 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 401 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 402 __cpu_to_le32(2), 403 }, 404 { 405 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 406 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 407 __cpu_to_le32(3), 408 }, 409 { 410 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 411 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 412 __cpu_to_le32(2), 413 }, 414 { 415 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 416 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 417 __cpu_to_le32(0), 418 }, 419 { 420 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 421 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 422 __cpu_to_le32(2), 423 }, 424 { /* not used */ 425 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 426 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 427 __cpu_to_le32(0), 428 }, 429 { /* not used */ 430 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 431 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 432 __cpu_to_le32(2), 433 }, 434 { 435 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 436 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 437 __cpu_to_le32(4), 438 }, 439 { 440 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 441 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 442 __cpu_to_le32(1), 443 }, 444 { /* not used */ 445 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 446 __cpu_to_le32(PIPEDIR_OUT), 447 __cpu_to_le32(5), 448 }, 449 { /* in = DL = target -> host */ 450 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG), 451 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 452 __cpu_to_le32(9), 453 }, 454 { /* in = DL = target -> host */ 455 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG), 456 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 457 __cpu_to_le32(10), 458 }, 459 { /* in = DL = target -> host pktlog */ 460 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG), 461 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 462 __cpu_to_le32(11), 463 }, 464 /* (Additions here) */ 465 466 { /* must be last */ 467 __cpu_to_le32(0), 468 __cpu_to_le32(0), 469 __cpu_to_le32(0), 470 }, 471 }; 472 473 static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value) 474 { 475 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 476 477 iowrite32(value, ar_snoc->mem + offset); 478 } 479 480 static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset) 481 { 482 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 483 u32 val; 484 485 val = ioread32(ar_snoc->mem + offset); 486 487 return val; 488 } 489 490 static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe) 491 { 492 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 493 struct ath10k *ar = pipe->hif_ce_state; 494 struct ath10k_ce *ce = ath10k_ce_priv(ar); 495 struct sk_buff *skb; 496 dma_addr_t paddr; 497 int ret; 498 499 skb = dev_alloc_skb(pipe->buf_sz); 500 if (!skb) 501 return -ENOMEM; 502 503 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 504 505 paddr = dma_map_single(ar->dev, skb->data, 506 skb->len + skb_tailroom(skb), 507 DMA_FROM_DEVICE); 508 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 509 ath10k_warn(ar, "failed to dma map snoc rx buf\n"); 510 dev_kfree_skb_any(skb); 511 return -EIO; 512 } 513 514 ATH10K_SKB_RXCB(skb)->paddr = paddr; 515 516 spin_lock_bh(&ce->ce_lock); 517 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr); 518 spin_unlock_bh(&ce->ce_lock); 519 if (ret) { 520 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 521 DMA_FROM_DEVICE); 522 dev_kfree_skb_any(skb); 523 return ret; 524 } 525 526 return 0; 527 } 528 529 static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe) 530 { 531 struct ath10k *ar = pipe->hif_ce_state; 532 struct ath10k_ce *ce = ath10k_ce_priv(ar); 533 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 534 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 535 int ret, num; 536 537 if (pipe->buf_sz == 0) 538 return; 539 540 if (!ce_pipe->dest_ring) 541 return; 542 543 spin_lock_bh(&ce->ce_lock); 544 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 545 spin_unlock_bh(&ce->ce_lock); 546 while (num--) { 547 ret = __ath10k_snoc_rx_post_buf(pipe); 548 if (ret) { 549 if (ret == -ENOSPC) 550 break; 551 ath10k_warn(ar, "failed to post rx buf: %d\n", ret); 552 mod_timer(&ar_snoc->rx_post_retry, jiffies + 553 ATH10K_SNOC_RX_POST_RETRY_MS); 554 break; 555 } 556 } 557 } 558 559 static void ath10k_snoc_rx_post(struct ath10k *ar) 560 { 561 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 562 int i; 563 564 for (i = 0; i < CE_COUNT; i++) 565 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]); 566 } 567 568 static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state, 569 void (*callback)(struct ath10k *ar, 570 struct sk_buff *skb)) 571 { 572 struct ath10k *ar = ce_state->ar; 573 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 574 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id]; 575 struct sk_buff *skb; 576 struct sk_buff_head list; 577 void *transfer_context; 578 unsigned int nbytes, max_nbytes; 579 580 __skb_queue_head_init(&list); 581 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 582 &nbytes) == 0) { 583 skb = transfer_context; 584 max_nbytes = skb->len + skb_tailroom(skb); 585 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 586 max_nbytes, DMA_FROM_DEVICE); 587 588 if (unlikely(max_nbytes < nbytes)) { 589 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n", 590 nbytes, max_nbytes); 591 dev_kfree_skb_any(skb); 592 continue; 593 } 594 595 skb_put(skb, nbytes); 596 __skb_queue_tail(&list, skb); 597 } 598 599 while ((skb = __skb_dequeue(&list))) { 600 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n", 601 ce_state->id, skb->len); 602 603 callback(ar, skb); 604 } 605 606 ath10k_snoc_rx_post_pipe(pipe_info); 607 } 608 609 static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 610 { 611 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 612 } 613 614 static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 615 { 616 /* CE4 polling needs to be done whenever CE pipe which transports 617 * HTT Rx (target->host) is processed. 618 */ 619 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 620 621 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 622 } 623 624 /* Called by lower (CE) layer when data is received from the Target. 625 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data. 626 */ 627 static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 628 { 629 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 630 } 631 632 static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 633 { 634 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 635 ath10k_htt_t2h_msg_handler(ar, skb); 636 } 637 638 static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 639 { 640 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE); 641 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver); 642 } 643 644 static void ath10k_snoc_rx_replenish_retry(struct timer_list *t) 645 { 646 struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry); 647 struct ath10k *ar = ar_snoc->ar; 648 649 ath10k_snoc_rx_post(ar); 650 } 651 652 static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 653 { 654 struct ath10k *ar = ce_state->ar; 655 struct sk_buff_head list; 656 struct sk_buff *skb; 657 658 __skb_queue_head_init(&list); 659 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 660 if (!skb) 661 continue; 662 663 __skb_queue_tail(&list, skb); 664 } 665 666 while ((skb = __skb_dequeue(&list))) 667 ath10k_htc_tx_completion_handler(ar, skb); 668 } 669 670 static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 671 { 672 struct ath10k *ar = ce_state->ar; 673 struct sk_buff *skb; 674 675 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 676 if (!skb) 677 continue; 678 679 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 680 skb->len, DMA_TO_DEVICE); 681 ath10k_htt_hif_tx_complete(ar, skb); 682 } 683 } 684 685 static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 686 struct ath10k_hif_sg_item *items, int n_items) 687 { 688 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 689 struct ath10k_ce *ce = ath10k_ce_priv(ar); 690 struct ath10k_snoc_pipe *snoc_pipe; 691 struct ath10k_ce_pipe *ce_pipe; 692 int err, i = 0; 693 694 snoc_pipe = &ar_snoc->pipe_info[pipe_id]; 695 ce_pipe = snoc_pipe->ce_hdl; 696 spin_lock_bh(&ce->ce_lock); 697 698 for (i = 0; i < n_items - 1; i++) { 699 ath10k_dbg(ar, ATH10K_DBG_SNOC, 700 "snoc tx item %d paddr %pad len %d n_items %d\n", 701 i, &items[i].paddr, items[i].len, n_items); 702 703 err = ath10k_ce_send_nolock(ce_pipe, 704 items[i].transfer_context, 705 items[i].paddr, 706 items[i].len, 707 items[i].transfer_id, 708 CE_SEND_FLAG_GATHER); 709 if (err) 710 goto err; 711 } 712 713 ath10k_dbg(ar, ATH10K_DBG_SNOC, 714 "snoc tx item %d paddr %pad len %d n_items %d\n", 715 i, &items[i].paddr, items[i].len, n_items); 716 717 err = ath10k_ce_send_nolock(ce_pipe, 718 items[i].transfer_context, 719 items[i].paddr, 720 items[i].len, 721 items[i].transfer_id, 722 0); 723 if (err) 724 goto err; 725 726 spin_unlock_bh(&ce->ce_lock); 727 728 return 0; 729 730 err: 731 for (; i > 0; i--) 732 __ath10k_ce_send_revert(ce_pipe); 733 734 spin_unlock_bh(&ce->ce_lock); 735 return err; 736 } 737 738 static int ath10k_snoc_hif_get_target_info(struct ath10k *ar, 739 struct bmi_target_info *target_info) 740 { 741 target_info->version = ATH10K_HW_WCN3990; 742 target_info->type = ATH10K_HW_WCN3990; 743 744 return 0; 745 } 746 747 static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 748 { 749 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 750 751 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n"); 752 753 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl); 754 } 755 756 static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe, 757 int force) 758 { 759 int resources; 760 761 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n"); 762 763 if (!force) { 764 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe); 765 766 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 767 return; 768 } 769 ath10k_ce_per_engine_service(ar, pipe); 770 } 771 772 static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar, 773 u16 service_id, 774 u8 *ul_pipe, u8 *dl_pipe) 775 { 776 const struct ce_service_to_pipe *entry; 777 bool ul_set = false, dl_set = false; 778 int i; 779 780 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n"); 781 782 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 783 entry = &target_service_to_ce_map_wlan[i]; 784 785 if (__le32_to_cpu(entry->service_id) != service_id) 786 continue; 787 788 switch (__le32_to_cpu(entry->pipedir)) { 789 case PIPEDIR_NONE: 790 break; 791 case PIPEDIR_IN: 792 WARN_ON(dl_set); 793 *dl_pipe = __le32_to_cpu(entry->pipenum); 794 dl_set = true; 795 break; 796 case PIPEDIR_OUT: 797 WARN_ON(ul_set); 798 *ul_pipe = __le32_to_cpu(entry->pipenum); 799 ul_set = true; 800 break; 801 case PIPEDIR_INOUT: 802 WARN_ON(dl_set); 803 WARN_ON(ul_set); 804 *dl_pipe = __le32_to_cpu(entry->pipenum); 805 *ul_pipe = __le32_to_cpu(entry->pipenum); 806 dl_set = true; 807 ul_set = true; 808 break; 809 } 810 } 811 812 if (!ul_set || !dl_set) 813 return -ENOENT; 814 815 return 0; 816 } 817 818 static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar, 819 u8 *ul_pipe, u8 *dl_pipe) 820 { 821 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n"); 822 823 (void)ath10k_snoc_hif_map_service_to_pipe(ar, 824 ATH10K_HTC_SVC_ID_RSVD_CTRL, 825 ul_pipe, dl_pipe); 826 } 827 828 static inline void ath10k_snoc_irq_disable(struct ath10k *ar) 829 { 830 ath10k_ce_disable_interrupts(ar); 831 } 832 833 static inline void ath10k_snoc_irq_enable(struct ath10k *ar) 834 { 835 ath10k_ce_enable_interrupts(ar); 836 } 837 838 static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 839 { 840 struct ath10k_ce_pipe *ce_pipe; 841 struct ath10k_ce_ring *ce_ring; 842 struct sk_buff *skb; 843 struct ath10k *ar; 844 int i; 845 846 ar = snoc_pipe->hif_ce_state; 847 ce_pipe = snoc_pipe->ce_hdl; 848 ce_ring = ce_pipe->dest_ring; 849 850 if (!ce_ring) 851 return; 852 853 if (!snoc_pipe->buf_sz) 854 return; 855 856 for (i = 0; i < ce_ring->nentries; i++) { 857 skb = ce_ring->per_transfer_context[i]; 858 if (!skb) 859 continue; 860 861 ce_ring->per_transfer_context[i] = NULL; 862 863 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 864 skb->len + skb_tailroom(skb), 865 DMA_FROM_DEVICE); 866 dev_kfree_skb_any(skb); 867 } 868 } 869 870 static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe) 871 { 872 struct ath10k_ce_pipe *ce_pipe; 873 struct ath10k_ce_ring *ce_ring; 874 struct sk_buff *skb; 875 struct ath10k *ar; 876 int i; 877 878 ar = snoc_pipe->hif_ce_state; 879 ce_pipe = snoc_pipe->ce_hdl; 880 ce_ring = ce_pipe->src_ring; 881 882 if (!ce_ring) 883 return; 884 885 if (!snoc_pipe->buf_sz) 886 return; 887 888 for (i = 0; i < ce_ring->nentries; i++) { 889 skb = ce_ring->per_transfer_context[i]; 890 if (!skb) 891 continue; 892 893 ce_ring->per_transfer_context[i] = NULL; 894 895 ath10k_htc_tx_completion_handler(ar, skb); 896 } 897 } 898 899 static void ath10k_snoc_buffer_cleanup(struct ath10k *ar) 900 { 901 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 902 struct ath10k_snoc_pipe *pipe_info; 903 int pipe_num; 904 905 del_timer_sync(&ar_snoc->rx_post_retry); 906 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 907 pipe_info = &ar_snoc->pipe_info[pipe_num]; 908 ath10k_snoc_rx_pipe_cleanup(pipe_info); 909 ath10k_snoc_tx_pipe_cleanup(pipe_info); 910 } 911 } 912 913 static void ath10k_snoc_hif_stop(struct ath10k *ar) 914 { 915 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) 916 ath10k_snoc_irq_disable(ar); 917 918 ath10k_core_napi_sync_disable(ar); 919 ath10k_snoc_buffer_cleanup(ar); 920 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 921 } 922 923 static int ath10k_snoc_hif_start(struct ath10k *ar) 924 { 925 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 926 927 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX); 928 929 ath10k_core_napi_enable(ar); 930 ath10k_snoc_irq_enable(ar); 931 ath10k_snoc_rx_post(ar); 932 933 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 934 935 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 936 937 return 0; 938 } 939 940 static int ath10k_snoc_init_pipes(struct ath10k *ar) 941 { 942 int i, ret; 943 944 for (i = 0; i < CE_COUNT; i++) { 945 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 946 if (ret) { 947 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 948 i, ret); 949 return ret; 950 } 951 } 952 953 return 0; 954 } 955 956 static int ath10k_snoc_wlan_enable(struct ath10k *ar, 957 enum ath10k_firmware_mode fw_mode) 958 { 959 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX]; 960 struct ath10k_qmi_wlan_enable_cfg cfg; 961 enum wlfw_driver_mode_enum_v01 mode; 962 int pipe_num; 963 964 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) { 965 tgt_cfg[pipe_num].pipe_num = 966 target_ce_config_wlan[pipe_num].pipenum; 967 tgt_cfg[pipe_num].pipe_dir = 968 target_ce_config_wlan[pipe_num].pipedir; 969 tgt_cfg[pipe_num].nentries = 970 target_ce_config_wlan[pipe_num].nentries; 971 tgt_cfg[pipe_num].nbytes_max = 972 target_ce_config_wlan[pipe_num].nbytes_max; 973 tgt_cfg[pipe_num].flags = 974 target_ce_config_wlan[pipe_num].flags; 975 tgt_cfg[pipe_num].reserved = 0; 976 } 977 978 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) / 979 sizeof(struct ath10k_tgt_pipe_cfg); 980 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *) 981 &tgt_cfg; 982 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) / 983 sizeof(struct ath10k_svc_pipe_cfg); 984 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *) 985 &target_service_to_ce_map_wlan; 986 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map); 987 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *) 988 &target_shadow_reg_cfg_map; 989 990 switch (fw_mode) { 991 case ATH10K_FIRMWARE_MODE_NORMAL: 992 mode = QMI_WLFW_MISSION_V01; 993 break; 994 case ATH10K_FIRMWARE_MODE_UTF: 995 mode = QMI_WLFW_FTM_V01; 996 break; 997 default: 998 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode); 999 return -EINVAL; 1000 } 1001 1002 return ath10k_qmi_wlan_enable(ar, &cfg, mode, 1003 NULL); 1004 } 1005 1006 static int ath10k_hw_power_on(struct ath10k *ar) 1007 { 1008 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1009 int ret; 1010 1011 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n"); 1012 1013 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs); 1014 if (ret) 1015 return ret; 1016 1017 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks); 1018 if (ret) 1019 goto vreg_off; 1020 1021 return ret; 1022 1023 vreg_off: 1024 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1025 return ret; 1026 } 1027 1028 static int ath10k_hw_power_off(struct ath10k *ar) 1029 { 1030 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1031 1032 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n"); 1033 1034 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks); 1035 1036 return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs); 1037 } 1038 1039 static void ath10k_snoc_wlan_disable(struct ath10k *ar) 1040 { 1041 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1042 1043 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY 1044 * flags are not set, it means that the driver has restarted 1045 * due to a crash inject via debugfs. In this case, the driver 1046 * needs to restart the firmware and hence send qmi wlan disable, 1047 * during the driver restart sequence. 1048 */ 1049 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) || 1050 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1051 ath10k_qmi_wlan_disable(ar); 1052 } 1053 1054 static void ath10k_snoc_hif_power_down(struct ath10k *ar) 1055 { 1056 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 1057 1058 ath10k_snoc_wlan_disable(ar); 1059 ath10k_ce_free_rri(ar); 1060 ath10k_hw_power_off(ar); 1061 } 1062 1063 static int ath10k_snoc_hif_power_up(struct ath10k *ar, 1064 enum ath10k_firmware_mode fw_mode) 1065 { 1066 int ret; 1067 1068 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n", 1069 __func__, ar->state); 1070 1071 ret = ath10k_hw_power_on(ar); 1072 if (ret) { 1073 ath10k_err(ar, "failed to power on device: %d\n", ret); 1074 return ret; 1075 } 1076 1077 ret = ath10k_snoc_wlan_enable(ar, fw_mode); 1078 if (ret) { 1079 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret); 1080 goto err_hw_power_off; 1081 } 1082 1083 ath10k_ce_alloc_rri(ar); 1084 1085 ret = ath10k_snoc_init_pipes(ar); 1086 if (ret) { 1087 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 1088 goto err_free_rri; 1089 } 1090 1091 return 0; 1092 1093 err_free_rri: 1094 ath10k_ce_free_rri(ar); 1095 ath10k_snoc_wlan_disable(ar); 1096 1097 err_hw_power_off: 1098 ath10k_hw_power_off(ar); 1099 1100 return ret; 1101 } 1102 1103 static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar, 1104 u8 fw_log_mode) 1105 { 1106 u8 fw_dbg_mode; 1107 1108 if (fw_log_mode) 1109 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE; 1110 else 1111 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG; 1112 1113 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode); 1114 } 1115 1116 #ifdef CONFIG_PM 1117 static int ath10k_snoc_hif_suspend(struct ath10k *ar) 1118 { 1119 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1120 int ret; 1121 1122 if (!device_may_wakeup(ar->dev)) 1123 return -EPERM; 1124 1125 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1126 if (ret) { 1127 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret); 1128 return ret; 1129 } 1130 1131 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n"); 1132 1133 return ret; 1134 } 1135 1136 static int ath10k_snoc_hif_resume(struct ath10k *ar) 1137 { 1138 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1139 int ret; 1140 1141 if (!device_may_wakeup(ar->dev)) 1142 return -EPERM; 1143 1144 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line); 1145 if (ret) { 1146 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret); 1147 return ret; 1148 } 1149 1150 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n"); 1151 1152 return ret; 1153 } 1154 #endif 1155 1156 static const struct ath10k_hif_ops ath10k_snoc_hif_ops = { 1157 .read32 = ath10k_snoc_read32, 1158 .write32 = ath10k_snoc_write32, 1159 .start = ath10k_snoc_hif_start, 1160 .stop = ath10k_snoc_hif_stop, 1161 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe, 1162 .get_default_pipe = ath10k_snoc_hif_get_default_pipe, 1163 .power_up = ath10k_snoc_hif_power_up, 1164 .power_down = ath10k_snoc_hif_power_down, 1165 .tx_sg = ath10k_snoc_hif_tx_sg, 1166 .send_complete_check = ath10k_snoc_hif_send_complete_check, 1167 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number, 1168 .get_target_info = ath10k_snoc_hif_get_target_info, 1169 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode, 1170 1171 #ifdef CONFIG_PM 1172 .suspend = ath10k_snoc_hif_suspend, 1173 .resume = ath10k_snoc_hif_resume, 1174 #endif 1175 }; 1176 1177 static const struct ath10k_bus_ops ath10k_snoc_bus_ops = { 1178 .read32 = ath10k_snoc_read32, 1179 .write32 = ath10k_snoc_write32, 1180 }; 1181 1182 static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq) 1183 { 1184 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1185 int i; 1186 1187 for (i = 0; i < CE_COUNT_MAX; i++) { 1188 if (ar_snoc->ce_irqs[i].irq_line == irq) 1189 return i; 1190 } 1191 ath10k_err(ar, "No matching CE id for irq %d\n", irq); 1192 1193 return -EINVAL; 1194 } 1195 1196 static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg) 1197 { 1198 struct ath10k *ar = arg; 1199 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1200 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq); 1201 1202 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) { 1203 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, 1204 ce_id); 1205 return IRQ_HANDLED; 1206 } 1207 1208 ath10k_ce_disable_interrupt(ar, ce_id); 1209 set_bit(ce_id, ar_snoc->pending_ce_irqs); 1210 1211 napi_schedule(&ar->napi); 1212 1213 return IRQ_HANDLED; 1214 } 1215 1216 static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget) 1217 { 1218 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 1219 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1220 int done = 0; 1221 int ce_id; 1222 1223 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) { 1224 napi_complete(ctx); 1225 return done; 1226 } 1227 1228 for (ce_id = 0; ce_id < CE_COUNT; ce_id++) 1229 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) { 1230 ath10k_ce_per_engine_service(ar, ce_id); 1231 ath10k_ce_enable_interrupt(ar, ce_id); 1232 } 1233 1234 done = ath10k_htt_txrx_compl_task(ar, budget); 1235 1236 if (done < budget) 1237 napi_complete(ctx); 1238 1239 return done; 1240 } 1241 1242 static void ath10k_snoc_init_napi(struct ath10k *ar) 1243 { 1244 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll, 1245 ATH10K_NAPI_BUDGET); 1246 } 1247 1248 static int ath10k_snoc_request_irq(struct ath10k *ar) 1249 { 1250 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1251 int irqflags = IRQF_TRIGGER_RISING; 1252 int ret, id; 1253 1254 for (id = 0; id < CE_COUNT_MAX; id++) { 1255 ret = request_irq(ar_snoc->ce_irqs[id].irq_line, 1256 ath10k_snoc_per_engine_handler, 1257 irqflags, ce_name[id], ar); 1258 if (ret) { 1259 ath10k_err(ar, 1260 "failed to register IRQ handler for CE %d: %d\n", 1261 id, ret); 1262 goto err_irq; 1263 } 1264 } 1265 1266 return 0; 1267 1268 err_irq: 1269 for (id -= 1; id >= 0; id--) 1270 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1271 1272 return ret; 1273 } 1274 1275 static void ath10k_snoc_free_irq(struct ath10k *ar) 1276 { 1277 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1278 int id; 1279 1280 for (id = 0; id < CE_COUNT_MAX; id++) 1281 free_irq(ar_snoc->ce_irqs[id].irq_line, ar); 1282 } 1283 1284 static int ath10k_snoc_resource_init(struct ath10k *ar) 1285 { 1286 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1287 struct platform_device *pdev; 1288 struct resource *res; 1289 int i, ret = 0; 1290 1291 pdev = ar_snoc->dev; 1292 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase"); 1293 if (!res) { 1294 ath10k_err(ar, "Memory base not found in DT\n"); 1295 return -EINVAL; 1296 } 1297 1298 ar_snoc->mem_pa = res->start; 1299 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa, 1300 resource_size(res)); 1301 if (!ar_snoc->mem) { 1302 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n", 1303 &ar_snoc->mem_pa); 1304 return -EINVAL; 1305 } 1306 1307 for (i = 0; i < CE_COUNT; i++) { 1308 res = platform_get_resource(ar_snoc->dev, IORESOURCE_IRQ, i); 1309 if (!res) { 1310 ath10k_err(ar, "failed to get IRQ%d\n", i); 1311 ret = -ENODEV; 1312 goto out; 1313 } 1314 ar_snoc->ce_irqs[i].irq_line = res->start; 1315 } 1316 1317 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data", 1318 &ar_snoc->xo_cal_data); 1319 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret); 1320 if (ret == 0) { 1321 ar_snoc->xo_cal_supported = true; 1322 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n", 1323 ar_snoc->xo_cal_data); 1324 } 1325 ret = 0; 1326 1327 out: 1328 return ret; 1329 } 1330 1331 static void ath10k_snoc_quirks_init(struct ath10k *ar) 1332 { 1333 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1334 struct device *dev = &ar_snoc->dev->dev; 1335 1336 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk")) 1337 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags); 1338 } 1339 1340 int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type) 1341 { 1342 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1343 struct ath10k_bus_params bus_params = {}; 1344 int ret; 1345 1346 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags)) 1347 return 0; 1348 1349 switch (type) { 1350 case ATH10K_QMI_EVENT_FW_READY_IND: 1351 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) { 1352 ath10k_core_start_recovery(ar); 1353 break; 1354 } 1355 1356 bus_params.dev_type = ATH10K_DEV_TYPE_LL; 1357 bus_params.chip_id = ar_snoc->target_info.soc_version; 1358 ret = ath10k_core_register(ar, &bus_params); 1359 if (ret) { 1360 ath10k_err(ar, "Failed to register driver core: %d\n", 1361 ret); 1362 return ret; 1363 } 1364 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags); 1365 break; 1366 case ATH10K_QMI_EVENT_FW_DOWN_IND: 1367 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags); 1368 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); 1369 break; 1370 default: 1371 ath10k_err(ar, "invalid fw indication: %llx\n", type); 1372 return -EINVAL; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int ath10k_snoc_setup_resource(struct ath10k *ar) 1379 { 1380 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1381 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1382 struct ath10k_snoc_pipe *pipe; 1383 int i, ret; 1384 1385 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0); 1386 spin_lock_init(&ce->ce_lock); 1387 for (i = 0; i < CE_COUNT; i++) { 1388 pipe = &ar_snoc->pipe_info[i]; 1389 pipe->ce_hdl = &ce->ce_states[i]; 1390 pipe->pipe_num = i; 1391 pipe->hif_ce_state = ar; 1392 1393 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 1394 if (ret) { 1395 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 1396 i, ret); 1397 return ret; 1398 } 1399 1400 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max; 1401 } 1402 ath10k_snoc_init_napi(ar); 1403 1404 return 0; 1405 } 1406 1407 static void ath10k_snoc_release_resource(struct ath10k *ar) 1408 { 1409 int i; 1410 1411 netif_napi_del(&ar->napi); 1412 for (i = 0; i < CE_COUNT; i++) 1413 ath10k_ce_free_pipe(ar, i); 1414 } 1415 1416 static void ath10k_msa_dump_memory(struct ath10k *ar, 1417 struct ath10k_fw_crash_data *crash_data) 1418 { 1419 const struct ath10k_hw_mem_layout *mem_layout; 1420 const struct ath10k_mem_region *current_region; 1421 struct ath10k_dump_ram_data_hdr *hdr; 1422 size_t buf_len; 1423 u8 *buf; 1424 1425 if (!crash_data || !crash_data->ramdump_buf) 1426 return; 1427 1428 mem_layout = ath10k_coredump_get_mem_layout(ar); 1429 if (!mem_layout) 1430 return; 1431 1432 current_region = &mem_layout->region_table.regions[0]; 1433 1434 buf = crash_data->ramdump_buf; 1435 buf_len = crash_data->ramdump_buf_len; 1436 memset(buf, 0, buf_len); 1437 1438 /* Reserve space for the header. */ 1439 hdr = (void *)buf; 1440 buf += sizeof(*hdr); 1441 buf_len -= sizeof(*hdr); 1442 1443 hdr->region_type = cpu_to_le32(current_region->type); 1444 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr); 1445 hdr->length = cpu_to_le32(ar->msa.mem_size); 1446 1447 if (current_region->len < ar->msa.mem_size) { 1448 memcpy(buf, ar->msa.vaddr, current_region->len); 1449 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n", 1450 current_region->len, ar->msa.mem_size); 1451 } else { 1452 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size); 1453 } 1454 } 1455 1456 void ath10k_snoc_fw_crashed_dump(struct ath10k *ar) 1457 { 1458 struct ath10k_fw_crash_data *crash_data; 1459 char guid[UUID_STRING_LEN + 1]; 1460 1461 mutex_lock(&ar->dump_mutex); 1462 1463 spin_lock_bh(&ar->data_lock); 1464 ar->stats.fw_crash_counter++; 1465 spin_unlock_bh(&ar->data_lock); 1466 1467 crash_data = ath10k_coredump_new(ar); 1468 1469 if (crash_data) 1470 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1471 else 1472 scnprintf(guid, sizeof(guid), "n/a"); 1473 1474 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1475 ath10k_print_driver_info(ar); 1476 ath10k_msa_dump_memory(ar, crash_data); 1477 mutex_unlock(&ar->dump_mutex); 1478 } 1479 1480 static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size) 1481 { 1482 struct device *dev = ar->dev; 1483 struct device_node *node; 1484 struct resource r; 1485 int ret; 1486 1487 node = of_parse_phandle(dev->of_node, "memory-region", 0); 1488 if (node) { 1489 ret = of_address_to_resource(node, 0, &r); 1490 if (ret) { 1491 dev_err(dev, "failed to resolve msa fixed region\n"); 1492 return ret; 1493 } 1494 of_node_put(node); 1495 1496 ar->msa.paddr = r.start; 1497 ar->msa.mem_size = resource_size(&r); 1498 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr, 1499 ar->msa.mem_size, 1500 MEMREMAP_WT); 1501 if (IS_ERR(ar->msa.vaddr)) { 1502 dev_err(dev, "failed to map memory region: %pa\n", 1503 &r.start); 1504 return PTR_ERR(ar->msa.vaddr); 1505 } 1506 } else { 1507 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size, 1508 &ar->msa.paddr, 1509 GFP_KERNEL); 1510 if (!ar->msa.vaddr) { 1511 ath10k_err(ar, "failed to allocate dma memory for msa region\n"); 1512 return -ENOMEM; 1513 } 1514 ar->msa.mem_size = msa_size; 1515 } 1516 1517 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n", 1518 &ar->msa.paddr, 1519 ar->msa.vaddr); 1520 1521 return 0; 1522 } 1523 1524 static int ath10k_fw_init(struct ath10k *ar) 1525 { 1526 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1527 struct device *host_dev = &ar_snoc->dev->dev; 1528 struct platform_device_info info; 1529 struct iommu_domain *iommu_dom; 1530 struct platform_device *pdev; 1531 struct device_node *node; 1532 int ret; 1533 1534 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware"); 1535 if (!node) { 1536 ar_snoc->use_tz = true; 1537 return 0; 1538 } 1539 1540 memset(&info, 0, sizeof(info)); 1541 info.fwnode = &node->fwnode; 1542 info.parent = host_dev; 1543 info.name = node->name; 1544 info.dma_mask = DMA_BIT_MASK(32); 1545 1546 pdev = platform_device_register_full(&info); 1547 if (IS_ERR(pdev)) { 1548 of_node_put(node); 1549 return PTR_ERR(pdev); 1550 } 1551 1552 pdev->dev.of_node = node; 1553 1554 ret = of_dma_configure(&pdev->dev, node, true); 1555 if (ret) { 1556 ath10k_err(ar, "dma configure fail: %d\n", ret); 1557 goto err_unregister; 1558 } 1559 1560 ar_snoc->fw.dev = &pdev->dev; 1561 1562 iommu_dom = iommu_domain_alloc(&platform_bus_type); 1563 if (!iommu_dom) { 1564 ath10k_err(ar, "failed to allocate iommu domain\n"); 1565 ret = -ENOMEM; 1566 goto err_unregister; 1567 } 1568 1569 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev); 1570 if (ret) { 1571 ath10k_err(ar, "could not attach device: %d\n", ret); 1572 goto err_iommu_free; 1573 } 1574 1575 ar_snoc->fw.iommu_domain = iommu_dom; 1576 ar_snoc->fw.fw_start_addr = ar->msa.paddr; 1577 1578 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr, 1579 ar->msa.paddr, ar->msa.mem_size, 1580 IOMMU_READ | IOMMU_WRITE); 1581 if (ret) { 1582 ath10k_err(ar, "failed to map firmware region: %d\n", ret); 1583 goto err_iommu_detach; 1584 } 1585 1586 of_node_put(node); 1587 1588 return 0; 1589 1590 err_iommu_detach: 1591 iommu_detach_device(iommu_dom, ar_snoc->fw.dev); 1592 1593 err_iommu_free: 1594 iommu_domain_free(iommu_dom); 1595 1596 err_unregister: 1597 platform_device_unregister(pdev); 1598 of_node_put(node); 1599 1600 return ret; 1601 } 1602 1603 static int ath10k_fw_deinit(struct ath10k *ar) 1604 { 1605 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1606 const size_t mapped_size = ar_snoc->fw.mapped_mem_size; 1607 struct iommu_domain *iommu; 1608 size_t unmapped_size; 1609 1610 if (ar_snoc->use_tz) 1611 return 0; 1612 1613 iommu = ar_snoc->fw.iommu_domain; 1614 1615 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr, 1616 mapped_size); 1617 if (unmapped_size != mapped_size) 1618 ath10k_err(ar, "failed to unmap firmware: %zu\n", 1619 unmapped_size); 1620 1621 iommu_detach_device(iommu, ar_snoc->fw.dev); 1622 iommu_domain_free(iommu); 1623 1624 platform_device_unregister(to_platform_device(ar_snoc->fw.dev)); 1625 1626 return 0; 1627 } 1628 1629 static const struct of_device_id ath10k_snoc_dt_match[] = { 1630 { .compatible = "qcom,wcn3990-wifi", 1631 .data = &drv_priv, 1632 }, 1633 { } 1634 }; 1635 MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match); 1636 1637 static int ath10k_snoc_probe(struct platform_device *pdev) 1638 { 1639 const struct ath10k_snoc_drv_priv *drv_data; 1640 struct ath10k_snoc *ar_snoc; 1641 struct device *dev; 1642 struct ath10k *ar; 1643 u32 msa_size; 1644 int ret; 1645 u32 i; 1646 1647 dev = &pdev->dev; 1648 drv_data = device_get_match_data(dev); 1649 if (!drv_data) { 1650 dev_err(dev, "failed to find matching device tree id\n"); 1651 return -EINVAL; 1652 } 1653 1654 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask); 1655 if (ret) { 1656 dev_err(dev, "failed to set dma mask: %d\n", ret); 1657 return ret; 1658 } 1659 1660 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC, 1661 drv_data->hw_rev, &ath10k_snoc_hif_ops); 1662 if (!ar) { 1663 dev_err(dev, "failed to allocate core\n"); 1664 return -ENOMEM; 1665 } 1666 1667 ar_snoc = ath10k_snoc_priv(ar); 1668 ar_snoc->dev = pdev; 1669 platform_set_drvdata(pdev, ar); 1670 ar_snoc->ar = ar; 1671 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops; 1672 ar->ce_priv = &ar_snoc->ce; 1673 msa_size = drv_data->msa_size; 1674 1675 ath10k_snoc_quirks_init(ar); 1676 1677 ret = ath10k_snoc_resource_init(ar); 1678 if (ret) { 1679 ath10k_warn(ar, "failed to initialize resource: %d\n", ret); 1680 goto err_core_destroy; 1681 } 1682 1683 ret = ath10k_snoc_setup_resource(ar); 1684 if (ret) { 1685 ath10k_warn(ar, "failed to setup resource: %d\n", ret); 1686 goto err_core_destroy; 1687 } 1688 ret = ath10k_snoc_request_irq(ar); 1689 if (ret) { 1690 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 1691 goto err_release_resource; 1692 } 1693 1694 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators); 1695 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs, 1696 sizeof(*ar_snoc->vregs), GFP_KERNEL); 1697 if (!ar_snoc->vregs) { 1698 ret = -ENOMEM; 1699 goto err_free_irq; 1700 } 1701 for (i = 0; i < ar_snoc->num_vregs; i++) 1702 ar_snoc->vregs[i].supply = ath10k_regulators[i]; 1703 1704 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs, 1705 ar_snoc->vregs); 1706 if (ret < 0) 1707 goto err_free_irq; 1708 1709 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks); 1710 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks, 1711 sizeof(*ar_snoc->clks), GFP_KERNEL); 1712 if (!ar_snoc->clks) { 1713 ret = -ENOMEM; 1714 goto err_free_irq; 1715 } 1716 1717 for (i = 0; i < ar_snoc->num_clks; i++) 1718 ar_snoc->clks[i].id = ath10k_clocks[i]; 1719 1720 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks, 1721 ar_snoc->clks); 1722 if (ret) 1723 goto err_free_irq; 1724 1725 ret = ath10k_setup_msa_resources(ar, msa_size); 1726 if (ret) { 1727 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret); 1728 goto err_free_irq; 1729 } 1730 1731 ret = ath10k_fw_init(ar); 1732 if (ret) { 1733 ath10k_err(ar, "failed to initialize firmware: %d\n", ret); 1734 goto err_free_irq; 1735 } 1736 1737 ret = ath10k_qmi_init(ar, msa_size); 1738 if (ret) { 1739 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret); 1740 goto err_fw_deinit; 1741 } 1742 1743 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n"); 1744 1745 return 0; 1746 1747 err_fw_deinit: 1748 ath10k_fw_deinit(ar); 1749 1750 err_free_irq: 1751 ath10k_snoc_free_irq(ar); 1752 1753 err_release_resource: 1754 ath10k_snoc_release_resource(ar); 1755 1756 err_core_destroy: 1757 ath10k_core_destroy(ar); 1758 1759 return ret; 1760 } 1761 1762 static int ath10k_snoc_remove(struct platform_device *pdev) 1763 { 1764 struct ath10k *ar = platform_get_drvdata(pdev); 1765 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); 1766 1767 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n"); 1768 1769 reinit_completion(&ar->driver_recovery); 1770 1771 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags)) 1772 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ); 1773 1774 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags); 1775 1776 ath10k_core_unregister(ar); 1777 ath10k_fw_deinit(ar); 1778 ath10k_snoc_free_irq(ar); 1779 ath10k_snoc_release_resource(ar); 1780 ath10k_qmi_deinit(ar); 1781 ath10k_core_destroy(ar); 1782 1783 return 0; 1784 } 1785 1786 static void ath10k_snoc_shutdown(struct platform_device *pdev) 1787 { 1788 struct ath10k *ar = platform_get_drvdata(pdev); 1789 1790 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n"); 1791 ath10k_snoc_remove(pdev); 1792 } 1793 1794 static struct platform_driver ath10k_snoc_driver = { 1795 .probe = ath10k_snoc_probe, 1796 .remove = ath10k_snoc_remove, 1797 .shutdown = ath10k_snoc_shutdown, 1798 .driver = { 1799 .name = "ath10k_snoc", 1800 .of_match_table = ath10k_snoc_dt_match, 1801 }, 1802 }; 1803 module_platform_driver(ath10k_snoc_driver); 1804 1805 MODULE_AUTHOR("Qualcomm"); 1806 MODULE_LICENSE("Dual BSD/GPL"); 1807 MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices"); 1808