1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2004-2011 Atheros Communications Inc. 4 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc. 5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com> 6 */ 7 8 #include <linux/module.h> 9 #include <linux/mmc/card.h> 10 #include <linux/mmc/mmc.h> 11 #include <linux/mmc/host.h> 12 #include <linux/mmc/sdio_func.h> 13 #include <linux/mmc/sdio_ids.h> 14 #include <linux/mmc/sdio.h> 15 #include <linux/mmc/sd.h> 16 #include <linux/bitfield.h> 17 #include "core.h" 18 #include "bmi.h" 19 #include "debug.h" 20 #include "hif.h" 21 #include "htc.h" 22 #include "mac.h" 23 #include "targaddrs.h" 24 #include "trace.h" 25 #include "sdio.h" 26 27 #define ATH10K_SDIO_VSG_BUF_SIZE (64 * 1024) 28 29 /* inlined helper functions */ 30 31 static inline int ath10k_sdio_calc_txrx_padded_len(struct ath10k_sdio *ar_sdio, 32 size_t len) 33 { 34 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask); 35 } 36 37 static inline enum ath10k_htc_ep_id pipe_id_to_eid(u8 pipe_id) 38 { 39 return (enum ath10k_htc_ep_id)pipe_id; 40 } 41 42 static inline void ath10k_sdio_mbox_free_rx_pkt(struct ath10k_sdio_rx_data *pkt) 43 { 44 dev_kfree_skb(pkt->skb); 45 pkt->skb = NULL; 46 pkt->alloc_len = 0; 47 pkt->act_len = 0; 48 pkt->trailer_only = false; 49 } 50 51 static inline int ath10k_sdio_mbox_alloc_rx_pkt(struct ath10k_sdio_rx_data *pkt, 52 size_t act_len, size_t full_len, 53 bool part_of_bundle, 54 bool last_in_bundle) 55 { 56 pkt->skb = dev_alloc_skb(full_len); 57 if (!pkt->skb) 58 return -ENOMEM; 59 60 pkt->act_len = act_len; 61 pkt->alloc_len = full_len; 62 pkt->part_of_bundle = part_of_bundle; 63 pkt->last_in_bundle = last_in_bundle; 64 pkt->trailer_only = false; 65 66 return 0; 67 } 68 69 static inline bool is_trailer_only_msg(struct ath10k_sdio_rx_data *pkt) 70 { 71 bool trailer_only = false; 72 struct ath10k_htc_hdr *htc_hdr = 73 (struct ath10k_htc_hdr *)pkt->skb->data; 74 u16 len = __le16_to_cpu(htc_hdr->len); 75 76 if (len == htc_hdr->trailer_len) 77 trailer_only = true; 78 79 return trailer_only; 80 } 81 82 /* sdio/mmc functions */ 83 84 static inline void ath10k_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw, 85 unsigned int address, 86 unsigned char val) 87 { 88 *arg = FIELD_PREP(BIT(31), write) | 89 FIELD_PREP(BIT(27), raw) | 90 FIELD_PREP(BIT(26), 1) | 91 FIELD_PREP(GENMASK(25, 9), address) | 92 FIELD_PREP(BIT(8), 1) | 93 FIELD_PREP(GENMASK(7, 0), val); 94 } 95 96 static int ath10k_sdio_func0_cmd52_wr_byte(struct mmc_card *card, 97 unsigned int address, 98 unsigned char byte) 99 { 100 struct mmc_command io_cmd; 101 102 memset(&io_cmd, 0, sizeof(io_cmd)); 103 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte); 104 io_cmd.opcode = SD_IO_RW_DIRECT; 105 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 106 107 return mmc_wait_for_cmd(card->host, &io_cmd, 0); 108 } 109 110 static int ath10k_sdio_func0_cmd52_rd_byte(struct mmc_card *card, 111 unsigned int address, 112 unsigned char *byte) 113 { 114 struct mmc_command io_cmd; 115 int ret; 116 117 memset(&io_cmd, 0, sizeof(io_cmd)); 118 ath10k_sdio_set_cmd52_arg(&io_cmd.arg, 0, 0, address, 0); 119 io_cmd.opcode = SD_IO_RW_DIRECT; 120 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC; 121 122 ret = mmc_wait_for_cmd(card->host, &io_cmd, 0); 123 if (!ret) 124 *byte = io_cmd.resp[0]; 125 126 return ret; 127 } 128 129 static int ath10k_sdio_config(struct ath10k *ar) 130 { 131 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 132 struct sdio_func *func = ar_sdio->func; 133 unsigned char byte, asyncintdelay = 2; 134 int ret; 135 136 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio configuration\n"); 137 138 sdio_claim_host(func); 139 140 byte = 0; 141 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card, 142 SDIO_CCCR_DRIVE_STRENGTH, 143 &byte); 144 145 byte &= ~ATH10K_SDIO_DRIVE_DTSX_MASK; 146 byte |= FIELD_PREP(ATH10K_SDIO_DRIVE_DTSX_MASK, 147 ATH10K_SDIO_DRIVE_DTSX_TYPE_D); 148 149 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card, 150 SDIO_CCCR_DRIVE_STRENGTH, 151 byte); 152 153 byte = 0; 154 ret = ath10k_sdio_func0_cmd52_rd_byte( 155 func->card, 156 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR, 157 &byte); 158 159 byte |= (CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A | 160 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C | 161 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D); 162 163 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card, 164 CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR, 165 byte); 166 if (ret) { 167 ath10k_warn(ar, "failed to enable driver strength: %d\n", ret); 168 goto out; 169 } 170 171 byte = 0; 172 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card, 173 CCCR_SDIO_IRQ_MODE_REG_SDIO3, 174 &byte); 175 176 byte |= SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3; 177 178 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card, 179 CCCR_SDIO_IRQ_MODE_REG_SDIO3, 180 byte); 181 if (ret) { 182 ath10k_warn(ar, "failed to enable 4-bit async irq mode: %d\n", 183 ret); 184 goto out; 185 } 186 187 byte = 0; 188 ret = ath10k_sdio_func0_cmd52_rd_byte(func->card, 189 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS, 190 &byte); 191 192 byte &= ~CCCR_SDIO_ASYNC_INT_DELAY_MASK; 193 byte |= FIELD_PREP(CCCR_SDIO_ASYNC_INT_DELAY_MASK, asyncintdelay); 194 195 ret = ath10k_sdio_func0_cmd52_wr_byte(func->card, 196 CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS, 197 byte); 198 199 /* give us some time to enable, in ms */ 200 func->enable_timeout = 100; 201 202 ret = sdio_set_block_size(func, ar_sdio->mbox_info.block_size); 203 if (ret) { 204 ath10k_warn(ar, "failed to set sdio block size to %d: %d\n", 205 ar_sdio->mbox_info.block_size, ret); 206 goto out; 207 } 208 209 out: 210 sdio_release_host(func); 211 return ret; 212 } 213 214 static int ath10k_sdio_write32(struct ath10k *ar, u32 addr, u32 val) 215 { 216 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 217 struct sdio_func *func = ar_sdio->func; 218 int ret; 219 220 sdio_claim_host(func); 221 222 sdio_writel(func, val, addr, &ret); 223 if (ret) { 224 ath10k_warn(ar, "failed to write 0x%x to address 0x%x: %d\n", 225 val, addr, ret); 226 goto out; 227 } 228 229 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write32 addr 0x%x val 0x%x\n", 230 addr, val); 231 232 out: 233 sdio_release_host(func); 234 235 return ret; 236 } 237 238 static int ath10k_sdio_writesb32(struct ath10k *ar, u32 addr, u32 val) 239 { 240 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 241 struct sdio_func *func = ar_sdio->func; 242 __le32 *buf; 243 int ret; 244 245 buf = kzalloc(sizeof(*buf), GFP_KERNEL); 246 if (!buf) 247 return -ENOMEM; 248 249 *buf = cpu_to_le32(val); 250 251 sdio_claim_host(func); 252 253 ret = sdio_writesb(func, addr, buf, sizeof(*buf)); 254 if (ret) { 255 ath10k_warn(ar, "failed to write value 0x%x to fixed sb address 0x%x: %d\n", 256 val, addr, ret); 257 goto out; 258 } 259 260 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio writesb32 addr 0x%x val 0x%x\n", 261 addr, val); 262 263 out: 264 sdio_release_host(func); 265 266 kfree(buf); 267 268 return ret; 269 } 270 271 static int ath10k_sdio_read32(struct ath10k *ar, u32 addr, u32 *val) 272 { 273 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 274 struct sdio_func *func = ar_sdio->func; 275 int ret; 276 277 sdio_claim_host(func); 278 *val = sdio_readl(func, addr, &ret); 279 if (ret) { 280 ath10k_warn(ar, "failed to read from address 0x%x: %d\n", 281 addr, ret); 282 goto out; 283 } 284 285 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read32 addr 0x%x val 0x%x\n", 286 addr, *val); 287 288 out: 289 sdio_release_host(func); 290 291 return ret; 292 } 293 294 static int ath10k_sdio_read(struct ath10k *ar, u32 addr, void *buf, size_t len) 295 { 296 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 297 struct sdio_func *func = ar_sdio->func; 298 int ret; 299 300 sdio_claim_host(func); 301 302 ret = sdio_memcpy_fromio(func, buf, addr, len); 303 if (ret) { 304 ath10k_warn(ar, "failed to read from address 0x%x: %d\n", 305 addr, ret); 306 goto out; 307 } 308 309 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read addr 0x%x buf 0x%p len %zu\n", 310 addr, buf, len); 311 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio read ", buf, len); 312 313 out: 314 sdio_release_host(func); 315 316 return ret; 317 } 318 319 static int ath10k_sdio_write(struct ath10k *ar, u32 addr, const void *buf, size_t len) 320 { 321 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 322 struct sdio_func *func = ar_sdio->func; 323 int ret; 324 325 sdio_claim_host(func); 326 327 /* For some reason toio() doesn't have const for the buffer, need 328 * an ugly hack to workaround that. 329 */ 330 ret = sdio_memcpy_toio(func, addr, (void *)buf, len); 331 if (ret) { 332 ath10k_warn(ar, "failed to write to address 0x%x: %d\n", 333 addr, ret); 334 goto out; 335 } 336 337 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio write addr 0x%x buf 0x%p len %zu\n", 338 addr, buf, len); 339 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio write ", buf, len); 340 341 out: 342 sdio_release_host(func); 343 344 return ret; 345 } 346 347 static int ath10k_sdio_readsb(struct ath10k *ar, u32 addr, void *buf, size_t len) 348 { 349 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 350 struct sdio_func *func = ar_sdio->func; 351 int ret; 352 353 sdio_claim_host(func); 354 355 len = round_down(len, ar_sdio->mbox_info.block_size); 356 357 ret = sdio_readsb(func, buf, addr, len); 358 if (ret) { 359 ath10k_warn(ar, "failed to read from fixed (sb) address 0x%x: %d\n", 360 addr, ret); 361 goto out; 362 } 363 364 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio readsb addr 0x%x buf 0x%p len %zu\n", 365 addr, buf, len); 366 ath10k_dbg_dump(ar, ATH10K_DBG_SDIO_DUMP, NULL, "sdio readsb ", buf, len); 367 368 out: 369 sdio_release_host(func); 370 371 return ret; 372 } 373 374 /* HIF mbox functions */ 375 376 static int ath10k_sdio_mbox_rx_process_packet(struct ath10k *ar, 377 struct ath10k_sdio_rx_data *pkt, 378 u32 *lookaheads, 379 int *n_lookaheads) 380 { 381 struct ath10k_htc *htc = &ar->htc; 382 struct sk_buff *skb = pkt->skb; 383 struct ath10k_htc_hdr *htc_hdr = (struct ath10k_htc_hdr *)skb->data; 384 bool trailer_present = htc_hdr->flags & ATH10K_HTC_FLAG_TRAILER_PRESENT; 385 enum ath10k_htc_ep_id eid; 386 u8 *trailer; 387 int ret; 388 389 if (trailer_present) { 390 trailer = skb->data + skb->len - htc_hdr->trailer_len; 391 392 eid = pipe_id_to_eid(htc_hdr->eid); 393 394 ret = ath10k_htc_process_trailer(htc, 395 trailer, 396 htc_hdr->trailer_len, 397 eid, 398 lookaheads, 399 n_lookaheads); 400 if (ret) 401 return ret; 402 403 if (is_trailer_only_msg(pkt)) 404 pkt->trailer_only = true; 405 406 skb_trim(skb, skb->len - htc_hdr->trailer_len); 407 } 408 409 skb_pull(skb, sizeof(*htc_hdr)); 410 411 return 0; 412 } 413 414 static int ath10k_sdio_mbox_rx_process_packets(struct ath10k *ar, 415 u32 lookaheads[], 416 int *n_lookahead) 417 { 418 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 419 struct ath10k_htc *htc = &ar->htc; 420 struct ath10k_sdio_rx_data *pkt; 421 struct ath10k_htc_ep *ep; 422 struct ath10k_skb_rxcb *cb; 423 enum ath10k_htc_ep_id id; 424 int ret, i, *n_lookahead_local; 425 u32 *lookaheads_local; 426 int lookahead_idx = 0; 427 428 for (i = 0; i < ar_sdio->n_rx_pkts; i++) { 429 lookaheads_local = lookaheads; 430 n_lookahead_local = n_lookahead; 431 432 id = ((struct ath10k_htc_hdr *) 433 &lookaheads[lookahead_idx++])->eid; 434 435 if (id >= ATH10K_HTC_EP_COUNT) { 436 ath10k_warn(ar, "invalid endpoint in look-ahead: %d\n", 437 id); 438 ret = -ENOMEM; 439 goto out; 440 } 441 442 ep = &htc->endpoint[id]; 443 444 if (ep->service_id == 0) { 445 ath10k_warn(ar, "ep %d is not connected\n", id); 446 ret = -ENOMEM; 447 goto out; 448 } 449 450 pkt = &ar_sdio->rx_pkts[i]; 451 452 if (pkt->part_of_bundle && !pkt->last_in_bundle) { 453 /* Only read lookahead's from RX trailers 454 * for the last packet in a bundle. 455 */ 456 lookahead_idx--; 457 lookaheads_local = NULL; 458 n_lookahead_local = NULL; 459 } 460 461 ret = ath10k_sdio_mbox_rx_process_packet(ar, 462 pkt, 463 lookaheads_local, 464 n_lookahead_local); 465 if (ret) 466 goto out; 467 468 if (!pkt->trailer_only) { 469 cb = ATH10K_SKB_RXCB(pkt->skb); 470 cb->eid = id; 471 472 skb_queue_tail(&ar_sdio->rx_head, pkt->skb); 473 queue_work(ar->workqueue_aux, 474 &ar_sdio->async_work_rx); 475 } else { 476 kfree_skb(pkt->skb); 477 } 478 479 /* The RX complete handler now owns the skb...*/ 480 pkt->skb = NULL; 481 pkt->alloc_len = 0; 482 } 483 484 ret = 0; 485 486 out: 487 /* Free all packets that was not passed on to the RX completion 488 * handler... 489 */ 490 for (; i < ar_sdio->n_rx_pkts; i++) 491 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]); 492 493 return ret; 494 } 495 496 static int ath10k_sdio_mbox_alloc_bundle(struct ath10k *ar, 497 struct ath10k_sdio_rx_data *rx_pkts, 498 struct ath10k_htc_hdr *htc_hdr, 499 size_t full_len, size_t act_len, 500 size_t *bndl_cnt) 501 { 502 int ret, i; 503 u8 max_msgs = ar->htc.max_msgs_per_htc_bundle; 504 505 *bndl_cnt = ath10k_htc_get_bundle_count(max_msgs, htc_hdr->flags); 506 507 if (*bndl_cnt > max_msgs) { 508 ath10k_warn(ar, 509 "HTC bundle length %u exceeds maximum %u\n", 510 le16_to_cpu(htc_hdr->len), 511 max_msgs); 512 return -ENOMEM; 513 } 514 515 /* Allocate bndl_cnt extra skb's for the bundle. 516 * The package containing the 517 * ATH10K_HTC_FLAG_BUNDLE_MASK flag is not included 518 * in bndl_cnt. The skb for that packet will be 519 * allocated separately. 520 */ 521 for (i = 0; i < *bndl_cnt; i++) { 522 ret = ath10k_sdio_mbox_alloc_rx_pkt(&rx_pkts[i], 523 act_len, 524 full_len, 525 true, 526 false); 527 if (ret) 528 return ret; 529 } 530 531 return 0; 532 } 533 534 static int ath10k_sdio_mbox_rx_alloc(struct ath10k *ar, 535 u32 lookaheads[], int n_lookaheads) 536 { 537 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 538 struct ath10k_htc_hdr *htc_hdr; 539 size_t full_len, act_len; 540 bool last_in_bundle; 541 int ret, i; 542 int pkt_cnt = 0; 543 544 if (n_lookaheads > ATH10K_SDIO_MAX_RX_MSGS) { 545 ath10k_warn(ar, "the total number of pkts to be fetched (%u) exceeds maximum %u\n", 546 n_lookaheads, ATH10K_SDIO_MAX_RX_MSGS); 547 ret = -ENOMEM; 548 goto err; 549 } 550 551 for (i = 0; i < n_lookaheads; i++) { 552 htc_hdr = (struct ath10k_htc_hdr *)&lookaheads[i]; 553 last_in_bundle = false; 554 555 if (le16_to_cpu(htc_hdr->len) > ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH) { 556 ath10k_warn(ar, "payload length %d exceeds max htc length: %zu\n", 557 le16_to_cpu(htc_hdr->len), 558 ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH); 559 ret = -ENOMEM; 560 561 queue_work(ar->workqueue, &ar->restart_work); 562 ath10k_warn(ar, "exceeds length, start recovery\n"); 563 564 goto err; 565 } 566 567 act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr); 568 full_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, act_len); 569 570 if (full_len > ATH10K_SDIO_MAX_BUFFER_SIZE) { 571 ath10k_warn(ar, "rx buffer requested with invalid htc_hdr length (%d, 0x%x): %d\n", 572 htc_hdr->eid, htc_hdr->flags, 573 le16_to_cpu(htc_hdr->len)); 574 ret = -EINVAL; 575 goto err; 576 } 577 578 if (ath10k_htc_get_bundle_count( 579 ar->htc.max_msgs_per_htc_bundle, htc_hdr->flags)) { 580 /* HTC header indicates that every packet to follow 581 * has the same padded length so that it can be 582 * optimally fetched as a full bundle. 583 */ 584 size_t bndl_cnt; 585 586 ret = ath10k_sdio_mbox_alloc_bundle(ar, 587 &ar_sdio->rx_pkts[pkt_cnt], 588 htc_hdr, 589 full_len, 590 act_len, 591 &bndl_cnt); 592 593 if (ret) { 594 ath10k_warn(ar, "failed to allocate a bundle: %d\n", 595 ret); 596 goto err; 597 } 598 599 pkt_cnt += bndl_cnt; 600 601 /* next buffer will be the last in the bundle */ 602 last_in_bundle = true; 603 } 604 605 /* Allocate skb for packet. If the packet had the 606 * ATH10K_HTC_FLAG_BUNDLE_MASK flag set, all bundled 607 * packet skb's have been allocated in the previous step. 608 */ 609 if (htc_hdr->flags & ATH10K_HTC_FLAGS_RECV_1MORE_BLOCK) 610 full_len += ATH10K_HIF_MBOX_BLOCK_SIZE; 611 612 ret = ath10k_sdio_mbox_alloc_rx_pkt(&ar_sdio->rx_pkts[pkt_cnt], 613 act_len, 614 full_len, 615 last_in_bundle, 616 last_in_bundle); 617 if (ret) { 618 ath10k_warn(ar, "alloc_rx_pkt error %d\n", ret); 619 goto err; 620 } 621 622 pkt_cnt++; 623 } 624 625 ar_sdio->n_rx_pkts = pkt_cnt; 626 627 return 0; 628 629 err: 630 for (i = 0; i < ATH10K_SDIO_MAX_RX_MSGS; i++) { 631 if (!ar_sdio->rx_pkts[i].alloc_len) 632 break; 633 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]); 634 } 635 636 return ret; 637 } 638 639 static int ath10k_sdio_mbox_rx_fetch(struct ath10k *ar) 640 { 641 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 642 struct ath10k_sdio_rx_data *pkt = &ar_sdio->rx_pkts[0]; 643 struct sk_buff *skb = pkt->skb; 644 struct ath10k_htc_hdr *htc_hdr; 645 int ret; 646 647 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr, 648 skb->data, pkt->alloc_len); 649 if (ret) 650 goto err; 651 652 htc_hdr = (struct ath10k_htc_hdr *)skb->data; 653 pkt->act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr); 654 655 if (pkt->act_len > pkt->alloc_len) { 656 ret = -EINVAL; 657 goto err; 658 } 659 660 skb_put(skb, pkt->act_len); 661 return 0; 662 663 err: 664 ar_sdio->n_rx_pkts = 0; 665 ath10k_sdio_mbox_free_rx_pkt(pkt); 666 667 return ret; 668 } 669 670 static int ath10k_sdio_mbox_rx_fetch_bundle(struct ath10k *ar) 671 { 672 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 673 struct ath10k_sdio_rx_data *pkt; 674 struct ath10k_htc_hdr *htc_hdr; 675 int ret, i; 676 u32 pkt_offset, virt_pkt_len; 677 678 virt_pkt_len = 0; 679 for (i = 0; i < ar_sdio->n_rx_pkts; i++) 680 virt_pkt_len += ar_sdio->rx_pkts[i].alloc_len; 681 682 if (virt_pkt_len > ATH10K_SDIO_VSG_BUF_SIZE) { 683 ath10k_warn(ar, "sdio vsg buffer size limit: %d\n", virt_pkt_len); 684 ret = -E2BIG; 685 goto err; 686 } 687 688 ret = ath10k_sdio_readsb(ar, ar_sdio->mbox_info.htc_addr, 689 ar_sdio->vsg_buffer, virt_pkt_len); 690 if (ret) { 691 ath10k_warn(ar, "failed to read bundle packets: %d", ret); 692 goto err; 693 } 694 695 pkt_offset = 0; 696 for (i = 0; i < ar_sdio->n_rx_pkts; i++) { 697 pkt = &ar_sdio->rx_pkts[i]; 698 htc_hdr = (struct ath10k_htc_hdr *)(ar_sdio->vsg_buffer + pkt_offset); 699 pkt->act_len = le16_to_cpu(htc_hdr->len) + sizeof(*htc_hdr); 700 701 if (pkt->act_len > pkt->alloc_len) { 702 ret = -EINVAL; 703 goto err; 704 } 705 706 skb_put_data(pkt->skb, htc_hdr, pkt->act_len); 707 pkt_offset += pkt->alloc_len; 708 } 709 710 return 0; 711 712 err: 713 /* Free all packets that was not successfully fetched. */ 714 for (i = 0; i < ar_sdio->n_rx_pkts; i++) 715 ath10k_sdio_mbox_free_rx_pkt(&ar_sdio->rx_pkts[i]); 716 717 ar_sdio->n_rx_pkts = 0; 718 719 return ret; 720 } 721 722 /* This is the timeout for mailbox processing done in the sdio irq 723 * handler. The timeout is deliberately set quite high since SDIO dump logs 724 * over serial port can/will add a substantial overhead to the processing 725 * (if enabled). 726 */ 727 #define SDIO_MBOX_PROCESSING_TIMEOUT_HZ (20 * HZ) 728 729 static int ath10k_sdio_mbox_rxmsg_pending_handler(struct ath10k *ar, 730 u32 msg_lookahead, bool *done) 731 { 732 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 733 u32 lookaheads[ATH10K_SDIO_MAX_RX_MSGS]; 734 int n_lookaheads = 1; 735 unsigned long timeout; 736 int ret; 737 738 *done = true; 739 740 /* Copy the lookahead obtained from the HTC register table into our 741 * temp array as a start value. 742 */ 743 lookaheads[0] = msg_lookahead; 744 745 timeout = jiffies + SDIO_MBOX_PROCESSING_TIMEOUT_HZ; 746 do { 747 /* Try to allocate as many HTC RX packets indicated by 748 * n_lookaheads. 749 */ 750 ret = ath10k_sdio_mbox_rx_alloc(ar, lookaheads, 751 n_lookaheads); 752 if (ret) 753 break; 754 755 if (ar_sdio->n_rx_pkts >= 2) 756 /* A recv bundle was detected, force IRQ status 757 * re-check again. 758 */ 759 *done = false; 760 761 if (ar_sdio->n_rx_pkts > 1) 762 ret = ath10k_sdio_mbox_rx_fetch_bundle(ar); 763 else 764 ret = ath10k_sdio_mbox_rx_fetch(ar); 765 766 /* Process fetched packets. This will potentially update 767 * n_lookaheads depending on if the packets contain lookahead 768 * reports. 769 */ 770 n_lookaheads = 0; 771 ret = ath10k_sdio_mbox_rx_process_packets(ar, 772 lookaheads, 773 &n_lookaheads); 774 775 if (!n_lookaheads || ret) 776 break; 777 778 /* For SYNCH processing, if we get here, we are running 779 * through the loop again due to updated lookaheads. Set 780 * flag that we should re-check IRQ status registers again 781 * before leaving IRQ processing, this can net better 782 * performance in high throughput situations. 783 */ 784 *done = false; 785 } while (time_before(jiffies, timeout)); 786 787 if (ret && (ret != -ECANCELED)) 788 ath10k_warn(ar, "failed to get pending recv messages: %d\n", 789 ret); 790 791 return ret; 792 } 793 794 static int ath10k_sdio_mbox_proc_dbg_intr(struct ath10k *ar) 795 { 796 u32 val; 797 int ret; 798 799 /* TODO: Add firmware crash handling */ 800 ath10k_warn(ar, "firmware crashed\n"); 801 802 /* read counter to clear the interrupt, the debug error interrupt is 803 * counter 0. 804 */ 805 ret = ath10k_sdio_read32(ar, MBOX_COUNT_DEC_ADDRESS, &val); 806 if (ret) 807 ath10k_warn(ar, "failed to clear debug interrupt: %d\n", ret); 808 809 return ret; 810 } 811 812 static int ath10k_sdio_mbox_proc_counter_intr(struct ath10k *ar) 813 { 814 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 815 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 816 u8 counter_int_status; 817 int ret; 818 819 mutex_lock(&irq_data->mtx); 820 counter_int_status = irq_data->irq_proc_reg->counter_int_status & 821 irq_data->irq_en_reg->cntr_int_status_en; 822 823 /* NOTE: other modules like GMBOX may use the counter interrupt for 824 * credit flow control on other counters, we only need to check for 825 * the debug assertion counter interrupt. 826 */ 827 if (counter_int_status & ATH10K_SDIO_TARGET_DEBUG_INTR_MASK) 828 ret = ath10k_sdio_mbox_proc_dbg_intr(ar); 829 else 830 ret = 0; 831 832 mutex_unlock(&irq_data->mtx); 833 834 return ret; 835 } 836 837 static int ath10k_sdio_mbox_proc_err_intr(struct ath10k *ar) 838 { 839 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 840 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 841 u8 error_int_status; 842 int ret; 843 844 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio error interrupt\n"); 845 846 error_int_status = irq_data->irq_proc_reg->error_int_status & 0x0F; 847 if (!error_int_status) { 848 ath10k_warn(ar, "invalid error interrupt status: 0x%x\n", 849 error_int_status); 850 return -EIO; 851 } 852 853 ath10k_dbg(ar, ATH10K_DBG_SDIO, 854 "sdio error_int_status 0x%x\n", error_int_status); 855 856 if (FIELD_GET(MBOX_ERROR_INT_STATUS_WAKEUP_MASK, 857 error_int_status)) 858 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio interrupt error wakeup\n"); 859 860 if (FIELD_GET(MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, 861 error_int_status)) 862 ath10k_warn(ar, "rx underflow interrupt error\n"); 863 864 if (FIELD_GET(MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK, 865 error_int_status)) 866 ath10k_warn(ar, "tx overflow interrupt error\n"); 867 868 /* Clear the interrupt */ 869 irq_data->irq_proc_reg->error_int_status &= ~error_int_status; 870 871 /* set W1C value to clear the interrupt, this hits the register first */ 872 ret = ath10k_sdio_writesb32(ar, MBOX_ERROR_INT_STATUS_ADDRESS, 873 error_int_status); 874 if (ret) { 875 ath10k_warn(ar, "unable to write to error int status address: %d\n", 876 ret); 877 return ret; 878 } 879 880 return 0; 881 } 882 883 static int ath10k_sdio_mbox_proc_cpu_intr(struct ath10k *ar) 884 { 885 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 886 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 887 u8 cpu_int_status; 888 int ret; 889 890 mutex_lock(&irq_data->mtx); 891 cpu_int_status = irq_data->irq_proc_reg->cpu_int_status & 892 irq_data->irq_en_reg->cpu_int_status_en; 893 if (!cpu_int_status) { 894 ath10k_warn(ar, "CPU interrupt status is zero\n"); 895 ret = -EIO; 896 goto out; 897 } 898 899 /* Clear the interrupt */ 900 irq_data->irq_proc_reg->cpu_int_status &= ~cpu_int_status; 901 902 /* Set up the register transfer buffer to hit the register 4 times, 903 * this is done to make the access 4-byte aligned to mitigate issues 904 * with host bus interconnects that restrict bus transfer lengths to 905 * be a multiple of 4-bytes. 906 * 907 * Set W1C value to clear the interrupt, this hits the register first. 908 */ 909 ret = ath10k_sdio_writesb32(ar, MBOX_CPU_INT_STATUS_ADDRESS, 910 cpu_int_status); 911 if (ret) { 912 ath10k_warn(ar, "unable to write to cpu interrupt status address: %d\n", 913 ret); 914 goto out; 915 } 916 917 out: 918 mutex_unlock(&irq_data->mtx); 919 if (cpu_int_status & MBOX_CPU_STATUS_ENABLE_ASSERT_MASK) { 920 ath10k_err(ar, "firmware crashed!\n"); 921 queue_work(ar->workqueue, &ar->restart_work); 922 } 923 return ret; 924 } 925 926 static int ath10k_sdio_mbox_read_int_status(struct ath10k *ar, 927 u8 *host_int_status, 928 u32 *lookahead) 929 { 930 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 931 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 932 struct ath10k_sdio_irq_proc_regs *irq_proc_reg = irq_data->irq_proc_reg; 933 struct ath10k_sdio_irq_enable_regs *irq_en_reg = irq_data->irq_en_reg; 934 u8 htc_mbox = FIELD_PREP(ATH10K_HTC_MAILBOX_MASK, 1); 935 int ret; 936 937 mutex_lock(&irq_data->mtx); 938 939 *lookahead = 0; 940 *host_int_status = 0; 941 942 /* int_status_en is supposed to be non zero, otherwise interrupts 943 * shouldn't be enabled. There is however a short time frame during 944 * initialization between the irq register and int_status_en init 945 * where this can happen. 946 * We silently ignore this condition. 947 */ 948 if (!irq_en_reg->int_status_en) { 949 ret = 0; 950 goto out; 951 } 952 953 /* Read the first sizeof(struct ath10k_irq_proc_registers) 954 * bytes of the HTC register table. This 955 * will yield us the value of different int status 956 * registers and the lookahead registers. 957 */ 958 ret = ath10k_sdio_read(ar, MBOX_HOST_INT_STATUS_ADDRESS, 959 irq_proc_reg, sizeof(*irq_proc_reg)); 960 if (ret) { 961 queue_work(ar->workqueue, &ar->restart_work); 962 ath10k_warn(ar, "read int status fail, start recovery\n"); 963 goto out; 964 } 965 966 /* Update only those registers that are enabled */ 967 *host_int_status = irq_proc_reg->host_int_status & 968 irq_en_reg->int_status_en; 969 970 /* Look at mbox status */ 971 if (!(*host_int_status & htc_mbox)) { 972 *lookahead = 0; 973 ret = 0; 974 goto out; 975 } 976 977 /* Mask out pending mbox value, we use look ahead as 978 * the real flag for mbox processing. 979 */ 980 *host_int_status &= ~htc_mbox; 981 if (irq_proc_reg->rx_lookahead_valid & htc_mbox) { 982 *lookahead = le32_to_cpu( 983 irq_proc_reg->rx_lookahead[ATH10K_HTC_MAILBOX]); 984 if (!*lookahead) 985 ath10k_warn(ar, "sdio mbox lookahead is zero\n"); 986 } 987 988 out: 989 mutex_unlock(&irq_data->mtx); 990 return ret; 991 } 992 993 static int ath10k_sdio_mbox_proc_pending_irqs(struct ath10k *ar, 994 bool *done) 995 { 996 u8 host_int_status; 997 u32 lookahead; 998 int ret; 999 1000 /* NOTE: HIF implementation guarantees that the context of this 1001 * call allows us to perform SYNCHRONOUS I/O, that is we can block, 1002 * sleep or call any API that can block or switch thread/task 1003 * contexts. This is a fully schedulable context. 1004 */ 1005 1006 ret = ath10k_sdio_mbox_read_int_status(ar, 1007 &host_int_status, 1008 &lookahead); 1009 if (ret) { 1010 *done = true; 1011 goto out; 1012 } 1013 1014 if (!host_int_status && !lookahead) { 1015 ret = 0; 1016 *done = true; 1017 goto out; 1018 } 1019 1020 if (lookahead) { 1021 ath10k_dbg(ar, ATH10K_DBG_SDIO, 1022 "sdio pending mailbox msg lookahead 0x%08x\n", 1023 lookahead); 1024 1025 ret = ath10k_sdio_mbox_rxmsg_pending_handler(ar, 1026 lookahead, 1027 done); 1028 if (ret) 1029 goto out; 1030 } 1031 1032 /* now, handle the rest of the interrupts */ 1033 ath10k_dbg(ar, ATH10K_DBG_SDIO, 1034 "sdio host_int_status 0x%x\n", host_int_status); 1035 1036 if (FIELD_GET(MBOX_HOST_INT_STATUS_CPU_MASK, host_int_status)) { 1037 /* CPU Interrupt */ 1038 ret = ath10k_sdio_mbox_proc_cpu_intr(ar); 1039 if (ret) 1040 goto out; 1041 } 1042 1043 if (FIELD_GET(MBOX_HOST_INT_STATUS_ERROR_MASK, host_int_status)) { 1044 /* Error Interrupt */ 1045 ret = ath10k_sdio_mbox_proc_err_intr(ar); 1046 if (ret) 1047 goto out; 1048 } 1049 1050 if (FIELD_GET(MBOX_HOST_INT_STATUS_COUNTER_MASK, host_int_status)) 1051 /* Counter Interrupt */ 1052 ret = ath10k_sdio_mbox_proc_counter_intr(ar); 1053 1054 ret = 0; 1055 1056 out: 1057 /* An optimization to bypass reading the IRQ status registers 1058 * unecessarily which can re-wake the target, if upper layers 1059 * determine that we are in a low-throughput mode, we can rely on 1060 * taking another interrupt rather than re-checking the status 1061 * registers which can re-wake the target. 1062 * 1063 * NOTE : for host interfaces that makes use of detecting pending 1064 * mbox messages at hif can not use this optimization due to 1065 * possible side effects, SPI requires the host to drain all 1066 * messages from the mailbox before exiting the ISR routine. 1067 */ 1068 1069 ath10k_dbg(ar, ATH10K_DBG_SDIO, 1070 "sdio pending irqs done %d status %d", 1071 *done, ret); 1072 1073 return ret; 1074 } 1075 1076 static void ath10k_sdio_set_mbox_info(struct ath10k *ar) 1077 { 1078 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1079 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info; 1080 u16 device = ar_sdio->func->device, dev_id_base, dev_id_chiprev; 1081 1082 mbox_info->htc_addr = ATH10K_HIF_MBOX_BASE_ADDR; 1083 mbox_info->block_size = ATH10K_HIF_MBOX_BLOCK_SIZE; 1084 mbox_info->block_mask = ATH10K_HIF_MBOX_BLOCK_SIZE - 1; 1085 mbox_info->gmbox_addr = ATH10K_HIF_GMBOX_BASE_ADDR; 1086 mbox_info->gmbox_sz = ATH10K_HIF_GMBOX_WIDTH; 1087 1088 mbox_info->ext_info[0].htc_ext_addr = ATH10K_HIF_MBOX0_EXT_BASE_ADDR; 1089 1090 dev_id_base = (device & 0x0F00); 1091 dev_id_chiprev = (device & 0x00FF); 1092 switch (dev_id_base) { 1093 case (SDIO_DEVICE_ID_ATHEROS_AR6005 & 0x0F00): 1094 if (dev_id_chiprev < 4) 1095 mbox_info->ext_info[0].htc_ext_sz = 1096 ATH10K_HIF_MBOX0_EXT_WIDTH; 1097 else 1098 /* from QCA6174 2.0(0x504), the width has been extended 1099 * to 56K 1100 */ 1101 mbox_info->ext_info[0].htc_ext_sz = 1102 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0; 1103 break; 1104 case (SDIO_DEVICE_ID_ATHEROS_QCA9377 & 0x0F00): 1105 mbox_info->ext_info[0].htc_ext_sz = 1106 ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0; 1107 break; 1108 default: 1109 mbox_info->ext_info[0].htc_ext_sz = 1110 ATH10K_HIF_MBOX0_EXT_WIDTH; 1111 } 1112 1113 mbox_info->ext_info[1].htc_ext_addr = 1114 mbox_info->ext_info[0].htc_ext_addr + 1115 mbox_info->ext_info[0].htc_ext_sz + 1116 ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE; 1117 mbox_info->ext_info[1].htc_ext_sz = ATH10K_HIF_MBOX1_EXT_WIDTH; 1118 } 1119 1120 /* BMI functions */ 1121 1122 static int ath10k_sdio_bmi_credits(struct ath10k *ar) 1123 { 1124 u32 addr, cmd_credits; 1125 unsigned long timeout; 1126 int ret; 1127 1128 /* Read the counter register to get the command credits */ 1129 addr = MBOX_COUNT_DEC_ADDRESS + ATH10K_HIF_MBOX_NUM_MAX * 4; 1130 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1131 cmd_credits = 0; 1132 1133 while (time_before(jiffies, timeout) && !cmd_credits) { 1134 /* Hit the credit counter with a 4-byte access, the first byte 1135 * read will hit the counter and cause a decrement, while the 1136 * remaining 3 bytes has no effect. The rationale behind this 1137 * is to make all HIF accesses 4-byte aligned. 1138 */ 1139 ret = ath10k_sdio_read32(ar, addr, &cmd_credits); 1140 if (ret) { 1141 ath10k_warn(ar, 1142 "unable to decrement the command credit count register: %d\n", 1143 ret); 1144 return ret; 1145 } 1146 1147 /* The counter is only 8 bits. 1148 * Ignore anything in the upper 3 bytes 1149 */ 1150 cmd_credits &= 0xFF; 1151 } 1152 1153 if (!cmd_credits) { 1154 ath10k_warn(ar, "bmi communication timeout\n"); 1155 return -ETIMEDOUT; 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int ath10k_sdio_bmi_get_rx_lookahead(struct ath10k *ar) 1162 { 1163 unsigned long timeout; 1164 u32 rx_word; 1165 int ret; 1166 1167 timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1168 rx_word = 0; 1169 1170 while ((time_before(jiffies, timeout)) && !rx_word) { 1171 ret = ath10k_sdio_read32(ar, 1172 MBOX_HOST_INT_STATUS_ADDRESS, 1173 &rx_word); 1174 if (ret) { 1175 ath10k_warn(ar, "unable to read RX_LOOKAHEAD_VALID: %d\n", ret); 1176 return ret; 1177 } 1178 1179 /* all we really want is one bit */ 1180 rx_word &= 1; 1181 } 1182 1183 if (!rx_word) { 1184 ath10k_warn(ar, "bmi_recv_buf FIFO empty\n"); 1185 return -EINVAL; 1186 } 1187 1188 return ret; 1189 } 1190 1191 static int ath10k_sdio_bmi_exchange_msg(struct ath10k *ar, 1192 void *req, u32 req_len, 1193 void *resp, u32 *resp_len) 1194 { 1195 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1196 u32 addr; 1197 int ret; 1198 1199 if (req) { 1200 ret = ath10k_sdio_bmi_credits(ar); 1201 if (ret) 1202 return ret; 1203 1204 addr = ar_sdio->mbox_info.htc_addr; 1205 1206 memcpy(ar_sdio->bmi_buf, req, req_len); 1207 ret = ath10k_sdio_write(ar, addr, ar_sdio->bmi_buf, req_len); 1208 if (ret) { 1209 ath10k_warn(ar, 1210 "unable to send the bmi data to the device: %d\n", 1211 ret); 1212 return ret; 1213 } 1214 } 1215 1216 if (!resp || !resp_len) 1217 /* No response expected */ 1218 return 0; 1219 1220 /* During normal bootup, small reads may be required. 1221 * Rather than issue an HIF Read and then wait as the Target 1222 * adds successive bytes to the FIFO, we wait here until 1223 * we know that response data is available. 1224 * 1225 * This allows us to cleanly timeout on an unexpected 1226 * Target failure rather than risk problems at the HIF level. 1227 * In particular, this avoids SDIO timeouts and possibly garbage 1228 * data on some host controllers. And on an interconnect 1229 * such as Compact Flash (as well as some SDIO masters) which 1230 * does not provide any indication on data timeout, it avoids 1231 * a potential hang or garbage response. 1232 * 1233 * Synchronization is more difficult for reads larger than the 1234 * size of the MBOX FIFO (128B), because the Target is unable 1235 * to push the 129th byte of data until AFTER the Host posts an 1236 * HIF Read and removes some FIFO data. So for large reads the 1237 * Host proceeds to post an HIF Read BEFORE all the data is 1238 * actually available to read. Fortunately, large BMI reads do 1239 * not occur in practice -- they're supported for debug/development. 1240 * 1241 * So Host/Target BMI synchronization is divided into these cases: 1242 * CASE 1: length < 4 1243 * Should not happen 1244 * 1245 * CASE 2: 4 <= length <= 128 1246 * Wait for first 4 bytes to be in FIFO 1247 * If CONSERVATIVE_BMI_READ is enabled, also wait for 1248 * a BMI command credit, which indicates that the ENTIRE 1249 * response is available in the the FIFO 1250 * 1251 * CASE 3: length > 128 1252 * Wait for the first 4 bytes to be in FIFO 1253 * 1254 * For most uses, a small timeout should be sufficient and we will 1255 * usually see a response quickly; but there may be some unusual 1256 * (debug) cases of BMI_EXECUTE where we want an larger timeout. 1257 * For now, we use an unbounded busy loop while waiting for 1258 * BMI_EXECUTE. 1259 * 1260 * If BMI_EXECUTE ever needs to support longer-latency execution, 1261 * especially in production, this code needs to be enhanced to sleep 1262 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently 1263 * a function of Host processor speed. 1264 */ 1265 ret = ath10k_sdio_bmi_get_rx_lookahead(ar); 1266 if (ret) 1267 return ret; 1268 1269 /* We always read from the start of the mbox address */ 1270 addr = ar_sdio->mbox_info.htc_addr; 1271 ret = ath10k_sdio_read(ar, addr, ar_sdio->bmi_buf, *resp_len); 1272 if (ret) { 1273 ath10k_warn(ar, 1274 "unable to read the bmi data from the device: %d\n", 1275 ret); 1276 return ret; 1277 } 1278 1279 memcpy(resp, ar_sdio->bmi_buf, *resp_len); 1280 1281 return 0; 1282 } 1283 1284 /* sdio async handling functions */ 1285 1286 static struct ath10k_sdio_bus_request 1287 *ath10k_sdio_alloc_busreq(struct ath10k *ar) 1288 { 1289 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1290 struct ath10k_sdio_bus_request *bus_req; 1291 1292 spin_lock_bh(&ar_sdio->lock); 1293 1294 if (list_empty(&ar_sdio->bus_req_freeq)) { 1295 bus_req = NULL; 1296 goto out; 1297 } 1298 1299 bus_req = list_first_entry(&ar_sdio->bus_req_freeq, 1300 struct ath10k_sdio_bus_request, list); 1301 list_del(&bus_req->list); 1302 1303 out: 1304 spin_unlock_bh(&ar_sdio->lock); 1305 return bus_req; 1306 } 1307 1308 static void ath10k_sdio_free_bus_req(struct ath10k *ar, 1309 struct ath10k_sdio_bus_request *bus_req) 1310 { 1311 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1312 1313 memset(bus_req, 0, sizeof(*bus_req)); 1314 1315 spin_lock_bh(&ar_sdio->lock); 1316 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq); 1317 spin_unlock_bh(&ar_sdio->lock); 1318 } 1319 1320 static void __ath10k_sdio_write_async(struct ath10k *ar, 1321 struct ath10k_sdio_bus_request *req) 1322 { 1323 struct ath10k_htc_ep *ep; 1324 struct sk_buff *skb; 1325 int ret; 1326 1327 skb = req->skb; 1328 ret = ath10k_sdio_write(ar, req->address, skb->data, skb->len); 1329 if (ret) 1330 ath10k_warn(ar, "failed to write skb to 0x%x asynchronously: %d", 1331 req->address, ret); 1332 1333 if (req->htc_msg) { 1334 ep = &ar->htc.endpoint[req->eid]; 1335 ath10k_htc_notify_tx_completion(ep, skb); 1336 } else if (req->comp) { 1337 complete(req->comp); 1338 } 1339 1340 ath10k_sdio_free_bus_req(ar, req); 1341 } 1342 1343 /* To improve throughput use workqueue to deliver packets to HTC layer, 1344 * this way SDIO bus is utilised much better. 1345 */ 1346 static void ath10k_rx_indication_async_work(struct work_struct *work) 1347 { 1348 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio, 1349 async_work_rx); 1350 struct ath10k *ar = ar_sdio->ar; 1351 struct ath10k_htc_ep *ep; 1352 struct ath10k_skb_rxcb *cb; 1353 struct sk_buff *skb; 1354 1355 while (true) { 1356 skb = skb_dequeue(&ar_sdio->rx_head); 1357 if (!skb) 1358 break; 1359 cb = ATH10K_SKB_RXCB(skb); 1360 ep = &ar->htc.endpoint[cb->eid]; 1361 ep->ep_ops.ep_rx_complete(ar, skb); 1362 } 1363 1364 if (test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) 1365 napi_schedule(&ar->napi); 1366 } 1367 1368 static int ath10k_sdio_read_rtc_state(struct ath10k_sdio *ar_sdio, unsigned char *state) 1369 { 1370 struct ath10k *ar = ar_sdio->ar; 1371 unsigned char rtc_state = 0; 1372 int ret = 0; 1373 1374 rtc_state = sdio_f0_readb(ar_sdio->func, ATH10K_CIS_RTC_STATE_ADDR, &ret); 1375 if (ret) { 1376 ath10k_warn(ar, "failed to read rtc state: %d\n", ret); 1377 return ret; 1378 } 1379 1380 *state = rtc_state & 0x3; 1381 1382 return ret; 1383 } 1384 1385 static int ath10k_sdio_set_mbox_sleep(struct ath10k *ar, bool enable_sleep) 1386 { 1387 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1388 u32 val; 1389 int retry = ATH10K_CIS_READ_RETRY, ret = 0; 1390 unsigned char rtc_state = 0; 1391 1392 sdio_claim_host(ar_sdio->func); 1393 1394 ret = ath10k_sdio_read32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, &val); 1395 if (ret) { 1396 ath10k_warn(ar, "failed to read fifo/chip control register: %d\n", 1397 ret); 1398 goto release; 1399 } 1400 1401 if (enable_sleep) { 1402 val &= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF; 1403 ar_sdio->mbox_state = SDIO_MBOX_SLEEP_STATE; 1404 } else { 1405 val |= ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON; 1406 ar_sdio->mbox_state = SDIO_MBOX_AWAKE_STATE; 1407 } 1408 1409 ret = ath10k_sdio_write32(ar, ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL, val); 1410 if (ret) { 1411 ath10k_warn(ar, "failed to write to FIFO_TIMEOUT_AND_CHIP_CONTROL: %d", 1412 ret); 1413 } 1414 1415 if (!enable_sleep) { 1416 do { 1417 udelay(ATH10K_CIS_READ_WAIT_4_RTC_CYCLE_IN_US); 1418 ret = ath10k_sdio_read_rtc_state(ar_sdio, &rtc_state); 1419 1420 if (ret) { 1421 ath10k_warn(ar, "failed to disable mbox sleep: %d", ret); 1422 break; 1423 } 1424 1425 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio read rtc state: %d\n", 1426 rtc_state); 1427 1428 if (rtc_state == ATH10K_CIS_RTC_STATE_ON) 1429 break; 1430 1431 udelay(ATH10K_CIS_XTAL_SETTLE_DURATION_IN_US); 1432 retry--; 1433 } while (retry > 0); 1434 } 1435 1436 release: 1437 sdio_release_host(ar_sdio->func); 1438 1439 return ret; 1440 } 1441 1442 static void ath10k_sdio_sleep_timer_handler(struct timer_list *t) 1443 { 1444 struct ath10k_sdio *ar_sdio = from_timer(ar_sdio, t, sleep_timer); 1445 1446 ar_sdio->mbox_state = SDIO_MBOX_REQUEST_TO_SLEEP_STATE; 1447 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work); 1448 } 1449 1450 static void ath10k_sdio_write_async_work(struct work_struct *work) 1451 { 1452 struct ath10k_sdio *ar_sdio = container_of(work, struct ath10k_sdio, 1453 wr_async_work); 1454 struct ath10k *ar = ar_sdio->ar; 1455 struct ath10k_sdio_bus_request *req, *tmp_req; 1456 struct ath10k_mbox_info *mbox_info = &ar_sdio->mbox_info; 1457 1458 spin_lock_bh(&ar_sdio->wr_async_lock); 1459 1460 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 1461 list_del(&req->list); 1462 spin_unlock_bh(&ar_sdio->wr_async_lock); 1463 1464 if (req->address >= mbox_info->htc_addr && 1465 ar_sdio->mbox_state == SDIO_MBOX_SLEEP_STATE) { 1466 ath10k_sdio_set_mbox_sleep(ar, false); 1467 mod_timer(&ar_sdio->sleep_timer, jiffies + 1468 msecs_to_jiffies(ATH10K_MIN_SLEEP_INACTIVITY_TIME_MS)); 1469 } 1470 1471 __ath10k_sdio_write_async(ar, req); 1472 spin_lock_bh(&ar_sdio->wr_async_lock); 1473 } 1474 1475 spin_unlock_bh(&ar_sdio->wr_async_lock); 1476 1477 if (ar_sdio->mbox_state == SDIO_MBOX_REQUEST_TO_SLEEP_STATE) 1478 ath10k_sdio_set_mbox_sleep(ar, true); 1479 } 1480 1481 static int ath10k_sdio_prep_async_req(struct ath10k *ar, u32 addr, 1482 struct sk_buff *skb, 1483 struct completion *comp, 1484 bool htc_msg, enum ath10k_htc_ep_id eid) 1485 { 1486 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1487 struct ath10k_sdio_bus_request *bus_req; 1488 1489 /* Allocate a bus request for the message and queue it on the 1490 * SDIO workqueue. 1491 */ 1492 bus_req = ath10k_sdio_alloc_busreq(ar); 1493 if (!bus_req) { 1494 ath10k_warn(ar, 1495 "unable to allocate bus request for async request\n"); 1496 return -ENOMEM; 1497 } 1498 1499 bus_req->skb = skb; 1500 bus_req->eid = eid; 1501 bus_req->address = addr; 1502 bus_req->htc_msg = htc_msg; 1503 bus_req->comp = comp; 1504 1505 spin_lock_bh(&ar_sdio->wr_async_lock); 1506 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq); 1507 spin_unlock_bh(&ar_sdio->wr_async_lock); 1508 1509 return 0; 1510 } 1511 1512 /* IRQ handler */ 1513 1514 static void ath10k_sdio_irq_handler(struct sdio_func *func) 1515 { 1516 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func); 1517 struct ath10k *ar = ar_sdio->ar; 1518 unsigned long timeout; 1519 bool done = false; 1520 int ret; 1521 1522 /* Release the host during interrupts so we can pick it back up when 1523 * we process commands. 1524 */ 1525 sdio_release_host(ar_sdio->func); 1526 1527 timeout = jiffies + ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ; 1528 do { 1529 ret = ath10k_sdio_mbox_proc_pending_irqs(ar, &done); 1530 if (ret) 1531 break; 1532 } while (time_before(jiffies, timeout) && !done); 1533 1534 ath10k_mac_tx_push_pending(ar); 1535 1536 sdio_claim_host(ar_sdio->func); 1537 1538 if (ret && ret != -ECANCELED) 1539 ath10k_warn(ar, "failed to process pending SDIO interrupts: %d\n", 1540 ret); 1541 } 1542 1543 /* sdio HIF functions */ 1544 1545 static int ath10k_sdio_disable_intrs(struct ath10k *ar) 1546 { 1547 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1548 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 1549 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg; 1550 int ret; 1551 1552 mutex_lock(&irq_data->mtx); 1553 1554 memset(regs, 0, sizeof(*regs)); 1555 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS, 1556 ®s->int_status_en, sizeof(*regs)); 1557 if (ret) 1558 ath10k_warn(ar, "unable to disable sdio interrupts: %d\n", ret); 1559 1560 mutex_unlock(&irq_data->mtx); 1561 1562 return ret; 1563 } 1564 1565 static int ath10k_sdio_hif_power_up(struct ath10k *ar, 1566 enum ath10k_firmware_mode fw_mode) 1567 { 1568 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1569 struct sdio_func *func = ar_sdio->func; 1570 int ret; 1571 1572 if (!ar_sdio->is_disabled) 1573 return 0; 1574 1575 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power on\n"); 1576 1577 ret = ath10k_sdio_config(ar); 1578 if (ret) { 1579 ath10k_err(ar, "failed to config sdio: %d\n", ret); 1580 return ret; 1581 } 1582 1583 sdio_claim_host(func); 1584 1585 ret = sdio_enable_func(func); 1586 if (ret) { 1587 ath10k_warn(ar, "unable to enable sdio function: %d)\n", ret); 1588 sdio_release_host(func); 1589 return ret; 1590 } 1591 1592 sdio_release_host(func); 1593 1594 /* Wait for hardware to initialise. It should take a lot less than 1595 * 20 ms but let's be conservative here. 1596 */ 1597 msleep(20); 1598 1599 ar_sdio->is_disabled = false; 1600 1601 ret = ath10k_sdio_disable_intrs(ar); 1602 if (ret) 1603 return ret; 1604 1605 return 0; 1606 } 1607 1608 static void ath10k_sdio_hif_power_down(struct ath10k *ar) 1609 { 1610 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1611 int ret; 1612 1613 if (ar_sdio->is_disabled) 1614 return; 1615 1616 ath10k_dbg(ar, ATH10K_DBG_BOOT, "sdio power off\n"); 1617 1618 del_timer_sync(&ar_sdio->sleep_timer); 1619 ath10k_sdio_set_mbox_sleep(ar, true); 1620 1621 /* Disable the card */ 1622 sdio_claim_host(ar_sdio->func); 1623 1624 ret = sdio_disable_func(ar_sdio->func); 1625 if (ret) { 1626 ath10k_warn(ar, "unable to disable sdio function: %d\n", ret); 1627 sdio_release_host(ar_sdio->func); 1628 return; 1629 } 1630 1631 ret = mmc_hw_reset(ar_sdio->func->card->host); 1632 if (ret) 1633 ath10k_warn(ar, "unable to reset sdio: %d\n", ret); 1634 1635 sdio_release_host(ar_sdio->func); 1636 1637 ar_sdio->is_disabled = true; 1638 } 1639 1640 static int ath10k_sdio_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1641 struct ath10k_hif_sg_item *items, int n_items) 1642 { 1643 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1644 enum ath10k_htc_ep_id eid; 1645 struct sk_buff *skb; 1646 int ret, i; 1647 1648 eid = pipe_id_to_eid(pipe_id); 1649 1650 for (i = 0; i < n_items; i++) { 1651 size_t padded_len; 1652 u32 address; 1653 1654 skb = items[i].transfer_context; 1655 padded_len = ath10k_sdio_calc_txrx_padded_len(ar_sdio, 1656 skb->len); 1657 skb_trim(skb, padded_len); 1658 1659 /* Write TX data to the end of the mbox address space */ 1660 address = ar_sdio->mbox_addr[eid] + ar_sdio->mbox_size[eid] - 1661 skb->len; 1662 ret = ath10k_sdio_prep_async_req(ar, address, skb, 1663 NULL, true, eid); 1664 if (ret) 1665 return ret; 1666 } 1667 1668 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work); 1669 1670 return 0; 1671 } 1672 1673 static int ath10k_sdio_enable_intrs(struct ath10k *ar) 1674 { 1675 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1676 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 1677 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg; 1678 int ret; 1679 1680 mutex_lock(&irq_data->mtx); 1681 1682 /* Enable all but CPU interrupts */ 1683 regs->int_status_en = FIELD_PREP(MBOX_INT_STATUS_ENABLE_ERROR_MASK, 1) | 1684 FIELD_PREP(MBOX_INT_STATUS_ENABLE_CPU_MASK, 1) | 1685 FIELD_PREP(MBOX_INT_STATUS_ENABLE_COUNTER_MASK, 1); 1686 1687 /* NOTE: There are some cases where HIF can do detection of 1688 * pending mbox messages which is disabled now. 1689 */ 1690 regs->int_status_en |= 1691 FIELD_PREP(MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK, 1); 1692 1693 /* Set up the CPU Interrupt Status Register, enable CPU sourced interrupt #0 1694 * #0 is used for report assertion from target 1695 */ 1696 regs->cpu_int_status_en = FIELD_PREP(MBOX_CPU_STATUS_ENABLE_ASSERT_MASK, 1); 1697 1698 /* Set up the Error Interrupt status Register */ 1699 regs->err_int_status_en = 1700 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, 1) | 1701 FIELD_PREP(MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, 1); 1702 1703 /* Enable Counter interrupt status register to get fatal errors for 1704 * debugging. 1705 */ 1706 regs->cntr_int_status_en = 1707 FIELD_PREP(MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK, 1708 ATH10K_SDIO_TARGET_DEBUG_INTR_MASK); 1709 1710 ret = ath10k_sdio_write(ar, MBOX_INT_STATUS_ENABLE_ADDRESS, 1711 ®s->int_status_en, sizeof(*regs)); 1712 if (ret) 1713 ath10k_warn(ar, 1714 "failed to update mbox interrupt status register : %d\n", 1715 ret); 1716 1717 mutex_unlock(&irq_data->mtx); 1718 return ret; 1719 } 1720 1721 /* HIF diagnostics */ 1722 1723 static int ath10k_sdio_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1724 size_t buf_len) 1725 { 1726 int ret; 1727 void *mem; 1728 1729 mem = kzalloc(buf_len, GFP_KERNEL); 1730 if (!mem) 1731 return -ENOMEM; 1732 1733 /* set window register to start read cycle */ 1734 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_READ_ADDR_ADDRESS, address); 1735 if (ret) { 1736 ath10k_warn(ar, "failed to set mbox window read address: %d", ret); 1737 goto out; 1738 } 1739 1740 /* read the data */ 1741 ret = ath10k_sdio_read(ar, MBOX_WINDOW_DATA_ADDRESS, mem, buf_len); 1742 if (ret) { 1743 ath10k_warn(ar, "failed to read from mbox window data address: %d\n", 1744 ret); 1745 goto out; 1746 } 1747 1748 memcpy(buf, mem, buf_len); 1749 1750 out: 1751 kfree(mem); 1752 1753 return ret; 1754 } 1755 1756 static int ath10k_sdio_diag_read32(struct ath10k *ar, u32 address, 1757 u32 *value) 1758 { 1759 __le32 *val; 1760 int ret; 1761 1762 val = kzalloc(sizeof(*val), GFP_KERNEL); 1763 if (!val) 1764 return -ENOMEM; 1765 1766 ret = ath10k_sdio_hif_diag_read(ar, address, val, sizeof(*val)); 1767 if (ret) 1768 goto out; 1769 1770 *value = __le32_to_cpu(*val); 1771 1772 out: 1773 kfree(val); 1774 1775 return ret; 1776 } 1777 1778 static int ath10k_sdio_hif_diag_write_mem(struct ath10k *ar, u32 address, 1779 const void *data, int nbytes) 1780 { 1781 int ret; 1782 1783 /* set write data */ 1784 ret = ath10k_sdio_write(ar, MBOX_WINDOW_DATA_ADDRESS, data, nbytes); 1785 if (ret) { 1786 ath10k_warn(ar, 1787 "failed to write 0x%p to mbox window data address: %d\n", 1788 data, ret); 1789 return ret; 1790 } 1791 1792 /* set window register, which starts the write cycle */ 1793 ret = ath10k_sdio_write32(ar, MBOX_WINDOW_WRITE_ADDR_ADDRESS, address); 1794 if (ret) { 1795 ath10k_warn(ar, "failed to set mbox window write address: %d", ret); 1796 return ret; 1797 } 1798 1799 return 0; 1800 } 1801 1802 static int ath10k_sdio_hif_start_post(struct ath10k *ar) 1803 { 1804 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1805 u32 addr, val; 1806 int ret = 0; 1807 1808 addr = host_interest_item_address(HI_ITEM(hi_acs_flags)); 1809 1810 ret = ath10k_sdio_diag_read32(ar, addr, &val); 1811 if (ret) { 1812 ath10k_warn(ar, "unable to read hi_acs_flags : %d\n", ret); 1813 return ret; 1814 } 1815 1816 if (val & HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK) { 1817 ath10k_dbg(ar, ATH10K_DBG_SDIO, 1818 "sdio mailbox swap service enabled\n"); 1819 ar_sdio->swap_mbox = true; 1820 } else { 1821 ath10k_dbg(ar, ATH10K_DBG_SDIO, 1822 "sdio mailbox swap service disabled\n"); 1823 ar_sdio->swap_mbox = false; 1824 } 1825 1826 ath10k_sdio_set_mbox_sleep(ar, true); 1827 1828 return 0; 1829 } 1830 1831 static int ath10k_sdio_get_htt_tx_complete(struct ath10k *ar) 1832 { 1833 u32 addr, val; 1834 int ret; 1835 1836 addr = host_interest_item_address(HI_ITEM(hi_acs_flags)); 1837 1838 ret = ath10k_sdio_diag_read32(ar, addr, &val); 1839 if (ret) { 1840 ath10k_warn(ar, 1841 "unable to read hi_acs_flags for htt tx comple : %d\n", ret); 1842 return ret; 1843 } 1844 1845 ret = (val & HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK); 1846 1847 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio reduce tx complete fw%sack\n", 1848 ret ? " " : " not "); 1849 1850 return ret; 1851 } 1852 1853 /* HIF start/stop */ 1854 1855 static int ath10k_sdio_hif_start(struct ath10k *ar) 1856 { 1857 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1858 int ret; 1859 1860 napi_enable(&ar->napi); 1861 1862 /* Sleep 20 ms before HIF interrupts are disabled. 1863 * This will give target plenty of time to process the BMI done 1864 * request before interrupts are disabled. 1865 */ 1866 msleep(20); 1867 ret = ath10k_sdio_disable_intrs(ar); 1868 if (ret) 1869 return ret; 1870 1871 /* eid 0 always uses the lower part of the extended mailbox address 1872 * space (ext_info[0].htc_ext_addr). 1873 */ 1874 ar_sdio->mbox_addr[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_addr; 1875 ar_sdio->mbox_size[0] = ar_sdio->mbox_info.ext_info[0].htc_ext_sz; 1876 1877 sdio_claim_host(ar_sdio->func); 1878 1879 /* Register the isr */ 1880 ret = sdio_claim_irq(ar_sdio->func, ath10k_sdio_irq_handler); 1881 if (ret) { 1882 ath10k_warn(ar, "failed to claim sdio interrupt: %d\n", ret); 1883 sdio_release_host(ar_sdio->func); 1884 return ret; 1885 } 1886 1887 sdio_release_host(ar_sdio->func); 1888 1889 ret = ath10k_sdio_enable_intrs(ar); 1890 if (ret) 1891 ath10k_warn(ar, "failed to enable sdio interrupts: %d\n", ret); 1892 1893 /* Enable sleep and then disable it again */ 1894 ret = ath10k_sdio_set_mbox_sleep(ar, true); 1895 if (ret) 1896 return ret; 1897 1898 /* Wait for 20ms for the written value to take effect */ 1899 msleep(20); 1900 1901 ret = ath10k_sdio_set_mbox_sleep(ar, false); 1902 if (ret) 1903 return ret; 1904 1905 return 0; 1906 } 1907 1908 #define SDIO_IRQ_DISABLE_TIMEOUT_HZ (3 * HZ) 1909 1910 static void ath10k_sdio_irq_disable(struct ath10k *ar) 1911 { 1912 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1913 struct ath10k_sdio_irq_data *irq_data = &ar_sdio->irq_data; 1914 struct ath10k_sdio_irq_enable_regs *regs = irq_data->irq_en_reg; 1915 struct sk_buff *skb; 1916 struct completion irqs_disabled_comp; 1917 int ret; 1918 1919 skb = dev_alloc_skb(sizeof(*regs)); 1920 if (!skb) 1921 return; 1922 1923 mutex_lock(&irq_data->mtx); 1924 1925 memset(regs, 0, sizeof(*regs)); /* disable all interrupts */ 1926 memcpy(skb->data, regs, sizeof(*regs)); 1927 skb_put(skb, sizeof(*regs)); 1928 1929 mutex_unlock(&irq_data->mtx); 1930 1931 init_completion(&irqs_disabled_comp); 1932 ret = ath10k_sdio_prep_async_req(ar, MBOX_INT_STATUS_ENABLE_ADDRESS, 1933 skb, &irqs_disabled_comp, false, 0); 1934 if (ret) 1935 goto out; 1936 1937 queue_work(ar_sdio->workqueue, &ar_sdio->wr_async_work); 1938 1939 /* Wait for the completion of the IRQ disable request. 1940 * If there is a timeout we will try to disable irq's anyway. 1941 */ 1942 ret = wait_for_completion_timeout(&irqs_disabled_comp, 1943 SDIO_IRQ_DISABLE_TIMEOUT_HZ); 1944 if (!ret) 1945 ath10k_warn(ar, "sdio irq disable request timed out\n"); 1946 1947 sdio_claim_host(ar_sdio->func); 1948 1949 ret = sdio_release_irq(ar_sdio->func); 1950 if (ret) 1951 ath10k_warn(ar, "failed to release sdio interrupt: %d\n", ret); 1952 1953 sdio_release_host(ar_sdio->func); 1954 1955 out: 1956 kfree_skb(skb); 1957 } 1958 1959 static void ath10k_sdio_hif_stop(struct ath10k *ar) 1960 { 1961 struct ath10k_sdio_bus_request *req, *tmp_req; 1962 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 1963 1964 ath10k_sdio_irq_disable(ar); 1965 1966 cancel_work_sync(&ar_sdio->wr_async_work); 1967 1968 spin_lock_bh(&ar_sdio->wr_async_lock); 1969 1970 /* Free all bus requests that have not been handled */ 1971 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) { 1972 struct ath10k_htc_ep *ep; 1973 1974 list_del(&req->list); 1975 1976 if (req->htc_msg) { 1977 ep = &ar->htc.endpoint[req->eid]; 1978 ath10k_htc_notify_tx_completion(ep, req->skb); 1979 } else if (req->skb) { 1980 kfree_skb(req->skb); 1981 } 1982 ath10k_sdio_free_bus_req(ar, req); 1983 } 1984 1985 spin_unlock_bh(&ar_sdio->wr_async_lock); 1986 1987 napi_synchronize(&ar->napi); 1988 napi_disable(&ar->napi); 1989 } 1990 1991 #ifdef CONFIG_PM 1992 1993 static int ath10k_sdio_hif_suspend(struct ath10k *ar) 1994 { 1995 return 0; 1996 } 1997 1998 static int ath10k_sdio_hif_resume(struct ath10k *ar) 1999 { 2000 switch (ar->state) { 2001 case ATH10K_STATE_OFF: 2002 ath10k_dbg(ar, ATH10K_DBG_SDIO, 2003 "sdio resume configuring sdio\n"); 2004 2005 /* need to set sdio settings after power is cut from sdio */ 2006 ath10k_sdio_config(ar); 2007 break; 2008 2009 case ATH10K_STATE_ON: 2010 default: 2011 break; 2012 } 2013 2014 return 0; 2015 } 2016 #endif 2017 2018 static int ath10k_sdio_hif_map_service_to_pipe(struct ath10k *ar, 2019 u16 service_id, 2020 u8 *ul_pipe, u8 *dl_pipe) 2021 { 2022 struct ath10k_sdio *ar_sdio = ath10k_sdio_priv(ar); 2023 struct ath10k_htc *htc = &ar->htc; 2024 u32 htt_addr, wmi_addr, htt_mbox_size, wmi_mbox_size; 2025 enum ath10k_htc_ep_id eid; 2026 bool ep_found = false; 2027 int i; 2028 2029 /* For sdio, we are interested in the mapping between eid 2030 * and pipeid rather than service_id to pipe_id. 2031 * First we find out which eid has been allocated to the 2032 * service... 2033 */ 2034 for (i = 0; i < ATH10K_HTC_EP_COUNT; i++) { 2035 if (htc->endpoint[i].service_id == service_id) { 2036 eid = htc->endpoint[i].eid; 2037 ep_found = true; 2038 break; 2039 } 2040 } 2041 2042 if (!ep_found) 2043 return -EINVAL; 2044 2045 /* Then we create the simplest mapping possible between pipeid 2046 * and eid 2047 */ 2048 *ul_pipe = *dl_pipe = (u8)eid; 2049 2050 /* Normally, HTT will use the upper part of the extended 2051 * mailbox address space (ext_info[1].htc_ext_addr) and WMI ctrl 2052 * the lower part (ext_info[0].htc_ext_addr). 2053 * If fw wants swapping of mailbox addresses, the opposite is true. 2054 */ 2055 if (ar_sdio->swap_mbox) { 2056 htt_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr; 2057 wmi_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr; 2058 htt_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz; 2059 wmi_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz; 2060 } else { 2061 htt_addr = ar_sdio->mbox_info.ext_info[1].htc_ext_addr; 2062 wmi_addr = ar_sdio->mbox_info.ext_info[0].htc_ext_addr; 2063 htt_mbox_size = ar_sdio->mbox_info.ext_info[1].htc_ext_sz; 2064 wmi_mbox_size = ar_sdio->mbox_info.ext_info[0].htc_ext_sz; 2065 } 2066 2067 switch (service_id) { 2068 case ATH10K_HTC_SVC_ID_RSVD_CTRL: 2069 /* HTC ctrl ep mbox address has already been setup in 2070 * ath10k_sdio_hif_start 2071 */ 2072 break; 2073 case ATH10K_HTC_SVC_ID_WMI_CONTROL: 2074 ar_sdio->mbox_addr[eid] = wmi_addr; 2075 ar_sdio->mbox_size[eid] = wmi_mbox_size; 2076 ath10k_dbg(ar, ATH10K_DBG_SDIO, 2077 "sdio wmi ctrl mbox_addr 0x%x mbox_size %d\n", 2078 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]); 2079 break; 2080 case ATH10K_HTC_SVC_ID_HTT_DATA_MSG: 2081 ar_sdio->mbox_addr[eid] = htt_addr; 2082 ar_sdio->mbox_size[eid] = htt_mbox_size; 2083 ath10k_dbg(ar, ATH10K_DBG_SDIO, 2084 "sdio htt data mbox_addr 0x%x mbox_size %d\n", 2085 ar_sdio->mbox_addr[eid], ar_sdio->mbox_size[eid]); 2086 break; 2087 default: 2088 ath10k_warn(ar, "unsupported HTC service id: %d\n", 2089 service_id); 2090 return -EINVAL; 2091 } 2092 2093 return 0; 2094 } 2095 2096 static void ath10k_sdio_hif_get_default_pipe(struct ath10k *ar, 2097 u8 *ul_pipe, u8 *dl_pipe) 2098 { 2099 ath10k_dbg(ar, ATH10K_DBG_SDIO, "sdio hif get default pipe\n"); 2100 2101 /* HTC ctrl ep (SVC id 1) always has eid (and pipe_id in our 2102 * case) == 0 2103 */ 2104 *ul_pipe = 0; 2105 *dl_pipe = 0; 2106 } 2107 2108 static const struct ath10k_hif_ops ath10k_sdio_hif_ops = { 2109 .tx_sg = ath10k_sdio_hif_tx_sg, 2110 .diag_read = ath10k_sdio_hif_diag_read, 2111 .diag_write = ath10k_sdio_hif_diag_write_mem, 2112 .exchange_bmi_msg = ath10k_sdio_bmi_exchange_msg, 2113 .start = ath10k_sdio_hif_start, 2114 .stop = ath10k_sdio_hif_stop, 2115 .start_post = ath10k_sdio_hif_start_post, 2116 .get_htt_tx_complete = ath10k_sdio_get_htt_tx_complete, 2117 .map_service_to_pipe = ath10k_sdio_hif_map_service_to_pipe, 2118 .get_default_pipe = ath10k_sdio_hif_get_default_pipe, 2119 .power_up = ath10k_sdio_hif_power_up, 2120 .power_down = ath10k_sdio_hif_power_down, 2121 #ifdef CONFIG_PM 2122 .suspend = ath10k_sdio_hif_suspend, 2123 .resume = ath10k_sdio_hif_resume, 2124 #endif 2125 }; 2126 2127 #ifdef CONFIG_PM_SLEEP 2128 2129 /* Empty handlers so that mmc subsystem doesn't remove us entirely during 2130 * suspend. We instead follow cfg80211 suspend/resume handlers. 2131 */ 2132 static int ath10k_sdio_pm_suspend(struct device *device) 2133 { 2134 struct sdio_func *func = dev_to_sdio_func(device); 2135 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func); 2136 struct ath10k *ar = ar_sdio->ar; 2137 mmc_pm_flag_t pm_flag, pm_caps; 2138 int ret; 2139 2140 if (!device_may_wakeup(ar->dev)) 2141 return 0; 2142 2143 ath10k_sdio_set_mbox_sleep(ar, true); 2144 2145 pm_flag = MMC_PM_KEEP_POWER; 2146 2147 ret = sdio_set_host_pm_flags(func, pm_flag); 2148 if (ret) { 2149 pm_caps = sdio_get_host_pm_caps(func); 2150 ath10k_warn(ar, "failed to set sdio host pm flags (0x%x, 0x%x): %d\n", 2151 pm_flag, pm_caps, ret); 2152 return ret; 2153 } 2154 2155 return ret; 2156 } 2157 2158 static int ath10k_sdio_pm_resume(struct device *device) 2159 { 2160 return 0; 2161 } 2162 2163 static SIMPLE_DEV_PM_OPS(ath10k_sdio_pm_ops, ath10k_sdio_pm_suspend, 2164 ath10k_sdio_pm_resume); 2165 2166 #define ATH10K_SDIO_PM_OPS (&ath10k_sdio_pm_ops) 2167 2168 #else 2169 2170 #define ATH10K_SDIO_PM_OPS NULL 2171 2172 #endif /* CONFIG_PM_SLEEP */ 2173 2174 static int ath10k_sdio_napi_poll(struct napi_struct *ctx, int budget) 2175 { 2176 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 2177 int done; 2178 2179 done = ath10k_htt_rx_hl_indication(ar, budget); 2180 ath10k_dbg(ar, ATH10K_DBG_SDIO, "napi poll: done: %d, budget:%d\n", done, budget); 2181 2182 if (done < budget) 2183 napi_complete_done(ctx, done); 2184 2185 return done; 2186 } 2187 2188 static int ath10k_sdio_probe(struct sdio_func *func, 2189 const struct sdio_device_id *id) 2190 { 2191 struct ath10k_sdio *ar_sdio; 2192 struct ath10k *ar; 2193 enum ath10k_hw_rev hw_rev; 2194 u32 dev_id_base; 2195 struct ath10k_bus_params bus_params = {}; 2196 int ret, i; 2197 2198 /* Assumption: All SDIO based chipsets (so far) are QCA6174 based. 2199 * If there will be newer chipsets that does not use the hw reg 2200 * setup as defined in qca6174_regs and qca6174_values, this 2201 * assumption is no longer valid and hw_rev must be setup differently 2202 * depending on chipset. 2203 */ 2204 hw_rev = ATH10K_HW_QCA6174; 2205 2206 ar = ath10k_core_create(sizeof(*ar_sdio), &func->dev, ATH10K_BUS_SDIO, 2207 hw_rev, &ath10k_sdio_hif_ops); 2208 if (!ar) { 2209 dev_err(&func->dev, "failed to allocate core\n"); 2210 return -ENOMEM; 2211 } 2212 2213 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_sdio_napi_poll, 2214 ATH10K_NAPI_BUDGET); 2215 2216 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2217 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n", 2218 func->num, func->vendor, func->device, 2219 func->max_blksize, func->cur_blksize); 2220 2221 ar_sdio = ath10k_sdio_priv(ar); 2222 2223 ar_sdio->irq_data.irq_proc_reg = 2224 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_proc_regs), 2225 GFP_KERNEL); 2226 if (!ar_sdio->irq_data.irq_proc_reg) { 2227 ret = -ENOMEM; 2228 goto err_core_destroy; 2229 } 2230 2231 ar_sdio->vsg_buffer = devm_kmalloc(ar->dev, ATH10K_SDIO_VSG_BUF_SIZE, GFP_KERNEL); 2232 if (!ar_sdio->vsg_buffer) { 2233 ret = -ENOMEM; 2234 goto err_core_destroy; 2235 } 2236 2237 ar_sdio->irq_data.irq_en_reg = 2238 devm_kzalloc(ar->dev, sizeof(struct ath10k_sdio_irq_enable_regs), 2239 GFP_KERNEL); 2240 if (!ar_sdio->irq_data.irq_en_reg) { 2241 ret = -ENOMEM; 2242 goto err_core_destroy; 2243 } 2244 2245 ar_sdio->bmi_buf = devm_kzalloc(ar->dev, BMI_MAX_LARGE_CMDBUF_SIZE, GFP_KERNEL); 2246 if (!ar_sdio->bmi_buf) { 2247 ret = -ENOMEM; 2248 goto err_core_destroy; 2249 } 2250 2251 ar_sdio->func = func; 2252 sdio_set_drvdata(func, ar_sdio); 2253 2254 ar_sdio->is_disabled = true; 2255 ar_sdio->ar = ar; 2256 2257 spin_lock_init(&ar_sdio->lock); 2258 spin_lock_init(&ar_sdio->wr_async_lock); 2259 mutex_init(&ar_sdio->irq_data.mtx); 2260 2261 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq); 2262 INIT_LIST_HEAD(&ar_sdio->wr_asyncq); 2263 2264 INIT_WORK(&ar_sdio->wr_async_work, ath10k_sdio_write_async_work); 2265 ar_sdio->workqueue = create_singlethread_workqueue("ath10k_sdio_wq"); 2266 if (!ar_sdio->workqueue) { 2267 ret = -ENOMEM; 2268 goto err_core_destroy; 2269 } 2270 2271 for (i = 0; i < ATH10K_SDIO_BUS_REQUEST_MAX_NUM; i++) 2272 ath10k_sdio_free_bus_req(ar, &ar_sdio->bus_req[i]); 2273 2274 skb_queue_head_init(&ar_sdio->rx_head); 2275 INIT_WORK(&ar_sdio->async_work_rx, ath10k_rx_indication_async_work); 2276 2277 dev_id_base = (id->device & 0x0F00); 2278 if (dev_id_base != (SDIO_DEVICE_ID_ATHEROS_AR6005 & 0x0F00) && 2279 dev_id_base != (SDIO_DEVICE_ID_ATHEROS_QCA9377 & 0x0F00)) { 2280 ret = -ENODEV; 2281 ath10k_err(ar, "unsupported device id %u (0x%x)\n", 2282 dev_id_base, id->device); 2283 goto err_free_wq; 2284 } 2285 2286 ar->dev_id = QCA9377_1_0_DEVICE_ID; 2287 ar->id.vendor = id->vendor; 2288 ar->id.device = id->device; 2289 2290 ath10k_sdio_set_mbox_info(ar); 2291 2292 bus_params.dev_type = ATH10K_DEV_TYPE_HL; 2293 /* TODO: don't know yet how to get chip_id with SDIO */ 2294 bus_params.chip_id = 0; 2295 bus_params.hl_msdu_ids = true; 2296 2297 ar->hw->max_mtu = ETH_DATA_LEN; 2298 2299 ret = ath10k_core_register(ar, &bus_params); 2300 if (ret) { 2301 ath10k_err(ar, "failed to register driver core: %d\n", ret); 2302 goto err_free_wq; 2303 } 2304 2305 timer_setup(&ar_sdio->sleep_timer, ath10k_sdio_sleep_timer_handler, 0); 2306 2307 return 0; 2308 2309 err_free_wq: 2310 destroy_workqueue(ar_sdio->workqueue); 2311 err_core_destroy: 2312 ath10k_core_destroy(ar); 2313 2314 return ret; 2315 } 2316 2317 static void ath10k_sdio_remove(struct sdio_func *func) 2318 { 2319 struct ath10k_sdio *ar_sdio = sdio_get_drvdata(func); 2320 struct ath10k *ar = ar_sdio->ar; 2321 2322 ath10k_dbg(ar, ATH10K_DBG_BOOT, 2323 "sdio removed func %d vendor 0x%x device 0x%x\n", 2324 func->num, func->vendor, func->device); 2325 2326 ath10k_core_unregister(ar); 2327 2328 netif_napi_del(&ar->napi); 2329 2330 ath10k_core_destroy(ar); 2331 2332 flush_workqueue(ar_sdio->workqueue); 2333 destroy_workqueue(ar_sdio->workqueue); 2334 } 2335 2336 static const struct sdio_device_id ath10k_sdio_devices[] = { 2337 {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_AR6005)}, 2338 {SDIO_DEVICE(SDIO_VENDOR_ID_ATHEROS, SDIO_DEVICE_ID_ATHEROS_QCA9377)}, 2339 {}, 2340 }; 2341 2342 MODULE_DEVICE_TABLE(sdio, ath10k_sdio_devices); 2343 2344 static struct sdio_driver ath10k_sdio_driver = { 2345 .name = "ath10k_sdio", 2346 .id_table = ath10k_sdio_devices, 2347 .probe = ath10k_sdio_probe, 2348 .remove = ath10k_sdio_remove, 2349 .drv = { 2350 .owner = THIS_MODULE, 2351 .pm = ATH10K_SDIO_PM_OPS, 2352 }, 2353 }; 2354 2355 static int __init ath10k_sdio_init(void) 2356 { 2357 int ret; 2358 2359 ret = sdio_register_driver(&ath10k_sdio_driver); 2360 if (ret) 2361 pr_err("sdio driver registration failed: %d\n", ret); 2362 2363 return ret; 2364 } 2365 2366 static void __exit ath10k_sdio_exit(void) 2367 { 2368 sdio_unregister_driver(&ath10k_sdio_driver); 2369 } 2370 2371 module_init(ath10k_sdio_init); 2372 module_exit(ath10k_sdio_exit); 2373 2374 MODULE_AUTHOR("Qualcomm Atheros"); 2375 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN SDIO devices"); 2376 MODULE_LICENSE("Dual BSD/GPL"); 2377