1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _RX_DESC_H_ 19 #define _RX_DESC_H_ 20 21 #include <linux/bitops.h> 22 23 enum rx_attention_flags { 24 RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0), 25 RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1), 26 RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2), 27 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3), 28 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4), 29 RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5), 30 RX_ATTENTION_FLAGS_NON_QOS = BIT(6), 31 RX_ATTENTION_FLAGS_NULL_DATA = BIT(7), 32 RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8), 33 RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9), 34 RX_ATTENTION_FLAGS_MORE_DATA = BIT(10), 35 RX_ATTENTION_FLAGS_EOSP = BIT(11), 36 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = BIT(12), 37 RX_ATTENTION_FLAGS_FRAGMENT = BIT(13), 38 RX_ATTENTION_FLAGS_ORDER = BIT(14), 39 RX_ATTENTION_FLAGS_CLASSIFICATION = BIT(15), 40 RX_ATTENTION_FLAGS_OVERFLOW_ERR = BIT(16), 41 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = BIT(17), 42 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18), 43 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = BIT(19), 44 RX_ATTENTION_FLAGS_SA_IDX_INVALID = BIT(20), 45 RX_ATTENTION_FLAGS_DA_IDX_INVALID = BIT(21), 46 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = BIT(22), 47 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = BIT(23), 48 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = BIT(24), 49 RX_ATTENTION_FLAGS_DIRECTED = BIT(25), 50 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26), 51 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27), 52 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = BIT(28), 53 RX_ATTENTION_FLAGS_DECRYPT_ERR = BIT(29), 54 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30), 55 RX_ATTENTION_FLAGS_MSDU_DONE = BIT(31), 56 }; 57 58 struct rx_attention { 59 __le32 flags; /* %RX_ATTENTION_FLAGS_ */ 60 } __packed; 61 62 /* 63 * first_mpdu 64 * Indicates the first MSDU of the PPDU. If both first_mpdu 65 * and last_mpdu are set in the MSDU then this is a not an 66 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 67 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 68 * 0. The PPDU start status will only be valid when this bit 69 * is set. 70 * 71 * last_mpdu 72 * Indicates the last MSDU of the last MPDU of the PPDU. The 73 * PPDU end status will only be valid when this bit is set. 74 * 75 * mcast_bcast 76 * Multicast / broadcast indicator. Only set when the MAC 77 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 78 * matches one of the 4 BSSID registers. Only set when 79 * first_msdu is set. 80 * 81 * peer_idx_invalid 82 * Indicates no matching entries within the the max search 83 * count. Only set when first_msdu is set. 84 * 85 * peer_idx_timeout 86 * Indicates an unsuccessful search for the peer index due to 87 * timeout. Only set when first_msdu is set. 88 * 89 * power_mgmt 90 * Power management bit set in the 802.11 header. Only set 91 * when first_msdu is set. 92 * 93 * non_qos 94 * Set if packet is not a non-QoS data frame. Only set when 95 * first_msdu is set. 96 * 97 * null_data 98 * Set if frame type indicates either null data or QoS null 99 * data format. Only set when first_msdu is set. 100 * 101 * mgmt_type 102 * Set if packet is a management packet. Only set when 103 * first_msdu is set. 104 * 105 * ctrl_type 106 * Set if packet is a control packet. Only set when first_msdu 107 * is set. 108 * 109 * more_data 110 * Set if more bit in frame control is set. Only set when 111 * first_msdu is set. 112 * 113 * eosp 114 * Set if the EOSP (end of service period) bit in the QoS 115 * control field is set. Only set when first_msdu is set. 116 * 117 * u_apsd_trigger 118 * Set if packet is U-APSD trigger. Key table will have bits 119 * per TID to indicate U-APSD trigger. 120 * 121 * fragment 122 * Indicates that this is an 802.11 fragment frame. This is 123 * set when either the more_frag bit is set in the frame 124 * control or the fragment number is not zero. Only set when 125 * first_msdu is set. 126 * 127 * order 128 * Set if the order bit in the frame control is set. Only set 129 * when first_msdu is set. 130 * 131 * classification 132 * Indicates that this status has a corresponding MSDU that 133 * requires FW processing. The OLE will have classification 134 * ring mask registers which will indicate the ring(s) for 135 * packets and descriptors which need FW attention. 136 * 137 * overflow_err 138 * PCU Receive FIFO does not have enough space to store the 139 * full receive packet. Enough space is reserved in the 140 * receive FIFO for the status is written. This MPDU remaining 141 * packets in the PPDU will be filtered and no Ack response 142 * will be transmitted. 143 * 144 * msdu_length_err 145 * Indicates that the MSDU length from the 802.3 encapsulated 146 * length field extends beyond the MPDU boundary. 147 * 148 * tcp_udp_chksum_fail 149 * Indicates that the computed checksum (tcp_udp_chksum) did 150 * not match the checksum in the TCP/UDP header. 151 * 152 * ip_chksum_fail 153 * Indicates that the computed checksum did not match the 154 * checksum in the IP header. 155 * 156 * sa_idx_invalid 157 * Indicates no matching entry was found in the address search 158 * table for the source MAC address. 159 * 160 * da_idx_invalid 161 * Indicates no matching entry was found in the address search 162 * table for the destination MAC address. 163 * 164 * sa_idx_timeout 165 * Indicates an unsuccessful search for the source MAC address 166 * due to the expiring of the search timer. 167 * 168 * da_idx_timeout 169 * Indicates an unsuccessful search for the destination MAC 170 * address due to the expiring of the search timer. 171 * 172 * encrypt_required 173 * Indicates that this data type frame is not encrypted even if 174 * the policy for this MPDU requires encryption as indicated in 175 * the peer table key type. 176 * 177 * directed 178 * MPDU is a directed packet which means that the RA matched 179 * our STA addresses. In proxySTA it means that the TA matched 180 * an entry in our address search table with the corresponding 181 * 'no_ack' bit is the address search entry cleared. 182 * 183 * buffer_fragment 184 * Indicates that at least one of the rx buffers has been 185 * fragmented. If set the FW should look at the rx_frag_info 186 * descriptor described below. 187 * 188 * mpdu_length_err 189 * Indicates that the MPDU was pre-maturely terminated 190 * resulting in a truncated MPDU. Don't trust the MPDU length 191 * field. 192 * 193 * tkip_mic_err 194 * Indicates that the MPDU Michael integrity check failed 195 * 196 * decrypt_err 197 * Indicates that the MPDU decrypt integrity check failed 198 * 199 * fcs_err 200 * Indicates that the MPDU FCS check failed 201 * 202 * msdu_done 203 * If set indicates that the RX packet data, RX header data, RX 204 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 205 * start/end descriptors and RX Attention descriptor are all 206 * valid. This bit must be in the last octet of the 207 * descriptor. 208 */ 209 210 struct rx_frag_info { 211 u8 ring0_more_count; 212 u8 ring1_more_count; 213 u8 ring2_more_count; 214 u8 ring3_more_count; 215 u8 ring4_more_count; 216 u8 ring5_more_count; 217 u8 ring6_more_count; 218 u8 ring7_more_count; 219 } __packed; 220 221 /* 222 * ring0_more_count 223 * Indicates the number of more buffers associated with RX DMA 224 * ring 0. Field is filled in by the RX_DMA. 225 * 226 * ring1_more_count 227 * Indicates the number of more buffers associated with RX DMA 228 * ring 1. Field is filled in by the RX_DMA. 229 * 230 * ring2_more_count 231 * Indicates the number of more buffers associated with RX DMA 232 * ring 2. Field is filled in by the RX_DMA. 233 * 234 * ring3_more_count 235 * Indicates the number of more buffers associated with RX DMA 236 * ring 3. Field is filled in by the RX_DMA. 237 */ 238 239 enum htt_rx_mpdu_encrypt_type { 240 HTT_RX_MPDU_ENCRYPT_WEP40 = 0, 241 HTT_RX_MPDU_ENCRYPT_WEP104 = 1, 242 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2, 243 HTT_RX_MPDU_ENCRYPT_WEP128 = 3, 244 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4, 245 HTT_RX_MPDU_ENCRYPT_WAPI = 5, 246 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6, 247 HTT_RX_MPDU_ENCRYPT_NONE = 7, 248 HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2 = 8, 249 HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2 = 9, 250 HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10, 251 }; 252 253 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff 254 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0 255 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000 256 #define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16 257 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000 258 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28 259 #define RX_MPDU_START_INFO0_FROM_DS BIT(11) 260 #define RX_MPDU_START_INFO0_TO_DS BIT(12) 261 #define RX_MPDU_START_INFO0_ENCRYPTED BIT(13) 262 #define RX_MPDU_START_INFO0_RETRY BIT(14) 263 #define RX_MPDU_START_INFO0_TXBF_H_INFO BIT(15) 264 265 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000 266 #define RX_MPDU_START_INFO1_TID_LSB 28 267 #define RX_MPDU_START_INFO1_DIRECTED BIT(16) 268 269 struct rx_mpdu_start { 270 __le32 info0; 271 union { 272 struct { 273 __le32 pn31_0; 274 __le32 info1; /* %RX_MPDU_START_INFO1_ */ 275 } __packed; 276 struct { 277 u8 pn[6]; 278 } __packed; 279 } __packed; 280 } __packed; 281 282 /* 283 * peer_idx 284 * The index of the address search table which associated with 285 * the peer table entry corresponding to this MPDU. Only valid 286 * when first_msdu is set. 287 * 288 * fr_ds 289 * Set if the from DS bit is set in the frame control. Only 290 * valid when first_msdu is set. 291 * 292 * to_ds 293 * Set if the to DS bit is set in the frame control. Only 294 * valid when first_msdu is set. 295 * 296 * encrypted 297 * Protected bit from the frame control. Only valid when 298 * first_msdu is set. 299 * 300 * retry 301 * Retry bit from the frame control. Only valid when 302 * first_msdu is set. 303 * 304 * txbf_h_info 305 * The MPDU data will contain H information. Primarily used 306 * for debug. 307 * 308 * seq_num 309 * The sequence number from the 802.11 header. Only valid when 310 * first_msdu is set. 311 * 312 * encrypt_type 313 * Indicates type of decrypt cipher used (as defined in the 314 * peer table) 315 * 0: WEP40 316 * 1: WEP104 317 * 2: TKIP without MIC 318 * 3: WEP128 319 * 4: TKIP (WPA) 320 * 5: WAPI 321 * 6: AES-CCM (WPA2) 322 * 7: No cipher 323 * Only valid when first_msdu_is set 324 * 325 * pn_31_0 326 * Bits [31:0] of the PN number extracted from the IV field 327 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is 328 * valid. 329 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 330 * WEPSeed[1], pn1}. Only pn[47:0] is valid. 331 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 332 * pn0}. Only pn[47:0] is valid. 333 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 334 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 335 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and 336 * pn[47:0] are valid. 337 * Only valid when first_msdu is set. 338 * 339 * pn_47_32 340 * Bits [47:32] of the PN number. See description for 341 * pn_31_0. The remaining PN fields are in the rx_msdu_end 342 * descriptor 343 * 344 * pn 345 * Use this field to access the pn without worrying about 346 * byte-order and bitmasking/bitshifting. 347 * 348 * directed 349 * See definition in RX attention descriptor 350 * 351 * reserved_2 352 * Reserved: HW should fill with zero. FW should ignore. 353 * 354 * tid 355 * The TID field in the QoS control field 356 */ 357 358 #define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff 359 #define RX_MPDU_END_INFO0_RESERVED_0_LSB 0 360 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000 361 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16 362 #define RX_MPDU_END_INFO0_OVERFLOW_ERR BIT(13) 363 #define RX_MPDU_END_INFO0_LAST_MPDU BIT(14) 364 #define RX_MPDU_END_INFO0_POST_DELIM_ERR BIT(15) 365 #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR BIT(28) 366 #define RX_MPDU_END_INFO0_TKIP_MIC_ERR BIT(29) 367 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30) 368 #define RX_MPDU_END_INFO0_FCS_ERR BIT(31) 369 370 struct rx_mpdu_end { 371 __le32 info0; 372 } __packed; 373 374 /* 375 * reserved_0 376 * Reserved 377 * 378 * overflow_err 379 * PCU Receive FIFO does not have enough space to store the 380 * full receive packet. Enough space is reserved in the 381 * receive FIFO for the status is written. This MPDU remaining 382 * packets in the PPDU will be filtered and no Ack response 383 * will be transmitted. 384 * 385 * last_mpdu 386 * Indicates that this is the last MPDU of a PPDU. 387 * 388 * post_delim_err 389 * Indicates that a delimiter FCS error occurred after this 390 * MPDU before the next MPDU. Only valid when last_msdu is 391 * set. 392 * 393 * post_delim_cnt 394 * Count of the delimiters after this MPDU. This requires the 395 * last MPDU to be held until all the EOF descriptors have been 396 * received. This may be inefficient in the future when 397 * ML-MIMO is used. Only valid when last_mpdu is set. 398 * 399 * mpdu_length_err 400 * See definition in RX attention descriptor 401 * 402 * tkip_mic_err 403 * See definition in RX attention descriptor 404 * 405 * decrypt_err 406 * See definition in RX attention descriptor 407 * 408 * fcs_err 409 * See definition in RX attention descriptor 410 */ 411 412 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff 413 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0 414 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000 415 #define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14 416 #define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000 417 #define RX_MSDU_START_INFO0_RING_MASK_LSB 20 418 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000 419 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24 420 421 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff 422 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0 423 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300 424 #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8 425 #define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000 426 #define RX_MSDU_START_INFO1_SA_IDX_LSB 16 427 #define RX_MSDU_START_INFO1_IPV4_PROTO BIT(10) 428 #define RX_MSDU_START_INFO1_IPV6_PROTO BIT(11) 429 #define RX_MSDU_START_INFO1_TCP_PROTO BIT(12) 430 #define RX_MSDU_START_INFO1_UDP_PROTO BIT(13) 431 #define RX_MSDU_START_INFO1_IP_FRAG BIT(14) 432 #define RX_MSDU_START_INFO1_TCP_ONLY_ACK BIT(15) 433 434 #define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff 435 #define RX_MSDU_START_INFO2_DA_IDX_LSB 0 436 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000 437 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16 438 #define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) 439 440 /* The decapped header (rx_hdr_status) contains the following: 441 * a) 802.11 header 442 * [padding to 4 bytes] 443 * b) HW crypto parameter 444 * - 0 bytes for no security 445 * - 4 bytes for WEP 446 * - 8 bytes for TKIP, AES 447 * [padding to 4 bytes] 448 * c) A-MSDU subframe header (14 bytes) if appliable 449 * d) LLC/SNAP (RFC1042, 8 bytes) 450 * 451 * In case of A-MSDU only first frame in sequence contains (a) and (b). 452 */ 453 enum rx_msdu_decap_format { 454 RX_MSDU_DECAP_RAW = 0, 455 456 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in 457 * htt_rx_desc contains the original decapped 802.11 header. 458 */ 459 RX_MSDU_DECAP_NATIVE_WIFI = 1, 460 461 /* Payload contains an ethernet header (struct ethhdr). */ 462 RX_MSDU_DECAP_ETHERNET2_DIX = 2, 463 464 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes 465 * total), followed by an RFC1042 header (8 bytes). 466 */ 467 RX_MSDU_DECAP_8023_SNAP_LLC = 3 468 }; 469 470 struct rx_msdu_start_common { 471 __le32 info0; /* %RX_MSDU_START_INFO0_ */ 472 __le32 flow_id_crc; 473 __le32 info1; /* %RX_MSDU_START_INFO1_ */ 474 } __packed; 475 476 struct rx_msdu_start_qca99x0 { 477 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 478 } __packed; 479 480 struct rx_msdu_start_wcn3990 { 481 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 482 __le32 info3; /* %RX_MSDU_START_INFO3_ */ 483 } __packed; 484 485 struct rx_msdu_start { 486 struct rx_msdu_start_common common; 487 union { 488 struct rx_msdu_start_qca99x0 qca99x0; 489 struct rx_msdu_start_wcn3990 wcn3990; 490 } __packed; 491 } __packed; 492 493 /* 494 * msdu_length 495 * MSDU length in bytes after decapsulation. This field is 496 * still valid for MPDU frames without A-MSDU. It still 497 * represents MSDU length after decapsulation 498 * 499 * ip_offset 500 * Indicates the IP offset in bytes from the start of the 501 * packet after decapsulation. Only valid if ipv4_proto or 502 * ipv6_proto is set. 503 * 504 * ring_mask 505 * Indicates the destination RX rings for this MSDU. 506 * 507 * tcp_udp_offset 508 * Indicates the offset in bytes to the start of TCP or UDP 509 * header from the start of the IP header after decapsulation. 510 * Only valid if tcp_prot or udp_prot is set. The value 0 511 * indicates that the offset is longer than 127 bytes. 512 * 513 * reserved_0c 514 * Reserved: HW should fill with zero. FW should ignore. 515 * 516 * flow_id_crc 517 * The flow_id_crc runs CRC32 on the following information: 518 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0, 519 * protocol[7:0]}. 520 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0, 521 * next_header[7:0]} 522 * UDP case: sort_port[15:0], dest_port[15:0] 523 * TCP case: sort_port[15:0], dest_port[15:0], 524 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]}, 525 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit 526 * timestamp. 527 * 528 * msdu_number 529 * Indicates the MSDU number within a MPDU. This value is 530 * reset to zero at the start of each MPDU. If the number of 531 * MSDU exceeds 255 this number will wrap using modulo 256. 532 * 533 * decap_format 534 * Indicates the format after decapsulation: 535 * 0: RAW: No decapsulation 536 * 1: Native WiFi 537 * 2: Ethernet 2 (DIX) 538 * 3: 802.3 (SNAP/LLC) 539 * 540 * ipv4_proto 541 * Set if L2 layer indicates IPv4 protocol. 542 * 543 * ipv6_proto 544 * Set if L2 layer indicates IPv6 protocol. 545 * 546 * tcp_proto 547 * Set if the ipv4_proto or ipv6_proto are set and the IP 548 * protocol indicates TCP. 549 * 550 * udp_proto 551 * Set if the ipv4_proto or ipv6_proto are set and the IP 552 * protocol indicates UDP. 553 * 554 * ip_frag 555 * Indicates that either the IP More frag bit is set or IP frag 556 * number is non-zero. If set indicates that this is a 557 * fragmented IP packet. 558 * 559 * tcp_only_ack 560 * Set if only the TCP Ack bit is set in the TCP flags and if 561 * the TCP payload is 0. 562 * 563 * sa_idx 564 * The offset in the address table which matches the MAC source 565 * address. 566 * 567 * reserved_2b 568 * Reserved: HW should fill with zero. FW should ignore. 569 */ 570 571 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff 572 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0 573 #define RX_MSDU_END_INFO0_FIRST_MSDU BIT(14) 574 #define RX_MSDU_END_INFO0_LAST_MSDU BIT(15) 575 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30) 576 #define RX_MSDU_END_INFO0_RESERVED_3B BIT(31) 577 578 struct rx_msdu_end_common { 579 __le16 ip_hdr_cksum; 580 __le16 tcp_hdr_cksum; 581 u8 key_id_octet; 582 u8 classification_filter; 583 u8 wapi_pn[10]; 584 __le32 info0; 585 } __packed; 586 587 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff 588 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0 589 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00 590 #define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10 591 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000 592 #define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16 593 #define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) 594 595 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f 596 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0 597 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0 598 #define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6 599 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000 600 #define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12 601 602 struct rx_msdu_end_qca99x0 { 603 __le32 ipv6_crc; 604 __le32 tcp_seq_no; 605 __le32 tcp_ack_no; 606 __le32 info1; 607 __le32 info2; 608 } __packed; 609 610 struct rx_msdu_end_wcn3990 { 611 __le32 ipv6_crc; 612 __le32 tcp_seq_no; 613 __le32 tcp_ack_no; 614 __le32 info1; 615 __le32 info2; 616 __le32 rule_indication_0; 617 __le32 rule_indication_1; 618 __le32 rule_indication_2; 619 __le32 rule_indication_3; 620 } __packed; 621 622 struct rx_msdu_end { 623 struct rx_msdu_end_common common; 624 union { 625 struct rx_msdu_end_qca99x0 qca99x0; 626 struct rx_msdu_end_wcn3990 wcn3990; 627 } __packed; 628 } __packed; 629 630 /* 631 *ip_hdr_chksum 632 * This can include the IP header checksum or the pseudo header 633 * checksum used by TCP/UDP checksum. 634 * 635 *tcp_udp_chksum 636 * The value of the computed TCP/UDP checksum. A mode bit 637 * selects whether this checksum is the full checksum or the 638 * partial checksum which does not include the pseudo header. 639 * 640 *key_id_octet 641 * The key ID octet from the IV. Only valid when first_msdu is 642 * set. 643 * 644 *classification_filter 645 * Indicates the number classification filter rule 646 * 647 *ext_wapi_pn_63_48 648 * Extension PN (packet number) which is only used by WAPI. 649 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The 650 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start 651 * descriptor. 652 * 653 *ext_wapi_pn_95_64 654 * Extension PN (packet number) which is only used by WAPI. 655 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and 656 * pn11). 657 * 658 *ext_wapi_pn_127_96 659 * Extension PN (packet number) which is only used by WAPI. 660 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, 661 * pn15). 662 * 663 *reported_mpdu_length 664 * MPDU length before decapsulation. Only valid when 665 * first_msdu is set. This field is taken directly from the 666 * length field of the A-MPDU delimiter or the preamble length 667 * field for non-A-MPDU frames. 668 * 669 *first_msdu 670 * Indicates the first MSDU of A-MSDU. If both first_msdu and 671 * last_msdu are set in the MSDU then this is a non-aggregated 672 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 673 * have both first_mpdu and last_mpdu bits set to 0. 674 * 675 *last_msdu 676 * Indicates the last MSDU of the A-MSDU. MPDU end status is 677 * only valid when last_msdu is set. 678 * 679 *reserved_3a 680 * Reserved: HW should fill with zero. FW should ignore. 681 * 682 *pre_delim_err 683 * Indicates that the first delimiter had a FCS failure. Only 684 * valid when first_mpdu and first_msdu are set. 685 * 686 *reserved_3b 687 * Reserved: HW should fill with zero. FW should ignore. 688 */ 689 690 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 691 #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 692 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 693 #define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C 694 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D 695 696 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0) 697 698 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f 699 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0 700 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0 701 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5 702 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000 703 #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18 704 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000 705 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24 706 #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT BIT(4) 707 #define RX_PPDU_START_INFO1_L_SIG_PARITY BIT(17) 708 709 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff 710 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0 711 712 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff 713 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0 714 #define RX_PPDU_START_INFO3_TXBF_H_INFO BIT(24) 715 716 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff 717 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0 718 719 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff 720 #define RX_PPDU_START_INFO5_SERVICE_LSB 0 721 722 /* No idea what this flag means. It seems to be always set in rate. */ 723 #define RX_PPDU_START_RATE_FLAG BIT(3) 724 725 struct rx_ppdu_start { 726 struct { 727 u8 pri20_mhz; 728 u8 ext20_mhz; 729 u8 ext40_mhz; 730 u8 ext80_mhz; 731 } rssi_chains[4]; 732 u8 rssi_comb; 733 __le16 rsvd0; 734 u8 info0; /* %RX_PPDU_START_INFO0_ */ 735 __le32 info1; /* %RX_PPDU_START_INFO1_ */ 736 __le32 info2; /* %RX_PPDU_START_INFO2_ */ 737 __le32 info3; /* %RX_PPDU_START_INFO3_ */ 738 __le32 info4; /* %RX_PPDU_START_INFO4_ */ 739 __le32 info5; /* %RX_PPDU_START_INFO5_ */ 740 } __packed; 741 742 /* 743 * rssi_chain0_pri20 744 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 745 * Value of 0x80 indicates invalid. 746 * 747 * rssi_chain0_sec20 748 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth. 749 * Value of 0x80 indicates invalid. 750 * 751 * rssi_chain0_sec40 752 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth. 753 * Value of 0x80 indicates invalid. 754 * 755 * rssi_chain0_sec80 756 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth. 757 * Value of 0x80 indicates invalid. 758 * 759 * rssi_chain1_pri20 760 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 761 * Value of 0x80 indicates invalid. 762 * 763 * rssi_chain1_sec20 764 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth. 765 * Value of 0x80 indicates invalid. 766 * 767 * rssi_chain1_sec40 768 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth. 769 * Value of 0x80 indicates invalid. 770 * 771 * rssi_chain1_sec80 772 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth. 773 * Value of 0x80 indicates invalid. 774 * 775 * rssi_chain2_pri20 776 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 777 * Value of 0x80 indicates invalid. 778 * 779 * rssi_chain2_sec20 780 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth. 781 * Value of 0x80 indicates invalid. 782 * 783 * rssi_chain2_sec40 784 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth. 785 * Value of 0x80 indicates invalid. 786 * 787 * rssi_chain2_sec80 788 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth. 789 * Value of 0x80 indicates invalid. 790 * 791 * rssi_chain3_pri20 792 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 793 * Value of 0x80 indicates invalid. 794 * 795 * rssi_chain3_sec20 796 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth. 797 * Value of 0x80 indicates invalid. 798 * 799 * rssi_chain3_sec40 800 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth. 801 * Value of 0x80 indicates invalid. 802 * 803 * rssi_chain3_sec80 804 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth. 805 * Value of 0x80 indicates invalid. 806 * 807 * rssi_comb 808 * The combined RSSI of RX PPDU of all active chains and 809 * bandwidths. Value of 0x80 indicates invalid. 810 * 811 * reserved_4a 812 * Reserved: HW should fill with 0, FW should ignore. 813 * 814 * is_greenfield 815 * Do we really support this? 816 * 817 * reserved_4b 818 * Reserved: HW should fill with 0, FW should ignore. 819 * 820 * l_sig_rate 821 * If l_sig_rate_select is 0: 822 * 0x8: OFDM 48 Mbps 823 * 0x9: OFDM 24 Mbps 824 * 0xA: OFDM 12 Mbps 825 * 0xB: OFDM 6 Mbps 826 * 0xC: OFDM 54 Mbps 827 * 0xD: OFDM 36 Mbps 828 * 0xE: OFDM 18 Mbps 829 * 0xF: OFDM 9 Mbps 830 * If l_sig_rate_select is 1: 831 * 0x8: CCK 11 Mbps long preamble 832 * 0x9: CCK 5.5 Mbps long preamble 833 * 0xA: CCK 2 Mbps long preamble 834 * 0xB: CCK 1 Mbps long preamble 835 * 0xC: CCK 11 Mbps short preamble 836 * 0xD: CCK 5.5 Mbps short preamble 837 * 0xE: CCK 2 Mbps short preamble 838 * 839 * l_sig_rate_select 840 * Legacy signal rate select. If set then l_sig_rate indicates 841 * CCK rates. If clear then l_sig_rate indicates OFDM rates. 842 * 843 * l_sig_length 844 * Length of legacy frame in octets. 845 * 846 * l_sig_parity 847 * Odd parity over l_sig_rate and l_sig_length 848 * 849 * l_sig_tail 850 * Tail bits for Viterbi decoder 851 * 852 * preamble_type 853 * Indicates the type of preamble ahead: 854 * 0x4: Legacy (OFDM/CCK) 855 * 0x8: HT 856 * 0x9: HT with TxBF 857 * 0xC: VHT 858 * 0xD: VHT with TxBF 859 * 0x80 - 0xFF: Reserved for special baseband data types such 860 * as radar and spectral scan. 861 * 862 * ht_sig_vht_sig_a_1 863 * If preamble_type == 0x8 or 0x9 864 * HT-SIG (first 24 bits) 865 * If preamble_type == 0xC or 0xD 866 * VHT-SIG A (first 24 bits) 867 * Else 868 * Reserved 869 * 870 * reserved_6 871 * Reserved: HW should fill with 0, FW should ignore. 872 * 873 * ht_sig_vht_sig_a_2 874 * If preamble_type == 0x8 or 0x9 875 * HT-SIG (last 24 bits) 876 * If preamble_type == 0xC or 0xD 877 * VHT-SIG A (last 24 bits) 878 * Else 879 * Reserved 880 * 881 * txbf_h_info 882 * Indicates that the packet data carries H information which 883 * is used for TxBF debug. 884 * 885 * reserved_7 886 * Reserved: HW should fill with 0, FW should ignore. 887 * 888 * vht_sig_b 889 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all 890 * 0s since the BB does not plan on decoding VHT SIG-B. 891 * 892 * reserved_8 893 * Reserved: HW should fill with 0, FW should ignore. 894 * 895 * service 896 * Service field from BB for OFDM, HT and VHT packets. CCK 897 * packets will have service field of 0. 898 * 899 * reserved_9 900 * Reserved: HW should fill with 0, FW should ignore. 901 */ 902 903 #define RX_PPDU_END_FLAGS_PHY_ERR BIT(0) 904 #define RX_PPDU_END_FLAGS_RX_LOCATION BIT(1) 905 #define RX_PPDU_END_FLAGS_TXBF_H_INFO BIT(2) 906 907 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff 908 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0 909 #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24) 910 #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25) 911 912 #define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc 913 #define RX_PPDU_END_INFO1_PEER_IDX_LSB 2 914 #define RX_PPDU_END_INFO1_BB_DATA BIT(0) 915 #define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) 916 #define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) 917 918 struct rx_ppdu_end_common { 919 __le32 evm_p0; 920 __le32 evm_p1; 921 __le32 evm_p2; 922 __le32 evm_p3; 923 __le32 evm_p4; 924 __le32 evm_p5; 925 __le32 evm_p6; 926 __le32 evm_p7; 927 __le32 evm_p8; 928 __le32 evm_p9; 929 __le32 evm_p10; 930 __le32 evm_p11; 931 __le32 evm_p12; 932 __le32 evm_p13; 933 __le32 evm_p14; 934 __le32 evm_p15; 935 __le32 tsf_timestamp; 936 __le32 wb_timestamp; 937 } __packed; 938 939 struct rx_ppdu_end_qca988x { 940 u8 locationing_timestamp; 941 u8 phy_err_code; 942 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 943 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 944 __le16 bb_length; 945 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 946 } __packed; 947 948 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff 949 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0 950 #define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000 951 #define RX_PPDU_END_RTT_UNUSED_LSB 24 952 #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) 953 954 struct rx_ppdu_end_qca6174 { 955 u8 locationing_timestamp; 956 u8 phy_err_code; 957 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 958 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 959 __le32 rtt; /* %RX_PPDU_END_RTT_ */ 960 __le16 bb_length; 961 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 962 } __packed; 963 964 #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) 965 #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) 966 #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) 967 #define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) 968 #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) 969 #define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) 970 971 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff 972 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0 973 #define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000 974 #define RX_LOCATION_INFO_FAC_STATUS_LSB 18 975 #define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000 976 #define RX_LOCATION_INFO_PKT_BW_LSB 20 977 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000 978 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23 979 #define RX_LOCATION_INFO_CIR_STATUS BIT(17) 980 #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) 981 #define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) 982 #define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) 983 #define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) 984 985 struct rx_pkt_end { 986 __le32 info0; /* %RX_PKT_END_INFO0_ */ 987 __le32 phy_timestamp_1; 988 __le32 phy_timestamp_2; 989 } __packed; 990 991 struct rx_pkt_end_wcn3990 { 992 __le32 info0; /* %RX_PKT_END_INFO0_ */ 993 __le64 phy_timestamp_1; 994 __le64 phy_timestamp_2; 995 } __packed; 996 997 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff 998 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 999 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 1000 #define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 1001 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 1002 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 1003 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) 1004 #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) 1005 1006 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c 1007 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 1008 #define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 1009 #define RX_LOCATION_INFO1_PKT_BW_LSB 4 1010 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 1011 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 1012 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 1013 #define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 1014 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 1015 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 1016 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 1017 #define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 1018 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 1019 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 1020 #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) 1021 #define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) 1022 #define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) 1023 #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) 1024 #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) 1025 #define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) 1026 1027 struct rx_location_info { 1028 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1029 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1030 } __packed; 1031 1032 struct rx_location_info_wcn3990 { 1033 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1034 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1035 __le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */ 1036 } __packed; 1037 1038 enum rx_phy_ppdu_end_info0 { 1039 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), 1040 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), 1041 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), 1042 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), 1043 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), 1044 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), 1045 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), 1046 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), 1047 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), 1048 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), 1049 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), 1050 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), 1051 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), 1052 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), 1053 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), 1054 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), 1055 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), 1056 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), 1057 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), 1058 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), 1059 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), 1060 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), 1061 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), 1062 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), 1063 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), 1064 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), 1065 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), 1066 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), 1067 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), 1068 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), 1069 }; 1070 1071 enum rx_phy_ppdu_end_info1 { 1072 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), 1073 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), 1074 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), 1075 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), 1076 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), 1077 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), 1078 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), 1079 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), 1080 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), 1081 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), 1082 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), 1083 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), 1084 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), 1085 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), 1086 }; 1087 1088 struct rx_phy_ppdu_end { 1089 __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */ 1090 __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */ 1091 } __packed; 1092 1093 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff 1094 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0 1095 1096 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff 1097 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0 1098 #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) 1099 #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) 1100 #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) 1101 #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) 1102 #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) 1103 #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) 1104 #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) 1105 1106 struct rx_ppdu_end_qca99x0 { 1107 struct rx_pkt_end rx_pkt_end; 1108 __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ 1109 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1110 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1111 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1112 __le16 bb_length; 1113 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1114 } __packed; 1115 1116 struct rx_ppdu_end_qca9984 { 1117 struct rx_pkt_end rx_pkt_end; 1118 struct rx_location_info rx_location_info; 1119 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1120 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1121 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1122 __le16 bb_length; 1123 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1124 } __packed; 1125 1126 struct rx_ppdu_end_wcn3990 { 1127 struct rx_pkt_end_wcn3990 rx_pkt_end; 1128 struct rx_location_info_wcn3990 rx_location_info; 1129 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1130 __le32 rx_timing_offset; 1131 __le32 reserved_info_0; 1132 __le32 reserved_info_1; 1133 __le32 rx_antenna_info; 1134 __le32 rx_coex_info; 1135 __le32 rx_mpdu_cnt_info; 1136 __le64 phy_timestamp_tx; 1137 __le32 rx_bb_length; 1138 } __packed; 1139 1140 struct rx_ppdu_end { 1141 struct rx_ppdu_end_common common; 1142 union { 1143 struct rx_ppdu_end_qca988x qca988x; 1144 struct rx_ppdu_end_qca6174 qca6174; 1145 struct rx_ppdu_end_qca99x0 qca99x0; 1146 struct rx_ppdu_end_qca9984 qca9984; 1147 struct rx_ppdu_end_wcn3990 wcn3990; 1148 } __packed; 1149 } __packed; 1150 1151 /* 1152 * evm_p0 1153 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3. 1154 * 1155 * evm_p1 1156 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3. 1157 * 1158 * evm_p2 1159 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3. 1160 * 1161 * evm_p3 1162 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3. 1163 * 1164 * evm_p4 1165 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3. 1166 * 1167 * evm_p5 1168 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3. 1169 * 1170 * evm_p6 1171 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3. 1172 * 1173 * evm_p7 1174 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3. 1175 * 1176 * evm_p8 1177 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3. 1178 * 1179 * evm_p9 1180 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3. 1181 * 1182 * evm_p10 1183 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3. 1184 * 1185 * evm_p11 1186 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3. 1187 * 1188 * evm_p12 1189 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3. 1190 * 1191 * evm_p13 1192 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3. 1193 * 1194 * evm_p14 1195 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3. 1196 * 1197 * evm_p15 1198 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3. 1199 * 1200 * tsf_timestamp 1201 * Receive TSF timestamp sampled on the rising edge of 1202 * rx_clear. For PHY errors this may be the current TSF when 1203 * phy_error is asserted if the rx_clear does not assert before 1204 * the end of the PHY error. 1205 * 1206 * wb_timestamp 1207 * WLAN/BT timestamp is a 1 usec resolution timestamp which 1208 * does not get updated based on receive beacon like TSF. The 1209 * same rules for capturing tsf_timestamp are used to capture 1210 * the wb_timestamp. 1211 * 1212 * locationing_timestamp 1213 * Timestamp used for locationing. This timestamp is used to 1214 * indicate fractions of usec. For example if the MAC clock is 1215 * running at 80 MHz, the timestamp will increment every 12.5 1216 * nsec. The value starts at 0 and increments to 79 and 1217 * returns to 0 and repeats. This information is valid for 1218 * every PPDU. This information can be used in conjunction 1219 * with wb_timestamp to capture large delta times. 1220 * 1221 * phy_err_code 1222 * See the 1.10.8.1.2 for the list of the PHY error codes. 1223 * 1224 * phy_err 1225 * Indicates a PHY error was detected for this PPDU. 1226 * 1227 * rx_location 1228 * Indicates that location information was requested. 1229 * 1230 * txbf_h_info 1231 * Indicates that the packet data carries H information which 1232 * is used for TxBF debug. 1233 * 1234 * reserved_18 1235 * Reserved: HW should fill with 0, FW should ignore. 1236 * 1237 * rx_antenna 1238 * Receive antenna value 1239 * 1240 * tx_ht_vht_ack 1241 * Indicates that a HT or VHT Ack/BA frame was transmitted in 1242 * response to this receive packet. 1243 * 1244 * bb_captured_channel 1245 * Indicates that the BB has captured a channel dump. FW can 1246 * then read the channel dump memory. This may indicate that 1247 * the channel was captured either based on PCU setting the 1248 * capture_channel bit BB descriptor or FW setting the 1249 * capture_channel mode bit. 1250 * 1251 * reserved_19 1252 * Reserved: HW should fill with 0, FW should ignore. 1253 * 1254 * bb_length 1255 * Indicates the number of bytes of baseband information for 1256 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF 1257 * which indicates that this is not a normal PPDU but rather 1258 * contains baseband debug information. 1259 * 1260 * reserved_20 1261 * Reserved: HW should fill with 0, FW should ignore. 1262 * 1263 * ppdu_done 1264 * PPDU end status is only valid when ppdu_done bit is set. 1265 * Every time HW sets this bit in memory FW/SW must clear this 1266 * bit in memory. FW will initialize all the ppdu_done dword 1267 * to 0. 1268 */ 1269 1270 #define FW_RX_DESC_INFO0_DISCARD BIT(0) 1271 #define FW_RX_DESC_INFO0_FORWARD BIT(1) 1272 #define FW_RX_DESC_INFO0_INSPECT BIT(5) 1273 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0 1274 #define FW_RX_DESC_INFO0_EXT_LSB 6 1275 1276 struct fw_rx_desc_base { 1277 u8 info0; 1278 } __packed; 1279 1280 #endif /* _RX_DESC_H_ */ 1281