1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (c) 2005-2011 Atheros Communications Inc.
4  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5  */
6 
7 #ifndef _RX_DESC_H_
8 #define _RX_DESC_H_
9 
10 #include <linux/bitops.h>
11 
12 enum rx_attention_flags {
13 	RX_ATTENTION_FLAGS_FIRST_MPDU          = BIT(0),
14 	RX_ATTENTION_FLAGS_LAST_MPDU           = BIT(1),
15 	RX_ATTENTION_FLAGS_MCAST_BCAST         = BIT(2),
16 	RX_ATTENTION_FLAGS_PEER_IDX_INVALID    = BIT(3),
17 	RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT    = BIT(4),
18 	RX_ATTENTION_FLAGS_POWER_MGMT          = BIT(5),
19 	RX_ATTENTION_FLAGS_NON_QOS             = BIT(6),
20 	RX_ATTENTION_FLAGS_NULL_DATA           = BIT(7),
21 	RX_ATTENTION_FLAGS_MGMT_TYPE           = BIT(8),
22 	RX_ATTENTION_FLAGS_CTRL_TYPE           = BIT(9),
23 	RX_ATTENTION_FLAGS_MORE_DATA           = BIT(10),
24 	RX_ATTENTION_FLAGS_EOSP                = BIT(11),
25 	RX_ATTENTION_FLAGS_U_APSD_TRIGGER      = BIT(12),
26 	RX_ATTENTION_FLAGS_FRAGMENT            = BIT(13),
27 	RX_ATTENTION_FLAGS_ORDER               = BIT(14),
28 	RX_ATTENTION_FLAGS_CLASSIFICATION      = BIT(15),
29 	RX_ATTENTION_FLAGS_OVERFLOW_ERR        = BIT(16),
30 	RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR     = BIT(17),
31 	RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18),
32 	RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL      = BIT(19),
33 	RX_ATTENTION_FLAGS_SA_IDX_INVALID      = BIT(20),
34 	RX_ATTENTION_FLAGS_DA_IDX_INVALID      = BIT(21),
35 	RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT      = BIT(22),
36 	RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT      = BIT(23),
37 	RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED    = BIT(24),
38 	RX_ATTENTION_FLAGS_DIRECTED            = BIT(25),
39 	RX_ATTENTION_FLAGS_BUFFER_FRAGMENT     = BIT(26),
40 	RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR     = BIT(27),
41 	RX_ATTENTION_FLAGS_TKIP_MIC_ERR        = BIT(28),
42 	RX_ATTENTION_FLAGS_DECRYPT_ERR         = BIT(29),
43 	RX_ATTENTION_FLAGS_FCS_ERR             = BIT(30),
44 	RX_ATTENTION_FLAGS_MSDU_DONE           = BIT(31),
45 };
46 
47 struct rx_attention {
48 	__le32 flags; /* %RX_ATTENTION_FLAGS_ */
49 } __packed;
50 
51 /*
52  * first_mpdu
53  *		Indicates the first MSDU of the PPDU.  If both first_mpdu
54  *		and last_mpdu are set in the MSDU then this is a not an
55  *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
56  *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
57  *		0.  The PPDU start status will only be valid when this bit
58  *		is set.
59  *
60  * last_mpdu
61  *		Indicates the last MSDU of the last MPDU of the PPDU.  The
62  *		PPDU end status will only be valid when this bit is set.
63  *
64  * mcast_bcast
65  *		Multicast / broadcast indicator.  Only set when the MAC
66  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
67  *		matches one of the 4 BSSID registers. Only set when
68  *		first_msdu is set.
69  *
70  * peer_idx_invalid
71  *		Indicates no matching entries within the max search
72  *		count.  Only set when first_msdu is set.
73  *
74  * peer_idx_timeout
75  *		Indicates an unsuccessful search for the peer index due to
76  *		timeout.  Only set when first_msdu is set.
77  *
78  * power_mgmt
79  *		Power management bit set in the 802.11 header.  Only set
80  *		when first_msdu is set.
81  *
82  * non_qos
83  *		Set if packet is not a non-QoS data frame.  Only set when
84  *		first_msdu is set.
85  *
86  * null_data
87  *		Set if frame type indicates either null data or QoS null
88  *		data format.  Only set when first_msdu is set.
89  *
90  * mgmt_type
91  *		Set if packet is a management packet.  Only set when
92  *		first_msdu is set.
93  *
94  * ctrl_type
95  *		Set if packet is a control packet.  Only set when first_msdu
96  *		is set.
97  *
98  * more_data
99  *		Set if more bit in frame control is set.  Only set when
100  *		first_msdu is set.
101  *
102  * eosp
103  *		Set if the EOSP (end of service period) bit in the QoS
104  *		control field is set.  Only set when first_msdu is set.
105  *
106  * u_apsd_trigger
107  *		Set if packet is U-APSD trigger.  Key table will have bits
108  *		per TID to indicate U-APSD trigger.
109  *
110  * fragment
111  *		Indicates that this is an 802.11 fragment frame.  This is
112  *		set when either the more_frag bit is set in the frame
113  *		control or the fragment number is not zero.  Only set when
114  *		first_msdu is set.
115  *
116  * order
117  *		Set if the order bit in the frame control is set.  Only set
118  *		when first_msdu is set.
119  *
120  * classification
121  *		Indicates that this status has a corresponding MSDU that
122  *		requires FW processing.  The OLE will have classification
123  *		ring mask registers which will indicate the ring(s) for
124  *		packets and descriptors which need FW attention.
125  *
126  * overflow_err
127  *		PCU Receive FIFO does not have enough space to store the
128  *		full receive packet.  Enough space is reserved in the
129  *		receive FIFO for the status is written.  This MPDU remaining
130  *		packets in the PPDU will be filtered and no Ack response
131  *		will be transmitted.
132  *
133  * msdu_length_err
134  *		Indicates that the MSDU length from the 802.3 encapsulated
135  *		length field extends beyond the MPDU boundary.
136  *
137  * tcp_udp_chksum_fail
138  *		Indicates that the computed checksum (tcp_udp_chksum) did
139  *		not match the checksum in the TCP/UDP header.
140  *
141  * ip_chksum_fail
142  *		Indicates that the computed checksum did not match the
143  *		checksum in the IP header.
144  *
145  * sa_idx_invalid
146  *		Indicates no matching entry was found in the address search
147  *		table for the source MAC address.
148  *
149  * da_idx_invalid
150  *		Indicates no matching entry was found in the address search
151  *		table for the destination MAC address.
152  *
153  * sa_idx_timeout
154  *		Indicates an unsuccessful search for the source MAC address
155  *		due to the expiring of the search timer.
156  *
157  * da_idx_timeout
158  *		Indicates an unsuccessful search for the destination MAC
159  *		address due to the expiring of the search timer.
160  *
161  * encrypt_required
162  *		Indicates that this data type frame is not encrypted even if
163  *		the policy for this MPDU requires encryption as indicated in
164  *		the peer table key type.
165  *
166  * directed
167  *		MPDU is a directed packet which means that the RA matched
168  *		our STA addresses.  In proxySTA it means that the TA matched
169  *		an entry in our address search table with the corresponding
170  *		'no_ack' bit is the address search entry cleared.
171  *
172  * buffer_fragment
173  *		Indicates that at least one of the rx buffers has been
174  *		fragmented.  If set the FW should look at the rx_frag_info
175  *		descriptor described below.
176  *
177  * mpdu_length_err
178  *		Indicates that the MPDU was pre-maturely terminated
179  *		resulting in a truncated MPDU.  Don't trust the MPDU length
180  *		field.
181  *
182  * tkip_mic_err
183  *		Indicates that the MPDU Michael integrity check failed
184  *
185  * decrypt_err
186  *		Indicates that the MPDU decrypt integrity check failed
187  *
188  * fcs_err
189  *		Indicates that the MPDU FCS check failed
190  *
191  * msdu_done
192  *		If set indicates that the RX packet data, RX header data, RX
193  *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
194  *		start/end descriptors and RX Attention descriptor are all
195  *		valid.  This bit must be in the last octet of the
196  *		descriptor.
197  */
198 
199 struct rx_frag_info_common {
200 	u8 ring0_more_count;
201 	u8 ring1_more_count;
202 	u8 ring2_more_count;
203 	u8 ring3_more_count;
204 } __packed;
205 
206 struct rx_frag_info_wcn3990 {
207 	u8 ring4_more_count;
208 	u8 ring5_more_count;
209 	u8 ring6_more_count;
210 	u8 ring7_more_count;
211 } __packed;
212 
213 struct rx_frag_info {
214 	struct rx_frag_info_common common;
215 	union {
216 		struct rx_frag_info_wcn3990 wcn3990;
217 	} __packed;
218 } __packed;
219 
220 struct rx_frag_info_v1 {
221 	struct rx_frag_info_common common;
222 } __packed;
223 
224 /*
225  * ring0_more_count
226  *		Indicates the number of more buffers associated with RX DMA
227  *		ring 0.  Field is filled in by the RX_DMA.
228  *
229  * ring1_more_count
230  *		Indicates the number of more buffers associated with RX DMA
231  *		ring 1. Field is filled in by the RX_DMA.
232  *
233  * ring2_more_count
234  *		Indicates the number of more buffers associated with RX DMA
235  *		ring 2. Field is filled in by the RX_DMA.
236  *
237  * ring3_more_count
238  *		Indicates the number of more buffers associated with RX DMA
239  *		ring 3. Field is filled in by the RX_DMA.
240  */
241 
242 enum htt_rx_mpdu_encrypt_type {
243 	HTT_RX_MPDU_ENCRYPT_WEP40            = 0,
244 	HTT_RX_MPDU_ENCRYPT_WEP104           = 1,
245 	HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2,
246 	HTT_RX_MPDU_ENCRYPT_WEP128           = 3,
247 	HTT_RX_MPDU_ENCRYPT_TKIP_WPA         = 4,
248 	HTT_RX_MPDU_ENCRYPT_WAPI             = 5,
249 	HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2     = 6,
250 	HTT_RX_MPDU_ENCRYPT_NONE             = 7,
251 	HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2  = 8,
252 	HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2    = 9,
253 	HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10,
254 };
255 
256 #define RX_MPDU_START_INFO0_PEER_IDX_MASK     0x000007ff
257 #define RX_MPDU_START_INFO0_PEER_IDX_LSB      0
258 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK      0x0fff0000
259 #define RX_MPDU_START_INFO0_SEQ_NUM_LSB       16
260 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
261 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB  28
262 #define RX_MPDU_START_INFO0_FROM_DS           BIT(11)
263 #define RX_MPDU_START_INFO0_TO_DS             BIT(12)
264 #define RX_MPDU_START_INFO0_ENCRYPTED         BIT(13)
265 #define RX_MPDU_START_INFO0_RETRY             BIT(14)
266 #define RX_MPDU_START_INFO0_TXBF_H_INFO       BIT(15)
267 
268 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
269 #define RX_MPDU_START_INFO1_TID_LSB  28
270 #define RX_MPDU_START_INFO1_DIRECTED BIT(16)
271 
272 struct rx_mpdu_start {
273 	__le32 info0;
274 	union {
275 		struct {
276 			__le32 pn31_0;
277 			__le32 info1; /* %RX_MPDU_START_INFO1_ */
278 		} __packed;
279 		struct {
280 			u8 pn[6];
281 		} __packed;
282 	} __packed;
283 } __packed;
284 
285 /*
286  * peer_idx
287  *		The index of the address search table which associated with
288  *		the peer table entry corresponding to this MPDU.  Only valid
289  *		when first_msdu is set.
290  *
291  * fr_ds
292  *		Set if the from DS bit is set in the frame control.  Only
293  *		valid when first_msdu is set.
294  *
295  * to_ds
296  *		Set if the to DS bit is set in the frame control.  Only
297  *		valid when first_msdu is set.
298  *
299  * encrypted
300  *		Protected bit from the frame control.  Only valid when
301  *		first_msdu is set.
302  *
303  * retry
304  *		Retry bit from the frame control.  Only valid when
305  *		first_msdu is set.
306  *
307  * txbf_h_info
308  *		The MPDU data will contain H information.  Primarily used
309  *		for debug.
310  *
311  * seq_num
312  *		The sequence number from the 802.11 header.  Only valid when
313  *		first_msdu is set.
314  *
315  * encrypt_type
316  *		Indicates type of decrypt cipher used (as defined in the
317  *		peer table)
318  *		0: WEP40
319  *		1: WEP104
320  *		2: TKIP without MIC
321  *		3: WEP128
322  *		4: TKIP (WPA)
323  *		5: WAPI
324  *		6: AES-CCM (WPA2)
325  *		7: No cipher
326  *		Only valid when first_msdu_is set
327  *
328  * pn_31_0
329  *		Bits [31:0] of the PN number extracted from the IV field
330  *		WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0] is
331  *		valid.
332  *		TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
333  *		WEPSeed[1], pn1}.  Only pn[47:0] is valid.
334  *		AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
335  *		pn0}.  Only pn[47:0] is valid.
336  *		WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
337  *		pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}.
338  *		The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and
339  *		pn[47:0] are valid.
340  *		Only valid when first_msdu is set.
341  *
342  * pn_47_32
343  *		Bits [47:32] of the PN number.   See description for
344  *		pn_31_0.  The remaining PN fields are in the rx_msdu_end
345  *		descriptor
346  *
347  * pn
348  *		Use this field to access the pn without worrying about
349  *		byte-order and bitmasking/bitshifting.
350  *
351  * directed
352  *		See definition in RX attention descriptor
353  *
354  * reserved_2
355  *		Reserved: HW should fill with zero.  FW should ignore.
356  *
357  * tid
358  *		The TID field in the QoS control field
359  */
360 
361 #define RX_MPDU_END_INFO0_RESERVED_0_MASK     0x00001fff
362 #define RX_MPDU_END_INFO0_RESERVED_0_LSB      0
363 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
364 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB  16
365 #define RX_MPDU_END_INFO0_OVERFLOW_ERR        BIT(13)
366 #define RX_MPDU_END_INFO0_LAST_MPDU           BIT(14)
367 #define RX_MPDU_END_INFO0_POST_DELIM_ERR      BIT(15)
368 #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR     BIT(28)
369 #define RX_MPDU_END_INFO0_TKIP_MIC_ERR        BIT(29)
370 #define RX_MPDU_END_INFO0_DECRYPT_ERR         BIT(30)
371 #define RX_MPDU_END_INFO0_FCS_ERR             BIT(31)
372 
373 struct rx_mpdu_end {
374 	__le32 info0;
375 } __packed;
376 
377 /*
378  * reserved_0
379  *		Reserved
380  *
381  * overflow_err
382  *		PCU Receive FIFO does not have enough space to store the
383  *		full receive packet.  Enough space is reserved in the
384  *		receive FIFO for the status is written.  This MPDU remaining
385  *		packets in the PPDU will be filtered and no Ack response
386  *		will be transmitted.
387  *
388  * last_mpdu
389  *		Indicates that this is the last MPDU of a PPDU.
390  *
391  * post_delim_err
392  *		Indicates that a delimiter FCS error occurred after this
393  *		MPDU before the next MPDU.  Only valid when last_msdu is
394  *		set.
395  *
396  * post_delim_cnt
397  *		Count of the delimiters after this MPDU.  This requires the
398  *		last MPDU to be held until all the EOF descriptors have been
399  *		received.  This may be inefficient in the future when
400  *		ML-MIMO is used.  Only valid when last_mpdu is set.
401  *
402  * mpdu_length_err
403  *		See definition in RX attention descriptor
404  *
405  * tkip_mic_err
406  *		See definition in RX attention descriptor
407  *
408  * decrypt_err
409  *		See definition in RX attention descriptor
410  *
411  * fcs_err
412  *		See definition in RX attention descriptor
413  */
414 
415 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK    0x00003fff
416 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB     0
417 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK      0x000fc000
418 #define RX_MSDU_START_INFO0_IP_OFFSET_LSB       14
419 #define RX_MSDU_START_INFO0_RING_MASK_MASK      0x00f00000
420 #define RX_MSDU_START_INFO0_RING_MASK_LSB       20
421 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
422 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB  24
423 
424 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK    0x000000ff
425 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB     0
426 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK   0x00000300
427 #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB    8
428 #define RX_MSDU_START_INFO1_SA_IDX_MASK         0x07ff0000
429 #define RX_MSDU_START_INFO1_SA_IDX_LSB          16
430 #define RX_MSDU_START_INFO1_IPV4_PROTO          BIT(10)
431 #define RX_MSDU_START_INFO1_IPV6_PROTO          BIT(11)
432 #define RX_MSDU_START_INFO1_TCP_PROTO           BIT(12)
433 #define RX_MSDU_START_INFO1_UDP_PROTO           BIT(13)
434 #define RX_MSDU_START_INFO1_IP_FRAG             BIT(14)
435 #define RX_MSDU_START_INFO1_TCP_ONLY_ACK        BIT(15)
436 
437 #define RX_MSDU_START_INFO2_DA_IDX_MASK         0x000007ff
438 #define RX_MSDU_START_INFO2_DA_IDX_LSB          0
439 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000
440 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB  16
441 #define RX_MSDU_START_INFO2_DA_BCAST_MCAST      BIT(11)
442 
443 /* The decapped header (rx_hdr_status) contains the following:
444  *  a) 802.11 header
445  *  [padding to 4 bytes]
446  *  b) HW crypto parameter
447  *     - 0 bytes for no security
448  *     - 4 bytes for WEP
449  *     - 8 bytes for TKIP, AES
450  *  [padding to 4 bytes]
451  *  c) A-MSDU subframe header (14 bytes) if appliable
452  *  d) LLC/SNAP (RFC1042, 8 bytes)
453  *
454  * In case of A-MSDU only first frame in sequence contains (a) and (b).
455  */
456 enum rx_msdu_decap_format {
457 	RX_MSDU_DECAP_RAW = 0,
458 
459 	/* Note: QoS frames are reported as non-QoS. The rx_hdr_status in
460 	 * htt_rx_desc contains the original decapped 802.11 header.
461 	 */
462 	RX_MSDU_DECAP_NATIVE_WIFI = 1,
463 
464 	/* Payload contains an ethernet header (struct ethhdr). */
465 	RX_MSDU_DECAP_ETHERNET2_DIX = 2,
466 
467 	/* Payload contains two 48-bit addresses and 2-byte length (14 bytes
468 	 * total), followed by an RFC1042 header (8 bytes).
469 	 */
470 	RX_MSDU_DECAP_8023_SNAP_LLC = 3
471 };
472 
473 struct rx_msdu_start_common {
474 	__le32 info0; /* %RX_MSDU_START_INFO0_ */
475 	__le32 flow_id_crc;
476 	__le32 info1; /* %RX_MSDU_START_INFO1_ */
477 } __packed;
478 
479 struct rx_msdu_start_qca99x0 {
480 	__le32 info2; /* %RX_MSDU_START_INFO2_ */
481 } __packed;
482 
483 struct rx_msdu_start_wcn3990 {
484 	__le32 info2; /* %RX_MSDU_START_INFO2_ */
485 	__le32 info3; /* %RX_MSDU_START_INFO3_ */
486 } __packed;
487 
488 struct rx_msdu_start {
489 	struct rx_msdu_start_common common;
490 	union {
491 		struct rx_msdu_start_wcn3990 wcn3990;
492 	} __packed;
493 } __packed;
494 
495 struct rx_msdu_start_v1 {
496 	struct rx_msdu_start_common common;
497 	union {
498 		struct rx_msdu_start_qca99x0 qca99x0;
499 	} __packed;
500 } __packed;
501 
502 /*
503  * msdu_length
504  *		MSDU length in bytes after decapsulation.  This field is
505  *		still valid for MPDU frames without A-MSDU.  It still
506  *		represents MSDU length after decapsulation
507  *
508  * ip_offset
509  *		Indicates the IP offset in bytes from the start of the
510  *		packet after decapsulation.  Only valid if ipv4_proto or
511  *		ipv6_proto is set.
512  *
513  * ring_mask
514  *		Indicates the destination RX rings for this MSDU.
515  *
516  * tcp_udp_offset
517  *		Indicates the offset in bytes to the start of TCP or UDP
518  *		header from the start of the IP header after decapsulation.
519  *		Only valid if tcp_prot or udp_prot is set.  The value 0
520  *		indicates that the offset is longer than 127 bytes.
521  *
522  * reserved_0c
523  *		Reserved: HW should fill with zero.  FW should ignore.
524  *
525  * flow_id_crc
526  *		The flow_id_crc runs CRC32 on the following information:
527  *		IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
528  *		protocol[7:0]}.
529  *		IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
530  *		next_header[7:0]}
531  *		UDP case: sort_port[15:0], dest_port[15:0]
532  *		TCP case: sort_port[15:0], dest_port[15:0],
533  *		{header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
534  *		{16'b0, urgent_ptr[15:0]}, all options except 32-bit
535  *		timestamp.
536  *
537  * msdu_number
538  *		Indicates the MSDU number within a MPDU.  This value is
539  *		reset to zero at the start of each MPDU.  If the number of
540  *		MSDU exceeds 255 this number will wrap using modulo 256.
541  *
542  * decap_format
543  *		Indicates the format after decapsulation:
544  *		0: RAW: No decapsulation
545  *		1: Native WiFi
546  *		2: Ethernet 2 (DIX)
547  *		3: 802.3 (SNAP/LLC)
548  *
549  * ipv4_proto
550  *		Set if L2 layer indicates IPv4 protocol.
551  *
552  * ipv6_proto
553  *		Set if L2 layer indicates IPv6 protocol.
554  *
555  * tcp_proto
556  *		Set if the ipv4_proto or ipv6_proto are set and the IP
557  *		protocol indicates TCP.
558  *
559  * udp_proto
560  *		Set if the ipv4_proto or ipv6_proto are set and the IP
561  *			protocol indicates UDP.
562  *
563  * ip_frag
564  *		Indicates that either the IP More frag bit is set or IP frag
565  *		number is non-zero.  If set indicates that this is a
566  *		fragmented IP packet.
567  *
568  * tcp_only_ack
569  *		Set if only the TCP Ack bit is set in the TCP flags and if
570  *		the TCP payload is 0.
571  *
572  * sa_idx
573  *		The offset in the address table which matches the MAC source
574  *		address.
575  *
576  * reserved_2b
577  *		Reserved: HW should fill with zero.  FW should ignore.
578  */
579 
580 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
581 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB  0
582 #define RX_MSDU_END_INFO0_FIRST_MSDU                BIT(14)
583 #define RX_MSDU_END_INFO0_LAST_MSDU                 BIT(15)
584 #define RX_MSDU_END_INFO0_MSDU_LIMIT_ERR            BIT(18)
585 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR             BIT(30)
586 #define RX_MSDU_END_INFO0_RESERVED_3B               BIT(31)
587 
588 struct rx_msdu_end_common {
589 	__le16 ip_hdr_cksum;
590 	__le16 tcp_hdr_cksum;
591 	u8 key_id_octet;
592 	u8 classification_filter;
593 	u8 wapi_pn[10];
594 	__le32 info0;
595 } __packed;
596 
597 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK     0x000001ff
598 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB      0
599 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK   0x00001c00
600 #define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB    10
601 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK  0xffff0000
602 #define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB   16
603 #define RX_MSDU_END_INFO1_IRO_ELIGIBLE      BIT(9)
604 
605 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK    0x0000003f
606 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB     0
607 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK    0x00000fc0
608 #define RX_MSDU_END_INFO2_SA_OFFSET_LSB     6
609 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK  0x0003f000
610 #define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB   12
611 
612 struct rx_msdu_end_qca99x0 {
613 	__le32 ipv6_crc;
614 	__le32 tcp_seq_no;
615 	__le32 tcp_ack_no;
616 	__le32 info1;
617 	__le32 info2;
618 } __packed;
619 
620 struct rx_msdu_end_wcn3990 {
621 	__le32 ipv6_crc;
622 	__le32 tcp_seq_no;
623 	__le32 tcp_ack_no;
624 	__le32 info1;
625 	__le32 info2;
626 	__le32 rule_indication_0;
627 	__le32 rule_indication_1;
628 	__le32 rule_indication_2;
629 	__le32 rule_indication_3;
630 } __packed;
631 
632 struct rx_msdu_end {
633 	struct rx_msdu_end_common common;
634 	union {
635 		struct rx_msdu_end_wcn3990 wcn3990;
636 	} __packed;
637 } __packed;
638 
639 struct rx_msdu_end_v1 {
640 	struct rx_msdu_end_common common;
641 	union {
642 		struct rx_msdu_end_qca99x0 qca99x0;
643 	} __packed;
644 } __packed;
645 
646 /*
647  *ip_hdr_chksum
648  *		This can include the IP header checksum or the pseudo header
649  *		checksum used by TCP/UDP checksum.
650  *
651  *tcp_udp_chksum
652  *		The value of the computed TCP/UDP checksum.  A mode bit
653  *		selects whether this checksum is the full checksum or the
654  *		partial checksum which does not include the pseudo header.
655  *
656  *key_id_octet
657  *		The key ID octet from the IV.  Only valid when first_msdu is
658  *		set.
659  *
660  *classification_filter
661  *		Indicates the number classification filter rule
662  *
663  *ext_wapi_pn_63_48
664  *		Extension PN (packet number) which is only used by WAPI.
665  *		This corresponds to WAPI PN bits [63:48] (pn6 and pn7).  The
666  *		WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
667  *		descriptor.
668  *
669  *ext_wapi_pn_95_64
670  *		Extension PN (packet number) which is only used by WAPI.
671  *		This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and
672  *		pn11).
673  *
674  *ext_wapi_pn_127_96
675  *		Extension PN (packet number) which is only used by WAPI.
676  *		This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14,
677  *		pn15).
678  *
679  *reported_mpdu_length
680  *		MPDU length before decapsulation.  Only valid when
681  *		first_msdu is set.  This field is taken directly from the
682  *		length field of the A-MPDU delimiter or the preamble length
683  *		field for non-A-MPDU frames.
684  *
685  *first_msdu
686  *		Indicates the first MSDU of A-MSDU.  If both first_msdu and
687  *		last_msdu are set in the MSDU then this is a non-aggregated
688  *		MSDU frame: normal MPDU.  Interior MSDU in an A-MSDU shall
689  *		have both first_mpdu and last_mpdu bits set to 0.
690  *
691  *last_msdu
692  *		Indicates the last MSDU of the A-MSDU.  MPDU end status is
693  *		only valid when last_msdu is set.
694  *
695  *msdu_limit_error
696  *		Indicates that the MSDU threshold was exceeded and thus
697  *		all the rest of the MSDUs will not be scattered and
698  *		will not be decapsulated but will be received in RAW format
699  *		as a single MSDU buffer.
700  *
701  *reserved_3a
702  *		Reserved: HW should fill with zero.  FW should ignore.
703  *
704  *pre_delim_err
705  *		Indicates that the first delimiter had a FCS failure.  Only
706  *		valid when first_mpdu and first_msdu are set.
707  *
708  *reserved_3b
709  *		Reserved: HW should fill with zero.  FW should ignore.
710  */
711 
712 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY        0x04
713 #define HTT_RX_PPDU_START_PREAMBLE_HT            0x08
714 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF  0x09
715 #define HTT_RX_PPDU_START_PREAMBLE_VHT           0x0C
716 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
717 
718 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0)
719 
720 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK    0x0000000f
721 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB     0
722 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK  0x0001ffe0
723 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB   5
724 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK    0x00fc0000
725 #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB     18
726 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
727 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB  24
728 #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT  BIT(4)
729 #define RX_PPDU_START_INFO1_L_SIG_PARITY       BIT(17)
730 
731 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
732 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB  0
733 
734 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
735 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB  0
736 #define RX_PPDU_START_INFO3_TXBF_H_INFO             BIT(24)
737 
738 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
739 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB  0
740 
741 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
742 #define RX_PPDU_START_INFO5_SERVICE_LSB  0
743 
744 /* No idea what this flag means. It seems to be always set in rate. */
745 #define RX_PPDU_START_RATE_FLAG BIT(3)
746 
747 struct rx_ppdu_start {
748 	struct {
749 		u8 pri20_mhz;
750 		u8 ext20_mhz;
751 		u8 ext40_mhz;
752 		u8 ext80_mhz;
753 	} rssi_chains[4];
754 	u8 rssi_comb;
755 	__le16 rsvd0;
756 	u8 info0; /* %RX_PPDU_START_INFO0_ */
757 	__le32 info1; /* %RX_PPDU_START_INFO1_ */
758 	__le32 info2; /* %RX_PPDU_START_INFO2_ */
759 	__le32 info3; /* %RX_PPDU_START_INFO3_ */
760 	__le32 info4; /* %RX_PPDU_START_INFO4_ */
761 	__le32 info5; /* %RX_PPDU_START_INFO5_ */
762 } __packed;
763 
764 /*
765  * rssi_chain0_pri20
766  *		RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
767  *		Value of 0x80 indicates invalid.
768  *
769  * rssi_chain0_sec20
770  *		RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
771  *		Value of 0x80 indicates invalid.
772  *
773  * rssi_chain0_sec40
774  *		RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
775  *		Value of 0x80 indicates invalid.
776  *
777  * rssi_chain0_sec80
778  *		RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
779  *		Value of 0x80 indicates invalid.
780  *
781  * rssi_chain1_pri20
782  *		RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
783  *		Value of 0x80 indicates invalid.
784  *
785  * rssi_chain1_sec20
786  *		RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
787  *		Value of 0x80 indicates invalid.
788  *
789  * rssi_chain1_sec40
790  *		RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
791  *		Value of 0x80 indicates invalid.
792  *
793  * rssi_chain1_sec80
794  *		RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
795  *		Value of 0x80 indicates invalid.
796  *
797  * rssi_chain2_pri20
798  *		RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
799  *		Value of 0x80 indicates invalid.
800  *
801  * rssi_chain2_sec20
802  *		RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth.
803  *		Value of 0x80 indicates invalid.
804  *
805  * rssi_chain2_sec40
806  *		RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth.
807  *		Value of 0x80 indicates invalid.
808  *
809  * rssi_chain2_sec80
810  *		RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth.
811  *		Value of 0x80 indicates invalid.
812  *
813  * rssi_chain3_pri20
814  *		RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
815  *		Value of 0x80 indicates invalid.
816  *
817  * rssi_chain3_sec20
818  *		RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth.
819  *		Value of 0x80 indicates invalid.
820  *
821  * rssi_chain3_sec40
822  *		RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth.
823  *		Value of 0x80 indicates invalid.
824  *
825  * rssi_chain3_sec80
826  *		RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth.
827  *		Value of 0x80 indicates invalid.
828  *
829  * rssi_comb
830  *		The combined RSSI of RX PPDU of all active chains and
831  *		bandwidths.  Value of 0x80 indicates invalid.
832  *
833  * reserved_4a
834  *		Reserved: HW should fill with 0, FW should ignore.
835  *
836  * is_greenfield
837  *		Do we really support this?
838  *
839  * reserved_4b
840  *		Reserved: HW should fill with 0, FW should ignore.
841  *
842  * l_sig_rate
843  *		If l_sig_rate_select is 0:
844  *		0x8: OFDM 48 Mbps
845  *		0x9: OFDM 24 Mbps
846  *		0xA: OFDM 12 Mbps
847  *		0xB: OFDM 6 Mbps
848  *		0xC: OFDM 54 Mbps
849  *		0xD: OFDM 36 Mbps
850  *		0xE: OFDM 18 Mbps
851  *		0xF: OFDM 9 Mbps
852  *		If l_sig_rate_select is 1:
853  *		0x8: CCK 11 Mbps long preamble
854  *		0x9: CCK 5.5 Mbps long preamble
855  *		0xA: CCK 2 Mbps long preamble
856  *		0xB: CCK 1 Mbps long preamble
857  *		0xC: CCK 11 Mbps short preamble
858  *		0xD: CCK 5.5 Mbps short preamble
859  *		0xE: CCK 2 Mbps short preamble
860  *
861  * l_sig_rate_select
862  *		Legacy signal rate select.  If set then l_sig_rate indicates
863  *		CCK rates.  If clear then l_sig_rate indicates OFDM rates.
864  *
865  * l_sig_length
866  *		Length of legacy frame in octets.
867  *
868  * l_sig_parity
869  *		Odd parity over l_sig_rate and l_sig_length
870  *
871  * l_sig_tail
872  *		Tail bits for Viterbi decoder
873  *
874  * preamble_type
875  *		Indicates the type of preamble ahead:
876  *		0x4: Legacy (OFDM/CCK)
877  *		0x8: HT
878  *		0x9: HT with TxBF
879  *		0xC: VHT
880  *		0xD: VHT with TxBF
881  *		0x80 - 0xFF: Reserved for special baseband data types such
882  *		as radar and spectral scan.
883  *
884  * ht_sig_vht_sig_a_1
885  *		If preamble_type == 0x8 or 0x9
886  *		HT-SIG (first 24 bits)
887  *		If preamble_type == 0xC or 0xD
888  *		VHT-SIG A (first 24 bits)
889  *		Else
890  *		Reserved
891  *
892  * reserved_6
893  *		Reserved: HW should fill with 0, FW should ignore.
894  *
895  * ht_sig_vht_sig_a_2
896  *		If preamble_type == 0x8 or 0x9
897  *		HT-SIG (last 24 bits)
898  *		If preamble_type == 0xC or 0xD
899  *		VHT-SIG A (last 24 bits)
900  *		Else
901  *		Reserved
902  *
903  * txbf_h_info
904  *		Indicates that the packet data carries H information which
905  *		is used for TxBF debug.
906  *
907  * reserved_7
908  *		Reserved: HW should fill with 0, FW should ignore.
909  *
910  * vht_sig_b
911  *		WiFi 1.0 and WiFi 2.0 will likely have this field to be all
912  *		0s since the BB does not plan on decoding VHT SIG-B.
913  *
914  * reserved_8
915  *		Reserved: HW should fill with 0, FW should ignore.
916  *
917  * service
918  *		Service field from BB for OFDM, HT and VHT packets.  CCK
919  *		packets will have service field of 0.
920  *
921  * reserved_9
922  *		Reserved: HW should fill with 0, FW should ignore.
923  */
924 
925 #define RX_PPDU_END_FLAGS_PHY_ERR             BIT(0)
926 #define RX_PPDU_END_FLAGS_RX_LOCATION         BIT(1)
927 #define RX_PPDU_END_FLAGS_TXBF_H_INFO         BIT(2)
928 
929 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK     0x00ffffff
930 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB      0
931 #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24)
932 #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25)
933 
934 #define RX_PPDU_END_INFO1_PEER_IDX_MASK       0x1ffc
935 #define RX_PPDU_END_INFO1_PEER_IDX_LSB        2
936 #define RX_PPDU_END_INFO1_BB_DATA             BIT(0)
937 #define RX_PPDU_END_INFO1_PEER_IDX_VALID      BIT(1)
938 #define RX_PPDU_END_INFO1_PPDU_DONE           BIT(15)
939 
940 struct rx_ppdu_end_common {
941 	__le32 evm_p0;
942 	__le32 evm_p1;
943 	__le32 evm_p2;
944 	__le32 evm_p3;
945 	__le32 evm_p4;
946 	__le32 evm_p5;
947 	__le32 evm_p6;
948 	__le32 evm_p7;
949 	__le32 evm_p8;
950 	__le32 evm_p9;
951 	__le32 evm_p10;
952 	__le32 evm_p11;
953 	__le32 evm_p12;
954 	__le32 evm_p13;
955 	__le32 evm_p14;
956 	__le32 evm_p15;
957 	__le32 tsf_timestamp;
958 	__le32 wb_timestamp;
959 } __packed;
960 
961 struct rx_ppdu_end_qca988x {
962 	u8 locationing_timestamp;
963 	u8 phy_err_code;
964 	__le16 flags; /* %RX_PPDU_END_FLAGS_ */
965 	__le32 info0; /* %RX_PPDU_END_INFO0_ */
966 	__le16 bb_length;
967 	__le16 info1; /* %RX_PPDU_END_INFO1_ */
968 } __packed;
969 
970 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
971 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB  0
972 #define RX_PPDU_END_RTT_UNUSED_MASK            0x7f000000
973 #define RX_PPDU_END_RTT_UNUSED_LSB             24
974 #define RX_PPDU_END_RTT_NORMAL_MODE            BIT(31)
975 
976 struct rx_ppdu_end_qca6174 {
977 	u8 locationing_timestamp;
978 	u8 phy_err_code;
979 	__le16 flags; /* %RX_PPDU_END_FLAGS_ */
980 	__le32 info0; /* %RX_PPDU_END_INFO0_ */
981 	__le32 rtt; /* %RX_PPDU_END_RTT_ */
982 	__le16 bb_length;
983 	__le16 info1; /* %RX_PPDU_END_INFO1_ */
984 } __packed;
985 
986 #define RX_PKT_END_INFO0_RX_SUCCESS              BIT(0)
987 #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX     BIT(3)
988 #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP     BIT(4)
989 #define RX_PKT_END_INFO0_ERR_OFDM_RESTART        BIT(5)
990 #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP      BIT(6)
991 #define RX_PKT_END_INFO0_ERR_CCK_RESTART         BIT(7)
992 
993 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK       0x0001ffff
994 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB        0
995 #define RX_LOCATION_INFO_FAC_STATUS_MASK         0x000c0000
996 #define RX_LOCATION_INFO_FAC_STATUS_LSB          18
997 #define RX_LOCATION_INFO_PKT_BW_MASK             0x00700000
998 #define RX_LOCATION_INFO_PKT_BW_LSB              20
999 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000
1000 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB  23
1001 #define RX_LOCATION_INFO_CIR_STATUS              BIT(17)
1002 #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE       BIT(25)
1003 #define RX_LOCATION_INFO_RTT_TX_DATA_START_X     BIT(26)
1004 #define RX_LOCATION_INFO_HW_IFFT_MODE            BIT(30)
1005 #define RX_LOCATION_INFO_RX_LOCATION_VALID       BIT(31)
1006 
1007 struct rx_pkt_end {
1008 	__le32 info0; /* %RX_PKT_END_INFO0_ */
1009 	__le32 phy_timestamp_1;
1010 	__le32 phy_timestamp_2;
1011 } __packed;
1012 
1013 struct rx_pkt_end_wcn3990 {
1014 	__le32 info0; /* %RX_PKT_END_INFO0_ */
1015 	__le64 phy_timestamp_1;
1016 	__le64 phy_timestamp_2;
1017 } __packed;
1018 
1019 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK		0x00003fff
1020 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB		0
1021 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK		0x1fff8000
1022 #define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB		15
1023 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK	0xc0000000
1024 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB	30
1025 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS		BIT(14)
1026 #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS		BIT(29)
1027 
1028 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK	0x0000000c
1029 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB		2
1030 #define RX_LOCATION_INFO1_PKT_BW_MASK			0x00000030
1031 #define RX_LOCATION_INFO1_PKT_BW_LSB			4
1032 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK		0x0000ff00
1033 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB		8
1034 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK		0x000f0000
1035 #define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB		16
1036 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK		0x00300000
1037 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB		20
1038 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK		0x07c00000
1039 #define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB		22
1040 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK	0x18000000
1041 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB	27
1042 #define RX_LOCATION_INFO1_RTT_CFR_STATUS		BIT(0)
1043 #define RX_LOCATION_INFO1_RTT_CIR_STATUS		BIT(1)
1044 #define RX_LOCATION_INFO1_RTT_GI_TYPE			BIT(7)
1045 #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE		BIT(29)
1046 #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE	BIT(30)
1047 #define RX_LOCATION_INFO1_RX_LOCATION_VALID		BIT(31)
1048 
1049 struct rx_location_info {
1050 	__le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */
1051 	__le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */
1052 } __packed;
1053 
1054 struct rx_location_info_wcn3990 {
1055 	__le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */
1056 	__le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */
1057 	__le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */
1058 } __packed;
1059 
1060 enum rx_phy_ppdu_end_info0 {
1061 	RX_PHY_PPDU_END_INFO0_ERR_RADAR           = BIT(2),
1062 	RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT        = BIT(3),
1063 	RX_PHY_PPDU_END_INFO0_ERR_RX_NAP          = BIT(4),
1064 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING     = BIT(5),
1065 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY     = BIT(6),
1066 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE       = BIT(7),
1067 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH     = BIT(8),
1068 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART    = BIT(9),
1069 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE    = BIT(10),
1070 	RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11),
1071 	RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER     = BIT(12),
1072 	RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING      = BIT(13),
1073 	RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC  = BIT(14),
1074 	RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE        = BIT(15),
1075 	RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH      = BIT(16),
1076 	RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART     = BIT(17),
1077 	RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE     = BIT(18),
1078 	RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP  = BIT(19),
1079 	RX_PHY_PPDU_END_INFO0_ERR_HT_CRC          = BIT(20),
1080 	RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH       = BIT(21),
1081 	RX_PHY_PPDU_END_INFO0_ERR_HT_RATE         = BIT(22),
1082 	RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF          = BIT(23),
1083 	RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24),
1084 	RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD     = BIT(25),
1085 	RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN   = BIT(26),
1086 	RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW       = BIT(27),
1087 	RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28),
1088 	RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC         = BIT(29),
1089 	RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA        = BIT(30),
1090 	RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG        = BIT(31),
1091 };
1092 
1093 enum rx_phy_ppdu_end_info1 {
1094 	RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP            = BIT(0),
1095 	RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM           = BIT(1),
1096 	RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM     = BIT(2),
1097 	RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0    = BIT(3),
1098 	RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4),
1099 	RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63   = BIT(5),
1100 	RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER  = BIT(6),
1101 	RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP          = BIT(7),
1102 	RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT    = BIT(8),
1103 	RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK     = BIT(9),
1104 	RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION       = BIT(10),
1105 	RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK        = BIT(11),
1106 	RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX    = BIT(12),
1107 	RX_PHY_PPDU_END_INFO1_ERR_RX_CBF             = BIT(13),
1108 };
1109 
1110 struct rx_phy_ppdu_end {
1111 	__le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */
1112 	__le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */
1113 } __packed;
1114 
1115 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK          0x00000fff
1116 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB           0
1117 
1118 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK        0x00ffffff
1119 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB         0
1120 #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK          BIT(24)
1121 #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID       BIT(25)
1122 #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID  BIT(26)
1123 #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27)
1124 #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL    BIT(28)
1125 #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC      BIT(29)
1126 #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE       BIT(30)
1127 
1128 struct rx_ppdu_end_qca99x0 {
1129 	struct rx_pkt_end rx_pkt_end;
1130 	__le32 rx_location_info; /* %RX_LOCATION_INFO_ */
1131 	struct rx_phy_ppdu_end rx_phy_ppdu_end;
1132 	__le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */
1133 	__le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */
1134 	__le16 bb_length;
1135 	__le16 info1; /* %RX_PPDU_END_INFO1_ */
1136 } __packed;
1137 
1138 struct rx_ppdu_end_qca9984 {
1139 	struct rx_pkt_end rx_pkt_end;
1140 	struct rx_location_info rx_location_info;
1141 	struct rx_phy_ppdu_end rx_phy_ppdu_end;
1142 	__le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */
1143 	__le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */
1144 	__le16 bb_length;
1145 	__le16 info1; /* %RX_PPDU_END_INFO1_ */
1146 } __packed;
1147 
1148 struct rx_ppdu_end_wcn3990 {
1149 	struct rx_pkt_end_wcn3990 rx_pkt_end;
1150 	struct rx_location_info_wcn3990 rx_location_info;
1151 	struct rx_phy_ppdu_end rx_phy_ppdu_end;
1152 	__le32 rx_timing_offset;
1153 	__le32 reserved_info_0;
1154 	__le32 reserved_info_1;
1155 	__le32 rx_antenna_info;
1156 	__le32 rx_coex_info;
1157 	__le32 rx_mpdu_cnt_info;
1158 	__le64 phy_timestamp_tx;
1159 	__le32 rx_bb_length;
1160 } __packed;
1161 
1162 struct rx_ppdu_end {
1163 	struct rx_ppdu_end_common common;
1164 	union {
1165 		struct rx_ppdu_end_wcn3990 wcn3990;
1166 	} __packed;
1167 } __packed;
1168 
1169 struct rx_ppdu_end_v1 {
1170 	struct rx_ppdu_end_common common;
1171 	union {
1172 		struct rx_ppdu_end_qca988x qca988x;
1173 		struct rx_ppdu_end_qca6174 qca6174;
1174 		struct rx_ppdu_end_qca99x0 qca99x0;
1175 		struct rx_ppdu_end_qca9984 qca9984;
1176 	} __packed;
1177 } __packed;
1178 
1179 /*
1180  * evm_p0
1181  *		EVM for pilot 0.  Contain EVM for streams: 0, 1, 2 and 3.
1182  *
1183  * evm_p1
1184  *		EVM for pilot 1.  Contain EVM for streams: 0, 1, 2 and 3.
1185  *
1186  * evm_p2
1187  *		EVM for pilot 2.  Contain EVM for streams: 0, 1, 2 and 3.
1188  *
1189  * evm_p3
1190  *		EVM for pilot 3.  Contain EVM for streams: 0, 1, 2 and 3.
1191  *
1192  * evm_p4
1193  *		EVM for pilot 4.  Contain EVM for streams: 0, 1, 2 and 3.
1194  *
1195  * evm_p5
1196  *		EVM for pilot 5.  Contain EVM for streams: 0, 1, 2 and 3.
1197  *
1198  * evm_p6
1199  *		EVM for pilot 6.  Contain EVM for streams: 0, 1, 2 and 3.
1200  *
1201  * evm_p7
1202  *		EVM for pilot 7.  Contain EVM for streams: 0, 1, 2 and 3.
1203  *
1204  * evm_p8
1205  *		EVM for pilot 8.  Contain EVM for streams: 0, 1, 2 and 3.
1206  *
1207  * evm_p9
1208  *		EVM for pilot 9.  Contain EVM for streams: 0, 1, 2 and 3.
1209  *
1210  * evm_p10
1211  *		EVM for pilot 10.  Contain EVM for streams: 0, 1, 2 and 3.
1212  *
1213  * evm_p11
1214  *		EVM for pilot 11.  Contain EVM for streams: 0, 1, 2 and 3.
1215  *
1216  * evm_p12
1217  *		EVM for pilot 12.  Contain EVM for streams: 0, 1, 2 and 3.
1218  *
1219  * evm_p13
1220  *		EVM for pilot 13.  Contain EVM for streams: 0, 1, 2 and 3.
1221  *
1222  * evm_p14
1223  *		EVM for pilot 14.  Contain EVM for streams: 0, 1, 2 and 3.
1224  *
1225  * evm_p15
1226  *		EVM for pilot 15.  Contain EVM for streams: 0, 1, 2 and 3.
1227  *
1228  * tsf_timestamp
1229  *		Receive TSF timestamp sampled on the rising edge of
1230  *		rx_clear.  For PHY errors this may be the current TSF when
1231  *		phy_error is asserted if the rx_clear does not assert before
1232  *		the end of the PHY error.
1233  *
1234  * wb_timestamp
1235  *		WLAN/BT timestamp is a 1 usec resolution timestamp which
1236  *		does not get updated based on receive beacon like TSF.  The
1237  *		same rules for capturing tsf_timestamp are used to capture
1238  *		the wb_timestamp.
1239  *
1240  * locationing_timestamp
1241  *		Timestamp used for locationing.  This timestamp is used to
1242  *		indicate fractions of usec.  For example if the MAC clock is
1243  *		running at 80 MHz, the timestamp will increment every 12.5
1244  *		nsec.  The value starts at 0 and increments to 79 and
1245  *		returns to 0 and repeats.  This information is valid for
1246  *		every PPDU.  This information can be used in conjunction
1247  *		with wb_timestamp to capture large delta times.
1248  *
1249  * phy_err_code
1250  *		See the 1.10.8.1.2 for the list of the PHY error codes.
1251  *
1252  * phy_err
1253  *		Indicates a PHY error was detected for this PPDU.
1254  *
1255  * rx_location
1256  *		Indicates that location information was requested.
1257  *
1258  * txbf_h_info
1259  *		Indicates that the packet data carries H information which
1260  *		is used for TxBF debug.
1261  *
1262  * reserved_18
1263  *		Reserved: HW should fill with 0, FW should ignore.
1264  *
1265  * rx_antenna
1266  *		Receive antenna value
1267  *
1268  * tx_ht_vht_ack
1269  *		Indicates that a HT or VHT Ack/BA frame was transmitted in
1270  *		response to this receive packet.
1271  *
1272  * bb_captured_channel
1273  *		Indicates that the BB has captured a channel dump.  FW can
1274  *		then read the channel dump memory.  This may indicate that
1275  *		the channel was captured either based on PCU setting the
1276  *		capture_channel bit  BB descriptor or FW setting the
1277  *		capture_channel mode bit.
1278  *
1279  * reserved_19
1280  *		Reserved: HW should fill with 0, FW should ignore.
1281  *
1282  * bb_length
1283  *		Indicates the number of bytes of baseband information for
1284  *		PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1285  *		which indicates that this is not a normal PPDU but rather
1286  *		contains baseband debug information.
1287  *
1288  * reserved_20
1289  *		Reserved: HW should fill with 0, FW should ignore.
1290  *
1291  * ppdu_done
1292  *		PPDU end status is only valid when ppdu_done bit is set.
1293  *		Every time HW sets this bit in memory FW/SW must clear this
1294  *		bit in memory.  FW will initialize all the ppdu_done dword
1295  *		to 0.
1296  */
1297 
1298 #define FW_RX_DESC_INFO0_DISCARD  BIT(0)
1299 #define FW_RX_DESC_INFO0_FORWARD  BIT(1)
1300 #define FW_RX_DESC_INFO0_INSPECT  BIT(5)
1301 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1302 #define FW_RX_DESC_INFO0_EXT_LSB  6
1303 
1304 struct fw_rx_desc_base {
1305 	u8 info0;
1306 } __packed;
1307 
1308 #define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0)
1309 #define FW_RX_DESC_FLAGS_LAST_MSDU  (1 << 1)
1310 #define FW_RX_DESC_C3_FAILED        (1 << 2)
1311 #define FW_RX_DESC_C4_FAILED        (1 << 3)
1312 #define FW_RX_DESC_IPV6             (1 << 4)
1313 #define FW_RX_DESC_TCP              (1 << 5)
1314 #define FW_RX_DESC_UDP              (1 << 6)
1315 
1316 struct fw_rx_desc_hl {
1317 	union {
1318 		struct {
1319 		u8 discard:1,
1320 		   forward:1,
1321 		   any_err:1,
1322 		   dup_err:1,
1323 		   reserved:1,
1324 		   inspect:1,
1325 		   extension:2;
1326 		} bits;
1327 		u8 info0;
1328 	} u;
1329 
1330 	u8 version;
1331 	u8 len;
1332 	u8 flags;
1333 } __packed;
1334 
1335 #endif /* _RX_DESC_H_ */
1336