1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _RX_DESC_H_ 19 #define _RX_DESC_H_ 20 21 enum rx_attention_flags { 22 RX_ATTENTION_FLAGS_FIRST_MPDU = 1 << 0, 23 RX_ATTENTION_FLAGS_LAST_MPDU = 1 << 1, 24 RX_ATTENTION_FLAGS_MCAST_BCAST = 1 << 2, 25 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = 1 << 3, 26 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = 1 << 4, 27 RX_ATTENTION_FLAGS_POWER_MGMT = 1 << 5, 28 RX_ATTENTION_FLAGS_NON_QOS = 1 << 6, 29 RX_ATTENTION_FLAGS_NULL_DATA = 1 << 7, 30 RX_ATTENTION_FLAGS_MGMT_TYPE = 1 << 8, 31 RX_ATTENTION_FLAGS_CTRL_TYPE = 1 << 9, 32 RX_ATTENTION_FLAGS_MORE_DATA = 1 << 10, 33 RX_ATTENTION_FLAGS_EOSP = 1 << 11, 34 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = 1 << 12, 35 RX_ATTENTION_FLAGS_FRAGMENT = 1 << 13, 36 RX_ATTENTION_FLAGS_ORDER = 1 << 14, 37 RX_ATTENTION_FLAGS_CLASSIFICATION = 1 << 15, 38 RX_ATTENTION_FLAGS_OVERFLOW_ERR = 1 << 16, 39 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = 1 << 17, 40 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = 1 << 18, 41 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = 1 << 19, 42 RX_ATTENTION_FLAGS_SA_IDX_INVALID = 1 << 20, 43 RX_ATTENTION_FLAGS_DA_IDX_INVALID = 1 << 21, 44 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = 1 << 22, 45 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = 1 << 23, 46 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = 1 << 24, 47 RX_ATTENTION_FLAGS_DIRECTED = 1 << 25, 48 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = 1 << 26, 49 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = 1 << 27, 50 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = 1 << 28, 51 RX_ATTENTION_FLAGS_DECRYPT_ERR = 1 << 29, 52 RX_ATTENTION_FLAGS_FCS_ERR = 1 << 30, 53 RX_ATTENTION_FLAGS_MSDU_DONE = 1 << 31, 54 }; 55 56 struct rx_attention { 57 __le32 flags; /* %RX_ATTENTION_FLAGS_ */ 58 } __packed; 59 60 /* 61 * first_mpdu 62 * Indicates the first MSDU of the PPDU. If both first_mpdu 63 * and last_mpdu are set in the MSDU then this is a not an 64 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 65 * A-MPDU shall have both first_mpdu and last_mpdu bits set to 66 * 0. The PPDU start status will only be valid when this bit 67 * is set. 68 * 69 * last_mpdu 70 * Indicates the last MSDU of the last MPDU of the PPDU. The 71 * PPDU end status will only be valid when this bit is set. 72 * 73 * mcast_bcast 74 * Multicast / broadcast indicator. Only set when the MAC 75 * address 1 bit 0 is set indicating mcast/bcast and the BSSID 76 * matches one of the 4 BSSID registers. Only set when 77 * first_msdu is set. 78 * 79 * peer_idx_invalid 80 * Indicates no matching entries within the the max search 81 * count. Only set when first_msdu is set. 82 * 83 * peer_idx_timeout 84 * Indicates an unsuccessful search for the peer index due to 85 * timeout. Only set when first_msdu is set. 86 * 87 * power_mgmt 88 * Power management bit set in the 802.11 header. Only set 89 * when first_msdu is set. 90 * 91 * non_qos 92 * Set if packet is not a non-QoS data frame. Only set when 93 * first_msdu is set. 94 * 95 * null_data 96 * Set if frame type indicates either null data or QoS null 97 * data format. Only set when first_msdu is set. 98 * 99 * mgmt_type 100 * Set if packet is a management packet. Only set when 101 * first_msdu is set. 102 * 103 * ctrl_type 104 * Set if packet is a control packet. Only set when first_msdu 105 * is set. 106 * 107 * more_data 108 * Set if more bit in frame control is set. Only set when 109 * first_msdu is set. 110 * 111 * eosp 112 * Set if the EOSP (end of service period) bit in the QoS 113 * control field is set. Only set when first_msdu is set. 114 * 115 * u_apsd_trigger 116 * Set if packet is U-APSD trigger. Key table will have bits 117 * per TID to indicate U-APSD trigger. 118 * 119 * fragment 120 * Indicates that this is an 802.11 fragment frame. This is 121 * set when either the more_frag bit is set in the frame 122 * control or the fragment number is not zero. Only set when 123 * first_msdu is set. 124 * 125 * order 126 * Set if the order bit in the frame control is set. Only set 127 * when first_msdu is set. 128 * 129 * classification 130 * Indicates that this status has a corresponding MSDU that 131 * requires FW processing. The OLE will have classification 132 * ring mask registers which will indicate the ring(s) for 133 * packets and descriptors which need FW attention. 134 * 135 * overflow_err 136 * PCU Receive FIFO does not have enough space to store the 137 * full receive packet. Enough space is reserved in the 138 * receive FIFO for the status is written. This MPDU remaining 139 * packets in the PPDU will be filtered and no Ack response 140 * will be transmitted. 141 * 142 * msdu_length_err 143 * Indicates that the MSDU length from the 802.3 encapsulated 144 * length field extends beyond the MPDU boundary. 145 * 146 * tcp_udp_chksum_fail 147 * Indicates that the computed checksum (tcp_udp_chksum) did 148 * not match the checksum in the TCP/UDP header. 149 * 150 * ip_chksum_fail 151 * Indicates that the computed checksum did not match the 152 * checksum in the IP header. 153 * 154 * sa_idx_invalid 155 * Indicates no matching entry was found in the address search 156 * table for the source MAC address. 157 * 158 * da_idx_invalid 159 * Indicates no matching entry was found in the address search 160 * table for the destination MAC address. 161 * 162 * sa_idx_timeout 163 * Indicates an unsuccessful search for the source MAC address 164 * due to the expiring of the search timer. 165 * 166 * da_idx_timeout 167 * Indicates an unsuccessful search for the destination MAC 168 * address due to the expiring of the search timer. 169 * 170 * encrypt_required 171 * Indicates that this data type frame is not encrypted even if 172 * the policy for this MPDU requires encryption as indicated in 173 * the peer table key type. 174 * 175 * directed 176 * MPDU is a directed packet which means that the RA matched 177 * our STA addresses. In proxySTA it means that the TA matched 178 * an entry in our address search table with the corresponding 179 * 'no_ack' bit is the address search entry cleared. 180 * 181 * buffer_fragment 182 * Indicates that at least one of the rx buffers has been 183 * fragmented. If set the FW should look at the rx_frag_info 184 * descriptor described below. 185 * 186 * mpdu_length_err 187 * Indicates that the MPDU was pre-maturely terminated 188 * resulting in a truncated MPDU. Don't trust the MPDU length 189 * field. 190 * 191 * tkip_mic_err 192 * Indicates that the MPDU Michael integrity check failed 193 * 194 * decrypt_err 195 * Indicates that the MPDU decrypt integrity check failed 196 * 197 * fcs_err 198 * Indicates that the MPDU FCS check failed 199 * 200 * msdu_done 201 * If set indicates that the RX packet data, RX header data, RX 202 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 203 * start/end descriptors and RX Attention descriptor are all 204 * valid. This bit must be in the last octet of the 205 * descriptor. 206 */ 207 208 struct rx_frag_info { 209 u8 ring0_more_count; 210 u8 ring1_more_count; 211 u8 ring2_more_count; 212 u8 ring3_more_count; 213 u8 ring4_more_count; 214 u8 ring5_more_count; 215 u8 ring6_more_count; 216 u8 ring7_more_count; 217 } __packed; 218 219 /* 220 * ring0_more_count 221 * Indicates the number of more buffers associated with RX DMA 222 * ring 0. Field is filled in by the RX_DMA. 223 * 224 * ring1_more_count 225 * Indicates the number of more buffers associated with RX DMA 226 * ring 1. Field is filled in by the RX_DMA. 227 * 228 * ring2_more_count 229 * Indicates the number of more buffers associated with RX DMA 230 * ring 2. Field is filled in by the RX_DMA. 231 * 232 * ring3_more_count 233 * Indicates the number of more buffers associated with RX DMA 234 * ring 3. Field is filled in by the RX_DMA. 235 */ 236 237 enum htt_rx_mpdu_encrypt_type { 238 HTT_RX_MPDU_ENCRYPT_WEP40 = 0, 239 HTT_RX_MPDU_ENCRYPT_WEP104 = 1, 240 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2, 241 HTT_RX_MPDU_ENCRYPT_WEP128 = 3, 242 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4, 243 HTT_RX_MPDU_ENCRYPT_WAPI = 5, 244 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6, 245 HTT_RX_MPDU_ENCRYPT_NONE = 7, 246 HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2 = 8, 247 HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2 = 9, 248 HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10, 249 }; 250 251 #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff 252 #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0 253 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000 254 #define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16 255 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000 256 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28 257 #define RX_MPDU_START_INFO0_FROM_DS (1 << 11) 258 #define RX_MPDU_START_INFO0_TO_DS (1 << 12) 259 #define RX_MPDU_START_INFO0_ENCRYPTED (1 << 13) 260 #define RX_MPDU_START_INFO0_RETRY (1 << 14) 261 #define RX_MPDU_START_INFO0_TXBF_H_INFO (1 << 15) 262 263 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000 264 #define RX_MPDU_START_INFO1_TID_LSB 28 265 #define RX_MPDU_START_INFO1_DIRECTED (1 << 16) 266 267 struct rx_mpdu_start { 268 __le32 info0; 269 union { 270 struct { 271 __le32 pn31_0; 272 __le32 info1; /* %RX_MPDU_START_INFO1_ */ 273 } __packed; 274 struct { 275 u8 pn[6]; 276 } __packed; 277 } __packed; 278 } __packed; 279 280 /* 281 * peer_idx 282 * The index of the address search table which associated with 283 * the peer table entry corresponding to this MPDU. Only valid 284 * when first_msdu is set. 285 * 286 * fr_ds 287 * Set if the from DS bit is set in the frame control. Only 288 * valid when first_msdu is set. 289 * 290 * to_ds 291 * Set if the to DS bit is set in the frame control. Only 292 * valid when first_msdu is set. 293 * 294 * encrypted 295 * Protected bit from the frame control. Only valid when 296 * first_msdu is set. 297 * 298 * retry 299 * Retry bit from the frame control. Only valid when 300 * first_msdu is set. 301 * 302 * txbf_h_info 303 * The MPDU data will contain H information. Primarily used 304 * for debug. 305 * 306 * seq_num 307 * The sequence number from the 802.11 header. Only valid when 308 * first_msdu is set. 309 * 310 * encrypt_type 311 * Indicates type of decrypt cipher used (as defined in the 312 * peer table) 313 * 0: WEP40 314 * 1: WEP104 315 * 2: TKIP without MIC 316 * 3: WEP128 317 * 4: TKIP (WPA) 318 * 5: WAPI 319 * 6: AES-CCM (WPA2) 320 * 7: No cipher 321 * Only valid when first_msdu_is set 322 * 323 * pn_31_0 324 * Bits [31:0] of the PN number extracted from the IV field 325 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is 326 * valid. 327 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 328 * WEPSeed[1], pn1}. Only pn[47:0] is valid. 329 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 330 * pn0}. Only pn[47:0] is valid. 331 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 332 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 333 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and 334 * pn[47:0] are valid. 335 * Only valid when first_msdu is set. 336 * 337 * pn_47_32 338 * Bits [47:32] of the PN number. See description for 339 * pn_31_0. The remaining PN fields are in the rx_msdu_end 340 * descriptor 341 * 342 * pn 343 * Use this field to access the pn without worrying about 344 * byte-order and bitmasking/bitshifting. 345 * 346 * directed 347 * See definition in RX attention descriptor 348 * 349 * reserved_2 350 * Reserved: HW should fill with zero. FW should ignore. 351 * 352 * tid 353 * The TID field in the QoS control field 354 */ 355 356 #define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff 357 #define RX_MPDU_END_INFO0_RESERVED_0_LSB 0 358 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000 359 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16 360 #define RX_MPDU_END_INFO0_OVERFLOW_ERR (1 << 13) 361 #define RX_MPDU_END_INFO0_LAST_MPDU (1 << 14) 362 #define RX_MPDU_END_INFO0_POST_DELIM_ERR (1 << 15) 363 #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR (1 << 28) 364 #define RX_MPDU_END_INFO0_TKIP_MIC_ERR (1 << 29) 365 #define RX_MPDU_END_INFO0_DECRYPT_ERR (1 << 30) 366 #define RX_MPDU_END_INFO0_FCS_ERR (1 << 31) 367 368 struct rx_mpdu_end { 369 __le32 info0; 370 } __packed; 371 372 /* 373 * reserved_0 374 * Reserved 375 * 376 * overflow_err 377 * PCU Receive FIFO does not have enough space to store the 378 * full receive packet. Enough space is reserved in the 379 * receive FIFO for the status is written. This MPDU remaining 380 * packets in the PPDU will be filtered and no Ack response 381 * will be transmitted. 382 * 383 * last_mpdu 384 * Indicates that this is the last MPDU of a PPDU. 385 * 386 * post_delim_err 387 * Indicates that a delimiter FCS error occurred after this 388 * MPDU before the next MPDU. Only valid when last_msdu is 389 * set. 390 * 391 * post_delim_cnt 392 * Count of the delimiters after this MPDU. This requires the 393 * last MPDU to be held until all the EOF descriptors have been 394 * received. This may be inefficient in the future when 395 * ML-MIMO is used. Only valid when last_mpdu is set. 396 * 397 * mpdu_length_err 398 * See definition in RX attention descriptor 399 * 400 * tkip_mic_err 401 * See definition in RX attention descriptor 402 * 403 * decrypt_err 404 * See definition in RX attention descriptor 405 * 406 * fcs_err 407 * See definition in RX attention descriptor 408 */ 409 410 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff 411 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0 412 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000 413 #define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14 414 #define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000 415 #define RX_MSDU_START_INFO0_RING_MASK_LSB 20 416 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000 417 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24 418 419 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff 420 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0 421 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300 422 #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8 423 #define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000 424 #define RX_MSDU_START_INFO1_SA_IDX_LSB 16 425 #define RX_MSDU_START_INFO1_IPV4_PROTO (1 << 10) 426 #define RX_MSDU_START_INFO1_IPV6_PROTO (1 << 11) 427 #define RX_MSDU_START_INFO1_TCP_PROTO (1 << 12) 428 #define RX_MSDU_START_INFO1_UDP_PROTO (1 << 13) 429 #define RX_MSDU_START_INFO1_IP_FRAG (1 << 14) 430 #define RX_MSDU_START_INFO1_TCP_ONLY_ACK (1 << 15) 431 432 #define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff 433 #define RX_MSDU_START_INFO2_DA_IDX_LSB 0 434 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000 435 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16 436 #define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) 437 438 /* The decapped header (rx_hdr_status) contains the following: 439 * a) 802.11 header 440 * [padding to 4 bytes] 441 * b) HW crypto parameter 442 * - 0 bytes for no security 443 * - 4 bytes for WEP 444 * - 8 bytes for TKIP, AES 445 * [padding to 4 bytes] 446 * c) A-MSDU subframe header (14 bytes) if appliable 447 * d) LLC/SNAP (RFC1042, 8 bytes) 448 * 449 * In case of A-MSDU only first frame in sequence contains (a) and (b). 450 */ 451 enum rx_msdu_decap_format { 452 RX_MSDU_DECAP_RAW = 0, 453 454 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in 455 * htt_rx_desc contains the original decapped 802.11 header. 456 */ 457 RX_MSDU_DECAP_NATIVE_WIFI = 1, 458 459 /* Payload contains an ethernet header (struct ethhdr). */ 460 RX_MSDU_DECAP_ETHERNET2_DIX = 2, 461 462 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes 463 * total), followed by an RFC1042 header (8 bytes). 464 */ 465 RX_MSDU_DECAP_8023_SNAP_LLC = 3 466 }; 467 468 struct rx_msdu_start_common { 469 __le32 info0; /* %RX_MSDU_START_INFO0_ */ 470 __le32 flow_id_crc; 471 __le32 info1; /* %RX_MSDU_START_INFO1_ */ 472 } __packed; 473 474 struct rx_msdu_start_qca99x0 { 475 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 476 } __packed; 477 478 struct rx_msdu_start_wcn3990 { 479 __le32 info2; /* %RX_MSDU_START_INFO2_ */ 480 __le32 info3; /* %RX_MSDU_START_INFO3_ */ 481 } __packed; 482 483 struct rx_msdu_start { 484 struct rx_msdu_start_common common; 485 union { 486 struct rx_msdu_start_qca99x0 qca99x0; 487 struct rx_msdu_start_wcn3990 wcn3990; 488 } __packed; 489 } __packed; 490 491 /* 492 * msdu_length 493 * MSDU length in bytes after decapsulation. This field is 494 * still valid for MPDU frames without A-MSDU. It still 495 * represents MSDU length after decapsulation 496 * 497 * ip_offset 498 * Indicates the IP offset in bytes from the start of the 499 * packet after decapsulation. Only valid if ipv4_proto or 500 * ipv6_proto is set. 501 * 502 * ring_mask 503 * Indicates the destination RX rings for this MSDU. 504 * 505 * tcp_udp_offset 506 * Indicates the offset in bytes to the start of TCP or UDP 507 * header from the start of the IP header after decapsulation. 508 * Only valid if tcp_prot or udp_prot is set. The value 0 509 * indicates that the offset is longer than 127 bytes. 510 * 511 * reserved_0c 512 * Reserved: HW should fill with zero. FW should ignore. 513 * 514 * flow_id_crc 515 * The flow_id_crc runs CRC32 on the following information: 516 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0, 517 * protocol[7:0]}. 518 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0, 519 * next_header[7:0]} 520 * UDP case: sort_port[15:0], dest_port[15:0] 521 * TCP case: sort_port[15:0], dest_port[15:0], 522 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]}, 523 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit 524 * timestamp. 525 * 526 * msdu_number 527 * Indicates the MSDU number within a MPDU. This value is 528 * reset to zero at the start of each MPDU. If the number of 529 * MSDU exceeds 255 this number will wrap using modulo 256. 530 * 531 * decap_format 532 * Indicates the format after decapsulation: 533 * 0: RAW: No decapsulation 534 * 1: Native WiFi 535 * 2: Ethernet 2 (DIX) 536 * 3: 802.3 (SNAP/LLC) 537 * 538 * ipv4_proto 539 * Set if L2 layer indicates IPv4 protocol. 540 * 541 * ipv6_proto 542 * Set if L2 layer indicates IPv6 protocol. 543 * 544 * tcp_proto 545 * Set if the ipv4_proto or ipv6_proto are set and the IP 546 * protocol indicates TCP. 547 * 548 * udp_proto 549 * Set if the ipv4_proto or ipv6_proto are set and the IP 550 * protocol indicates UDP. 551 * 552 * ip_frag 553 * Indicates that either the IP More frag bit is set or IP frag 554 * number is non-zero. If set indicates that this is a 555 * fragmented IP packet. 556 * 557 * tcp_only_ack 558 * Set if only the TCP Ack bit is set in the TCP flags and if 559 * the TCP payload is 0. 560 * 561 * sa_idx 562 * The offset in the address table which matches the MAC source 563 * address. 564 * 565 * reserved_2b 566 * Reserved: HW should fill with zero. FW should ignore. 567 */ 568 569 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff 570 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0 571 #define RX_MSDU_END_INFO0_FIRST_MSDU (1 << 14) 572 #define RX_MSDU_END_INFO0_LAST_MSDU (1 << 15) 573 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR (1 << 30) 574 #define RX_MSDU_END_INFO0_RESERVED_3B (1 << 31) 575 576 struct rx_msdu_end_common { 577 __le16 ip_hdr_cksum; 578 __le16 tcp_hdr_cksum; 579 u8 key_id_octet; 580 u8 classification_filter; 581 u8 wapi_pn[10]; 582 __le32 info0; 583 } __packed; 584 585 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff 586 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0 587 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00 588 #define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10 589 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000 590 #define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16 591 #define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) 592 593 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f 594 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0 595 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0 596 #define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6 597 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000 598 #define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12 599 600 struct rx_msdu_end_qca99x0 { 601 __le32 ipv6_crc; 602 __le32 tcp_seq_no; 603 __le32 tcp_ack_no; 604 __le32 info1; 605 __le32 info2; 606 } __packed; 607 608 struct rx_msdu_end_wcn3990 { 609 __le32 ipv6_crc; 610 __le32 tcp_seq_no; 611 __le32 tcp_ack_no; 612 __le32 info1; 613 __le32 info2; 614 __le32 rule_indication_0; 615 __le32 rule_indication_1; 616 __le32 rule_indication_2; 617 __le32 rule_indication_3; 618 } __packed; 619 620 struct rx_msdu_end { 621 struct rx_msdu_end_common common; 622 union { 623 struct rx_msdu_end_qca99x0 qca99x0; 624 struct rx_msdu_end_wcn3990 wcn3990; 625 } __packed; 626 } __packed; 627 628 /* 629 *ip_hdr_chksum 630 * This can include the IP header checksum or the pseudo header 631 * checksum used by TCP/UDP checksum. 632 * 633 *tcp_udp_chksum 634 * The value of the computed TCP/UDP checksum. A mode bit 635 * selects whether this checksum is the full checksum or the 636 * partial checksum which does not include the pseudo header. 637 * 638 *key_id_octet 639 * The key ID octet from the IV. Only valid when first_msdu is 640 * set. 641 * 642 *classification_filter 643 * Indicates the number classification filter rule 644 * 645 *ext_wapi_pn_63_48 646 * Extension PN (packet number) which is only used by WAPI. 647 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The 648 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start 649 * descriptor. 650 * 651 *ext_wapi_pn_95_64 652 * Extension PN (packet number) which is only used by WAPI. 653 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and 654 * pn11). 655 * 656 *ext_wapi_pn_127_96 657 * Extension PN (packet number) which is only used by WAPI. 658 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, 659 * pn15). 660 * 661 *reported_mpdu_length 662 * MPDU length before decapsulation. Only valid when 663 * first_msdu is set. This field is taken directly from the 664 * length field of the A-MPDU delimiter or the preamble length 665 * field for non-A-MPDU frames. 666 * 667 *first_msdu 668 * Indicates the first MSDU of A-MSDU. If both first_msdu and 669 * last_msdu are set in the MSDU then this is a non-aggregated 670 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 671 * have both first_mpdu and last_mpdu bits set to 0. 672 * 673 *last_msdu 674 * Indicates the last MSDU of the A-MSDU. MPDU end status is 675 * only valid when last_msdu is set. 676 * 677 *reserved_3a 678 * Reserved: HW should fill with zero. FW should ignore. 679 * 680 *pre_delim_err 681 * Indicates that the first delimiter had a FCS failure. Only 682 * valid when first_mpdu and first_msdu are set. 683 * 684 *reserved_3b 685 * Reserved: HW should fill with zero. FW should ignore. 686 */ 687 688 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 689 #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 690 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 691 #define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C 692 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D 693 694 #define RX_PPDU_START_INFO0_IS_GREENFIELD (1 << 0) 695 696 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f 697 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0 698 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0 699 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5 700 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000 701 #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18 702 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000 703 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24 704 #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT (1 << 4) 705 #define RX_PPDU_START_INFO1_L_SIG_PARITY (1 << 17) 706 707 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff 708 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0 709 710 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff 711 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0 712 #define RX_PPDU_START_INFO3_TXBF_H_INFO (1 << 24) 713 714 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff 715 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0 716 717 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff 718 #define RX_PPDU_START_INFO5_SERVICE_LSB 0 719 720 /* No idea what this flag means. It seems to be always set in rate. */ 721 #define RX_PPDU_START_RATE_FLAG BIT(3) 722 723 struct rx_ppdu_start { 724 struct { 725 u8 pri20_mhz; 726 u8 ext20_mhz; 727 u8 ext40_mhz; 728 u8 ext80_mhz; 729 } rssi_chains[4]; 730 u8 rssi_comb; 731 __le16 rsvd0; 732 u8 info0; /* %RX_PPDU_START_INFO0_ */ 733 __le32 info1; /* %RX_PPDU_START_INFO1_ */ 734 __le32 info2; /* %RX_PPDU_START_INFO2_ */ 735 __le32 info3; /* %RX_PPDU_START_INFO3_ */ 736 __le32 info4; /* %RX_PPDU_START_INFO4_ */ 737 __le32 info5; /* %RX_PPDU_START_INFO5_ */ 738 } __packed; 739 740 /* 741 * rssi_chain0_pri20 742 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 743 * Value of 0x80 indicates invalid. 744 * 745 * rssi_chain0_sec20 746 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth. 747 * Value of 0x80 indicates invalid. 748 * 749 * rssi_chain0_sec40 750 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth. 751 * Value of 0x80 indicates invalid. 752 * 753 * rssi_chain0_sec80 754 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth. 755 * Value of 0x80 indicates invalid. 756 * 757 * rssi_chain1_pri20 758 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 759 * Value of 0x80 indicates invalid. 760 * 761 * rssi_chain1_sec20 762 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth. 763 * Value of 0x80 indicates invalid. 764 * 765 * rssi_chain1_sec40 766 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth. 767 * Value of 0x80 indicates invalid. 768 * 769 * rssi_chain1_sec80 770 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth. 771 * Value of 0x80 indicates invalid. 772 * 773 * rssi_chain2_pri20 774 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 775 * Value of 0x80 indicates invalid. 776 * 777 * rssi_chain2_sec20 778 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth. 779 * Value of 0x80 indicates invalid. 780 * 781 * rssi_chain2_sec40 782 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth. 783 * Value of 0x80 indicates invalid. 784 * 785 * rssi_chain2_sec80 786 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth. 787 * Value of 0x80 indicates invalid. 788 * 789 * rssi_chain3_pri20 790 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 791 * Value of 0x80 indicates invalid. 792 * 793 * rssi_chain3_sec20 794 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth. 795 * Value of 0x80 indicates invalid. 796 * 797 * rssi_chain3_sec40 798 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth. 799 * Value of 0x80 indicates invalid. 800 * 801 * rssi_chain3_sec80 802 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth. 803 * Value of 0x80 indicates invalid. 804 * 805 * rssi_comb 806 * The combined RSSI of RX PPDU of all active chains and 807 * bandwidths. Value of 0x80 indicates invalid. 808 * 809 * reserved_4a 810 * Reserved: HW should fill with 0, FW should ignore. 811 * 812 * is_greenfield 813 * Do we really support this? 814 * 815 * reserved_4b 816 * Reserved: HW should fill with 0, FW should ignore. 817 * 818 * l_sig_rate 819 * If l_sig_rate_select is 0: 820 * 0x8: OFDM 48 Mbps 821 * 0x9: OFDM 24 Mbps 822 * 0xA: OFDM 12 Mbps 823 * 0xB: OFDM 6 Mbps 824 * 0xC: OFDM 54 Mbps 825 * 0xD: OFDM 36 Mbps 826 * 0xE: OFDM 18 Mbps 827 * 0xF: OFDM 9 Mbps 828 * If l_sig_rate_select is 1: 829 * 0x8: CCK 11 Mbps long preamble 830 * 0x9: CCK 5.5 Mbps long preamble 831 * 0xA: CCK 2 Mbps long preamble 832 * 0xB: CCK 1 Mbps long preamble 833 * 0xC: CCK 11 Mbps short preamble 834 * 0xD: CCK 5.5 Mbps short preamble 835 * 0xE: CCK 2 Mbps short preamble 836 * 837 * l_sig_rate_select 838 * Legacy signal rate select. If set then l_sig_rate indicates 839 * CCK rates. If clear then l_sig_rate indicates OFDM rates. 840 * 841 * l_sig_length 842 * Length of legacy frame in octets. 843 * 844 * l_sig_parity 845 * Odd parity over l_sig_rate and l_sig_length 846 * 847 * l_sig_tail 848 * Tail bits for Viterbi decoder 849 * 850 * preamble_type 851 * Indicates the type of preamble ahead: 852 * 0x4: Legacy (OFDM/CCK) 853 * 0x8: HT 854 * 0x9: HT with TxBF 855 * 0xC: VHT 856 * 0xD: VHT with TxBF 857 * 0x80 - 0xFF: Reserved for special baseband data types such 858 * as radar and spectral scan. 859 * 860 * ht_sig_vht_sig_a_1 861 * If preamble_type == 0x8 or 0x9 862 * HT-SIG (first 24 bits) 863 * If preamble_type == 0xC or 0xD 864 * VHT-SIG A (first 24 bits) 865 * Else 866 * Reserved 867 * 868 * reserved_6 869 * Reserved: HW should fill with 0, FW should ignore. 870 * 871 * ht_sig_vht_sig_a_2 872 * If preamble_type == 0x8 or 0x9 873 * HT-SIG (last 24 bits) 874 * If preamble_type == 0xC or 0xD 875 * VHT-SIG A (last 24 bits) 876 * Else 877 * Reserved 878 * 879 * txbf_h_info 880 * Indicates that the packet data carries H information which 881 * is used for TxBF debug. 882 * 883 * reserved_7 884 * Reserved: HW should fill with 0, FW should ignore. 885 * 886 * vht_sig_b 887 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all 888 * 0s since the BB does not plan on decoding VHT SIG-B. 889 * 890 * reserved_8 891 * Reserved: HW should fill with 0, FW should ignore. 892 * 893 * service 894 * Service field from BB for OFDM, HT and VHT packets. CCK 895 * packets will have service field of 0. 896 * 897 * reserved_9 898 * Reserved: HW should fill with 0, FW should ignore. 899 */ 900 901 #define RX_PPDU_END_FLAGS_PHY_ERR (1 << 0) 902 #define RX_PPDU_END_FLAGS_RX_LOCATION (1 << 1) 903 #define RX_PPDU_END_FLAGS_TXBF_H_INFO (1 << 2) 904 905 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff 906 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0 907 #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK (1 << 24) 908 #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL (1 << 25) 909 910 #define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc 911 #define RX_PPDU_END_INFO1_PEER_IDX_LSB 2 912 #define RX_PPDU_END_INFO1_BB_DATA BIT(0) 913 #define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) 914 #define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) 915 916 struct rx_ppdu_end_common { 917 __le32 evm_p0; 918 __le32 evm_p1; 919 __le32 evm_p2; 920 __le32 evm_p3; 921 __le32 evm_p4; 922 __le32 evm_p5; 923 __le32 evm_p6; 924 __le32 evm_p7; 925 __le32 evm_p8; 926 __le32 evm_p9; 927 __le32 evm_p10; 928 __le32 evm_p11; 929 __le32 evm_p12; 930 __le32 evm_p13; 931 __le32 evm_p14; 932 __le32 evm_p15; 933 __le32 tsf_timestamp; 934 __le32 wb_timestamp; 935 } __packed; 936 937 struct rx_ppdu_end_qca988x { 938 u8 locationing_timestamp; 939 u8 phy_err_code; 940 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 941 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 942 __le16 bb_length; 943 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 944 } __packed; 945 946 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff 947 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0 948 #define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000 949 #define RX_PPDU_END_RTT_UNUSED_LSB 24 950 #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) 951 952 struct rx_ppdu_end_qca6174 { 953 u8 locationing_timestamp; 954 u8 phy_err_code; 955 __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 956 __le32 info0; /* %RX_PPDU_END_INFO0_ */ 957 __le32 rtt; /* %RX_PPDU_END_RTT_ */ 958 __le16 bb_length; 959 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 960 } __packed; 961 962 #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) 963 #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) 964 #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) 965 #define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) 966 #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) 967 #define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) 968 969 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff 970 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0 971 #define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000 972 #define RX_LOCATION_INFO_FAC_STATUS_LSB 18 973 #define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000 974 #define RX_LOCATION_INFO_PKT_BW_LSB 20 975 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000 976 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23 977 #define RX_LOCATION_INFO_CIR_STATUS BIT(17) 978 #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) 979 #define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) 980 #define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) 981 #define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) 982 983 struct rx_pkt_end { 984 __le32 info0; /* %RX_PKT_END_INFO0_ */ 985 __le32 phy_timestamp_1; 986 __le32 phy_timestamp_2; 987 } __packed; 988 989 struct rx_pkt_end_wcn3990 { 990 __le32 info0; /* %RX_PKT_END_INFO0_ */ 991 __le64 phy_timestamp_1; 992 __le64 phy_timestamp_2; 993 } __packed; 994 995 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff 996 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 997 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 998 #define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 999 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 1000 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 1001 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) 1002 #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) 1003 1004 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c 1005 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 1006 #define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 1007 #define RX_LOCATION_INFO1_PKT_BW_LSB 4 1008 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 1009 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 1010 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 1011 #define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 1012 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 1013 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 1014 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 1015 #define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 1016 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 1017 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 1018 #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) 1019 #define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) 1020 #define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) 1021 #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) 1022 #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) 1023 #define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) 1024 1025 struct rx_location_info { 1026 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1027 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1028 } __packed; 1029 1030 struct rx_location_info_wcn3990 { 1031 __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1032 __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1033 __le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */ 1034 } __packed; 1035 1036 enum rx_phy_ppdu_end_info0 { 1037 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), 1038 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), 1039 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), 1040 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), 1041 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), 1042 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), 1043 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), 1044 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), 1045 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), 1046 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), 1047 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), 1048 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), 1049 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), 1050 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), 1051 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), 1052 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), 1053 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), 1054 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), 1055 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), 1056 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), 1057 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), 1058 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), 1059 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), 1060 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), 1061 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), 1062 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), 1063 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), 1064 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), 1065 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), 1066 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), 1067 }; 1068 1069 enum rx_phy_ppdu_end_info1 { 1070 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), 1071 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), 1072 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), 1073 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), 1074 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), 1075 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), 1076 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), 1077 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), 1078 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), 1079 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), 1080 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), 1081 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), 1082 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), 1083 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), 1084 }; 1085 1086 struct rx_phy_ppdu_end { 1087 __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */ 1088 __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */ 1089 } __packed; 1090 1091 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff 1092 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0 1093 1094 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff 1095 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0 1096 #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) 1097 #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) 1098 #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) 1099 #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) 1100 #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) 1101 #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) 1102 #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) 1103 1104 struct rx_ppdu_end_qca99x0 { 1105 struct rx_pkt_end rx_pkt_end; 1106 __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ 1107 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1108 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1109 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1110 __le16 bb_length; 1111 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1112 } __packed; 1113 1114 struct rx_ppdu_end_qca9984 { 1115 struct rx_pkt_end rx_pkt_end; 1116 struct rx_location_info rx_location_info; 1117 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1118 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1119 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1120 __le16 bb_length; 1121 __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1122 } __packed; 1123 1124 struct rx_ppdu_end_wcn3990 { 1125 struct rx_pkt_end_wcn3990 rx_pkt_end; 1126 struct rx_location_info_wcn3990 rx_location_info; 1127 struct rx_phy_ppdu_end rx_phy_ppdu_end; 1128 __le32 rx_timing_offset; 1129 __le32 reserved_info_0; 1130 __le32 reserved_info_1; 1131 __le32 rx_antenna_info; 1132 __le32 rx_coex_info; 1133 __le32 rx_mpdu_cnt_info; 1134 __le64 phy_timestamp_tx; 1135 __le32 rx_bb_length; 1136 } __packed; 1137 1138 struct rx_ppdu_end { 1139 struct rx_ppdu_end_common common; 1140 union { 1141 struct rx_ppdu_end_qca988x qca988x; 1142 struct rx_ppdu_end_qca6174 qca6174; 1143 struct rx_ppdu_end_qca99x0 qca99x0; 1144 struct rx_ppdu_end_qca9984 qca9984; 1145 struct rx_ppdu_end_wcn3990 wcn3990; 1146 } __packed; 1147 } __packed; 1148 1149 /* 1150 * evm_p0 1151 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3. 1152 * 1153 * evm_p1 1154 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3. 1155 * 1156 * evm_p2 1157 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3. 1158 * 1159 * evm_p3 1160 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3. 1161 * 1162 * evm_p4 1163 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3. 1164 * 1165 * evm_p5 1166 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3. 1167 * 1168 * evm_p6 1169 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3. 1170 * 1171 * evm_p7 1172 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3. 1173 * 1174 * evm_p8 1175 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3. 1176 * 1177 * evm_p9 1178 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3. 1179 * 1180 * evm_p10 1181 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3. 1182 * 1183 * evm_p11 1184 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3. 1185 * 1186 * evm_p12 1187 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3. 1188 * 1189 * evm_p13 1190 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3. 1191 * 1192 * evm_p14 1193 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3. 1194 * 1195 * evm_p15 1196 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3. 1197 * 1198 * tsf_timestamp 1199 * Receive TSF timestamp sampled on the rising edge of 1200 * rx_clear. For PHY errors this may be the current TSF when 1201 * phy_error is asserted if the rx_clear does not assert before 1202 * the end of the PHY error. 1203 * 1204 * wb_timestamp 1205 * WLAN/BT timestamp is a 1 usec resolution timestamp which 1206 * does not get updated based on receive beacon like TSF. The 1207 * same rules for capturing tsf_timestamp are used to capture 1208 * the wb_timestamp. 1209 * 1210 * locationing_timestamp 1211 * Timestamp used for locationing. This timestamp is used to 1212 * indicate fractions of usec. For example if the MAC clock is 1213 * running at 80 MHz, the timestamp will increment every 12.5 1214 * nsec. The value starts at 0 and increments to 79 and 1215 * returns to 0 and repeats. This information is valid for 1216 * every PPDU. This information can be used in conjunction 1217 * with wb_timestamp to capture large delta times. 1218 * 1219 * phy_err_code 1220 * See the 1.10.8.1.2 for the list of the PHY error codes. 1221 * 1222 * phy_err 1223 * Indicates a PHY error was detected for this PPDU. 1224 * 1225 * rx_location 1226 * Indicates that location information was requested. 1227 * 1228 * txbf_h_info 1229 * Indicates that the packet data carries H information which 1230 * is used for TxBF debug. 1231 * 1232 * reserved_18 1233 * Reserved: HW should fill with 0, FW should ignore. 1234 * 1235 * rx_antenna 1236 * Receive antenna value 1237 * 1238 * tx_ht_vht_ack 1239 * Indicates that a HT or VHT Ack/BA frame was transmitted in 1240 * response to this receive packet. 1241 * 1242 * bb_captured_channel 1243 * Indicates that the BB has captured a channel dump. FW can 1244 * then read the channel dump memory. This may indicate that 1245 * the channel was captured either based on PCU setting the 1246 * capture_channel bit BB descriptor or FW setting the 1247 * capture_channel mode bit. 1248 * 1249 * reserved_19 1250 * Reserved: HW should fill with 0, FW should ignore. 1251 * 1252 * bb_length 1253 * Indicates the number of bytes of baseband information for 1254 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF 1255 * which indicates that this is not a normal PPDU but rather 1256 * contains baseband debug information. 1257 * 1258 * reserved_20 1259 * Reserved: HW should fill with 0, FW should ignore. 1260 * 1261 * ppdu_done 1262 * PPDU end status is only valid when ppdu_done bit is set. 1263 * Every time HW sets this bit in memory FW/SW must clear this 1264 * bit in memory. FW will initialize all the ppdu_done dword 1265 * to 0. 1266 */ 1267 1268 #define FW_RX_DESC_INFO0_DISCARD (1 << 0) 1269 #define FW_RX_DESC_INFO0_FORWARD (1 << 1) 1270 #define FW_RX_DESC_INFO0_INSPECT (1 << 5) 1271 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0 1272 #define FW_RX_DESC_INFO0_EXT_LSB 6 1273 1274 struct fw_rx_desc_base { 1275 u8 info0; 1276 } __packed; 1277 1278 #endif /* _RX_DESC_H_ */ 1279