1f0553ca9SKalle Valo /* SPDX-License-Identifier: ISC */ 25e3dd157SKalle Valo /* 35e3dd157SKalle Valo * Copyright (c) 2005-2011 Atheros Communications Inc. 48b1083d6SKalle Valo * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 55e3dd157SKalle Valo */ 65e3dd157SKalle Valo 75e3dd157SKalle Valo #ifndef _RX_DESC_H_ 85e3dd157SKalle Valo #define _RX_DESC_H_ 95e3dd157SKalle Valo 10c3f7f31eSGovind Singh #include <linux/bitops.h> 11c3f7f31eSGovind Singh 125e3dd157SKalle Valo enum rx_attention_flags { 13c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_FIRST_MPDU = BIT(0), 14c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_LAST_MPDU = BIT(1), 15c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MCAST_BCAST = BIT(2), 16c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_PEER_IDX_INVALID = BIT(3), 17c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = BIT(4), 18c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_POWER_MGMT = BIT(5), 19c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_NON_QOS = BIT(6), 20c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_NULL_DATA = BIT(7), 21c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MGMT_TYPE = BIT(8), 22c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_CTRL_TYPE = BIT(9), 23c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MORE_DATA = BIT(10), 24c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_EOSP = BIT(11), 25c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_U_APSD_TRIGGER = BIT(12), 26c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_FRAGMENT = BIT(13), 27c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_ORDER = BIT(14), 28c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_CLASSIFICATION = BIT(15), 29c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_OVERFLOW_ERR = BIT(16), 30c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = BIT(17), 31c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = BIT(18), 32c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = BIT(19), 33c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_SA_IDX_INVALID = BIT(20), 34c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_DA_IDX_INVALID = BIT(21), 35c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = BIT(22), 36c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = BIT(23), 37c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = BIT(24), 38c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_DIRECTED = BIT(25), 39c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = BIT(26), 40c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = BIT(27), 41c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_TKIP_MIC_ERR = BIT(28), 42c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_DECRYPT_ERR = BIT(29), 43c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_FCS_ERR = BIT(30), 44c3f7f31eSGovind Singh RX_ATTENTION_FLAGS_MSDU_DONE = BIT(31), 455e3dd157SKalle Valo }; 465e3dd157SKalle Valo 475e3dd157SKalle Valo struct rx_attention { 485e3dd157SKalle Valo __le32 flags; /* %RX_ATTENTION_FLAGS_ */ 495e3dd157SKalle Valo } __packed; 505e3dd157SKalle Valo 515e3dd157SKalle Valo /* 525e3dd157SKalle Valo * first_mpdu 535e3dd157SKalle Valo * Indicates the first MSDU of the PPDU. If both first_mpdu 545e3dd157SKalle Valo * and last_mpdu are set in the MSDU then this is a not an 555e3dd157SKalle Valo * A-MPDU frame but a stand alone MPDU. Interior MPDU in an 565e3dd157SKalle Valo * A-MPDU shall have both first_mpdu and last_mpdu bits set to 575e3dd157SKalle Valo * 0. The PPDU start status will only be valid when this bit 585e3dd157SKalle Valo * is set. 595e3dd157SKalle Valo * 605e3dd157SKalle Valo * last_mpdu 615e3dd157SKalle Valo * Indicates the last MSDU of the last MPDU of the PPDU. The 625e3dd157SKalle Valo * PPDU end status will only be valid when this bit is set. 635e3dd157SKalle Valo * 645e3dd157SKalle Valo * mcast_bcast 655e3dd157SKalle Valo * Multicast / broadcast indicator. Only set when the MAC 665e3dd157SKalle Valo * address 1 bit 0 is set indicating mcast/bcast and the BSSID 675e3dd157SKalle Valo * matches one of the 4 BSSID registers. Only set when 685e3dd157SKalle Valo * first_msdu is set. 695e3dd157SKalle Valo * 705e3dd157SKalle Valo * peer_idx_invalid 71762fd1aeSKalle Valo * Indicates no matching entries within the max search 725e3dd157SKalle Valo * count. Only set when first_msdu is set. 735e3dd157SKalle Valo * 745e3dd157SKalle Valo * peer_idx_timeout 755e3dd157SKalle Valo * Indicates an unsuccessful search for the peer index due to 765e3dd157SKalle Valo * timeout. Only set when first_msdu is set. 775e3dd157SKalle Valo * 785e3dd157SKalle Valo * power_mgmt 795e3dd157SKalle Valo * Power management bit set in the 802.11 header. Only set 805e3dd157SKalle Valo * when first_msdu is set. 815e3dd157SKalle Valo * 825e3dd157SKalle Valo * non_qos 835e3dd157SKalle Valo * Set if packet is not a non-QoS data frame. Only set when 845e3dd157SKalle Valo * first_msdu is set. 855e3dd157SKalle Valo * 865e3dd157SKalle Valo * null_data 875e3dd157SKalle Valo * Set if frame type indicates either null data or QoS null 885e3dd157SKalle Valo * data format. Only set when first_msdu is set. 895e3dd157SKalle Valo * 905e3dd157SKalle Valo * mgmt_type 915e3dd157SKalle Valo * Set if packet is a management packet. Only set when 925e3dd157SKalle Valo * first_msdu is set. 935e3dd157SKalle Valo * 945e3dd157SKalle Valo * ctrl_type 955e3dd157SKalle Valo * Set if packet is a control packet. Only set when first_msdu 965e3dd157SKalle Valo * is set. 975e3dd157SKalle Valo * 985e3dd157SKalle Valo * more_data 995e3dd157SKalle Valo * Set if more bit in frame control is set. Only set when 1005e3dd157SKalle Valo * first_msdu is set. 1015e3dd157SKalle Valo * 1025e3dd157SKalle Valo * eosp 1035e3dd157SKalle Valo * Set if the EOSP (end of service period) bit in the QoS 1045e3dd157SKalle Valo * control field is set. Only set when first_msdu is set. 1055e3dd157SKalle Valo * 1065e3dd157SKalle Valo * u_apsd_trigger 1075e3dd157SKalle Valo * Set if packet is U-APSD trigger. Key table will have bits 1085e3dd157SKalle Valo * per TID to indicate U-APSD trigger. 1095e3dd157SKalle Valo * 1105e3dd157SKalle Valo * fragment 1115e3dd157SKalle Valo * Indicates that this is an 802.11 fragment frame. This is 1125e3dd157SKalle Valo * set when either the more_frag bit is set in the frame 1135e3dd157SKalle Valo * control or the fragment number is not zero. Only set when 1145e3dd157SKalle Valo * first_msdu is set. 1155e3dd157SKalle Valo * 1165e3dd157SKalle Valo * order 1175e3dd157SKalle Valo * Set if the order bit in the frame control is set. Only set 1185e3dd157SKalle Valo * when first_msdu is set. 1195e3dd157SKalle Valo * 1205e3dd157SKalle Valo * classification 1215e3dd157SKalle Valo * Indicates that this status has a corresponding MSDU that 1225e3dd157SKalle Valo * requires FW processing. The OLE will have classification 1235e3dd157SKalle Valo * ring mask registers which will indicate the ring(s) for 1245e3dd157SKalle Valo * packets and descriptors which need FW attention. 1255e3dd157SKalle Valo * 1265e3dd157SKalle Valo * overflow_err 1275e3dd157SKalle Valo * PCU Receive FIFO does not have enough space to store the 1285e3dd157SKalle Valo * full receive packet. Enough space is reserved in the 1295e3dd157SKalle Valo * receive FIFO for the status is written. This MPDU remaining 1305e3dd157SKalle Valo * packets in the PPDU will be filtered and no Ack response 1315e3dd157SKalle Valo * will be transmitted. 1325e3dd157SKalle Valo * 1335e3dd157SKalle Valo * msdu_length_err 1345e3dd157SKalle Valo * Indicates that the MSDU length from the 802.3 encapsulated 1355e3dd157SKalle Valo * length field extends beyond the MPDU boundary. 1365e3dd157SKalle Valo * 1375e3dd157SKalle Valo * tcp_udp_chksum_fail 1385e3dd157SKalle Valo * Indicates that the computed checksum (tcp_udp_chksum) did 1395e3dd157SKalle Valo * not match the checksum in the TCP/UDP header. 1405e3dd157SKalle Valo * 1415e3dd157SKalle Valo * ip_chksum_fail 1425e3dd157SKalle Valo * Indicates that the computed checksum did not match the 1435e3dd157SKalle Valo * checksum in the IP header. 1445e3dd157SKalle Valo * 1455e3dd157SKalle Valo * sa_idx_invalid 1465e3dd157SKalle Valo * Indicates no matching entry was found in the address search 1475e3dd157SKalle Valo * table for the source MAC address. 1485e3dd157SKalle Valo * 1495e3dd157SKalle Valo * da_idx_invalid 1505e3dd157SKalle Valo * Indicates no matching entry was found in the address search 1515e3dd157SKalle Valo * table for the destination MAC address. 1525e3dd157SKalle Valo * 1535e3dd157SKalle Valo * sa_idx_timeout 1545e3dd157SKalle Valo * Indicates an unsuccessful search for the source MAC address 1555e3dd157SKalle Valo * due to the expiring of the search timer. 1565e3dd157SKalle Valo * 1575e3dd157SKalle Valo * da_idx_timeout 1585e3dd157SKalle Valo * Indicates an unsuccessful search for the destination MAC 1595e3dd157SKalle Valo * address due to the expiring of the search timer. 1605e3dd157SKalle Valo * 1615e3dd157SKalle Valo * encrypt_required 1625e3dd157SKalle Valo * Indicates that this data type frame is not encrypted even if 1635e3dd157SKalle Valo * the policy for this MPDU requires encryption as indicated in 1645e3dd157SKalle Valo * the peer table key type. 1655e3dd157SKalle Valo * 1665e3dd157SKalle Valo * directed 1675e3dd157SKalle Valo * MPDU is a directed packet which means that the RA matched 1685e3dd157SKalle Valo * our STA addresses. In proxySTA it means that the TA matched 1695e3dd157SKalle Valo * an entry in our address search table with the corresponding 1705e3dd157SKalle Valo * 'no_ack' bit is the address search entry cleared. 1715e3dd157SKalle Valo * 1725e3dd157SKalle Valo * buffer_fragment 1735e3dd157SKalle Valo * Indicates that at least one of the rx buffers has been 1745e3dd157SKalle Valo * fragmented. If set the FW should look at the rx_frag_info 1755e3dd157SKalle Valo * descriptor described below. 1765e3dd157SKalle Valo * 1775e3dd157SKalle Valo * mpdu_length_err 1785e3dd157SKalle Valo * Indicates that the MPDU was pre-maturely terminated 1795e3dd157SKalle Valo * resulting in a truncated MPDU. Don't trust the MPDU length 1805e3dd157SKalle Valo * field. 1815e3dd157SKalle Valo * 1825e3dd157SKalle Valo * tkip_mic_err 1835e3dd157SKalle Valo * Indicates that the MPDU Michael integrity check failed 1845e3dd157SKalle Valo * 1855e3dd157SKalle Valo * decrypt_err 1865e3dd157SKalle Valo * Indicates that the MPDU decrypt integrity check failed 1875e3dd157SKalle Valo * 1885e3dd157SKalle Valo * fcs_err 1895e3dd157SKalle Valo * Indicates that the MPDU FCS check failed 1905e3dd157SKalle Valo * 1915e3dd157SKalle Valo * msdu_done 1925e3dd157SKalle Valo * If set indicates that the RX packet data, RX header data, RX 1935e3dd157SKalle Valo * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU 1945e3dd157SKalle Valo * start/end descriptors and RX Attention descriptor are all 1955e3dd157SKalle Valo * valid. This bit must be in the last octet of the 1965e3dd157SKalle Valo * descriptor. 1975e3dd157SKalle Valo */ 1985e3dd157SKalle Valo 199*6bae9de6SFrancesco Magliocca struct rx_frag_info_common { 2005e3dd157SKalle Valo u8 ring0_more_count; 2015e3dd157SKalle Valo u8 ring1_more_count; 2025e3dd157SKalle Valo u8 ring2_more_count; 2035e3dd157SKalle Valo u8 ring3_more_count; 204*6bae9de6SFrancesco Magliocca } __packed; 205*6bae9de6SFrancesco Magliocca 206*6bae9de6SFrancesco Magliocca struct rx_frag_info_wcn3990 { 207e3def6f7SGovind Singh u8 ring4_more_count; 208e3def6f7SGovind Singh u8 ring5_more_count; 209e3def6f7SGovind Singh u8 ring6_more_count; 210e3def6f7SGovind Singh u8 ring7_more_count; 2115e3dd157SKalle Valo } __packed; 2125e3dd157SKalle Valo 213*6bae9de6SFrancesco Magliocca struct rx_frag_info { 214*6bae9de6SFrancesco Magliocca struct rx_frag_info_common common; 215*6bae9de6SFrancesco Magliocca union { 216*6bae9de6SFrancesco Magliocca struct rx_frag_info_wcn3990 wcn3990; 217*6bae9de6SFrancesco Magliocca } __packed; 218*6bae9de6SFrancesco Magliocca } __packed; 219*6bae9de6SFrancesco Magliocca 220*6bae9de6SFrancesco Magliocca struct rx_frag_info_v1 { 221*6bae9de6SFrancesco Magliocca struct rx_frag_info_common common; 222*6bae9de6SFrancesco Magliocca } __packed; 223*6bae9de6SFrancesco Magliocca 2245e3dd157SKalle Valo /* 2255e3dd157SKalle Valo * ring0_more_count 2265e3dd157SKalle Valo * Indicates the number of more buffers associated with RX DMA 2275e3dd157SKalle Valo * ring 0. Field is filled in by the RX_DMA. 2285e3dd157SKalle Valo * 2295e3dd157SKalle Valo * ring1_more_count 2305e3dd157SKalle Valo * Indicates the number of more buffers associated with RX DMA 2315e3dd157SKalle Valo * ring 1. Field is filled in by the RX_DMA. 2325e3dd157SKalle Valo * 2335e3dd157SKalle Valo * ring2_more_count 2345e3dd157SKalle Valo * Indicates the number of more buffers associated with RX DMA 2355e3dd157SKalle Valo * ring 2. Field is filled in by the RX_DMA. 2365e3dd157SKalle Valo * 2375e3dd157SKalle Valo * ring3_more_count 2385e3dd157SKalle Valo * Indicates the number of more buffers associated with RX DMA 2395e3dd157SKalle Valo * ring 3. Field is filled in by the RX_DMA. 2405e3dd157SKalle Valo */ 2415e3dd157SKalle Valo 2425e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type { 2435e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_WEP40 = 0, 2445e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_WEP104 = 1, 2455e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2, 2465e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_WEP128 = 3, 2475e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4, 2485e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_WAPI = 5, 2495e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6, 2505e3dd157SKalle Valo HTT_RX_MPDU_ENCRYPT_NONE = 7, 2517eccb738SVasanthakumar Thiagarajan HTT_RX_MPDU_ENCRYPT_AES_CCM256_WPA2 = 8, 2527eccb738SVasanthakumar Thiagarajan HTT_RX_MPDU_ENCRYPT_AES_GCMP_WPA2 = 9, 2537eccb738SVasanthakumar Thiagarajan HTT_RX_MPDU_ENCRYPT_AES_GCMP256_WPA2 = 10, 2545e3dd157SKalle Valo }; 2555e3dd157SKalle Valo 2565e3dd157SKalle Valo #define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff 2575e3dd157SKalle Valo #define RX_MPDU_START_INFO0_PEER_IDX_LSB 0 2585e3dd157SKalle Valo #define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000 2595e3dd157SKalle Valo #define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16 2605e3dd157SKalle Valo #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000 2615e3dd157SKalle Valo #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28 262c3f7f31eSGovind Singh #define RX_MPDU_START_INFO0_FROM_DS BIT(11) 263c3f7f31eSGovind Singh #define RX_MPDU_START_INFO0_TO_DS BIT(12) 264c3f7f31eSGovind Singh #define RX_MPDU_START_INFO0_ENCRYPTED BIT(13) 265c3f7f31eSGovind Singh #define RX_MPDU_START_INFO0_RETRY BIT(14) 266c3f7f31eSGovind Singh #define RX_MPDU_START_INFO0_TXBF_H_INFO BIT(15) 2675e3dd157SKalle Valo 2685e3dd157SKalle Valo #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000 2695e3dd157SKalle Valo #define RX_MPDU_START_INFO1_TID_LSB 28 270c3f7f31eSGovind Singh #define RX_MPDU_START_INFO1_DIRECTED BIT(16) 2715e3dd157SKalle Valo 2725e3dd157SKalle Valo struct rx_mpdu_start { 2735e3dd157SKalle Valo __le32 info0; 2745e3dd157SKalle Valo union { 2755e3dd157SKalle Valo struct { 2765e3dd157SKalle Valo __le32 pn31_0; 2775e3dd157SKalle Valo __le32 info1; /* %RX_MPDU_START_INFO1_ */ 2785e3dd157SKalle Valo } __packed; 2795e3dd157SKalle Valo struct { 2805e3dd157SKalle Valo u8 pn[6]; 2815e3dd157SKalle Valo } __packed; 2825e3dd157SKalle Valo } __packed; 2835e3dd157SKalle Valo } __packed; 2845e3dd157SKalle Valo 2855e3dd157SKalle Valo /* 2865e3dd157SKalle Valo * peer_idx 2875e3dd157SKalle Valo * The index of the address search table which associated with 2885e3dd157SKalle Valo * the peer table entry corresponding to this MPDU. Only valid 2895e3dd157SKalle Valo * when first_msdu is set. 2905e3dd157SKalle Valo * 2915e3dd157SKalle Valo * fr_ds 2925e3dd157SKalle Valo * Set if the from DS bit is set in the frame control. Only 2935e3dd157SKalle Valo * valid when first_msdu is set. 2945e3dd157SKalle Valo * 2955e3dd157SKalle Valo * to_ds 2965e3dd157SKalle Valo * Set if the to DS bit is set in the frame control. Only 2975e3dd157SKalle Valo * valid when first_msdu is set. 2985e3dd157SKalle Valo * 2995e3dd157SKalle Valo * encrypted 3005e3dd157SKalle Valo * Protected bit from the frame control. Only valid when 3015e3dd157SKalle Valo * first_msdu is set. 3025e3dd157SKalle Valo * 3035e3dd157SKalle Valo * retry 3045e3dd157SKalle Valo * Retry bit from the frame control. Only valid when 3055e3dd157SKalle Valo * first_msdu is set. 3065e3dd157SKalle Valo * 3075e3dd157SKalle Valo * txbf_h_info 3085e3dd157SKalle Valo * The MPDU data will contain H information. Primarily used 3095e3dd157SKalle Valo * for debug. 3105e3dd157SKalle Valo * 3115e3dd157SKalle Valo * seq_num 3125e3dd157SKalle Valo * The sequence number from the 802.11 header. Only valid when 3135e3dd157SKalle Valo * first_msdu is set. 3145e3dd157SKalle Valo * 3155e3dd157SKalle Valo * encrypt_type 3165e3dd157SKalle Valo * Indicates type of decrypt cipher used (as defined in the 3175e3dd157SKalle Valo * peer table) 3185e3dd157SKalle Valo * 0: WEP40 3195e3dd157SKalle Valo * 1: WEP104 3205e3dd157SKalle Valo * 2: TKIP without MIC 3215e3dd157SKalle Valo * 3: WEP128 3225e3dd157SKalle Valo * 4: TKIP (WPA) 3235e3dd157SKalle Valo * 5: WAPI 3245e3dd157SKalle Valo * 6: AES-CCM (WPA2) 3255e3dd157SKalle Valo * 7: No cipher 3265e3dd157SKalle Valo * Only valid when first_msdu_is set 3275e3dd157SKalle Valo * 3285e3dd157SKalle Valo * pn_31_0 3295e3dd157SKalle Valo * Bits [31:0] of the PN number extracted from the IV field 3305e3dd157SKalle Valo * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is 3315e3dd157SKalle Valo * valid. 3325e3dd157SKalle Valo * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, 3335e3dd157SKalle Valo * WEPSeed[1], pn1}. Only pn[47:0] is valid. 3345e3dd157SKalle Valo * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, 3355e3dd157SKalle Valo * pn0}. Only pn[47:0] is valid. 3365e3dd157SKalle Valo * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, 3375e3dd157SKalle Valo * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. 3385e3dd157SKalle Valo * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and 3395e3dd157SKalle Valo * pn[47:0] are valid. 3405e3dd157SKalle Valo * Only valid when first_msdu is set. 3415e3dd157SKalle Valo * 3425e3dd157SKalle Valo * pn_47_32 3435e3dd157SKalle Valo * Bits [47:32] of the PN number. See description for 3445e3dd157SKalle Valo * pn_31_0. The remaining PN fields are in the rx_msdu_end 3455e3dd157SKalle Valo * descriptor 3465e3dd157SKalle Valo * 3475e3dd157SKalle Valo * pn 3485e3dd157SKalle Valo * Use this field to access the pn without worrying about 3495e3dd157SKalle Valo * byte-order and bitmasking/bitshifting. 3505e3dd157SKalle Valo * 3515e3dd157SKalle Valo * directed 3525e3dd157SKalle Valo * See definition in RX attention descriptor 3535e3dd157SKalle Valo * 3545e3dd157SKalle Valo * reserved_2 3555e3dd157SKalle Valo * Reserved: HW should fill with zero. FW should ignore. 3565e3dd157SKalle Valo * 3575e3dd157SKalle Valo * tid 3585e3dd157SKalle Valo * The TID field in the QoS control field 3595e3dd157SKalle Valo */ 3605e3dd157SKalle Valo 3615e3dd157SKalle Valo #define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff 3625e3dd157SKalle Valo #define RX_MPDU_END_INFO0_RESERVED_0_LSB 0 3635e3dd157SKalle Valo #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000 3645e3dd157SKalle Valo #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16 365c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_OVERFLOW_ERR BIT(13) 366c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_LAST_MPDU BIT(14) 367c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_POST_DELIM_ERR BIT(15) 368c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR BIT(28) 369c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_TKIP_MIC_ERR BIT(29) 370c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30) 371c3f7f31eSGovind Singh #define RX_MPDU_END_INFO0_FCS_ERR BIT(31) 3725e3dd157SKalle Valo 3735e3dd157SKalle Valo struct rx_mpdu_end { 3745e3dd157SKalle Valo __le32 info0; 3755e3dd157SKalle Valo } __packed; 3765e3dd157SKalle Valo 3775e3dd157SKalle Valo /* 3785e3dd157SKalle Valo * reserved_0 3795e3dd157SKalle Valo * Reserved 3805e3dd157SKalle Valo * 3815e3dd157SKalle Valo * overflow_err 3825e3dd157SKalle Valo * PCU Receive FIFO does not have enough space to store the 3835e3dd157SKalle Valo * full receive packet. Enough space is reserved in the 3845e3dd157SKalle Valo * receive FIFO for the status is written. This MPDU remaining 3855e3dd157SKalle Valo * packets in the PPDU will be filtered and no Ack response 3865e3dd157SKalle Valo * will be transmitted. 3875e3dd157SKalle Valo * 3885e3dd157SKalle Valo * last_mpdu 3895e3dd157SKalle Valo * Indicates that this is the last MPDU of a PPDU. 3905e3dd157SKalle Valo * 3915e3dd157SKalle Valo * post_delim_err 3925e3dd157SKalle Valo * Indicates that a delimiter FCS error occurred after this 3935e3dd157SKalle Valo * MPDU before the next MPDU. Only valid when last_msdu is 3945e3dd157SKalle Valo * set. 3955e3dd157SKalle Valo * 3965e3dd157SKalle Valo * post_delim_cnt 3975e3dd157SKalle Valo * Count of the delimiters after this MPDU. This requires the 3985e3dd157SKalle Valo * last MPDU to be held until all the EOF descriptors have been 3995e3dd157SKalle Valo * received. This may be inefficient in the future when 4005e3dd157SKalle Valo * ML-MIMO is used. Only valid when last_mpdu is set. 4015e3dd157SKalle Valo * 4025e3dd157SKalle Valo * mpdu_length_err 4035e3dd157SKalle Valo * See definition in RX attention descriptor 4045e3dd157SKalle Valo * 4055e3dd157SKalle Valo * tkip_mic_err 4065e3dd157SKalle Valo * See definition in RX attention descriptor 4075e3dd157SKalle Valo * 4085e3dd157SKalle Valo * decrypt_err 4095e3dd157SKalle Valo * See definition in RX attention descriptor 4105e3dd157SKalle Valo * 4115e3dd157SKalle Valo * fcs_err 4125e3dd157SKalle Valo * See definition in RX attention descriptor 4135e3dd157SKalle Valo */ 4145e3dd157SKalle Valo 4155e3dd157SKalle Valo #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff 4165e3dd157SKalle Valo #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0 4175e3dd157SKalle Valo #define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000 4185e3dd157SKalle Valo #define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14 4195e3dd157SKalle Valo #define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000 4205e3dd157SKalle Valo #define RX_MSDU_START_INFO0_RING_MASK_LSB 20 4215e3dd157SKalle Valo #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000 4225e3dd157SKalle Valo #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24 4235e3dd157SKalle Valo 4245e3dd157SKalle Valo #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff 4255e3dd157SKalle Valo #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0 4265e3dd157SKalle Valo #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300 4275e3dd157SKalle Valo #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8 4285e3dd157SKalle Valo #define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000 4295e3dd157SKalle Valo #define RX_MSDU_START_INFO1_SA_IDX_LSB 16 430c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_IPV4_PROTO BIT(10) 431c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_IPV6_PROTO BIT(11) 432c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_TCP_PROTO BIT(12) 433c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_UDP_PROTO BIT(13) 434c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_IP_FRAG BIT(14) 435c3f7f31eSGovind Singh #define RX_MSDU_START_INFO1_TCP_ONLY_ACK BIT(15) 4365e3dd157SKalle Valo 4371f5dbfbbSPeter Oh #define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff 4381f5dbfbbSPeter Oh #define RX_MSDU_START_INFO2_DA_IDX_LSB 0 4391f5dbfbbSPeter Oh #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000 4401f5dbfbbSPeter Oh #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16 4411f5dbfbbSPeter Oh #define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11) 4421f5dbfbbSPeter Oh 44326d1e9c2SMichal Kazior /* The decapped header (rx_hdr_status) contains the following: 44426d1e9c2SMichal Kazior * a) 802.11 header 44526d1e9c2SMichal Kazior * [padding to 4 bytes] 44626d1e9c2SMichal Kazior * b) HW crypto parameter 44726d1e9c2SMichal Kazior * - 0 bytes for no security 44826d1e9c2SMichal Kazior * - 4 bytes for WEP 44926d1e9c2SMichal Kazior * - 8 bytes for TKIP, AES 45026d1e9c2SMichal Kazior * [padding to 4 bytes] 45126d1e9c2SMichal Kazior * c) A-MSDU subframe header (14 bytes) if appliable 45226d1e9c2SMichal Kazior * d) LLC/SNAP (RFC1042, 8 bytes) 45326d1e9c2SMichal Kazior * 45437ff1b0dSMarcin Rokicki * In case of A-MSDU only first frame in sequence contains (a) and (b). 45537ff1b0dSMarcin Rokicki */ 4565e3dd157SKalle Valo enum rx_msdu_decap_format { 4575e3dd157SKalle Valo RX_MSDU_DECAP_RAW = 0, 45826d1e9c2SMichal Kazior 45926d1e9c2SMichal Kazior /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in 46037ff1b0dSMarcin Rokicki * htt_rx_desc contains the original decapped 802.11 header. 46137ff1b0dSMarcin Rokicki */ 4625e3dd157SKalle Valo RX_MSDU_DECAP_NATIVE_WIFI = 1, 46326d1e9c2SMichal Kazior 46426d1e9c2SMichal Kazior /* Payload contains an ethernet header (struct ethhdr). */ 4655e3dd157SKalle Valo RX_MSDU_DECAP_ETHERNET2_DIX = 2, 46626d1e9c2SMichal Kazior 46726d1e9c2SMichal Kazior /* Payload contains two 48-bit addresses and 2-byte length (14 bytes 46837ff1b0dSMarcin Rokicki * total), followed by an RFC1042 header (8 bytes). 46937ff1b0dSMarcin Rokicki */ 4705e3dd157SKalle Valo RX_MSDU_DECAP_8023_SNAP_LLC = 3 4715e3dd157SKalle Valo }; 4725e3dd157SKalle Valo 4731f5dbfbbSPeter Oh struct rx_msdu_start_common { 4745e3dd157SKalle Valo __le32 info0; /* %RX_MSDU_START_INFO0_ */ 4755e3dd157SKalle Valo __le32 flow_id_crc; 4765e3dd157SKalle Valo __le32 info1; /* %RX_MSDU_START_INFO1_ */ 4775e3dd157SKalle Valo } __packed; 4785e3dd157SKalle Valo 4791f5dbfbbSPeter Oh struct rx_msdu_start_qca99x0 { 4801f5dbfbbSPeter Oh __le32 info2; /* %RX_MSDU_START_INFO2_ */ 4811f5dbfbbSPeter Oh } __packed; 4821f5dbfbbSPeter Oh 483e3def6f7SGovind Singh struct rx_msdu_start_wcn3990 { 484e3def6f7SGovind Singh __le32 info2; /* %RX_MSDU_START_INFO2_ */ 485e3def6f7SGovind Singh __le32 info3; /* %RX_MSDU_START_INFO3_ */ 486e3def6f7SGovind Singh } __packed; 487e3def6f7SGovind Singh 4881f5dbfbbSPeter Oh struct rx_msdu_start { 4891f5dbfbbSPeter Oh struct rx_msdu_start_common common; 4901f5dbfbbSPeter Oh union { 491e3def6f7SGovind Singh struct rx_msdu_start_wcn3990 wcn3990; 4921f5dbfbbSPeter Oh } __packed; 4931f5dbfbbSPeter Oh } __packed; 4941f5dbfbbSPeter Oh 495*6bae9de6SFrancesco Magliocca struct rx_msdu_start_v1 { 496*6bae9de6SFrancesco Magliocca struct rx_msdu_start_common common; 497*6bae9de6SFrancesco Magliocca union { 498*6bae9de6SFrancesco Magliocca struct rx_msdu_start_qca99x0 qca99x0; 499*6bae9de6SFrancesco Magliocca } __packed; 500*6bae9de6SFrancesco Magliocca } __packed; 501*6bae9de6SFrancesco Magliocca 5025e3dd157SKalle Valo /* 5035e3dd157SKalle Valo * msdu_length 5045e3dd157SKalle Valo * MSDU length in bytes after decapsulation. This field is 5055e3dd157SKalle Valo * still valid for MPDU frames without A-MSDU. It still 5065e3dd157SKalle Valo * represents MSDU length after decapsulation 5075e3dd157SKalle Valo * 5085e3dd157SKalle Valo * ip_offset 5095e3dd157SKalle Valo * Indicates the IP offset in bytes from the start of the 5105e3dd157SKalle Valo * packet after decapsulation. Only valid if ipv4_proto or 5115e3dd157SKalle Valo * ipv6_proto is set. 5125e3dd157SKalle Valo * 5135e3dd157SKalle Valo * ring_mask 5145e3dd157SKalle Valo * Indicates the destination RX rings for this MSDU. 5155e3dd157SKalle Valo * 5165e3dd157SKalle Valo * tcp_udp_offset 5175e3dd157SKalle Valo * Indicates the offset in bytes to the start of TCP or UDP 5185e3dd157SKalle Valo * header from the start of the IP header after decapsulation. 5195e3dd157SKalle Valo * Only valid if tcp_prot or udp_prot is set. The value 0 5205e3dd157SKalle Valo * indicates that the offset is longer than 127 bytes. 5215e3dd157SKalle Valo * 5225e3dd157SKalle Valo * reserved_0c 5235e3dd157SKalle Valo * Reserved: HW should fill with zero. FW should ignore. 5245e3dd157SKalle Valo * 5255e3dd157SKalle Valo * flow_id_crc 5265e3dd157SKalle Valo * The flow_id_crc runs CRC32 on the following information: 5275e3dd157SKalle Valo * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0, 5285e3dd157SKalle Valo * protocol[7:0]}. 5295e3dd157SKalle Valo * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0, 5305e3dd157SKalle Valo * next_header[7:0]} 5315e3dd157SKalle Valo * UDP case: sort_port[15:0], dest_port[15:0] 5325e3dd157SKalle Valo * TCP case: sort_port[15:0], dest_port[15:0], 5335e3dd157SKalle Valo * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]}, 5345e3dd157SKalle Valo * {16'b0, urgent_ptr[15:0]}, all options except 32-bit 5355e3dd157SKalle Valo * timestamp. 5365e3dd157SKalle Valo * 5375e3dd157SKalle Valo * msdu_number 5385e3dd157SKalle Valo * Indicates the MSDU number within a MPDU. This value is 5395e3dd157SKalle Valo * reset to zero at the start of each MPDU. If the number of 5405e3dd157SKalle Valo * MSDU exceeds 255 this number will wrap using modulo 256. 5415e3dd157SKalle Valo * 5425e3dd157SKalle Valo * decap_format 5435e3dd157SKalle Valo * Indicates the format after decapsulation: 5445e3dd157SKalle Valo * 0: RAW: No decapsulation 5455e3dd157SKalle Valo * 1: Native WiFi 5465e3dd157SKalle Valo * 2: Ethernet 2 (DIX) 5475e3dd157SKalle Valo * 3: 802.3 (SNAP/LLC) 5485e3dd157SKalle Valo * 5495e3dd157SKalle Valo * ipv4_proto 5505e3dd157SKalle Valo * Set if L2 layer indicates IPv4 protocol. 5515e3dd157SKalle Valo * 5525e3dd157SKalle Valo * ipv6_proto 5535e3dd157SKalle Valo * Set if L2 layer indicates IPv6 protocol. 5545e3dd157SKalle Valo * 5555e3dd157SKalle Valo * tcp_proto 5565e3dd157SKalle Valo * Set if the ipv4_proto or ipv6_proto are set and the IP 5575e3dd157SKalle Valo * protocol indicates TCP. 5585e3dd157SKalle Valo * 5595e3dd157SKalle Valo * udp_proto 5605e3dd157SKalle Valo * Set if the ipv4_proto or ipv6_proto are set and the IP 5615e3dd157SKalle Valo * protocol indicates UDP. 5625e3dd157SKalle Valo * 5635e3dd157SKalle Valo * ip_frag 5645e3dd157SKalle Valo * Indicates that either the IP More frag bit is set or IP frag 5655e3dd157SKalle Valo * number is non-zero. If set indicates that this is a 5665e3dd157SKalle Valo * fragmented IP packet. 5675e3dd157SKalle Valo * 5685e3dd157SKalle Valo * tcp_only_ack 5695e3dd157SKalle Valo * Set if only the TCP Ack bit is set in the TCP flags and if 5705e3dd157SKalle Valo * the TCP payload is 0. 5715e3dd157SKalle Valo * 5725e3dd157SKalle Valo * sa_idx 5735e3dd157SKalle Valo * The offset in the address table which matches the MAC source 5745e3dd157SKalle Valo * address. 5755e3dd157SKalle Valo * 5765e3dd157SKalle Valo * reserved_2b 5775e3dd157SKalle Valo * Reserved: HW should fill with zero. FW should ignore. 5785e3dd157SKalle Valo */ 5795e3dd157SKalle Valo 5805e3dd157SKalle Valo #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff 5815e3dd157SKalle Valo #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0 582c3f7f31eSGovind Singh #define RX_MSDU_END_INFO0_FIRST_MSDU BIT(14) 583c3f7f31eSGovind Singh #define RX_MSDU_END_INFO0_LAST_MSDU BIT(15) 584a2864772SBhagavathi Perumal S #define RX_MSDU_END_INFO0_MSDU_LIMIT_ERR BIT(18) 585c3f7f31eSGovind Singh #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30) 586c3f7f31eSGovind Singh #define RX_MSDU_END_INFO0_RESERVED_3B BIT(31) 5875e3dd157SKalle Valo 5881f5dbfbbSPeter Oh struct rx_msdu_end_common { 5895e3dd157SKalle Valo __le16 ip_hdr_cksum; 5905e3dd157SKalle Valo __le16 tcp_hdr_cksum; 5915e3dd157SKalle Valo u8 key_id_octet; 5925e3dd157SKalle Valo u8 classification_filter; 5935e3dd157SKalle Valo u8 wapi_pn[10]; 5945e3dd157SKalle Valo __le32 info0; 5955e3dd157SKalle Valo } __packed; 5965e3dd157SKalle Valo 5971f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff 5981f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0 5991f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00 6001f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10 6011f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000 6021f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16 6031f5dbfbbSPeter Oh #define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9) 6041f5dbfbbSPeter Oh 6051f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f 6061f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0 6071f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0 6081f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6 6091f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000 6101f5dbfbbSPeter Oh #define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12 6111f5dbfbbSPeter Oh 6121f5dbfbbSPeter Oh struct rx_msdu_end_qca99x0 { 6131f5dbfbbSPeter Oh __le32 ipv6_crc; 6141f5dbfbbSPeter Oh __le32 tcp_seq_no; 6151f5dbfbbSPeter Oh __le32 tcp_ack_no; 6161f5dbfbbSPeter Oh __le32 info1; 6171f5dbfbbSPeter Oh __le32 info2; 6181f5dbfbbSPeter Oh } __packed; 6191f5dbfbbSPeter Oh 620e3def6f7SGovind Singh struct rx_msdu_end_wcn3990 { 621e3def6f7SGovind Singh __le32 ipv6_crc; 622e3def6f7SGovind Singh __le32 tcp_seq_no; 623e3def6f7SGovind Singh __le32 tcp_ack_no; 624e3def6f7SGovind Singh __le32 info1; 625e3def6f7SGovind Singh __le32 info2; 626e3def6f7SGovind Singh __le32 rule_indication_0; 627e3def6f7SGovind Singh __le32 rule_indication_1; 628e3def6f7SGovind Singh __le32 rule_indication_2; 629e3def6f7SGovind Singh __le32 rule_indication_3; 630e3def6f7SGovind Singh } __packed; 631e3def6f7SGovind Singh 6321f5dbfbbSPeter Oh struct rx_msdu_end { 6331f5dbfbbSPeter Oh struct rx_msdu_end_common common; 6341f5dbfbbSPeter Oh union { 635e3def6f7SGovind Singh struct rx_msdu_end_wcn3990 wcn3990; 6361f5dbfbbSPeter Oh } __packed; 6371f5dbfbbSPeter Oh } __packed; 6381f5dbfbbSPeter Oh 639*6bae9de6SFrancesco Magliocca struct rx_msdu_end_v1 { 640*6bae9de6SFrancesco Magliocca struct rx_msdu_end_common common; 641*6bae9de6SFrancesco Magliocca union { 642*6bae9de6SFrancesco Magliocca struct rx_msdu_end_qca99x0 qca99x0; 643*6bae9de6SFrancesco Magliocca } __packed; 644*6bae9de6SFrancesco Magliocca } __packed; 645*6bae9de6SFrancesco Magliocca 6465e3dd157SKalle Valo /* 6475e3dd157SKalle Valo *ip_hdr_chksum 6485e3dd157SKalle Valo * This can include the IP header checksum or the pseudo header 6495e3dd157SKalle Valo * checksum used by TCP/UDP checksum. 6505e3dd157SKalle Valo * 6515e3dd157SKalle Valo *tcp_udp_chksum 6525e3dd157SKalle Valo * The value of the computed TCP/UDP checksum. A mode bit 6535e3dd157SKalle Valo * selects whether this checksum is the full checksum or the 6545e3dd157SKalle Valo * partial checksum which does not include the pseudo header. 6555e3dd157SKalle Valo * 6565e3dd157SKalle Valo *key_id_octet 6575e3dd157SKalle Valo * The key ID octet from the IV. Only valid when first_msdu is 6585e3dd157SKalle Valo * set. 6595e3dd157SKalle Valo * 6605e3dd157SKalle Valo *classification_filter 6615e3dd157SKalle Valo * Indicates the number classification filter rule 6625e3dd157SKalle Valo * 6635e3dd157SKalle Valo *ext_wapi_pn_63_48 6645e3dd157SKalle Valo * Extension PN (packet number) which is only used by WAPI. 6655e3dd157SKalle Valo * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The 6665e3dd157SKalle Valo * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start 6675e3dd157SKalle Valo * descriptor. 6685e3dd157SKalle Valo * 6695e3dd157SKalle Valo *ext_wapi_pn_95_64 6705e3dd157SKalle Valo * Extension PN (packet number) which is only used by WAPI. 6715e3dd157SKalle Valo * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and 6725e3dd157SKalle Valo * pn11). 6735e3dd157SKalle Valo * 6745e3dd157SKalle Valo *ext_wapi_pn_127_96 6755e3dd157SKalle Valo * Extension PN (packet number) which is only used by WAPI. 6765e3dd157SKalle Valo * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14, 6775e3dd157SKalle Valo * pn15). 6785e3dd157SKalle Valo * 6795e3dd157SKalle Valo *reported_mpdu_length 6805e3dd157SKalle Valo * MPDU length before decapsulation. Only valid when 6815e3dd157SKalle Valo * first_msdu is set. This field is taken directly from the 6825e3dd157SKalle Valo * length field of the A-MPDU delimiter or the preamble length 6835e3dd157SKalle Valo * field for non-A-MPDU frames. 6845e3dd157SKalle Valo * 6855e3dd157SKalle Valo *first_msdu 6865e3dd157SKalle Valo * Indicates the first MSDU of A-MSDU. If both first_msdu and 6875e3dd157SKalle Valo * last_msdu are set in the MSDU then this is a non-aggregated 6885e3dd157SKalle Valo * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall 6895e3dd157SKalle Valo * have both first_mpdu and last_mpdu bits set to 0. 6905e3dd157SKalle Valo * 6915e3dd157SKalle Valo *last_msdu 6925e3dd157SKalle Valo * Indicates the last MSDU of the A-MSDU. MPDU end status is 6935e3dd157SKalle Valo * only valid when last_msdu is set. 6945e3dd157SKalle Valo * 695a2864772SBhagavathi Perumal S *msdu_limit_error 696a2864772SBhagavathi Perumal S * Indicates that the MSDU threshold was exceeded and thus 697a2864772SBhagavathi Perumal S * all the rest of the MSDUs will not be scattered and 698a2864772SBhagavathi Perumal S * will not be decapsulated but will be received in RAW format 699a2864772SBhagavathi Perumal S * as a single MSDU buffer. 700a2864772SBhagavathi Perumal S * 7015e3dd157SKalle Valo *reserved_3a 7025e3dd157SKalle Valo * Reserved: HW should fill with zero. FW should ignore. 7035e3dd157SKalle Valo * 7045e3dd157SKalle Valo *pre_delim_err 7055e3dd157SKalle Valo * Indicates that the first delimiter had a FCS failure. Only 7065e3dd157SKalle Valo * valid when first_mpdu and first_msdu are set. 7075e3dd157SKalle Valo * 7085e3dd157SKalle Valo *reserved_3b 7095e3dd157SKalle Valo * Reserved: HW should fill with zero. FW should ignore. 7105e3dd157SKalle Valo */ 7115e3dd157SKalle Valo 7125e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04 7135e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_HT 0x08 7145e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09 7155e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C 7165e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D 7175e3dd157SKalle Valo 718c3f7f31eSGovind Singh #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0) 7195e3dd157SKalle Valo 7205e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f 7215e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0 7225e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0 7235e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5 7245e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000 7255e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18 7265e3dd157SKalle Valo #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000 7275e3dd157SKalle Valo #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24 728c3f7f31eSGovind Singh #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT BIT(4) 729c3f7f31eSGovind Singh #define RX_PPDU_START_INFO1_L_SIG_PARITY BIT(17) 7305e3dd157SKalle Valo 7315e3dd157SKalle Valo #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff 7325e3dd157SKalle Valo #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0 7335e3dd157SKalle Valo 7345e3dd157SKalle Valo #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff 7355e3dd157SKalle Valo #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0 736c3f7f31eSGovind Singh #define RX_PPDU_START_INFO3_TXBF_H_INFO BIT(24) 7375e3dd157SKalle Valo 7385e3dd157SKalle Valo #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff 7395e3dd157SKalle Valo #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0 7405e3dd157SKalle Valo 7415e3dd157SKalle Valo #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff 7425e3dd157SKalle Valo #define RX_PPDU_START_INFO5_SERVICE_LSB 0 7435e3dd157SKalle Valo 7446aa4cf1cSMichal Kazior /* No idea what this flag means. It seems to be always set in rate. */ 7456aa4cf1cSMichal Kazior #define RX_PPDU_START_RATE_FLAG BIT(3) 7466aa4cf1cSMichal Kazior 7475e3dd157SKalle Valo struct rx_ppdu_start { 7485e3dd157SKalle Valo struct { 7495e3dd157SKalle Valo u8 pri20_mhz; 7505e3dd157SKalle Valo u8 ext20_mhz; 7515e3dd157SKalle Valo u8 ext40_mhz; 7525e3dd157SKalle Valo u8 ext80_mhz; 7535e3dd157SKalle Valo } rssi_chains[4]; 7545e3dd157SKalle Valo u8 rssi_comb; 7555e3dd157SKalle Valo __le16 rsvd0; 7565e3dd157SKalle Valo u8 info0; /* %RX_PPDU_START_INFO0_ */ 7575e3dd157SKalle Valo __le32 info1; /* %RX_PPDU_START_INFO1_ */ 7585e3dd157SKalle Valo __le32 info2; /* %RX_PPDU_START_INFO2_ */ 7595e3dd157SKalle Valo __le32 info3; /* %RX_PPDU_START_INFO3_ */ 7605e3dd157SKalle Valo __le32 info4; /* %RX_PPDU_START_INFO4_ */ 7615e3dd157SKalle Valo __le32 info5; /* %RX_PPDU_START_INFO5_ */ 7625e3dd157SKalle Valo } __packed; 7635e3dd157SKalle Valo 7645e3dd157SKalle Valo /* 7655e3dd157SKalle Valo * rssi_chain0_pri20 7665e3dd157SKalle Valo * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 7675e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7685e3dd157SKalle Valo * 7695e3dd157SKalle Valo * rssi_chain0_sec20 7705e3dd157SKalle Valo * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth. 7715e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7725e3dd157SKalle Valo * 7735e3dd157SKalle Valo * rssi_chain0_sec40 7745e3dd157SKalle Valo * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth. 7755e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7765e3dd157SKalle Valo * 7775e3dd157SKalle Valo * rssi_chain0_sec80 7785e3dd157SKalle Valo * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth. 7795e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7805e3dd157SKalle Valo * 7815e3dd157SKalle Valo * rssi_chain1_pri20 7825e3dd157SKalle Valo * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 7835e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7845e3dd157SKalle Valo * 7855e3dd157SKalle Valo * rssi_chain1_sec20 7865e3dd157SKalle Valo * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth. 7875e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7885e3dd157SKalle Valo * 7895e3dd157SKalle Valo * rssi_chain1_sec40 7905e3dd157SKalle Valo * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth. 7915e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7925e3dd157SKalle Valo * 7935e3dd157SKalle Valo * rssi_chain1_sec80 7945e3dd157SKalle Valo * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth. 7955e3dd157SKalle Valo * Value of 0x80 indicates invalid. 7965e3dd157SKalle Valo * 7975e3dd157SKalle Valo * rssi_chain2_pri20 7985e3dd157SKalle Valo * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 7995e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8005e3dd157SKalle Valo * 8015e3dd157SKalle Valo * rssi_chain2_sec20 8025e3dd157SKalle Valo * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth. 8035e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8045e3dd157SKalle Valo * 8055e3dd157SKalle Valo * rssi_chain2_sec40 8065e3dd157SKalle Valo * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth. 8075e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8085e3dd157SKalle Valo * 8095e3dd157SKalle Valo * rssi_chain2_sec80 8105e3dd157SKalle Valo * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth. 8115e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8125e3dd157SKalle Valo * 8135e3dd157SKalle Valo * rssi_chain3_pri20 8145e3dd157SKalle Valo * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 8155e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8165e3dd157SKalle Valo * 8175e3dd157SKalle Valo * rssi_chain3_sec20 8185e3dd157SKalle Valo * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth. 8195e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8205e3dd157SKalle Valo * 8215e3dd157SKalle Valo * rssi_chain3_sec40 8225e3dd157SKalle Valo * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth. 8235e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8245e3dd157SKalle Valo * 8255e3dd157SKalle Valo * rssi_chain3_sec80 8265e3dd157SKalle Valo * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth. 8275e3dd157SKalle Valo * Value of 0x80 indicates invalid. 8285e3dd157SKalle Valo * 8295e3dd157SKalle Valo * rssi_comb 8305e3dd157SKalle Valo * The combined RSSI of RX PPDU of all active chains and 8315e3dd157SKalle Valo * bandwidths. Value of 0x80 indicates invalid. 8325e3dd157SKalle Valo * 8335e3dd157SKalle Valo * reserved_4a 8345e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 8355e3dd157SKalle Valo * 8365e3dd157SKalle Valo * is_greenfield 8375e3dd157SKalle Valo * Do we really support this? 8385e3dd157SKalle Valo * 8395e3dd157SKalle Valo * reserved_4b 8405e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 8415e3dd157SKalle Valo * 8425e3dd157SKalle Valo * l_sig_rate 8435e3dd157SKalle Valo * If l_sig_rate_select is 0: 8445e3dd157SKalle Valo * 0x8: OFDM 48 Mbps 8455e3dd157SKalle Valo * 0x9: OFDM 24 Mbps 8465e3dd157SKalle Valo * 0xA: OFDM 12 Mbps 8475e3dd157SKalle Valo * 0xB: OFDM 6 Mbps 8485e3dd157SKalle Valo * 0xC: OFDM 54 Mbps 8495e3dd157SKalle Valo * 0xD: OFDM 36 Mbps 8505e3dd157SKalle Valo * 0xE: OFDM 18 Mbps 8515e3dd157SKalle Valo * 0xF: OFDM 9 Mbps 8525e3dd157SKalle Valo * If l_sig_rate_select is 1: 8535e3dd157SKalle Valo * 0x8: CCK 11 Mbps long preamble 8545e3dd157SKalle Valo * 0x9: CCK 5.5 Mbps long preamble 8555e3dd157SKalle Valo * 0xA: CCK 2 Mbps long preamble 8565e3dd157SKalle Valo * 0xB: CCK 1 Mbps long preamble 8575e3dd157SKalle Valo * 0xC: CCK 11 Mbps short preamble 8585e3dd157SKalle Valo * 0xD: CCK 5.5 Mbps short preamble 8595e3dd157SKalle Valo * 0xE: CCK 2 Mbps short preamble 8605e3dd157SKalle Valo * 8615e3dd157SKalle Valo * l_sig_rate_select 8625e3dd157SKalle Valo * Legacy signal rate select. If set then l_sig_rate indicates 8635e3dd157SKalle Valo * CCK rates. If clear then l_sig_rate indicates OFDM rates. 8645e3dd157SKalle Valo * 8655e3dd157SKalle Valo * l_sig_length 8665e3dd157SKalle Valo * Length of legacy frame in octets. 8675e3dd157SKalle Valo * 8685e3dd157SKalle Valo * l_sig_parity 8695e3dd157SKalle Valo * Odd parity over l_sig_rate and l_sig_length 8705e3dd157SKalle Valo * 8715e3dd157SKalle Valo * l_sig_tail 8725e3dd157SKalle Valo * Tail bits for Viterbi decoder 8735e3dd157SKalle Valo * 8745e3dd157SKalle Valo * preamble_type 8755e3dd157SKalle Valo * Indicates the type of preamble ahead: 8765e3dd157SKalle Valo * 0x4: Legacy (OFDM/CCK) 8775e3dd157SKalle Valo * 0x8: HT 8785e3dd157SKalle Valo * 0x9: HT with TxBF 8795e3dd157SKalle Valo * 0xC: VHT 8805e3dd157SKalle Valo * 0xD: VHT with TxBF 8815e3dd157SKalle Valo * 0x80 - 0xFF: Reserved for special baseband data types such 8825e3dd157SKalle Valo * as radar and spectral scan. 8835e3dd157SKalle Valo * 8845e3dd157SKalle Valo * ht_sig_vht_sig_a_1 8855e3dd157SKalle Valo * If preamble_type == 0x8 or 0x9 8865e3dd157SKalle Valo * HT-SIG (first 24 bits) 8875e3dd157SKalle Valo * If preamble_type == 0xC or 0xD 8885e3dd157SKalle Valo * VHT-SIG A (first 24 bits) 8895e3dd157SKalle Valo * Else 8905e3dd157SKalle Valo * Reserved 8915e3dd157SKalle Valo * 8925e3dd157SKalle Valo * reserved_6 8935e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 8945e3dd157SKalle Valo * 8955e3dd157SKalle Valo * ht_sig_vht_sig_a_2 8965e3dd157SKalle Valo * If preamble_type == 0x8 or 0x9 8975e3dd157SKalle Valo * HT-SIG (last 24 bits) 8985e3dd157SKalle Valo * If preamble_type == 0xC or 0xD 8995e3dd157SKalle Valo * VHT-SIG A (last 24 bits) 9005e3dd157SKalle Valo * Else 9015e3dd157SKalle Valo * Reserved 9025e3dd157SKalle Valo * 9035e3dd157SKalle Valo * txbf_h_info 9045e3dd157SKalle Valo * Indicates that the packet data carries H information which 9055e3dd157SKalle Valo * is used for TxBF debug. 9065e3dd157SKalle Valo * 9075e3dd157SKalle Valo * reserved_7 9085e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 9095e3dd157SKalle Valo * 9105e3dd157SKalle Valo * vht_sig_b 9115e3dd157SKalle Valo * WiFi 1.0 and WiFi 2.0 will likely have this field to be all 9125e3dd157SKalle Valo * 0s since the BB does not plan on decoding VHT SIG-B. 9135e3dd157SKalle Valo * 9145e3dd157SKalle Valo * reserved_8 9155e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 9165e3dd157SKalle Valo * 9175e3dd157SKalle Valo * service 9185e3dd157SKalle Valo * Service field from BB for OFDM, HT and VHT packets. CCK 9195e3dd157SKalle Valo * packets will have service field of 0. 9205e3dd157SKalle Valo * 9215e3dd157SKalle Valo * reserved_9 9225e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 9235e3dd157SKalle Valo */ 9245e3dd157SKalle Valo 925c3f7f31eSGovind Singh #define RX_PPDU_END_FLAGS_PHY_ERR BIT(0) 926c3f7f31eSGovind Singh #define RX_PPDU_END_FLAGS_RX_LOCATION BIT(1) 927c3f7f31eSGovind Singh #define RX_PPDU_END_FLAGS_TXBF_H_INFO BIT(2) 9285e3dd157SKalle Valo 9295e3dd157SKalle Valo #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff 9305e3dd157SKalle Valo #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0 931c3f7f31eSGovind Singh #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK BIT(24) 932c3f7f31eSGovind Singh #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL BIT(25) 9335e3dd157SKalle Valo 9341f5dbfbbSPeter Oh #define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc 9351f5dbfbbSPeter Oh #define RX_PPDU_END_INFO1_PEER_IDX_LSB 2 9361f5dbfbbSPeter Oh #define RX_PPDU_END_INFO1_BB_DATA BIT(0) 9371f5dbfbbSPeter Oh #define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1) 9381f5dbfbbSPeter Oh #define RX_PPDU_END_INFO1_PPDU_DONE BIT(15) 9395e3dd157SKalle Valo 9403ec79e3aSMichal Kazior struct rx_ppdu_end_common { 9415e3dd157SKalle Valo __le32 evm_p0; 9425e3dd157SKalle Valo __le32 evm_p1; 9435e3dd157SKalle Valo __le32 evm_p2; 9445e3dd157SKalle Valo __le32 evm_p3; 9455e3dd157SKalle Valo __le32 evm_p4; 9465e3dd157SKalle Valo __le32 evm_p5; 9475e3dd157SKalle Valo __le32 evm_p6; 9485e3dd157SKalle Valo __le32 evm_p7; 9495e3dd157SKalle Valo __le32 evm_p8; 9505e3dd157SKalle Valo __le32 evm_p9; 9515e3dd157SKalle Valo __le32 evm_p10; 9525e3dd157SKalle Valo __le32 evm_p11; 9535e3dd157SKalle Valo __le32 evm_p12; 9545e3dd157SKalle Valo __le32 evm_p13; 9555e3dd157SKalle Valo __le32 evm_p14; 9565e3dd157SKalle Valo __le32 evm_p15; 9575e3dd157SKalle Valo __le32 tsf_timestamp; 9585e3dd157SKalle Valo __le32 wb_timestamp; 95905a2cb0dSPeter Oh } __packed; 96005a2cb0dSPeter Oh 96105a2cb0dSPeter Oh struct rx_ppdu_end_qca988x { 9625e3dd157SKalle Valo u8 locationing_timestamp; 9635e3dd157SKalle Valo u8 phy_err_code; 9645e3dd157SKalle Valo __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 9655e3dd157SKalle Valo __le32 info0; /* %RX_PPDU_END_INFO0_ */ 9665e3dd157SKalle Valo __le16 bb_length; 9675e3dd157SKalle Valo __le16 info1; /* %RX_PPDU_END_INFO1_ */ 9685e3dd157SKalle Valo } __packed; 9695e3dd157SKalle Valo 9703ec79e3aSMichal Kazior #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff 9713ec79e3aSMichal Kazior #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0 9723ec79e3aSMichal Kazior #define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000 9733ec79e3aSMichal Kazior #define RX_PPDU_END_RTT_UNUSED_LSB 24 9743ec79e3aSMichal Kazior #define RX_PPDU_END_RTT_NORMAL_MODE BIT(31) 9753ec79e3aSMichal Kazior 9763ec79e3aSMichal Kazior struct rx_ppdu_end_qca6174 { 97705a2cb0dSPeter Oh u8 locationing_timestamp; 97805a2cb0dSPeter Oh u8 phy_err_code; 97905a2cb0dSPeter Oh __le16 flags; /* %RX_PPDU_END_FLAGS_ */ 98005a2cb0dSPeter Oh __le32 info0; /* %RX_PPDU_END_INFO0_ */ 9813ec79e3aSMichal Kazior __le32 rtt; /* %RX_PPDU_END_RTT_ */ 9823ec79e3aSMichal Kazior __le16 bb_length; 9833ec79e3aSMichal Kazior __le16 info1; /* %RX_PPDU_END_INFO1_ */ 9843ec79e3aSMichal Kazior } __packed; 9853ec79e3aSMichal Kazior 9861f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_RX_SUCCESS BIT(0) 9871f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3) 9881f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4) 9891f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5) 9901f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6) 9911f5dbfbbSPeter Oh #define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7) 9921f5dbfbbSPeter Oh 9931f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff 9941f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0 9951f5dbfbbSPeter Oh #define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000 9961f5dbfbbSPeter Oh #define RX_LOCATION_INFO_FAC_STATUS_LSB 18 9971f5dbfbbSPeter Oh #define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000 9981f5dbfbbSPeter Oh #define RX_LOCATION_INFO_PKT_BW_LSB 20 9991f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000 10001f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23 10011f5dbfbbSPeter Oh #define RX_LOCATION_INFO_CIR_STATUS BIT(17) 10021f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25) 10031f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26) 10041f5dbfbbSPeter Oh #define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30) 10051f5dbfbbSPeter Oh #define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31) 10061f5dbfbbSPeter Oh 10071f5dbfbbSPeter Oh struct rx_pkt_end { 10081f5dbfbbSPeter Oh __le32 info0; /* %RX_PKT_END_INFO0_ */ 10091f5dbfbbSPeter Oh __le32 phy_timestamp_1; 10101f5dbfbbSPeter Oh __le32 phy_timestamp_2; 10111f5dbfbbSPeter Oh } __packed; 10121f5dbfbbSPeter Oh 1013e3def6f7SGovind Singh struct rx_pkt_end_wcn3990 { 1014e3def6f7SGovind Singh __le32 info0; /* %RX_PKT_END_INFO0_ */ 1015e3def6f7SGovind Singh __le64 phy_timestamp_1; 1016e3def6f7SGovind Singh __le64 phy_timestamp_2; 1017e3def6f7SGovind Singh } __packed; 1018e3def6f7SGovind Singh 1019acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff 1020acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0 1021acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000 1022acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15 1023acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000 1024acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30 1025acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14) 1026acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29) 1027acc6b559SVasanthakumar Thiagarajan 1028acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c 1029acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2 1030acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030 1031acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_PKT_BW_LSB 4 1032acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00 1033acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8 1034acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000 1035acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16 1036acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000 1037acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20 1038acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000 1039acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22 1040acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000 1041acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27 1042acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0) 1043acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1) 1044acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7) 1045acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29) 1046acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30) 1047acc6b559SVasanthakumar Thiagarajan #define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31) 1048acc6b559SVasanthakumar Thiagarajan 1049acc6b559SVasanthakumar Thiagarajan struct rx_location_info { 1050acc6b559SVasanthakumar Thiagarajan __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1051acc6b559SVasanthakumar Thiagarajan __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1052acc6b559SVasanthakumar Thiagarajan } __packed; 1053acc6b559SVasanthakumar Thiagarajan 1054e3def6f7SGovind Singh struct rx_location_info_wcn3990 { 1055e3def6f7SGovind Singh __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */ 1056e3def6f7SGovind Singh __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */ 1057e3def6f7SGovind Singh __le32 rx_location_info2; /* %RX_LOCATION_INFO2_ */ 1058e3def6f7SGovind Singh } __packed; 1059e3def6f7SGovind Singh 10601f5dbfbbSPeter Oh enum rx_phy_ppdu_end_info0 { 10611f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2), 10621f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3), 10631f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4), 10641f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5), 10651f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6), 10661f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7), 10671f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8), 10681f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9), 10691f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10), 10701f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11), 10711f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12), 10721f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13), 10731f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14), 10741f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15), 10751f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16), 10761f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17), 10771f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18), 10781f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19), 10791f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20), 10801f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21), 10811f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22), 10821f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23), 10831f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24), 10841f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25), 10851f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26), 10861f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27), 10871f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28), 10881f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29), 10891f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30), 10901f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31), 10911f5dbfbbSPeter Oh }; 10921f5dbfbbSPeter Oh 10931f5dbfbbSPeter Oh enum rx_phy_ppdu_end_info1 { 10941f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0), 10951f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1), 10961f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2), 10971f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3), 10981f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4), 10991f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5), 11001f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6), 11011f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7), 11021f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8), 11031f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9), 11041f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10), 11051f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11), 11061f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12), 11071f5dbfbbSPeter Oh RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13), 11081f5dbfbbSPeter Oh }; 11091f5dbfbbSPeter Oh 11101f5dbfbbSPeter Oh struct rx_phy_ppdu_end { 11111f5dbfbbSPeter Oh __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */ 11121f5dbfbbSPeter Oh __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */ 11131f5dbfbbSPeter Oh } __packed; 11141f5dbfbbSPeter Oh 11151f5dbfbbSPeter Oh #define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff 11161f5dbfbbSPeter Oh #define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0 11171f5dbfbbSPeter Oh 11181f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff 11191f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0 11201f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24) 11211f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25) 11221f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26) 11231f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27) 11241f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28) 11251f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29) 11261f5dbfbbSPeter Oh #define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30) 11271f5dbfbbSPeter Oh 11281f5dbfbbSPeter Oh struct rx_ppdu_end_qca99x0 { 11291f5dbfbbSPeter Oh struct rx_pkt_end rx_pkt_end; 11308f09588bSVasanthakumar Thiagarajan __le32 rx_location_info; /* %RX_LOCATION_INFO_ */ 11311f5dbfbbSPeter Oh struct rx_phy_ppdu_end rx_phy_ppdu_end; 11321f5dbfbbSPeter Oh __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 11331f5dbfbbSPeter Oh __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 11341f5dbfbbSPeter Oh __le16 bb_length; 11351f5dbfbbSPeter Oh __le16 info1; /* %RX_PPDU_END_INFO1_ */ 11361f5dbfbbSPeter Oh } __packed; 11371f5dbfbbSPeter Oh 1138acc6b559SVasanthakumar Thiagarajan struct rx_ppdu_end_qca9984 { 1139acc6b559SVasanthakumar Thiagarajan struct rx_pkt_end rx_pkt_end; 1140acc6b559SVasanthakumar Thiagarajan struct rx_location_info rx_location_info; 1141acc6b559SVasanthakumar Thiagarajan struct rx_phy_ppdu_end rx_phy_ppdu_end; 1142acc6b559SVasanthakumar Thiagarajan __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */ 1143acc6b559SVasanthakumar Thiagarajan __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */ 1144acc6b559SVasanthakumar Thiagarajan __le16 bb_length; 1145acc6b559SVasanthakumar Thiagarajan __le16 info1; /* %RX_PPDU_END_INFO1_ */ 1146acc6b559SVasanthakumar Thiagarajan } __packed; 1147acc6b559SVasanthakumar Thiagarajan 1148e3def6f7SGovind Singh struct rx_ppdu_end_wcn3990 { 1149e3def6f7SGovind Singh struct rx_pkt_end_wcn3990 rx_pkt_end; 1150e3def6f7SGovind Singh struct rx_location_info_wcn3990 rx_location_info; 1151e3def6f7SGovind Singh struct rx_phy_ppdu_end rx_phy_ppdu_end; 1152e3def6f7SGovind Singh __le32 rx_timing_offset; 1153e3def6f7SGovind Singh __le32 reserved_info_0; 1154e3def6f7SGovind Singh __le32 reserved_info_1; 1155e3def6f7SGovind Singh __le32 rx_antenna_info; 1156e3def6f7SGovind Singh __le32 rx_coex_info; 1157e3def6f7SGovind Singh __le32 rx_mpdu_cnt_info; 1158e3def6f7SGovind Singh __le64 phy_timestamp_tx; 1159e3def6f7SGovind Singh __le32 rx_bb_length; 1160e3def6f7SGovind Singh } __packed; 1161e3def6f7SGovind Singh 11623ec79e3aSMichal Kazior struct rx_ppdu_end { 11633ec79e3aSMichal Kazior struct rx_ppdu_end_common common; 11643ec79e3aSMichal Kazior union { 1165*6bae9de6SFrancesco Magliocca struct rx_ppdu_end_wcn3990 wcn3990; 1166*6bae9de6SFrancesco Magliocca } __packed; 1167*6bae9de6SFrancesco Magliocca } __packed; 1168*6bae9de6SFrancesco Magliocca 1169*6bae9de6SFrancesco Magliocca struct rx_ppdu_end_v1 { 1170*6bae9de6SFrancesco Magliocca struct rx_ppdu_end_common common; 1171*6bae9de6SFrancesco Magliocca union { 11723ec79e3aSMichal Kazior struct rx_ppdu_end_qca988x qca988x; 11733ec79e3aSMichal Kazior struct rx_ppdu_end_qca6174 qca6174; 11741f5dbfbbSPeter Oh struct rx_ppdu_end_qca99x0 qca99x0; 1175acc6b559SVasanthakumar Thiagarajan struct rx_ppdu_end_qca9984 qca9984; 11763ec79e3aSMichal Kazior } __packed; 11773ec79e3aSMichal Kazior } __packed; 11783ec79e3aSMichal Kazior 11795e3dd157SKalle Valo /* 11805e3dd157SKalle Valo * evm_p0 11815e3dd157SKalle Valo * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3. 11825e3dd157SKalle Valo * 11835e3dd157SKalle Valo * evm_p1 11845e3dd157SKalle Valo * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3. 11855e3dd157SKalle Valo * 11865e3dd157SKalle Valo * evm_p2 11875e3dd157SKalle Valo * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3. 11885e3dd157SKalle Valo * 11895e3dd157SKalle Valo * evm_p3 11905e3dd157SKalle Valo * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3. 11915e3dd157SKalle Valo * 11925e3dd157SKalle Valo * evm_p4 11935e3dd157SKalle Valo * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3. 11945e3dd157SKalle Valo * 11955e3dd157SKalle Valo * evm_p5 11965e3dd157SKalle Valo * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3. 11975e3dd157SKalle Valo * 11985e3dd157SKalle Valo * evm_p6 11995e3dd157SKalle Valo * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3. 12005e3dd157SKalle Valo * 12015e3dd157SKalle Valo * evm_p7 12025e3dd157SKalle Valo * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3. 12035e3dd157SKalle Valo * 12045e3dd157SKalle Valo * evm_p8 12055e3dd157SKalle Valo * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3. 12065e3dd157SKalle Valo * 12075e3dd157SKalle Valo * evm_p9 12085e3dd157SKalle Valo * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3. 12095e3dd157SKalle Valo * 12105e3dd157SKalle Valo * evm_p10 12115e3dd157SKalle Valo * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3. 12125e3dd157SKalle Valo * 12135e3dd157SKalle Valo * evm_p11 12145e3dd157SKalle Valo * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3. 12155e3dd157SKalle Valo * 12165e3dd157SKalle Valo * evm_p12 12175e3dd157SKalle Valo * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3. 12185e3dd157SKalle Valo * 12195e3dd157SKalle Valo * evm_p13 12205e3dd157SKalle Valo * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3. 12215e3dd157SKalle Valo * 12225e3dd157SKalle Valo * evm_p14 12235e3dd157SKalle Valo * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3. 12245e3dd157SKalle Valo * 12255e3dd157SKalle Valo * evm_p15 12265e3dd157SKalle Valo * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3. 12275e3dd157SKalle Valo * 12285e3dd157SKalle Valo * tsf_timestamp 12295e3dd157SKalle Valo * Receive TSF timestamp sampled on the rising edge of 12305e3dd157SKalle Valo * rx_clear. For PHY errors this may be the current TSF when 12315e3dd157SKalle Valo * phy_error is asserted if the rx_clear does not assert before 12325e3dd157SKalle Valo * the end of the PHY error. 12335e3dd157SKalle Valo * 12345e3dd157SKalle Valo * wb_timestamp 12355e3dd157SKalle Valo * WLAN/BT timestamp is a 1 usec resolution timestamp which 12365e3dd157SKalle Valo * does not get updated based on receive beacon like TSF. The 12375e3dd157SKalle Valo * same rules for capturing tsf_timestamp are used to capture 12385e3dd157SKalle Valo * the wb_timestamp. 12395e3dd157SKalle Valo * 12405e3dd157SKalle Valo * locationing_timestamp 12415e3dd157SKalle Valo * Timestamp used for locationing. This timestamp is used to 12425e3dd157SKalle Valo * indicate fractions of usec. For example if the MAC clock is 12435e3dd157SKalle Valo * running at 80 MHz, the timestamp will increment every 12.5 12445e3dd157SKalle Valo * nsec. The value starts at 0 and increments to 79 and 12455e3dd157SKalle Valo * returns to 0 and repeats. This information is valid for 12465e3dd157SKalle Valo * every PPDU. This information can be used in conjunction 12475e3dd157SKalle Valo * with wb_timestamp to capture large delta times. 12485e3dd157SKalle Valo * 12495e3dd157SKalle Valo * phy_err_code 12505e3dd157SKalle Valo * See the 1.10.8.1.2 for the list of the PHY error codes. 12515e3dd157SKalle Valo * 12525e3dd157SKalle Valo * phy_err 12535e3dd157SKalle Valo * Indicates a PHY error was detected for this PPDU. 12545e3dd157SKalle Valo * 12555e3dd157SKalle Valo * rx_location 12565e3dd157SKalle Valo * Indicates that location information was requested. 12575e3dd157SKalle Valo * 12585e3dd157SKalle Valo * txbf_h_info 12595e3dd157SKalle Valo * Indicates that the packet data carries H information which 12605e3dd157SKalle Valo * is used for TxBF debug. 12615e3dd157SKalle Valo * 12625e3dd157SKalle Valo * reserved_18 12635e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 12645e3dd157SKalle Valo * 12655e3dd157SKalle Valo * rx_antenna 12665e3dd157SKalle Valo * Receive antenna value 12675e3dd157SKalle Valo * 12685e3dd157SKalle Valo * tx_ht_vht_ack 12695e3dd157SKalle Valo * Indicates that a HT or VHT Ack/BA frame was transmitted in 12705e3dd157SKalle Valo * response to this receive packet. 12715e3dd157SKalle Valo * 12725e3dd157SKalle Valo * bb_captured_channel 12735e3dd157SKalle Valo * Indicates that the BB has captured a channel dump. FW can 12745e3dd157SKalle Valo * then read the channel dump memory. This may indicate that 12755e3dd157SKalle Valo * the channel was captured either based on PCU setting the 12765e3dd157SKalle Valo * capture_channel bit BB descriptor or FW setting the 12775e3dd157SKalle Valo * capture_channel mode bit. 12785e3dd157SKalle Valo * 12795e3dd157SKalle Valo * reserved_19 12805e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 12815e3dd157SKalle Valo * 12825e3dd157SKalle Valo * bb_length 12835e3dd157SKalle Valo * Indicates the number of bytes of baseband information for 12845e3dd157SKalle Valo * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF 12855e3dd157SKalle Valo * which indicates that this is not a normal PPDU but rather 12865e3dd157SKalle Valo * contains baseband debug information. 12875e3dd157SKalle Valo * 12885e3dd157SKalle Valo * reserved_20 12895e3dd157SKalle Valo * Reserved: HW should fill with 0, FW should ignore. 12905e3dd157SKalle Valo * 12915e3dd157SKalle Valo * ppdu_done 12925e3dd157SKalle Valo * PPDU end status is only valid when ppdu_done bit is set. 12935e3dd157SKalle Valo * Every time HW sets this bit in memory FW/SW must clear this 12945e3dd157SKalle Valo * bit in memory. FW will initialize all the ppdu_done dword 12955e3dd157SKalle Valo * to 0. 12965e3dd157SKalle Valo */ 12975e3dd157SKalle Valo 1298c3f7f31eSGovind Singh #define FW_RX_DESC_INFO0_DISCARD BIT(0) 1299c3f7f31eSGovind Singh #define FW_RX_DESC_INFO0_FORWARD BIT(1) 1300c3f7f31eSGovind Singh #define FW_RX_DESC_INFO0_INSPECT BIT(5) 13015e3dd157SKalle Valo #define FW_RX_DESC_INFO0_EXT_MASK 0xC0 13025e3dd157SKalle Valo #define FW_RX_DESC_INFO0_EXT_LSB 6 13035e3dd157SKalle Valo 13045e3dd157SKalle Valo struct fw_rx_desc_base { 13055e3dd157SKalle Valo u8 info0; 13065e3dd157SKalle Valo } __packed; 13075e3dd157SKalle Valo 1308f88d4934SErik Stromdahl #define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0) 1309f88d4934SErik Stromdahl #define FW_RX_DESC_FLAGS_LAST_MSDU (1 << 1) 1310f88d4934SErik Stromdahl #define FW_RX_DESC_C3_FAILED (1 << 2) 1311f88d4934SErik Stromdahl #define FW_RX_DESC_C4_FAILED (1 << 3) 1312f88d4934SErik Stromdahl #define FW_RX_DESC_IPV6 (1 << 4) 1313f88d4934SErik Stromdahl #define FW_RX_DESC_TCP (1 << 5) 1314f88d4934SErik Stromdahl #define FW_RX_DESC_UDP (1 << 6) 1315f88d4934SErik Stromdahl 1316f88d4934SErik Stromdahl struct fw_rx_desc_hl { 1317079a108fSWen Gong union { 1318079a108fSWen Gong struct { 1319079a108fSWen Gong u8 discard:1, 1320079a108fSWen Gong forward:1, 1321079a108fSWen Gong any_err:1, 1322079a108fSWen Gong dup_err:1, 1323079a108fSWen Gong reserved:1, 1324079a108fSWen Gong inspect:1, 1325079a108fSWen Gong extension:2; 1326079a108fSWen Gong } bits; 1327f88d4934SErik Stromdahl u8 info0; 1328079a108fSWen Gong } u; 1329079a108fSWen Gong 1330f88d4934SErik Stromdahl u8 version; 1331f88d4934SErik Stromdahl u8 len; 1332f88d4934SErik Stromdahl u8 flags; 1333f88d4934SErik Stromdahl } __packed; 1334f88d4934SErik Stromdahl 13355e3dd157SKalle Valo #endif /* _RX_DESC_H_ */ 1336