15e3dd157SKalle Valo /*
25e3dd157SKalle Valo  * Copyright (c) 2005-2011 Atheros Communications Inc.
35e3dd157SKalle Valo  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
45e3dd157SKalle Valo  *
55e3dd157SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
65e3dd157SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
75e3dd157SKalle Valo  * copyright notice and this permission notice appear in all copies.
85e3dd157SKalle Valo  *
95e3dd157SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
105e3dd157SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
115e3dd157SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
125e3dd157SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
135e3dd157SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
145e3dd157SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
155e3dd157SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
165e3dd157SKalle Valo  */
175e3dd157SKalle Valo 
185e3dd157SKalle Valo #ifndef _RX_DESC_H_
195e3dd157SKalle Valo #define _RX_DESC_H_
205e3dd157SKalle Valo 
215e3dd157SKalle Valo enum rx_attention_flags {
225e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_FIRST_MPDU          = 1 << 0,
235e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_LAST_MPDU           = 1 << 1,
245e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MCAST_BCAST         = 1 << 2,
255e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_PEER_IDX_INVALID    = 1 << 3,
265e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT    = 1 << 4,
275e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_POWER_MGMT          = 1 << 5,
285e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_NON_QOS             = 1 << 6,
295e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_NULL_DATA           = 1 << 7,
305e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MGMT_TYPE           = 1 << 8,
315e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_CTRL_TYPE           = 1 << 9,
325e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MORE_DATA           = 1 << 10,
335e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_EOSP                = 1 << 11,
345e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_U_APSD_TRIGGER      = 1 << 12,
355e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_FRAGMENT            = 1 << 13,
365e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_ORDER               = 1 << 14,
375e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_CLASSIFICATION      = 1 << 15,
385e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_OVERFLOW_ERR        = 1 << 16,
395e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR     = 1 << 17,
405e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = 1 << 18,
415e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL      = 1 << 19,
425e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_SA_IDX_INVALID      = 1 << 20,
435e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_DA_IDX_INVALID      = 1 << 21,
445e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT      = 1 << 22,
455e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT      = 1 << 23,
465e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED    = 1 << 24,
475e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_DIRECTED            = 1 << 25,
485e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_BUFFER_FRAGMENT     = 1 << 26,
495e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR     = 1 << 27,
505e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_TKIP_MIC_ERR        = 1 << 28,
515e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_DECRYPT_ERR         = 1 << 29,
525e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_FCS_ERR             = 1 << 30,
535e3dd157SKalle Valo 	RX_ATTENTION_FLAGS_MSDU_DONE           = 1 << 31,
545e3dd157SKalle Valo };
555e3dd157SKalle Valo 
565e3dd157SKalle Valo struct rx_attention {
575e3dd157SKalle Valo 	__le32 flags; /* %RX_ATTENTION_FLAGS_ */
585e3dd157SKalle Valo } __packed;
595e3dd157SKalle Valo 
605e3dd157SKalle Valo /*
615e3dd157SKalle Valo  * first_mpdu
625e3dd157SKalle Valo  *		Indicates the first MSDU of the PPDU.  If both first_mpdu
635e3dd157SKalle Valo  *		and last_mpdu are set in the MSDU then this is a not an
645e3dd157SKalle Valo  *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
655e3dd157SKalle Valo  *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
665e3dd157SKalle Valo  *		0.  The PPDU start status will only be valid when this bit
675e3dd157SKalle Valo  *		is set.
685e3dd157SKalle Valo  *
695e3dd157SKalle Valo  * last_mpdu
705e3dd157SKalle Valo  *		Indicates the last MSDU of the last MPDU of the PPDU.  The
715e3dd157SKalle Valo  *		PPDU end status will only be valid when this bit is set.
725e3dd157SKalle Valo  *
735e3dd157SKalle Valo  * mcast_bcast
745e3dd157SKalle Valo  *		Multicast / broadcast indicator.  Only set when the MAC
755e3dd157SKalle Valo  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
765e3dd157SKalle Valo  *		matches one of the 4 BSSID registers. Only set when
775e3dd157SKalle Valo  *		first_msdu is set.
785e3dd157SKalle Valo  *
795e3dd157SKalle Valo  * peer_idx_invalid
805e3dd157SKalle Valo  *		Indicates no matching entries within the the max search
815e3dd157SKalle Valo  *		count.  Only set when first_msdu is set.
825e3dd157SKalle Valo  *
835e3dd157SKalle Valo  * peer_idx_timeout
845e3dd157SKalle Valo  *		Indicates an unsuccessful search for the peer index due to
855e3dd157SKalle Valo  *		timeout.  Only set when first_msdu is set.
865e3dd157SKalle Valo  *
875e3dd157SKalle Valo  * power_mgmt
885e3dd157SKalle Valo  *		Power management bit set in the 802.11 header.  Only set
895e3dd157SKalle Valo  *		when first_msdu is set.
905e3dd157SKalle Valo  *
915e3dd157SKalle Valo  * non_qos
925e3dd157SKalle Valo  *		Set if packet is not a non-QoS data frame.  Only set when
935e3dd157SKalle Valo  *		first_msdu is set.
945e3dd157SKalle Valo  *
955e3dd157SKalle Valo  * null_data
965e3dd157SKalle Valo  *		Set if frame type indicates either null data or QoS null
975e3dd157SKalle Valo  *		data format.  Only set when first_msdu is set.
985e3dd157SKalle Valo  *
995e3dd157SKalle Valo  * mgmt_type
1005e3dd157SKalle Valo  *		Set if packet is a management packet.  Only set when
1015e3dd157SKalle Valo  *		first_msdu is set.
1025e3dd157SKalle Valo  *
1035e3dd157SKalle Valo  * ctrl_type
1045e3dd157SKalle Valo  *		Set if packet is a control packet.  Only set when first_msdu
1055e3dd157SKalle Valo  *		is set.
1065e3dd157SKalle Valo  *
1075e3dd157SKalle Valo  * more_data
1085e3dd157SKalle Valo  *		Set if more bit in frame control is set.  Only set when
1095e3dd157SKalle Valo  *		first_msdu is set.
1105e3dd157SKalle Valo  *
1115e3dd157SKalle Valo  * eosp
1125e3dd157SKalle Valo  *		Set if the EOSP (end of service period) bit in the QoS
1135e3dd157SKalle Valo  *		control field is set.  Only set when first_msdu is set.
1145e3dd157SKalle Valo  *
1155e3dd157SKalle Valo  * u_apsd_trigger
1165e3dd157SKalle Valo  *		Set if packet is U-APSD trigger.  Key table will have bits
1175e3dd157SKalle Valo  *		per TID to indicate U-APSD trigger.
1185e3dd157SKalle Valo  *
1195e3dd157SKalle Valo  * fragment
1205e3dd157SKalle Valo  *		Indicates that this is an 802.11 fragment frame.  This is
1215e3dd157SKalle Valo  *		set when either the more_frag bit is set in the frame
1225e3dd157SKalle Valo  *		control or the fragment number is not zero.  Only set when
1235e3dd157SKalle Valo  *		first_msdu is set.
1245e3dd157SKalle Valo  *
1255e3dd157SKalle Valo  * order
1265e3dd157SKalle Valo  *		Set if the order bit in the frame control is set.  Only set
1275e3dd157SKalle Valo  *		when first_msdu is set.
1285e3dd157SKalle Valo  *
1295e3dd157SKalle Valo  * classification
1305e3dd157SKalle Valo  *		Indicates that this status has a corresponding MSDU that
1315e3dd157SKalle Valo  *		requires FW processing.  The OLE will have classification
1325e3dd157SKalle Valo  *		ring mask registers which will indicate the ring(s) for
1335e3dd157SKalle Valo  *		packets and descriptors which need FW attention.
1345e3dd157SKalle Valo  *
1355e3dd157SKalle Valo  * overflow_err
1365e3dd157SKalle Valo  *		PCU Receive FIFO does not have enough space to store the
1375e3dd157SKalle Valo  *		full receive packet.  Enough space is reserved in the
1385e3dd157SKalle Valo  *		receive FIFO for the status is written.  This MPDU remaining
1395e3dd157SKalle Valo  *		packets in the PPDU will be filtered and no Ack response
1405e3dd157SKalle Valo  *		will be transmitted.
1415e3dd157SKalle Valo  *
1425e3dd157SKalle Valo  * msdu_length_err
1435e3dd157SKalle Valo  *		Indicates that the MSDU length from the 802.3 encapsulated
1445e3dd157SKalle Valo  *		length field extends beyond the MPDU boundary.
1455e3dd157SKalle Valo  *
1465e3dd157SKalle Valo  * tcp_udp_chksum_fail
1475e3dd157SKalle Valo  *		Indicates that the computed checksum (tcp_udp_chksum) did
1485e3dd157SKalle Valo  *		not match the checksum in the TCP/UDP header.
1495e3dd157SKalle Valo  *
1505e3dd157SKalle Valo  * ip_chksum_fail
1515e3dd157SKalle Valo  *		Indicates that the computed checksum did not match the
1525e3dd157SKalle Valo  *		checksum in the IP header.
1535e3dd157SKalle Valo  *
1545e3dd157SKalle Valo  * sa_idx_invalid
1555e3dd157SKalle Valo  *		Indicates no matching entry was found in the address search
1565e3dd157SKalle Valo  *		table for the source MAC address.
1575e3dd157SKalle Valo  *
1585e3dd157SKalle Valo  * da_idx_invalid
1595e3dd157SKalle Valo  *		Indicates no matching entry was found in the address search
1605e3dd157SKalle Valo  *		table for the destination MAC address.
1615e3dd157SKalle Valo  *
1625e3dd157SKalle Valo  * sa_idx_timeout
1635e3dd157SKalle Valo  *		Indicates an unsuccessful search for the source MAC address
1645e3dd157SKalle Valo  *		due to the expiring of the search timer.
1655e3dd157SKalle Valo  *
1665e3dd157SKalle Valo  * da_idx_timeout
1675e3dd157SKalle Valo  *		Indicates an unsuccessful search for the destination MAC
1685e3dd157SKalle Valo  *		address due to the expiring of the search timer.
1695e3dd157SKalle Valo  *
1705e3dd157SKalle Valo  * encrypt_required
1715e3dd157SKalle Valo  *		Indicates that this data type frame is not encrypted even if
1725e3dd157SKalle Valo  *		the policy for this MPDU requires encryption as indicated in
1735e3dd157SKalle Valo  *		the peer table key type.
1745e3dd157SKalle Valo  *
1755e3dd157SKalle Valo  * directed
1765e3dd157SKalle Valo  *		MPDU is a directed packet which means that the RA matched
1775e3dd157SKalle Valo  *		our STA addresses.  In proxySTA it means that the TA matched
1785e3dd157SKalle Valo  *		an entry in our address search table with the corresponding
1795e3dd157SKalle Valo  *		'no_ack' bit is the address search entry cleared.
1805e3dd157SKalle Valo  *
1815e3dd157SKalle Valo  * buffer_fragment
1825e3dd157SKalle Valo  *		Indicates that at least one of the rx buffers has been
1835e3dd157SKalle Valo  *		fragmented.  If set the FW should look at the rx_frag_info
1845e3dd157SKalle Valo  *		descriptor described below.
1855e3dd157SKalle Valo  *
1865e3dd157SKalle Valo  * mpdu_length_err
1875e3dd157SKalle Valo  *		Indicates that the MPDU was pre-maturely terminated
1885e3dd157SKalle Valo  *		resulting in a truncated MPDU.  Don't trust the MPDU length
1895e3dd157SKalle Valo  *		field.
1905e3dd157SKalle Valo  *
1915e3dd157SKalle Valo  * tkip_mic_err
1925e3dd157SKalle Valo  *		Indicates that the MPDU Michael integrity check failed
1935e3dd157SKalle Valo  *
1945e3dd157SKalle Valo  * decrypt_err
1955e3dd157SKalle Valo  *		Indicates that the MPDU decrypt integrity check failed
1965e3dd157SKalle Valo  *
1975e3dd157SKalle Valo  * fcs_err
1985e3dd157SKalle Valo  *		Indicates that the MPDU FCS check failed
1995e3dd157SKalle Valo  *
2005e3dd157SKalle Valo  * msdu_done
2015e3dd157SKalle Valo  *		If set indicates that the RX packet data, RX header data, RX
2025e3dd157SKalle Valo  *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
2035e3dd157SKalle Valo  *		start/end descriptors and RX Attention descriptor are all
2045e3dd157SKalle Valo  *		valid.  This bit must be in the last octet of the
2055e3dd157SKalle Valo  *		descriptor.
2065e3dd157SKalle Valo  */
2075e3dd157SKalle Valo 
2085e3dd157SKalle Valo struct rx_frag_info {
2095e3dd157SKalle Valo 	u8 ring0_more_count;
2105e3dd157SKalle Valo 	u8 ring1_more_count;
2115e3dd157SKalle Valo 	u8 ring2_more_count;
2125e3dd157SKalle Valo 	u8 ring3_more_count;
2135e3dd157SKalle Valo } __packed;
2145e3dd157SKalle Valo 
2155e3dd157SKalle Valo /*
2165e3dd157SKalle Valo  * ring0_more_count
2175e3dd157SKalle Valo  *		Indicates the number of more buffers associated with RX DMA
2185e3dd157SKalle Valo  *		ring 0.  Field is filled in by the RX_DMA.
2195e3dd157SKalle Valo  *
2205e3dd157SKalle Valo  * ring1_more_count
2215e3dd157SKalle Valo  *		Indicates the number of more buffers associated with RX DMA
2225e3dd157SKalle Valo  *		ring 1. Field is filled in by the RX_DMA.
2235e3dd157SKalle Valo  *
2245e3dd157SKalle Valo  * ring2_more_count
2255e3dd157SKalle Valo  *		Indicates the number of more buffers associated with RX DMA
2265e3dd157SKalle Valo  *		ring 2. Field is filled in by the RX_DMA.
2275e3dd157SKalle Valo  *
2285e3dd157SKalle Valo  * ring3_more_count
2295e3dd157SKalle Valo  *		Indicates the number of more buffers associated with RX DMA
2305e3dd157SKalle Valo  *		ring 3. Field is filled in by the RX_DMA.
2315e3dd157SKalle Valo  */
2325e3dd157SKalle Valo 
2335e3dd157SKalle Valo enum htt_rx_mpdu_encrypt_type {
2345e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_WEP40            = 0,
2355e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_WEP104           = 1,
2365e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2,
2375e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_WEP128           = 3,
2385e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_TKIP_WPA         = 4,
2395e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_WAPI             = 5,
2405e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2     = 6,
2415e3dd157SKalle Valo 	HTT_RX_MPDU_ENCRYPT_NONE             = 7,
2425e3dd157SKalle Valo };
2435e3dd157SKalle Valo 
2445e3dd157SKalle Valo #define RX_MPDU_START_INFO0_PEER_IDX_MASK     0x000007ff
2455e3dd157SKalle Valo #define RX_MPDU_START_INFO0_PEER_IDX_LSB      0
2465e3dd157SKalle Valo #define RX_MPDU_START_INFO0_SEQ_NUM_MASK      0x0fff0000
2475e3dd157SKalle Valo #define RX_MPDU_START_INFO0_SEQ_NUM_LSB       16
2485e3dd157SKalle Valo #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
2495e3dd157SKalle Valo #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB  28
2505e3dd157SKalle Valo #define RX_MPDU_START_INFO0_FROM_DS           (1 << 11)
2515e3dd157SKalle Valo #define RX_MPDU_START_INFO0_TO_DS             (1 << 12)
2525e3dd157SKalle Valo #define RX_MPDU_START_INFO0_ENCRYPTED         (1 << 13)
2535e3dd157SKalle Valo #define RX_MPDU_START_INFO0_RETRY             (1 << 14)
2545e3dd157SKalle Valo #define RX_MPDU_START_INFO0_TXBF_H_INFO       (1 << 15)
2555e3dd157SKalle Valo 
2565e3dd157SKalle Valo #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
2575e3dd157SKalle Valo #define RX_MPDU_START_INFO1_TID_LSB  28
2585e3dd157SKalle Valo #define RX_MPDU_START_INFO1_DIRECTED (1 << 16)
2595e3dd157SKalle Valo 
2605e3dd157SKalle Valo struct rx_mpdu_start {
2615e3dd157SKalle Valo 	__le32 info0;
2625e3dd157SKalle Valo 	union {
2635e3dd157SKalle Valo 		struct {
2645e3dd157SKalle Valo 			__le32 pn31_0;
2655e3dd157SKalle Valo 			__le32 info1; /* %RX_MPDU_START_INFO1_ */
2665e3dd157SKalle Valo 		} __packed;
2675e3dd157SKalle Valo 		struct {
2685e3dd157SKalle Valo 			u8 pn[6];
2695e3dd157SKalle Valo 		} __packed;
2705e3dd157SKalle Valo 	} __packed;
2715e3dd157SKalle Valo } __packed;
2725e3dd157SKalle Valo 
2735e3dd157SKalle Valo /*
2745e3dd157SKalle Valo  * peer_idx
2755e3dd157SKalle Valo  *		The index of the address search table which associated with
2765e3dd157SKalle Valo  *		the peer table entry corresponding to this MPDU.  Only valid
2775e3dd157SKalle Valo  *		when first_msdu is set.
2785e3dd157SKalle Valo  *
2795e3dd157SKalle Valo  * fr_ds
2805e3dd157SKalle Valo  *		Set if the from DS bit is set in the frame control.  Only
2815e3dd157SKalle Valo  *		valid when first_msdu is set.
2825e3dd157SKalle Valo  *
2835e3dd157SKalle Valo  * to_ds
2845e3dd157SKalle Valo  *		Set if the to DS bit is set in the frame control.  Only
2855e3dd157SKalle Valo  *		valid when first_msdu is set.
2865e3dd157SKalle Valo  *
2875e3dd157SKalle Valo  * encrypted
2885e3dd157SKalle Valo  *		Protected bit from the frame control.  Only valid when
2895e3dd157SKalle Valo  *		first_msdu is set.
2905e3dd157SKalle Valo  *
2915e3dd157SKalle Valo  * retry
2925e3dd157SKalle Valo  *		Retry bit from the frame control.  Only valid when
2935e3dd157SKalle Valo  *		first_msdu is set.
2945e3dd157SKalle Valo  *
2955e3dd157SKalle Valo  * txbf_h_info
2965e3dd157SKalle Valo  *		The MPDU data will contain H information.  Primarily used
2975e3dd157SKalle Valo  *		for debug.
2985e3dd157SKalle Valo  *
2995e3dd157SKalle Valo  * seq_num
3005e3dd157SKalle Valo  *		The sequence number from the 802.11 header.  Only valid when
3015e3dd157SKalle Valo  *		first_msdu is set.
3025e3dd157SKalle Valo  *
3035e3dd157SKalle Valo  * encrypt_type
3045e3dd157SKalle Valo  *		Indicates type of decrypt cipher used (as defined in the
3055e3dd157SKalle Valo  *		peer table)
3065e3dd157SKalle Valo  *		0: WEP40
3075e3dd157SKalle Valo  *		1: WEP104
3085e3dd157SKalle Valo  *		2: TKIP without MIC
3095e3dd157SKalle Valo  *		3: WEP128
3105e3dd157SKalle Valo  *		4: TKIP (WPA)
3115e3dd157SKalle Valo  *		5: WAPI
3125e3dd157SKalle Valo  *		6: AES-CCM (WPA2)
3135e3dd157SKalle Valo  *		7: No cipher
3145e3dd157SKalle Valo  *		Only valid when first_msdu_is set
3155e3dd157SKalle Valo  *
3165e3dd157SKalle Valo  * pn_31_0
3175e3dd157SKalle Valo  *		Bits [31:0] of the PN number extracted from the IV field
3185e3dd157SKalle Valo  *		WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0] is
3195e3dd157SKalle Valo  *		valid.
3205e3dd157SKalle Valo  *		TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
3215e3dd157SKalle Valo  *		WEPSeed[1], pn1}.  Only pn[47:0] is valid.
3225e3dd157SKalle Valo  *		AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
3235e3dd157SKalle Valo  *		pn0}.  Only pn[47:0] is valid.
3245e3dd157SKalle Valo  *		WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
3255e3dd157SKalle Valo  *		pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}.
3265e3dd157SKalle Valo  *		The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and
3275e3dd157SKalle Valo  *		pn[47:0] are valid.
3285e3dd157SKalle Valo  *		Only valid when first_msdu is set.
3295e3dd157SKalle Valo  *
3305e3dd157SKalle Valo  * pn_47_32
3315e3dd157SKalle Valo  *		Bits [47:32] of the PN number.   See description for
3325e3dd157SKalle Valo  *		pn_31_0.  The remaining PN fields are in the rx_msdu_end
3335e3dd157SKalle Valo  *		descriptor
3345e3dd157SKalle Valo  *
3355e3dd157SKalle Valo  * pn
3365e3dd157SKalle Valo  *		Use this field to access the pn without worrying about
3375e3dd157SKalle Valo  *		byte-order and bitmasking/bitshifting.
3385e3dd157SKalle Valo  *
3395e3dd157SKalle Valo  * directed
3405e3dd157SKalle Valo  *		See definition in RX attention descriptor
3415e3dd157SKalle Valo  *
3425e3dd157SKalle Valo  * reserved_2
3435e3dd157SKalle Valo  *		Reserved: HW should fill with zero.  FW should ignore.
3445e3dd157SKalle Valo  *
3455e3dd157SKalle Valo  * tid
3465e3dd157SKalle Valo  *		The TID field in the QoS control field
3475e3dd157SKalle Valo  */
3485e3dd157SKalle Valo 
3495e3dd157SKalle Valo #define RX_MPDU_END_INFO0_RESERVED_0_MASK     0x00001fff
3505e3dd157SKalle Valo #define RX_MPDU_END_INFO0_RESERVED_0_LSB      0
3515e3dd157SKalle Valo #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
3525e3dd157SKalle Valo #define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB  16
3535e3dd157SKalle Valo #define RX_MPDU_END_INFO0_OVERFLOW_ERR        (1 << 13)
3545e3dd157SKalle Valo #define RX_MPDU_END_INFO0_LAST_MPDU           (1 << 14)
3555e3dd157SKalle Valo #define RX_MPDU_END_INFO0_POST_DELIM_ERR      (1 << 15)
3565e3dd157SKalle Valo #define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR     (1 << 28)
3575e3dd157SKalle Valo #define RX_MPDU_END_INFO0_TKIP_MIC_ERR        (1 << 29)
3585e3dd157SKalle Valo #define RX_MPDU_END_INFO0_DECRYPT_ERR         (1 << 30)
3595e3dd157SKalle Valo #define RX_MPDU_END_INFO0_FCS_ERR             (1 << 31)
3605e3dd157SKalle Valo 
3615e3dd157SKalle Valo struct rx_mpdu_end {
3625e3dd157SKalle Valo 	__le32 info0;
3635e3dd157SKalle Valo } __packed;
3645e3dd157SKalle Valo 
3655e3dd157SKalle Valo /*
3665e3dd157SKalle Valo  * reserved_0
3675e3dd157SKalle Valo  *		Reserved
3685e3dd157SKalle Valo  *
3695e3dd157SKalle Valo  * overflow_err
3705e3dd157SKalle Valo  *		PCU Receive FIFO does not have enough space to store the
3715e3dd157SKalle Valo  *		full receive packet.  Enough space is reserved in the
3725e3dd157SKalle Valo  *		receive FIFO for the status is written.  This MPDU remaining
3735e3dd157SKalle Valo  *		packets in the PPDU will be filtered and no Ack response
3745e3dd157SKalle Valo  *		will be transmitted.
3755e3dd157SKalle Valo  *
3765e3dd157SKalle Valo  * last_mpdu
3775e3dd157SKalle Valo  *		Indicates that this is the last MPDU of a PPDU.
3785e3dd157SKalle Valo  *
3795e3dd157SKalle Valo  * post_delim_err
3805e3dd157SKalle Valo  *		Indicates that a delimiter FCS error occurred after this
3815e3dd157SKalle Valo  *		MPDU before the next MPDU.  Only valid when last_msdu is
3825e3dd157SKalle Valo  *		set.
3835e3dd157SKalle Valo  *
3845e3dd157SKalle Valo  * post_delim_cnt
3855e3dd157SKalle Valo  *		Count of the delimiters after this MPDU.  This requires the
3865e3dd157SKalle Valo  *		last MPDU to be held until all the EOF descriptors have been
3875e3dd157SKalle Valo  *		received.  This may be inefficient in the future when
3885e3dd157SKalle Valo  *		ML-MIMO is used.  Only valid when last_mpdu is set.
3895e3dd157SKalle Valo  *
3905e3dd157SKalle Valo  * mpdu_length_err
3915e3dd157SKalle Valo  *		See definition in RX attention descriptor
3925e3dd157SKalle Valo  *
3935e3dd157SKalle Valo  * tkip_mic_err
3945e3dd157SKalle Valo  *		See definition in RX attention descriptor
3955e3dd157SKalle Valo  *
3965e3dd157SKalle Valo  * decrypt_err
3975e3dd157SKalle Valo  *		See definition in RX attention descriptor
3985e3dd157SKalle Valo  *
3995e3dd157SKalle Valo  * fcs_err
4005e3dd157SKalle Valo  *		See definition in RX attention descriptor
4015e3dd157SKalle Valo  */
4025e3dd157SKalle Valo 
4035e3dd157SKalle Valo #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK    0x00003fff
4045e3dd157SKalle Valo #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB     0
4055e3dd157SKalle Valo #define RX_MSDU_START_INFO0_IP_OFFSET_MASK      0x000fc000
4065e3dd157SKalle Valo #define RX_MSDU_START_INFO0_IP_OFFSET_LSB       14
4075e3dd157SKalle Valo #define RX_MSDU_START_INFO0_RING_MASK_MASK      0x00f00000
4085e3dd157SKalle Valo #define RX_MSDU_START_INFO0_RING_MASK_LSB       20
4095e3dd157SKalle Valo #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
4105e3dd157SKalle Valo #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB  24
4115e3dd157SKalle Valo 
4125e3dd157SKalle Valo #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK    0x000000ff
4135e3dd157SKalle Valo #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB     0
4145e3dd157SKalle Valo #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK   0x00000300
4155e3dd157SKalle Valo #define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB    8
4165e3dd157SKalle Valo #define RX_MSDU_START_INFO1_SA_IDX_MASK         0x07ff0000
4175e3dd157SKalle Valo #define RX_MSDU_START_INFO1_SA_IDX_LSB          16
4185e3dd157SKalle Valo #define RX_MSDU_START_INFO1_IPV4_PROTO          (1 << 10)
4195e3dd157SKalle Valo #define RX_MSDU_START_INFO1_IPV6_PROTO          (1 << 11)
4205e3dd157SKalle Valo #define RX_MSDU_START_INFO1_TCP_PROTO           (1 << 12)
4215e3dd157SKalle Valo #define RX_MSDU_START_INFO1_UDP_PROTO           (1 << 13)
4225e3dd157SKalle Valo #define RX_MSDU_START_INFO1_IP_FRAG             (1 << 14)
4235e3dd157SKalle Valo #define RX_MSDU_START_INFO1_TCP_ONLY_ACK        (1 << 15)
4245e3dd157SKalle Valo 
42526d1e9c2SMichal Kazior /* The decapped header (rx_hdr_status) contains the following:
42626d1e9c2SMichal Kazior  *  a) 802.11 header
42726d1e9c2SMichal Kazior  *  [padding to 4 bytes]
42826d1e9c2SMichal Kazior  *  b) HW crypto parameter
42926d1e9c2SMichal Kazior  *     - 0 bytes for no security
43026d1e9c2SMichal Kazior  *     - 4 bytes for WEP
43126d1e9c2SMichal Kazior  *     - 8 bytes for TKIP, AES
43226d1e9c2SMichal Kazior  *  [padding to 4 bytes]
43326d1e9c2SMichal Kazior  *  c) A-MSDU subframe header (14 bytes) if appliable
43426d1e9c2SMichal Kazior  *  d) LLC/SNAP (RFC1042, 8 bytes)
43526d1e9c2SMichal Kazior  *
43626d1e9c2SMichal Kazior  * In case of A-MSDU only first frame in sequence contains (a) and (b). */
4375e3dd157SKalle Valo enum rx_msdu_decap_format {
4385e3dd157SKalle Valo 	RX_MSDU_DECAP_RAW = 0,
43926d1e9c2SMichal Kazior 
44026d1e9c2SMichal Kazior 	/* Note: QoS frames are reported as non-QoS. The rx_hdr_status in
44126d1e9c2SMichal Kazior 	 * htt_rx_desc contains the original decapped 802.11 header. */
4425e3dd157SKalle Valo 	RX_MSDU_DECAP_NATIVE_WIFI = 1,
44326d1e9c2SMichal Kazior 
44426d1e9c2SMichal Kazior 	/* Payload contains an ethernet header (struct ethhdr). */
4455e3dd157SKalle Valo 	RX_MSDU_DECAP_ETHERNET2_DIX = 2,
44626d1e9c2SMichal Kazior 
44726d1e9c2SMichal Kazior 	/* Payload contains two 48-bit addresses and 2-byte length (14 bytes
44826d1e9c2SMichal Kazior 	 * total), followed by an RFC1042 header (8 bytes). */
4495e3dd157SKalle Valo 	RX_MSDU_DECAP_8023_SNAP_LLC = 3
4505e3dd157SKalle Valo };
4515e3dd157SKalle Valo 
4525e3dd157SKalle Valo struct rx_msdu_start {
4535e3dd157SKalle Valo 	__le32 info0; /* %RX_MSDU_START_INFO0_ */
4545e3dd157SKalle Valo 	__le32 flow_id_crc;
4555e3dd157SKalle Valo 	__le32 info1; /* %RX_MSDU_START_INFO1_ */
4565e3dd157SKalle Valo } __packed;
4575e3dd157SKalle Valo 
4585e3dd157SKalle Valo /*
4595e3dd157SKalle Valo  * msdu_length
4605e3dd157SKalle Valo  *		MSDU length in bytes after decapsulation.  This field is
4615e3dd157SKalle Valo  *		still valid for MPDU frames without A-MSDU.  It still
4625e3dd157SKalle Valo  *		represents MSDU length after decapsulation
4635e3dd157SKalle Valo  *
4645e3dd157SKalle Valo  * ip_offset
4655e3dd157SKalle Valo  *		Indicates the IP offset in bytes from the start of the
4665e3dd157SKalle Valo  *		packet after decapsulation.  Only valid if ipv4_proto or
4675e3dd157SKalle Valo  *		ipv6_proto is set.
4685e3dd157SKalle Valo  *
4695e3dd157SKalle Valo  * ring_mask
4705e3dd157SKalle Valo  *		Indicates the destination RX rings for this MSDU.
4715e3dd157SKalle Valo  *
4725e3dd157SKalle Valo  * tcp_udp_offset
4735e3dd157SKalle Valo  *		Indicates the offset in bytes to the start of TCP or UDP
4745e3dd157SKalle Valo  *		header from the start of the IP header after decapsulation.
4755e3dd157SKalle Valo  *		Only valid if tcp_prot or udp_prot is set.  The value 0
4765e3dd157SKalle Valo  *		indicates that the offset is longer than 127 bytes.
4775e3dd157SKalle Valo  *
4785e3dd157SKalle Valo  * reserved_0c
4795e3dd157SKalle Valo  *		Reserved: HW should fill with zero.  FW should ignore.
4805e3dd157SKalle Valo  *
4815e3dd157SKalle Valo  * flow_id_crc
4825e3dd157SKalle Valo  *		The flow_id_crc runs CRC32 on the following information:
4835e3dd157SKalle Valo  *		IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
4845e3dd157SKalle Valo  *		protocol[7:0]}.
4855e3dd157SKalle Valo  *		IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
4865e3dd157SKalle Valo  *		next_header[7:0]}
4875e3dd157SKalle Valo  *		UDP case: sort_port[15:0], dest_port[15:0]
4885e3dd157SKalle Valo  *		TCP case: sort_port[15:0], dest_port[15:0],
4895e3dd157SKalle Valo  *		{header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
4905e3dd157SKalle Valo  *		{16'b0, urgent_ptr[15:0]}, all options except 32-bit
4915e3dd157SKalle Valo  *		timestamp.
4925e3dd157SKalle Valo  *
4935e3dd157SKalle Valo  * msdu_number
4945e3dd157SKalle Valo  *		Indicates the MSDU number within a MPDU.  This value is
4955e3dd157SKalle Valo  *		reset to zero at the start of each MPDU.  If the number of
4965e3dd157SKalle Valo  *		MSDU exceeds 255 this number will wrap using modulo 256.
4975e3dd157SKalle Valo  *
4985e3dd157SKalle Valo  * decap_format
4995e3dd157SKalle Valo  *		Indicates the format after decapsulation:
5005e3dd157SKalle Valo  *		0: RAW: No decapsulation
5015e3dd157SKalle Valo  *		1: Native WiFi
5025e3dd157SKalle Valo  *		2: Ethernet 2 (DIX)
5035e3dd157SKalle Valo  *		3: 802.3 (SNAP/LLC)
5045e3dd157SKalle Valo  *
5055e3dd157SKalle Valo  * ipv4_proto
5065e3dd157SKalle Valo  *		Set if L2 layer indicates IPv4 protocol.
5075e3dd157SKalle Valo  *
5085e3dd157SKalle Valo  * ipv6_proto
5095e3dd157SKalle Valo  *		Set if L2 layer indicates IPv6 protocol.
5105e3dd157SKalle Valo  *
5115e3dd157SKalle Valo  * tcp_proto
5125e3dd157SKalle Valo  *		Set if the ipv4_proto or ipv6_proto are set and the IP
5135e3dd157SKalle Valo  *		protocol indicates TCP.
5145e3dd157SKalle Valo  *
5155e3dd157SKalle Valo  * udp_proto
5165e3dd157SKalle Valo  *		Set if the ipv4_proto or ipv6_proto are set and the IP
5175e3dd157SKalle Valo  *			protocol indicates UDP.
5185e3dd157SKalle Valo  *
5195e3dd157SKalle Valo  * ip_frag
5205e3dd157SKalle Valo  *		Indicates that either the IP More frag bit is set or IP frag
5215e3dd157SKalle Valo  *		number is non-zero.  If set indicates that this is a
5225e3dd157SKalle Valo  *		fragmented IP packet.
5235e3dd157SKalle Valo  *
5245e3dd157SKalle Valo  * tcp_only_ack
5255e3dd157SKalle Valo  *		Set if only the TCP Ack bit is set in the TCP flags and if
5265e3dd157SKalle Valo  *		the TCP payload is 0.
5275e3dd157SKalle Valo  *
5285e3dd157SKalle Valo  * sa_idx
5295e3dd157SKalle Valo  *		The offset in the address table which matches the MAC source
5305e3dd157SKalle Valo  *		address.
5315e3dd157SKalle Valo  *
5325e3dd157SKalle Valo  * reserved_2b
5335e3dd157SKalle Valo  *		Reserved: HW should fill with zero.  FW should ignore.
5345e3dd157SKalle Valo  */
5355e3dd157SKalle Valo 
5365e3dd157SKalle Valo #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
5375e3dd157SKalle Valo #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB  0
5385e3dd157SKalle Valo #define RX_MSDU_END_INFO0_FIRST_MSDU                (1 << 14)
5395e3dd157SKalle Valo #define RX_MSDU_END_INFO0_LAST_MSDU                 (1 << 15)
5405e3dd157SKalle Valo #define RX_MSDU_END_INFO0_PRE_DELIM_ERR             (1 << 30)
5415e3dd157SKalle Valo #define RX_MSDU_END_INFO0_RESERVED_3B               (1 << 31)
5425e3dd157SKalle Valo 
5435e3dd157SKalle Valo struct rx_msdu_end {
5445e3dd157SKalle Valo 	__le16 ip_hdr_cksum;
5455e3dd157SKalle Valo 	__le16 tcp_hdr_cksum;
5465e3dd157SKalle Valo 	u8 key_id_octet;
5475e3dd157SKalle Valo 	u8 classification_filter;
5485e3dd157SKalle Valo 	u8 wapi_pn[10];
5495e3dd157SKalle Valo 	__le32 info0;
5505e3dd157SKalle Valo } __packed;
5515e3dd157SKalle Valo 
5525e3dd157SKalle Valo /*
5535e3dd157SKalle Valo  *ip_hdr_chksum
5545e3dd157SKalle Valo  *		This can include the IP header checksum or the pseudo header
5555e3dd157SKalle Valo  *		checksum used by TCP/UDP checksum.
5565e3dd157SKalle Valo  *
5575e3dd157SKalle Valo  *tcp_udp_chksum
5585e3dd157SKalle Valo  *		The value of the computed TCP/UDP checksum.  A mode bit
5595e3dd157SKalle Valo  *		selects whether this checksum is the full checksum or the
5605e3dd157SKalle Valo  *		partial checksum which does not include the pseudo header.
5615e3dd157SKalle Valo  *
5625e3dd157SKalle Valo  *key_id_octet
5635e3dd157SKalle Valo  *		The key ID octet from the IV.  Only valid when first_msdu is
5645e3dd157SKalle Valo  *		set.
5655e3dd157SKalle Valo  *
5665e3dd157SKalle Valo  *classification_filter
5675e3dd157SKalle Valo  *		Indicates the number classification filter rule
5685e3dd157SKalle Valo  *
5695e3dd157SKalle Valo  *ext_wapi_pn_63_48
5705e3dd157SKalle Valo  *		Extension PN (packet number) which is only used by WAPI.
5715e3dd157SKalle Valo  *		This corresponds to WAPI PN bits [63:48] (pn6 and pn7).  The
5725e3dd157SKalle Valo  *		WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
5735e3dd157SKalle Valo  *		descriptor.
5745e3dd157SKalle Valo  *
5755e3dd157SKalle Valo  *ext_wapi_pn_95_64
5765e3dd157SKalle Valo  *		Extension PN (packet number) which is only used by WAPI.
5775e3dd157SKalle Valo  *		This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and
5785e3dd157SKalle Valo  *		pn11).
5795e3dd157SKalle Valo  *
5805e3dd157SKalle Valo  *ext_wapi_pn_127_96
5815e3dd157SKalle Valo  *		Extension PN (packet number) which is only used by WAPI.
5825e3dd157SKalle Valo  *		This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14,
5835e3dd157SKalle Valo  *		pn15).
5845e3dd157SKalle Valo  *
5855e3dd157SKalle Valo  *reported_mpdu_length
5865e3dd157SKalle Valo  *		MPDU length before decapsulation.  Only valid when
5875e3dd157SKalle Valo  *		first_msdu is set.  This field is taken directly from the
5885e3dd157SKalle Valo  *		length field of the A-MPDU delimiter or the preamble length
5895e3dd157SKalle Valo  *		field for non-A-MPDU frames.
5905e3dd157SKalle Valo  *
5915e3dd157SKalle Valo  *first_msdu
5925e3dd157SKalle Valo  *		Indicates the first MSDU of A-MSDU.  If both first_msdu and
5935e3dd157SKalle Valo  *		last_msdu are set in the MSDU then this is a non-aggregated
5945e3dd157SKalle Valo  *		MSDU frame: normal MPDU.  Interior MSDU in an A-MSDU shall
5955e3dd157SKalle Valo  *		have both first_mpdu and last_mpdu bits set to 0.
5965e3dd157SKalle Valo  *
5975e3dd157SKalle Valo  *last_msdu
5985e3dd157SKalle Valo  *		Indicates the last MSDU of the A-MSDU.  MPDU end status is
5995e3dd157SKalle Valo  *		only valid when last_msdu is set.
6005e3dd157SKalle Valo  *
6015e3dd157SKalle Valo  *reserved_3a
6025e3dd157SKalle Valo  *		Reserved: HW should fill with zero.  FW should ignore.
6035e3dd157SKalle Valo  *
6045e3dd157SKalle Valo  *pre_delim_err
6055e3dd157SKalle Valo  *		Indicates that the first delimiter had a FCS failure.  Only
6065e3dd157SKalle Valo  *		valid when first_mpdu and first_msdu are set.
6075e3dd157SKalle Valo  *
6085e3dd157SKalle Valo  *reserved_3b
6095e3dd157SKalle Valo  *		Reserved: HW should fill with zero.  FW should ignore.
6105e3dd157SKalle Valo  */
6115e3dd157SKalle Valo 
6125e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_SELECT_OFDM 0
6135e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_SELECT_CCK  1
6145e3dd157SKalle Valo 
6155e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_48 0
6165e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_24 1
6175e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_12 2
6185e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_6  3
6195e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_54 4
6205e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_36 5
6215e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_18 6
6225e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_OFDM_9  7
6235e3dd157SKalle Valo 
6245e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_LP_11  0
6255e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_LP_5_5 1
6265e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_LP_2   2
6275e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_LP_1   3
6285e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_SP_11  4
6295e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_SP_5_5 5
6305e3dd157SKalle Valo #define RX_PPDU_START_SIG_RATE_CCK_SP_2   6
6315e3dd157SKalle Valo 
6325e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_LEGACY        0x04
6335e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_HT            0x08
6345e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF  0x09
6355e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_VHT           0x0C
6365e3dd157SKalle Valo #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
6375e3dd157SKalle Valo 
6385e3dd157SKalle Valo #define RX_PPDU_START_INFO0_IS_GREENFIELD (1 << 0)
6395e3dd157SKalle Valo 
6405e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK    0x0000000f
6415e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB     0
6425e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK  0x0001ffe0
6435e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB   5
6445e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK    0x00fc0000
6455e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB     18
6465e3dd157SKalle Valo #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
6475e3dd157SKalle Valo #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB  24
6485e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT  (1 << 4)
6495e3dd157SKalle Valo #define RX_PPDU_START_INFO1_L_SIG_PARITY       (1 << 17)
6505e3dd157SKalle Valo 
6515e3dd157SKalle Valo #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
6525e3dd157SKalle Valo #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB  0
6535e3dd157SKalle Valo 
6545e3dd157SKalle Valo #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
6555e3dd157SKalle Valo #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB  0
6565e3dd157SKalle Valo #define RX_PPDU_START_INFO3_TXBF_H_INFO             (1 << 24)
6575e3dd157SKalle Valo 
6585e3dd157SKalle Valo #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
6595e3dd157SKalle Valo #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB  0
6605e3dd157SKalle Valo 
6615e3dd157SKalle Valo #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
6625e3dd157SKalle Valo #define RX_PPDU_START_INFO5_SERVICE_LSB  0
6635e3dd157SKalle Valo 
6645e3dd157SKalle Valo struct rx_ppdu_start {
6655e3dd157SKalle Valo 	struct {
6665e3dd157SKalle Valo 		u8 pri20_mhz;
6675e3dd157SKalle Valo 		u8 ext20_mhz;
6685e3dd157SKalle Valo 		u8 ext40_mhz;
6695e3dd157SKalle Valo 		u8 ext80_mhz;
6705e3dd157SKalle Valo 	} rssi_chains[4];
6715e3dd157SKalle Valo 	u8 rssi_comb;
6725e3dd157SKalle Valo 	__le16 rsvd0;
6735e3dd157SKalle Valo 	u8 info0; /* %RX_PPDU_START_INFO0_ */
6745e3dd157SKalle Valo 	__le32 info1; /* %RX_PPDU_START_INFO1_ */
6755e3dd157SKalle Valo 	__le32 info2; /* %RX_PPDU_START_INFO2_ */
6765e3dd157SKalle Valo 	__le32 info3; /* %RX_PPDU_START_INFO3_ */
6775e3dd157SKalle Valo 	__le32 info4; /* %RX_PPDU_START_INFO4_ */
6785e3dd157SKalle Valo 	__le32 info5; /* %RX_PPDU_START_INFO5_ */
6795e3dd157SKalle Valo } __packed;
6805e3dd157SKalle Valo 
6815e3dd157SKalle Valo /*
6825e3dd157SKalle Valo  * rssi_chain0_pri20
6835e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
6845e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
6855e3dd157SKalle Valo  *
6865e3dd157SKalle Valo  * rssi_chain0_sec20
6875e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
6885e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
6895e3dd157SKalle Valo  *
6905e3dd157SKalle Valo  * rssi_chain0_sec40
6915e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
6925e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
6935e3dd157SKalle Valo  *
6945e3dd157SKalle Valo  * rssi_chain0_sec80
6955e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
6965e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
6975e3dd157SKalle Valo  *
6985e3dd157SKalle Valo  * rssi_chain1_pri20
6995e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
7005e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7015e3dd157SKalle Valo  *
7025e3dd157SKalle Valo  * rssi_chain1_sec20
7035e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
7045e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7055e3dd157SKalle Valo  *
7065e3dd157SKalle Valo  * rssi_chain1_sec40
7075e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
7085e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7095e3dd157SKalle Valo  *
7105e3dd157SKalle Valo  * rssi_chain1_sec80
7115e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
7125e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7135e3dd157SKalle Valo  *
7145e3dd157SKalle Valo  * rssi_chain2_pri20
7155e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
7165e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7175e3dd157SKalle Valo  *
7185e3dd157SKalle Valo  * rssi_chain2_sec20
7195e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth.
7205e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7215e3dd157SKalle Valo  *
7225e3dd157SKalle Valo  * rssi_chain2_sec40
7235e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth.
7245e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7255e3dd157SKalle Valo  *
7265e3dd157SKalle Valo  * rssi_chain2_sec80
7275e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth.
7285e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7295e3dd157SKalle Valo  *
7305e3dd157SKalle Valo  * rssi_chain3_pri20
7315e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
7325e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7335e3dd157SKalle Valo  *
7345e3dd157SKalle Valo  * rssi_chain3_sec20
7355e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth.
7365e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7375e3dd157SKalle Valo  *
7385e3dd157SKalle Valo  * rssi_chain3_sec40
7395e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth.
7405e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7415e3dd157SKalle Valo  *
7425e3dd157SKalle Valo  * rssi_chain3_sec80
7435e3dd157SKalle Valo  *		RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth.
7445e3dd157SKalle Valo  *		Value of 0x80 indicates invalid.
7455e3dd157SKalle Valo  *
7465e3dd157SKalle Valo  * rssi_comb
7475e3dd157SKalle Valo  *		The combined RSSI of RX PPDU of all active chains and
7485e3dd157SKalle Valo  *		bandwidths.  Value of 0x80 indicates invalid.
7495e3dd157SKalle Valo  *
7505e3dd157SKalle Valo  * reserved_4a
7515e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
7525e3dd157SKalle Valo  *
7535e3dd157SKalle Valo  * is_greenfield
7545e3dd157SKalle Valo  *		Do we really support this?
7555e3dd157SKalle Valo  *
7565e3dd157SKalle Valo  * reserved_4b
7575e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
7585e3dd157SKalle Valo  *
7595e3dd157SKalle Valo  * l_sig_rate
7605e3dd157SKalle Valo  *		If l_sig_rate_select is 0:
7615e3dd157SKalle Valo  *		0x8: OFDM 48 Mbps
7625e3dd157SKalle Valo  *		0x9: OFDM 24 Mbps
7635e3dd157SKalle Valo  *		0xA: OFDM 12 Mbps
7645e3dd157SKalle Valo  *		0xB: OFDM 6 Mbps
7655e3dd157SKalle Valo  *		0xC: OFDM 54 Mbps
7665e3dd157SKalle Valo  *		0xD: OFDM 36 Mbps
7675e3dd157SKalle Valo  *		0xE: OFDM 18 Mbps
7685e3dd157SKalle Valo  *		0xF: OFDM 9 Mbps
7695e3dd157SKalle Valo  *		If l_sig_rate_select is 1:
7705e3dd157SKalle Valo  *		0x8: CCK 11 Mbps long preamble
7715e3dd157SKalle Valo  *		0x9: CCK 5.5 Mbps long preamble
7725e3dd157SKalle Valo  *		0xA: CCK 2 Mbps long preamble
7735e3dd157SKalle Valo  *		0xB: CCK 1 Mbps long preamble
7745e3dd157SKalle Valo  *		0xC: CCK 11 Mbps short preamble
7755e3dd157SKalle Valo  *		0xD: CCK 5.5 Mbps short preamble
7765e3dd157SKalle Valo  *		0xE: CCK 2 Mbps short preamble
7775e3dd157SKalle Valo  *
7785e3dd157SKalle Valo  * l_sig_rate_select
7795e3dd157SKalle Valo  *		Legacy signal rate select.  If set then l_sig_rate indicates
7805e3dd157SKalle Valo  *		CCK rates.  If clear then l_sig_rate indicates OFDM rates.
7815e3dd157SKalle Valo  *
7825e3dd157SKalle Valo  * l_sig_length
7835e3dd157SKalle Valo  *		Length of legacy frame in octets.
7845e3dd157SKalle Valo  *
7855e3dd157SKalle Valo  * l_sig_parity
7865e3dd157SKalle Valo  *		Odd parity over l_sig_rate and l_sig_length
7875e3dd157SKalle Valo  *
7885e3dd157SKalle Valo  * l_sig_tail
7895e3dd157SKalle Valo  *		Tail bits for Viterbi decoder
7905e3dd157SKalle Valo  *
7915e3dd157SKalle Valo  * preamble_type
7925e3dd157SKalle Valo  *		Indicates the type of preamble ahead:
7935e3dd157SKalle Valo  *		0x4: Legacy (OFDM/CCK)
7945e3dd157SKalle Valo  *		0x8: HT
7955e3dd157SKalle Valo  *		0x9: HT with TxBF
7965e3dd157SKalle Valo  *		0xC: VHT
7975e3dd157SKalle Valo  *		0xD: VHT with TxBF
7985e3dd157SKalle Valo  *		0x80 - 0xFF: Reserved for special baseband data types such
7995e3dd157SKalle Valo  *		as radar and spectral scan.
8005e3dd157SKalle Valo  *
8015e3dd157SKalle Valo  * ht_sig_vht_sig_a_1
8025e3dd157SKalle Valo  *		If preamble_type == 0x8 or 0x9
8035e3dd157SKalle Valo  *		HT-SIG (first 24 bits)
8045e3dd157SKalle Valo  *		If preamble_type == 0xC or 0xD
8055e3dd157SKalle Valo  *		VHT-SIG A (first 24 bits)
8065e3dd157SKalle Valo  *		Else
8075e3dd157SKalle Valo  *		Reserved
8085e3dd157SKalle Valo  *
8095e3dd157SKalle Valo  * reserved_6
8105e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
8115e3dd157SKalle Valo  *
8125e3dd157SKalle Valo  * ht_sig_vht_sig_a_2
8135e3dd157SKalle Valo  *		If preamble_type == 0x8 or 0x9
8145e3dd157SKalle Valo  *		HT-SIG (last 24 bits)
8155e3dd157SKalle Valo  *		If preamble_type == 0xC or 0xD
8165e3dd157SKalle Valo  *		VHT-SIG A (last 24 bits)
8175e3dd157SKalle Valo  *		Else
8185e3dd157SKalle Valo  *		Reserved
8195e3dd157SKalle Valo  *
8205e3dd157SKalle Valo  * txbf_h_info
8215e3dd157SKalle Valo  *		Indicates that the packet data carries H information which
8225e3dd157SKalle Valo  *		is used for TxBF debug.
8235e3dd157SKalle Valo  *
8245e3dd157SKalle Valo  * reserved_7
8255e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
8265e3dd157SKalle Valo  *
8275e3dd157SKalle Valo  * vht_sig_b
8285e3dd157SKalle Valo  *		WiFi 1.0 and WiFi 2.0 will likely have this field to be all
8295e3dd157SKalle Valo  *		0s since the BB does not plan on decoding VHT SIG-B.
8305e3dd157SKalle Valo  *
8315e3dd157SKalle Valo  * reserved_8
8325e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
8335e3dd157SKalle Valo  *
8345e3dd157SKalle Valo  * service
8355e3dd157SKalle Valo  *		Service field from BB for OFDM, HT and VHT packets.  CCK
8365e3dd157SKalle Valo  *		packets will have service field of 0.
8375e3dd157SKalle Valo  *
8385e3dd157SKalle Valo  * reserved_9
8395e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
8405e3dd157SKalle Valo */
8415e3dd157SKalle Valo 
8425e3dd157SKalle Valo 
8435e3dd157SKalle Valo #define RX_PPDU_END_FLAGS_PHY_ERR             (1 << 0)
8445e3dd157SKalle Valo #define RX_PPDU_END_FLAGS_RX_LOCATION         (1 << 1)
8455e3dd157SKalle Valo #define RX_PPDU_END_FLAGS_TXBF_H_INFO         (1 << 2)
8465e3dd157SKalle Valo 
8475e3dd157SKalle Valo #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK     0x00ffffff
8485e3dd157SKalle Valo #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB      0
8495e3dd157SKalle Valo #define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK (1 << 24)
8505e3dd157SKalle Valo #define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL (1 << 25)
8515e3dd157SKalle Valo 
8525e3dd157SKalle Valo #define RX_PPDU_END_INFO1_PPDU_DONE (1 << 15)
8535e3dd157SKalle Valo 
8545e3dd157SKalle Valo struct rx_ppdu_end {
8555e3dd157SKalle Valo 	__le32 evm_p0;
8565e3dd157SKalle Valo 	__le32 evm_p1;
8575e3dd157SKalle Valo 	__le32 evm_p2;
8585e3dd157SKalle Valo 	__le32 evm_p3;
8595e3dd157SKalle Valo 	__le32 evm_p4;
8605e3dd157SKalle Valo 	__le32 evm_p5;
8615e3dd157SKalle Valo 	__le32 evm_p6;
8625e3dd157SKalle Valo 	__le32 evm_p7;
8635e3dd157SKalle Valo 	__le32 evm_p8;
8645e3dd157SKalle Valo 	__le32 evm_p9;
8655e3dd157SKalle Valo 	__le32 evm_p10;
8665e3dd157SKalle Valo 	__le32 evm_p11;
8675e3dd157SKalle Valo 	__le32 evm_p12;
8685e3dd157SKalle Valo 	__le32 evm_p13;
8695e3dd157SKalle Valo 	__le32 evm_p14;
8705e3dd157SKalle Valo 	__le32 evm_p15;
8715e3dd157SKalle Valo 	__le32 tsf_timestamp;
8725e3dd157SKalle Valo 	__le32 wb_timestamp;
8735e3dd157SKalle Valo 	u8 locationing_timestamp;
8745e3dd157SKalle Valo 	u8 phy_err_code;
8755e3dd157SKalle Valo 	__le16 flags; /* %RX_PPDU_END_FLAGS_ */
8765e3dd157SKalle Valo 	__le32 info0; /* %RX_PPDU_END_INFO0_ */
8775e3dd157SKalle Valo 	__le16 bb_length;
8785e3dd157SKalle Valo 	__le16 info1; /* %RX_PPDU_END_INFO1_ */
8795e3dd157SKalle Valo } __packed;
8805e3dd157SKalle Valo 
8815e3dd157SKalle Valo /*
8825e3dd157SKalle Valo  * evm_p0
8835e3dd157SKalle Valo  *		EVM for pilot 0.  Contain EVM for streams: 0, 1, 2 and 3.
8845e3dd157SKalle Valo  *
8855e3dd157SKalle Valo  * evm_p1
8865e3dd157SKalle Valo  *		EVM for pilot 1.  Contain EVM for streams: 0, 1, 2 and 3.
8875e3dd157SKalle Valo  *
8885e3dd157SKalle Valo  * evm_p2
8895e3dd157SKalle Valo  *		EVM for pilot 2.  Contain EVM for streams: 0, 1, 2 and 3.
8905e3dd157SKalle Valo  *
8915e3dd157SKalle Valo  * evm_p3
8925e3dd157SKalle Valo  *		EVM for pilot 3.  Contain EVM for streams: 0, 1, 2 and 3.
8935e3dd157SKalle Valo  *
8945e3dd157SKalle Valo  * evm_p4
8955e3dd157SKalle Valo  *		EVM for pilot 4.  Contain EVM for streams: 0, 1, 2 and 3.
8965e3dd157SKalle Valo  *
8975e3dd157SKalle Valo  * evm_p5
8985e3dd157SKalle Valo  *		EVM for pilot 5.  Contain EVM for streams: 0, 1, 2 and 3.
8995e3dd157SKalle Valo  *
9005e3dd157SKalle Valo  * evm_p6
9015e3dd157SKalle Valo  *		EVM for pilot 6.  Contain EVM for streams: 0, 1, 2 and 3.
9025e3dd157SKalle Valo  *
9035e3dd157SKalle Valo  * evm_p7
9045e3dd157SKalle Valo  *		EVM for pilot 7.  Contain EVM for streams: 0, 1, 2 and 3.
9055e3dd157SKalle Valo  *
9065e3dd157SKalle Valo  * evm_p8
9075e3dd157SKalle Valo  *		EVM for pilot 8.  Contain EVM for streams: 0, 1, 2 and 3.
9085e3dd157SKalle Valo  *
9095e3dd157SKalle Valo  * evm_p9
9105e3dd157SKalle Valo  *		EVM for pilot 9.  Contain EVM for streams: 0, 1, 2 and 3.
9115e3dd157SKalle Valo  *
9125e3dd157SKalle Valo  * evm_p10
9135e3dd157SKalle Valo  *		EVM for pilot 10.  Contain EVM for streams: 0, 1, 2 and 3.
9145e3dd157SKalle Valo  *
9155e3dd157SKalle Valo  * evm_p11
9165e3dd157SKalle Valo  *		EVM for pilot 11.  Contain EVM for streams: 0, 1, 2 and 3.
9175e3dd157SKalle Valo  *
9185e3dd157SKalle Valo  * evm_p12
9195e3dd157SKalle Valo  *		EVM for pilot 12.  Contain EVM for streams: 0, 1, 2 and 3.
9205e3dd157SKalle Valo  *
9215e3dd157SKalle Valo  * evm_p13
9225e3dd157SKalle Valo  *		EVM for pilot 13.  Contain EVM for streams: 0, 1, 2 and 3.
9235e3dd157SKalle Valo  *
9245e3dd157SKalle Valo  * evm_p14
9255e3dd157SKalle Valo  *		EVM for pilot 14.  Contain EVM for streams: 0, 1, 2 and 3.
9265e3dd157SKalle Valo  *
9275e3dd157SKalle Valo  * evm_p15
9285e3dd157SKalle Valo  *		EVM for pilot 15.  Contain EVM for streams: 0, 1, 2 and 3.
9295e3dd157SKalle Valo  *
9305e3dd157SKalle Valo  * tsf_timestamp
9315e3dd157SKalle Valo  *		Receive TSF timestamp sampled on the rising edge of
9325e3dd157SKalle Valo  *		rx_clear.  For PHY errors this may be the current TSF when
9335e3dd157SKalle Valo  *		phy_error is asserted if the rx_clear does not assert before
9345e3dd157SKalle Valo  *		the end of the PHY error.
9355e3dd157SKalle Valo  *
9365e3dd157SKalle Valo  * wb_timestamp
9375e3dd157SKalle Valo  *		WLAN/BT timestamp is a 1 usec resolution timestamp which
9385e3dd157SKalle Valo  *		does not get updated based on receive beacon like TSF.  The
9395e3dd157SKalle Valo  *		same rules for capturing tsf_timestamp are used to capture
9405e3dd157SKalle Valo  *		the wb_timestamp.
9415e3dd157SKalle Valo  *
9425e3dd157SKalle Valo  * locationing_timestamp
9435e3dd157SKalle Valo  *		Timestamp used for locationing.  This timestamp is used to
9445e3dd157SKalle Valo  *		indicate fractions of usec.  For example if the MAC clock is
9455e3dd157SKalle Valo  *		running at 80 MHz, the timestamp will increment every 12.5
9465e3dd157SKalle Valo  *		nsec.  The value starts at 0 and increments to 79 and
9475e3dd157SKalle Valo  *		returns to 0 and repeats.  This information is valid for
9485e3dd157SKalle Valo  *		every PPDU.  This information can be used in conjunction
9495e3dd157SKalle Valo  *		with wb_timestamp to capture large delta times.
9505e3dd157SKalle Valo  *
9515e3dd157SKalle Valo  * phy_err_code
9525e3dd157SKalle Valo  *		See the 1.10.8.1.2 for the list of the PHY error codes.
9535e3dd157SKalle Valo  *
9545e3dd157SKalle Valo  * phy_err
9555e3dd157SKalle Valo  *		Indicates a PHY error was detected for this PPDU.
9565e3dd157SKalle Valo  *
9575e3dd157SKalle Valo  * rx_location
9585e3dd157SKalle Valo  *		Indicates that location information was requested.
9595e3dd157SKalle Valo  *
9605e3dd157SKalle Valo  * txbf_h_info
9615e3dd157SKalle Valo  *		Indicates that the packet data carries H information which
9625e3dd157SKalle Valo  *		is used for TxBF debug.
9635e3dd157SKalle Valo  *
9645e3dd157SKalle Valo  * reserved_18
9655e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
9665e3dd157SKalle Valo  *
9675e3dd157SKalle Valo  * rx_antenna
9685e3dd157SKalle Valo  *		Receive antenna value
9695e3dd157SKalle Valo  *
9705e3dd157SKalle Valo  * tx_ht_vht_ack
9715e3dd157SKalle Valo  *		Indicates that a HT or VHT Ack/BA frame was transmitted in
9725e3dd157SKalle Valo  *		response to this receive packet.
9735e3dd157SKalle Valo  *
9745e3dd157SKalle Valo  * bb_captured_channel
9755e3dd157SKalle Valo  *		Indicates that the BB has captured a channel dump.  FW can
9765e3dd157SKalle Valo  *		then read the channel dump memory.  This may indicate that
9775e3dd157SKalle Valo  *		the channel was captured either based on PCU setting the
9785e3dd157SKalle Valo  *		capture_channel bit  BB descriptor or FW setting the
9795e3dd157SKalle Valo  *		capture_channel mode bit.
9805e3dd157SKalle Valo  *
9815e3dd157SKalle Valo  * reserved_19
9825e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
9835e3dd157SKalle Valo  *
9845e3dd157SKalle Valo  * bb_length
9855e3dd157SKalle Valo  *		Indicates the number of bytes of baseband information for
9865e3dd157SKalle Valo  *		PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
9875e3dd157SKalle Valo  *		which indicates that this is not a normal PPDU but rather
9885e3dd157SKalle Valo  *		contains baseband debug information.
9895e3dd157SKalle Valo  *
9905e3dd157SKalle Valo  * reserved_20
9915e3dd157SKalle Valo  *		Reserved: HW should fill with 0, FW should ignore.
9925e3dd157SKalle Valo  *
9935e3dd157SKalle Valo  * ppdu_done
9945e3dd157SKalle Valo  *		PPDU end status is only valid when ppdu_done bit is set.
9955e3dd157SKalle Valo  *		Every time HW sets this bit in memory FW/SW must clear this
9965e3dd157SKalle Valo  *		bit in memory.  FW will initialize all the ppdu_done dword
9975e3dd157SKalle Valo  *		to 0.
9985e3dd157SKalle Valo */
9995e3dd157SKalle Valo 
10005e3dd157SKalle Valo #define FW_RX_DESC_INFO0_DISCARD  (1 << 0)
10015e3dd157SKalle Valo #define FW_RX_DESC_INFO0_FORWARD  (1 << 1)
10025e3dd157SKalle Valo #define FW_RX_DESC_INFO0_INSPECT  (1 << 5)
10035e3dd157SKalle Valo #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
10045e3dd157SKalle Valo #define FW_RX_DESC_INFO0_EXT_LSB  6
10055e3dd157SKalle Valo 
10065e3dd157SKalle Valo struct fw_rx_desc_base {
10075e3dd157SKalle Valo 	u8 info0;
10085e3dd157SKalle Valo } __packed;
10095e3dd157SKalle Valo 
10105e3dd157SKalle Valo #endif /* _RX_DESC_H_ */
1011