1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef _ATH10K_QMI_H_ 17 #define _ATH10K_QMI_H_ 18 19 #include <linux/soc/qcom/qmi.h> 20 #include <linux/qrtr.h> 21 #include "qmi_wlfw_v01.h" 22 23 #define MAX_NUM_MEMORY_REGIONS 2 24 #define MAX_TIMESTAMP_LEN 32 25 #define MAX_BUILD_ID_LEN 128 26 #define MAX_NUM_CAL_V01 5 27 28 enum ath10k_qmi_driver_event_type { 29 ATH10K_QMI_EVENT_SERVER_ARRIVE, 30 ATH10K_QMI_EVENT_SERVER_EXIT, 31 ATH10K_QMI_EVENT_FW_READY_IND, 32 ATH10K_QMI_EVENT_FW_DOWN_IND, 33 ATH10K_QMI_EVENT_MSA_READY_IND, 34 ATH10K_QMI_EVENT_MAX, 35 }; 36 37 struct ath10k_msa_mem_info { 38 phys_addr_t addr; 39 u32 size; 40 bool secure; 41 }; 42 43 struct ath10k_qmi_chip_info { 44 u32 chip_id; 45 u32 chip_family; 46 }; 47 48 struct ath10k_qmi_board_info { 49 u32 board_id; 50 }; 51 52 struct ath10k_qmi_soc_info { 53 u32 soc_id; 54 }; 55 56 struct ath10k_qmi_cal_data { 57 u32 cal_id; 58 u32 total_size; 59 u8 *data; 60 }; 61 62 struct ath10k_tgt_pipe_cfg { 63 __le32 pipe_num; 64 __le32 pipe_dir; 65 __le32 nentries; 66 __le32 nbytes_max; 67 __le32 flags; 68 __le32 reserved; 69 }; 70 71 struct ath10k_svc_pipe_cfg { 72 __le32 service_id; 73 __le32 pipe_dir; 74 __le32 pipe_num; 75 }; 76 77 struct ath10k_shadow_reg_cfg { 78 __le16 ce_id; 79 __le16 reg_offset; 80 }; 81 82 struct ath10k_qmi_wlan_enable_cfg { 83 u32 num_ce_tgt_cfg; 84 struct ath10k_tgt_pipe_cfg *ce_tgt_cfg; 85 u32 num_ce_svc_pipe_cfg; 86 struct ath10k_svc_pipe_cfg *ce_svc_cfg; 87 u32 num_shadow_reg_cfg; 88 struct ath10k_shadow_reg_cfg *shadow_reg_cfg; 89 }; 90 91 struct ath10k_qmi_driver_event { 92 struct list_head list; 93 enum ath10k_qmi_driver_event_type type; 94 void *data; 95 }; 96 97 struct ath10k_qmi { 98 struct ath10k *ar; 99 struct qmi_handle qmi_hdl; 100 struct sockaddr_qrtr sq; 101 struct work_struct event_work; 102 struct workqueue_struct *event_wq; 103 struct list_head event_list; 104 spinlock_t event_lock; /* spinlock for qmi event list */ 105 u32 nr_mem_region; 106 struct ath10k_msa_mem_info mem_region[MAX_NUM_MEMORY_REGIONS]; 107 dma_addr_t msa_pa; 108 u32 msa_mem_size; 109 void *msa_va; 110 struct ath10k_qmi_chip_info chip_info; 111 struct ath10k_qmi_board_info board_info; 112 struct ath10k_qmi_soc_info soc_info; 113 char fw_build_id[MAX_BUILD_ID_LEN + 1]; 114 u32 fw_version; 115 bool fw_ready; 116 char fw_build_timestamp[MAX_TIMESTAMP_LEN + 1]; 117 struct ath10k_qmi_cal_data cal_data[MAX_NUM_CAL_V01]; 118 }; 119 120 int ath10k_qmi_wlan_enable(struct ath10k *ar, 121 struct ath10k_qmi_wlan_enable_cfg *config, 122 enum wlfw_driver_mode_enum_v01 mode, 123 const char *version); 124 int ath10k_qmi_wlan_disable(struct ath10k *ar); 125 int ath10k_qmi_register_service_notifier(struct notifier_block *nb); 126 int ath10k_qmi_init(struct ath10k *ar, u32 msa_size); 127 int ath10k_qmi_deinit(struct ath10k *ar); 128 129 #endif /* ATH10K_QMI_H */ 130