1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _PCI_H_ 19 #define _PCI_H_ 20 21 #include <linux/interrupt.h> 22 23 #include "hw.h" 24 #include "ce.h" 25 #include "ahb.h" 26 27 /* 28 * maximum number of bytes that can be 29 * handled atomically by DiagRead/DiagWrite 30 */ 31 #define DIAG_TRANSFER_LIMIT 2048 32 33 struct bmi_xfer { 34 bool tx_done; 35 bool rx_done; 36 bool wait_for_resp; 37 u32 resp_len; 38 }; 39 40 /* 41 * PCI-specific Target state 42 * 43 * NOTE: Structure is shared between Host software and Target firmware! 44 * 45 * Much of this may be of interest to the Host so 46 * HOST_INTEREST->hi_interconnect_state points here 47 * (and all members are 32-bit quantities in order to 48 * facilitate Host access). In particular, Host software is 49 * required to initialize pipe_cfg_addr and svc_to_pipe_map. 50 */ 51 struct pcie_state { 52 /* Pipe configuration Target address */ 53 /* NB: ce_pipe_config[CE_COUNT] */ 54 u32 pipe_cfg_addr; 55 56 /* Service to pipe map Target address */ 57 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ 58 u32 svc_to_pipe_map; 59 60 /* number of MSI interrupts requested */ 61 u32 msi_requested; 62 63 /* number of MSI interrupts granted */ 64 u32 msi_granted; 65 66 /* Message Signalled Interrupt address */ 67 u32 msi_addr; 68 69 /* Base data */ 70 u32 msi_data; 71 72 /* 73 * Data for firmware interrupt; 74 * MSI data for other interrupts are 75 * in various SoC registers 76 */ 77 u32 msi_fw_intr_data; 78 79 /* PCIE_PWR_METHOD_* */ 80 u32 power_mgmt_method; 81 82 /* PCIE_CONFIG_FLAG_* */ 83 u32 config_flags; 84 }; 85 86 /* PCIE_CONFIG_FLAG definitions */ 87 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 88 89 /* Per-pipe state. */ 90 struct ath10k_pci_pipe { 91 /* Handle of underlying Copy Engine */ 92 struct ath10k_ce_pipe *ce_hdl; 93 94 /* Our pipe number; facilitiates use of pipe_info ptrs. */ 95 u8 pipe_num; 96 97 /* Convenience back pointer to hif_ce_state. */ 98 struct ath10k *hif_ce_state; 99 100 size_t buf_sz; 101 102 /* protects compl_free and num_send_allowed */ 103 spinlock_t pipe_lock; 104 }; 105 106 struct ath10k_pci_supp_chip { 107 u32 dev_id; 108 u32 rev_id; 109 }; 110 111 enum ath10k_pci_irq_mode { 112 ATH10K_PCI_IRQ_AUTO = 0, 113 ATH10K_PCI_IRQ_LEGACY = 1, 114 ATH10K_PCI_IRQ_MSI = 2, 115 }; 116 117 struct ath10k_pci { 118 struct pci_dev *pdev; 119 struct device *dev; 120 struct ath10k *ar; 121 void __iomem *mem; 122 size_t mem_len; 123 124 /* Operating interrupt mode */ 125 enum ath10k_pci_irq_mode oper_irq_mode; 126 127 struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; 128 129 /* Copy Engine used for Diagnostic Accesses */ 130 struct ath10k_ce_pipe *ce_diag; 131 132 struct ath10k_ce ce; 133 struct timer_list rx_post_retry; 134 135 /* Due to HW quirks it is recommended to disable ASPM during device 136 * bootup. To do that the original PCI-E Link Control is stored before 137 * device bootup is executed and re-programmed later. 138 */ 139 u16 link_ctl; 140 141 /* Protects ps_awake and ps_wake_refcount */ 142 spinlock_t ps_lock; 143 144 /* The device has a special powersave-oriented register. When device is 145 * considered asleep it drains less power and driver is forbidden from 146 * accessing most MMIO registers. If host were to access them without 147 * waking up the device might scribble over host memory or return 148 * 0xdeadbeef readouts. 149 */ 150 unsigned long ps_wake_refcount; 151 152 /* Waking up takes some time (up to 2ms in some cases) so it can be bad 153 * for latency. To mitigate this the device isn't immediately allowed 154 * to sleep after all references are undone - instead there's a grace 155 * period after which the powersave register is updated unless some 156 * activity to/from device happened in the meantime. 157 * 158 * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC. 159 */ 160 struct timer_list ps_timer; 161 162 /* MMIO registers are used to communicate with the device. With 163 * intensive traffic accessing powersave register would be a bit 164 * wasteful overhead and would needlessly stall CPU. It is far more 165 * efficient to rely on a variable in RAM and update it only upon 166 * powersave register state changes. 167 */ 168 bool ps_awake; 169 170 /* pci power save, disable for QCA988X and QCA99X0. 171 * Writing 'false' to this variable avoids frequent locking 172 * on MMIO read/write. 173 */ 174 bool pci_ps; 175 176 /* Chip specific pci reset routine used to do a safe reset */ 177 int (*pci_soft_reset)(struct ath10k *ar); 178 179 /* Chip specific pci full reset function */ 180 int (*pci_hard_reset)(struct ath10k *ar); 181 182 /* chip specific methods for converting target CPU virtual address 183 * space to CE address space 184 */ 185 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 186 187 /* Keep this entry in the last, memory for struct ath10k_ahb is 188 * allocated (ahb support enabled case) in the continuation of 189 * this struct. 190 */ 191 struct ath10k_ahb ahb[0]; 192 }; 193 194 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) 195 { 196 return (struct ath10k_pci *)ar->drv_priv; 197 } 198 199 #define ATH10K_PCI_RX_POST_RETRY_MS 50 200 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */ 201 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */ 202 #define PCIE_WAKE_LATE_US 10000 /* 10ms */ 203 204 #define BAR_NUM 0 205 206 #define CDC_WAR_MAGIC_STR 0xceef0000 207 #define CDC_WAR_DATA_CE 4 208 209 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */ 210 #define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */ 211 #define DIAG_ACCESS_CE_WAIT_US 50 212 213 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value); 214 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val); 215 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val); 216 217 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset); 218 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr); 219 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr); 220 221 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 222 struct ath10k_hif_sg_item *items, int n_items); 223 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 224 size_t buf_len); 225 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 226 const void *data, int nbytes); 227 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len, 228 void *resp, u32 *resp_len); 229 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 230 u8 *ul_pipe, u8 *dl_pipe); 231 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe, 232 u8 *dl_pipe); 233 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 234 int force); 235 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe); 236 void ath10k_pci_hif_power_down(struct ath10k *ar); 237 int ath10k_pci_alloc_pipes(struct ath10k *ar); 238 void ath10k_pci_free_pipes(struct ath10k *ar); 239 void ath10k_pci_free_pipes(struct ath10k *ar); 240 void ath10k_pci_rx_replenish_retry(struct timer_list *t); 241 void ath10k_pci_ce_deinit(struct ath10k *ar); 242 void ath10k_pci_init_napi(struct ath10k *ar); 243 int ath10k_pci_init_pipes(struct ath10k *ar); 244 int ath10k_pci_init_config(struct ath10k *ar); 245 void ath10k_pci_rx_post(struct ath10k *ar); 246 void ath10k_pci_flush(struct ath10k *ar); 247 void ath10k_pci_enable_legacy_irq(struct ath10k *ar); 248 bool ath10k_pci_irq_pending(struct ath10k *ar); 249 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar); 250 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar); 251 int ath10k_pci_wait_for_target_init(struct ath10k *ar); 252 int ath10k_pci_setup_resource(struct ath10k *ar); 253 void ath10k_pci_release_resource(struct ath10k *ar); 254 255 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too 256 * frequently. To avoid this put SoC to sleep after a very conservative grace 257 * period. Adjust with great care. 258 */ 259 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60 260 261 #endif /* _PCI_H_ */ 262