1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/pci.h> 19 #include <linux/module.h> 20 #include <linux/interrupt.h> 21 #include <linux/spinlock.h> 22 #include <linux/bitops.h> 23 24 #include "core.h" 25 #include "debug.h" 26 27 #include "targaddrs.h" 28 #include "bmi.h" 29 30 #include "hif.h" 31 #include "htc.h" 32 33 #include "ce.h" 34 #include "pci.h" 35 36 enum ath10k_pci_reset_mode { 37 ATH10K_PCI_RESET_AUTO = 0, 38 ATH10K_PCI_RESET_WARM_ONLY = 1, 39 }; 40 41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 43 44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 46 47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 49 50 /* how long wait to wait for target to initialise, in ms */ 51 #define ATH10K_PCI_TARGET_WAIT 3000 52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 53 54 static const struct pci_device_id ath10k_pci_id_table[] = { 55 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 56 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 57 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 58 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 59 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 60 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 61 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 62 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 63 {0} 64 }; 65 66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 67 /* QCA988X pre 2.0 chips are not supported because they need some nasty 68 * hacks. ath10k doesn't have them and these devices crash horribly 69 * because of that. 70 */ 71 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 72 73 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 74 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 75 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 78 79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 80 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 81 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 84 85 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 86 87 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 88 89 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 90 91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 92 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 93 94 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 95 }; 96 97 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 98 static int ath10k_pci_cold_reset(struct ath10k *ar); 99 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 100 static int ath10k_pci_init_irq(struct ath10k *ar); 101 static int ath10k_pci_deinit_irq(struct ath10k *ar); 102 static int ath10k_pci_request_irq(struct ath10k *ar); 103 static void ath10k_pci_free_irq(struct ath10k *ar); 104 static int ath10k_pci_bmi_wait(struct ath10k *ar, 105 struct ath10k_ce_pipe *tx_pipe, 106 struct ath10k_ce_pipe *rx_pipe, 107 struct bmi_xfer *xfer); 108 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 109 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 110 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 111 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 112 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 113 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 114 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 115 116 static struct ce_attr host_ce_config_wlan[] = { 117 /* CE0: host->target HTC control and raw streams */ 118 { 119 .flags = CE_ATTR_FLAGS, 120 .src_nentries = 16, 121 .src_sz_max = 256, 122 .dest_nentries = 0, 123 .send_cb = ath10k_pci_htc_tx_cb, 124 }, 125 126 /* CE1: target->host HTT + HTC control */ 127 { 128 .flags = CE_ATTR_FLAGS, 129 .src_nentries = 0, 130 .src_sz_max = 2048, 131 .dest_nentries = 512, 132 .recv_cb = ath10k_pci_htt_htc_rx_cb, 133 }, 134 135 /* CE2: target->host WMI */ 136 { 137 .flags = CE_ATTR_FLAGS, 138 .src_nentries = 0, 139 .src_sz_max = 2048, 140 .dest_nentries = 128, 141 .recv_cb = ath10k_pci_htc_rx_cb, 142 }, 143 144 /* CE3: host->target WMI */ 145 { 146 .flags = CE_ATTR_FLAGS, 147 .src_nentries = 32, 148 .src_sz_max = 2048, 149 .dest_nentries = 0, 150 .send_cb = ath10k_pci_htc_tx_cb, 151 }, 152 153 /* CE4: host->target HTT */ 154 { 155 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 156 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 157 .src_sz_max = 256, 158 .dest_nentries = 0, 159 .send_cb = ath10k_pci_htt_tx_cb, 160 }, 161 162 /* CE5: target->host HTT (HIF->HTT) */ 163 { 164 .flags = CE_ATTR_FLAGS, 165 .src_nentries = 0, 166 .src_sz_max = 512, 167 .dest_nentries = 512, 168 .recv_cb = ath10k_pci_htt_rx_cb, 169 }, 170 171 /* CE6: target autonomous hif_memcpy */ 172 { 173 .flags = CE_ATTR_FLAGS, 174 .src_nentries = 0, 175 .src_sz_max = 0, 176 .dest_nentries = 0, 177 }, 178 179 /* CE7: ce_diag, the Diagnostic Window */ 180 { 181 .flags = CE_ATTR_FLAGS, 182 .src_nentries = 2, 183 .src_sz_max = DIAG_TRANSFER_LIMIT, 184 .dest_nentries = 2, 185 }, 186 187 /* CE8: target->host pktlog */ 188 { 189 .flags = CE_ATTR_FLAGS, 190 .src_nentries = 0, 191 .src_sz_max = 2048, 192 .dest_nentries = 128, 193 .recv_cb = ath10k_pci_pktlog_rx_cb, 194 }, 195 196 /* CE9 target autonomous qcache memcpy */ 197 { 198 .flags = CE_ATTR_FLAGS, 199 .src_nentries = 0, 200 .src_sz_max = 0, 201 .dest_nentries = 0, 202 }, 203 204 /* CE10: target autonomous hif memcpy */ 205 { 206 .flags = CE_ATTR_FLAGS, 207 .src_nentries = 0, 208 .src_sz_max = 0, 209 .dest_nentries = 0, 210 }, 211 212 /* CE11: target autonomous hif memcpy */ 213 { 214 .flags = CE_ATTR_FLAGS, 215 .src_nentries = 0, 216 .src_sz_max = 0, 217 .dest_nentries = 0, 218 }, 219 }; 220 221 /* Target firmware's Copy Engine configuration. */ 222 static struct ce_pipe_config target_ce_config_wlan[] = { 223 /* CE0: host->target HTC control and raw streams */ 224 { 225 .pipenum = __cpu_to_le32(0), 226 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 227 .nentries = __cpu_to_le32(32), 228 .nbytes_max = __cpu_to_le32(256), 229 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 230 .reserved = __cpu_to_le32(0), 231 }, 232 233 /* CE1: target->host HTT + HTC control */ 234 { 235 .pipenum = __cpu_to_le32(1), 236 .pipedir = __cpu_to_le32(PIPEDIR_IN), 237 .nentries = __cpu_to_le32(32), 238 .nbytes_max = __cpu_to_le32(2048), 239 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 240 .reserved = __cpu_to_le32(0), 241 }, 242 243 /* CE2: target->host WMI */ 244 { 245 .pipenum = __cpu_to_le32(2), 246 .pipedir = __cpu_to_le32(PIPEDIR_IN), 247 .nentries = __cpu_to_le32(64), 248 .nbytes_max = __cpu_to_le32(2048), 249 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 250 .reserved = __cpu_to_le32(0), 251 }, 252 253 /* CE3: host->target WMI */ 254 { 255 .pipenum = __cpu_to_le32(3), 256 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 257 .nentries = __cpu_to_le32(32), 258 .nbytes_max = __cpu_to_le32(2048), 259 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 260 .reserved = __cpu_to_le32(0), 261 }, 262 263 /* CE4: host->target HTT */ 264 { 265 .pipenum = __cpu_to_le32(4), 266 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 267 .nentries = __cpu_to_le32(256), 268 .nbytes_max = __cpu_to_le32(256), 269 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 270 .reserved = __cpu_to_le32(0), 271 }, 272 273 /* NB: 50% of src nentries, since tx has 2 frags */ 274 275 /* CE5: target->host HTT (HIF->HTT) */ 276 { 277 .pipenum = __cpu_to_le32(5), 278 .pipedir = __cpu_to_le32(PIPEDIR_IN), 279 .nentries = __cpu_to_le32(32), 280 .nbytes_max = __cpu_to_le32(512), 281 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 282 .reserved = __cpu_to_le32(0), 283 }, 284 285 /* CE6: Reserved for target autonomous hif_memcpy */ 286 { 287 .pipenum = __cpu_to_le32(6), 288 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 289 .nentries = __cpu_to_le32(32), 290 .nbytes_max = __cpu_to_le32(4096), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE7 used only by Host */ 296 { 297 .pipenum = __cpu_to_le32(7), 298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 299 .nentries = __cpu_to_le32(0), 300 .nbytes_max = __cpu_to_le32(0), 301 .flags = __cpu_to_le32(0), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE8 target->host packtlog */ 306 { 307 .pipenum = __cpu_to_le32(8), 308 .pipedir = __cpu_to_le32(PIPEDIR_IN), 309 .nentries = __cpu_to_le32(64), 310 .nbytes_max = __cpu_to_le32(2048), 311 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE9 target autonomous qcache memcpy */ 316 { 317 .pipenum = __cpu_to_le32(9), 318 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 319 .nentries = __cpu_to_le32(32), 320 .nbytes_max = __cpu_to_le32(2048), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* It not necessary to send target wlan configuration for CE10 & CE11 326 * as these CEs are not actively used in target. 327 */ 328 }; 329 330 /* 331 * Map from service/endpoint to Copy Engine. 332 * This table is derived from the CE_PCI TABLE, above. 333 * It is passed to the Target at startup for use by firmware. 334 */ 335 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 336 { 337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 338 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 339 __cpu_to_le32(3), 340 }, 341 { 342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 343 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 344 __cpu_to_le32(2), 345 }, 346 { 347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 349 __cpu_to_le32(3), 350 }, 351 { 352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 354 __cpu_to_le32(2), 355 }, 356 { 357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 359 __cpu_to_le32(3), 360 }, 361 { 362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 364 __cpu_to_le32(2), 365 }, 366 { 367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 369 __cpu_to_le32(3), 370 }, 371 { 372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 374 __cpu_to_le32(2), 375 }, 376 { 377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 379 __cpu_to_le32(3), 380 }, 381 { 382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 384 __cpu_to_le32(2), 385 }, 386 { 387 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 389 __cpu_to_le32(0), 390 }, 391 { 392 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 394 __cpu_to_le32(1), 395 }, 396 { /* not used */ 397 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 399 __cpu_to_le32(0), 400 }, 401 { /* not used */ 402 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 404 __cpu_to_le32(1), 405 }, 406 { 407 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 409 __cpu_to_le32(4), 410 }, 411 { 412 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 414 __cpu_to_le32(5), 415 }, 416 417 /* (Additions here) */ 418 419 { /* must be last */ 420 __cpu_to_le32(0), 421 __cpu_to_le32(0), 422 __cpu_to_le32(0), 423 }, 424 }; 425 426 static bool ath10k_pci_is_awake(struct ath10k *ar) 427 { 428 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 429 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 430 RTC_STATE_ADDRESS); 431 432 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 433 } 434 435 static void __ath10k_pci_wake(struct ath10k *ar) 436 { 437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 438 439 lockdep_assert_held(&ar_pci->ps_lock); 440 441 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 442 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 443 444 iowrite32(PCIE_SOC_WAKE_V_MASK, 445 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 446 PCIE_SOC_WAKE_ADDRESS); 447 } 448 449 static void __ath10k_pci_sleep(struct ath10k *ar) 450 { 451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 452 453 lockdep_assert_held(&ar_pci->ps_lock); 454 455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 456 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 457 458 iowrite32(PCIE_SOC_WAKE_RESET, 459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 460 PCIE_SOC_WAKE_ADDRESS); 461 ar_pci->ps_awake = false; 462 } 463 464 static int ath10k_pci_wake_wait(struct ath10k *ar) 465 { 466 int tot_delay = 0; 467 int curr_delay = 5; 468 469 while (tot_delay < PCIE_WAKE_TIMEOUT) { 470 if (ath10k_pci_is_awake(ar)) { 471 if (tot_delay > PCIE_WAKE_LATE_US) 472 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 473 tot_delay / 1000); 474 return 0; 475 } 476 477 udelay(curr_delay); 478 tot_delay += curr_delay; 479 480 if (curr_delay < 50) 481 curr_delay += 5; 482 } 483 484 return -ETIMEDOUT; 485 } 486 487 static int ath10k_pci_force_wake(struct ath10k *ar) 488 { 489 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 490 unsigned long flags; 491 int ret = 0; 492 493 if (ar_pci->pci_ps) 494 return ret; 495 496 spin_lock_irqsave(&ar_pci->ps_lock, flags); 497 498 if (!ar_pci->ps_awake) { 499 iowrite32(PCIE_SOC_WAKE_V_MASK, 500 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 501 PCIE_SOC_WAKE_ADDRESS); 502 503 ret = ath10k_pci_wake_wait(ar); 504 if (ret == 0) 505 ar_pci->ps_awake = true; 506 } 507 508 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 509 510 return ret; 511 } 512 513 static void ath10k_pci_force_sleep(struct ath10k *ar) 514 { 515 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 516 unsigned long flags; 517 518 spin_lock_irqsave(&ar_pci->ps_lock, flags); 519 520 iowrite32(PCIE_SOC_WAKE_RESET, 521 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 522 PCIE_SOC_WAKE_ADDRESS); 523 ar_pci->ps_awake = false; 524 525 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 526 } 527 528 static int ath10k_pci_wake(struct ath10k *ar) 529 { 530 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 531 unsigned long flags; 532 int ret = 0; 533 534 if (ar_pci->pci_ps == 0) 535 return ret; 536 537 spin_lock_irqsave(&ar_pci->ps_lock, flags); 538 539 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 540 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 541 542 /* This function can be called very frequently. To avoid excessive 543 * CPU stalls for MMIO reads use a cache var to hold the device state. 544 */ 545 if (!ar_pci->ps_awake) { 546 __ath10k_pci_wake(ar); 547 548 ret = ath10k_pci_wake_wait(ar); 549 if (ret == 0) 550 ar_pci->ps_awake = true; 551 } 552 553 if (ret == 0) { 554 ar_pci->ps_wake_refcount++; 555 WARN_ON(ar_pci->ps_wake_refcount == 0); 556 } 557 558 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 559 560 return ret; 561 } 562 563 static void ath10k_pci_sleep(struct ath10k *ar) 564 { 565 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 566 unsigned long flags; 567 568 if (ar_pci->pci_ps == 0) 569 return; 570 571 spin_lock_irqsave(&ar_pci->ps_lock, flags); 572 573 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 574 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 575 576 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 577 goto skip; 578 579 ar_pci->ps_wake_refcount--; 580 581 mod_timer(&ar_pci->ps_timer, jiffies + 582 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 583 584 skip: 585 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 586 } 587 588 static void ath10k_pci_ps_timer(struct timer_list *t) 589 { 590 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer); 591 struct ath10k *ar = ar_pci->ar; 592 unsigned long flags; 593 594 spin_lock_irqsave(&ar_pci->ps_lock, flags); 595 596 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 597 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 598 599 if (ar_pci->ps_wake_refcount > 0) 600 goto skip; 601 602 __ath10k_pci_sleep(ar); 603 604 skip: 605 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 606 } 607 608 static void ath10k_pci_sleep_sync(struct ath10k *ar) 609 { 610 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 611 unsigned long flags; 612 613 if (ar_pci->pci_ps == 0) { 614 ath10k_pci_force_sleep(ar); 615 return; 616 } 617 618 del_timer_sync(&ar_pci->ps_timer); 619 620 spin_lock_irqsave(&ar_pci->ps_lock, flags); 621 WARN_ON(ar_pci->ps_wake_refcount > 0); 622 __ath10k_pci_sleep(ar); 623 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 624 } 625 626 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 627 { 628 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 629 int ret; 630 631 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 632 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 633 offset, offset + sizeof(value), ar_pci->mem_len); 634 return; 635 } 636 637 ret = ath10k_pci_wake(ar); 638 if (ret) { 639 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 640 value, offset, ret); 641 return; 642 } 643 644 iowrite32(value, ar_pci->mem + offset); 645 ath10k_pci_sleep(ar); 646 } 647 648 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 649 { 650 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 651 u32 val; 652 int ret; 653 654 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 655 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 656 offset, offset + sizeof(val), ar_pci->mem_len); 657 return 0; 658 } 659 660 ret = ath10k_pci_wake(ar); 661 if (ret) { 662 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 663 offset, ret); 664 return 0xffffffff; 665 } 666 667 val = ioread32(ar_pci->mem + offset); 668 ath10k_pci_sleep(ar); 669 670 return val; 671 } 672 673 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 674 { 675 struct ath10k_ce *ce = ath10k_ce_priv(ar); 676 677 ce->bus_ops->write32(ar, offset, value); 678 } 679 680 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 681 { 682 struct ath10k_ce *ce = ath10k_ce_priv(ar); 683 684 return ce->bus_ops->read32(ar, offset); 685 } 686 687 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 688 { 689 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 690 } 691 692 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 693 { 694 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 695 } 696 697 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 698 { 699 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 700 } 701 702 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 703 { 704 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 705 } 706 707 bool ath10k_pci_irq_pending(struct ath10k *ar) 708 { 709 u32 cause; 710 711 /* Check if the shared legacy irq is for us */ 712 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 713 PCIE_INTR_CAUSE_ADDRESS); 714 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 715 return true; 716 717 return false; 718 } 719 720 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 721 { 722 /* IMPORTANT: INTR_CLR register has to be set after 723 * INTR_ENABLE is set to 0, otherwise interrupt can not be 724 * really cleared. 725 */ 726 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 727 0); 728 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 729 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 730 731 /* IMPORTANT: this extra read transaction is required to 732 * flush the posted write buffer. 733 */ 734 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 735 PCIE_INTR_ENABLE_ADDRESS); 736 } 737 738 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 739 { 740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 741 PCIE_INTR_ENABLE_ADDRESS, 742 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 743 744 /* IMPORTANT: this extra read transaction is required to 745 * flush the posted write buffer. 746 */ 747 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 748 PCIE_INTR_ENABLE_ADDRESS); 749 } 750 751 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 752 { 753 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 754 755 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 756 return "msi"; 757 758 return "legacy"; 759 } 760 761 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 762 { 763 struct ath10k *ar = pipe->hif_ce_state; 764 struct ath10k_ce *ce = ath10k_ce_priv(ar); 765 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 766 struct sk_buff *skb; 767 dma_addr_t paddr; 768 int ret; 769 770 skb = dev_alloc_skb(pipe->buf_sz); 771 if (!skb) 772 return -ENOMEM; 773 774 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 775 776 paddr = dma_map_single(ar->dev, skb->data, 777 skb->len + skb_tailroom(skb), 778 DMA_FROM_DEVICE); 779 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 780 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 781 dev_kfree_skb_any(skb); 782 return -EIO; 783 } 784 785 ATH10K_SKB_RXCB(skb)->paddr = paddr; 786 787 spin_lock_bh(&ce->ce_lock); 788 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); 789 spin_unlock_bh(&ce->ce_lock); 790 if (ret) { 791 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 792 DMA_FROM_DEVICE); 793 dev_kfree_skb_any(skb); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 801 { 802 struct ath10k *ar = pipe->hif_ce_state; 803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 804 struct ath10k_ce *ce = ath10k_ce_priv(ar); 805 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 806 int ret, num; 807 808 if (pipe->buf_sz == 0) 809 return; 810 811 if (!ce_pipe->dest_ring) 812 return; 813 814 spin_lock_bh(&ce->ce_lock); 815 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 816 spin_unlock_bh(&ce->ce_lock); 817 818 while (num >= 0) { 819 ret = __ath10k_pci_rx_post_buf(pipe); 820 if (ret) { 821 if (ret == -ENOSPC) 822 break; 823 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 824 mod_timer(&ar_pci->rx_post_retry, jiffies + 825 ATH10K_PCI_RX_POST_RETRY_MS); 826 break; 827 } 828 num--; 829 } 830 } 831 832 void ath10k_pci_rx_post(struct ath10k *ar) 833 { 834 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 835 int i; 836 837 for (i = 0; i < CE_COUNT; i++) 838 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 839 } 840 841 void ath10k_pci_rx_replenish_retry(struct timer_list *t) 842 { 843 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry); 844 struct ath10k *ar = ar_pci->ar; 845 846 ath10k_pci_rx_post(ar); 847 } 848 849 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 850 { 851 u32 val = 0, region = addr & 0xfffff; 852 853 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 854 & 0x7ff) << 21; 855 val |= 0x100000 | region; 856 return val; 857 } 858 859 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 860 { 861 u32 val = 0, region = addr & 0xfffff; 862 863 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 864 val |= 0x100000 | region; 865 return val; 866 } 867 868 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 869 { 870 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 871 872 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 873 return -ENOTSUPP; 874 875 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 876 } 877 878 /* 879 * Diagnostic read/write access is provided for startup/config/debug usage. 880 * Caller must guarantee proper alignment, when applicable, and single user 881 * at any moment. 882 */ 883 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 884 int nbytes) 885 { 886 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 887 struct ath10k_ce *ce = ath10k_ce_priv(ar); 888 int ret = 0; 889 u32 *buf; 890 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 891 struct ath10k_ce_pipe *ce_diag; 892 /* Host buffer address in CE space */ 893 u32 ce_data; 894 dma_addr_t ce_data_base = 0; 895 void *data_buf = NULL; 896 int i; 897 898 spin_lock_bh(&ce->ce_lock); 899 900 ce_diag = ar_pci->ce_diag; 901 902 /* 903 * Allocate a temporary bounce buffer to hold caller's data 904 * to be DMA'ed from Target. This guarantees 905 * 1) 4-byte alignment 906 * 2) Buffer in DMA-able space 907 */ 908 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 909 910 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev, 911 alloc_nbytes, 912 &ce_data_base, 913 GFP_ATOMIC); 914 915 if (!data_buf) { 916 ret = -ENOMEM; 917 goto done; 918 } 919 920 remaining_bytes = nbytes; 921 ce_data = ce_data_base; 922 while (remaining_bytes) { 923 nbytes = min_t(unsigned int, remaining_bytes, 924 DIAG_TRANSFER_LIMIT); 925 926 ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 927 if (ret != 0) 928 goto done; 929 930 /* Request CE to send from Target(!) address to Host buffer */ 931 /* 932 * The address supplied by the caller is in the 933 * Target CPU virtual address space. 934 * 935 * In order to use this address with the diagnostic CE, 936 * convert it from Target CPU virtual address space 937 * to CE address space 938 */ 939 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 940 941 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, 942 0); 943 if (ret) 944 goto done; 945 946 i = 0; 947 while (ath10k_ce_completed_send_next_nolock(ce_diag, 948 NULL) != 0) { 949 mdelay(1); 950 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 951 ret = -EBUSY; 952 goto done; 953 } 954 } 955 956 i = 0; 957 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 958 (void **)&buf, 959 &completed_nbytes) 960 != 0) { 961 mdelay(1); 962 963 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 964 ret = -EBUSY; 965 goto done; 966 } 967 } 968 969 if (nbytes != completed_nbytes) { 970 ret = -EIO; 971 goto done; 972 } 973 974 if (*buf != ce_data) { 975 ret = -EIO; 976 goto done; 977 } 978 979 remaining_bytes -= nbytes; 980 memcpy(data, data_buf, nbytes); 981 982 address += nbytes; 983 data += nbytes; 984 } 985 986 done: 987 988 if (data_buf) 989 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 990 ce_data_base); 991 992 spin_unlock_bh(&ce->ce_lock); 993 994 return ret; 995 } 996 997 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 998 { 999 __le32 val = 0; 1000 int ret; 1001 1002 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1003 *value = __le32_to_cpu(val); 1004 1005 return ret; 1006 } 1007 1008 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1009 u32 src, u32 len) 1010 { 1011 u32 host_addr, addr; 1012 int ret; 1013 1014 host_addr = host_interest_item_address(src); 1015 1016 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1017 if (ret != 0) { 1018 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1019 src, ret); 1020 return ret; 1021 } 1022 1023 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1024 if (ret != 0) { 1025 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1026 addr, len, ret); 1027 return ret; 1028 } 1029 1030 return 0; 1031 } 1032 1033 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1034 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1035 1036 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1037 const void *data, int nbytes) 1038 { 1039 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1040 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1041 int ret = 0; 1042 u32 *buf; 1043 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 1044 struct ath10k_ce_pipe *ce_diag; 1045 void *data_buf = NULL; 1046 u32 ce_data; /* Host buffer address in CE space */ 1047 dma_addr_t ce_data_base = 0; 1048 int i; 1049 1050 spin_lock_bh(&ce->ce_lock); 1051 1052 ce_diag = ar_pci->ce_diag; 1053 1054 /* 1055 * Allocate a temporary bounce buffer to hold caller's data 1056 * to be DMA'ed to Target. This guarantees 1057 * 1) 4-byte alignment 1058 * 2) Buffer in DMA-able space 1059 */ 1060 orig_nbytes = nbytes; 1061 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 1062 orig_nbytes, 1063 &ce_data_base, 1064 GFP_ATOMIC); 1065 if (!data_buf) { 1066 ret = -ENOMEM; 1067 goto done; 1068 } 1069 1070 /* Copy caller's data to allocated DMA buf */ 1071 memcpy(data_buf, data, orig_nbytes); 1072 1073 /* 1074 * The address supplied by the caller is in the 1075 * Target CPU virtual address space. 1076 * 1077 * In order to use this address with the diagnostic CE, 1078 * convert it from 1079 * Target CPU virtual address space 1080 * to 1081 * CE address space 1082 */ 1083 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1084 1085 remaining_bytes = orig_nbytes; 1086 ce_data = ce_data_base; 1087 while (remaining_bytes) { 1088 /* FIXME: check cast */ 1089 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1090 1091 /* Set up to receive directly into Target(!) address */ 1092 ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address); 1093 if (ret != 0) 1094 goto done; 1095 1096 /* 1097 * Request CE to send caller-supplied data that 1098 * was copied to bounce buffer to Target(!) address. 1099 */ 1100 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, 1101 nbytes, 0, 0); 1102 if (ret != 0) 1103 goto done; 1104 1105 i = 0; 1106 while (ath10k_ce_completed_send_next_nolock(ce_diag, 1107 NULL) != 0) { 1108 mdelay(1); 1109 1110 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1111 ret = -EBUSY; 1112 goto done; 1113 } 1114 } 1115 1116 i = 0; 1117 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 1118 (void **)&buf, 1119 &completed_nbytes) 1120 != 0) { 1121 mdelay(1); 1122 1123 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1124 ret = -EBUSY; 1125 goto done; 1126 } 1127 } 1128 1129 if (nbytes != completed_nbytes) { 1130 ret = -EIO; 1131 goto done; 1132 } 1133 1134 if (*buf != address) { 1135 ret = -EIO; 1136 goto done; 1137 } 1138 1139 remaining_bytes -= nbytes; 1140 address += nbytes; 1141 ce_data += nbytes; 1142 } 1143 1144 done: 1145 if (data_buf) { 1146 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 1147 ce_data_base); 1148 } 1149 1150 if (ret != 0) 1151 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1152 address, ret); 1153 1154 spin_unlock_bh(&ce->ce_lock); 1155 1156 return ret; 1157 } 1158 1159 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1160 { 1161 __le32 val = __cpu_to_le32(value); 1162 1163 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1164 } 1165 1166 /* Called by lower (CE) layer when a send to Target completes. */ 1167 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1168 { 1169 struct ath10k *ar = ce_state->ar; 1170 struct sk_buff_head list; 1171 struct sk_buff *skb; 1172 1173 __skb_queue_head_init(&list); 1174 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1175 /* no need to call tx completion for NULL pointers */ 1176 if (skb == NULL) 1177 continue; 1178 1179 __skb_queue_tail(&list, skb); 1180 } 1181 1182 while ((skb = __skb_dequeue(&list))) 1183 ath10k_htc_tx_completion_handler(ar, skb); 1184 } 1185 1186 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1187 void (*callback)(struct ath10k *ar, 1188 struct sk_buff *skb)) 1189 { 1190 struct ath10k *ar = ce_state->ar; 1191 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1192 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1193 struct sk_buff *skb; 1194 struct sk_buff_head list; 1195 void *transfer_context; 1196 unsigned int nbytes, max_nbytes; 1197 1198 __skb_queue_head_init(&list); 1199 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1200 &nbytes) == 0) { 1201 skb = transfer_context; 1202 max_nbytes = skb->len + skb_tailroom(skb); 1203 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1204 max_nbytes, DMA_FROM_DEVICE); 1205 1206 if (unlikely(max_nbytes < nbytes)) { 1207 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1208 nbytes, max_nbytes); 1209 dev_kfree_skb_any(skb); 1210 continue; 1211 } 1212 1213 skb_put(skb, nbytes); 1214 __skb_queue_tail(&list, skb); 1215 } 1216 1217 while ((skb = __skb_dequeue(&list))) { 1218 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1219 ce_state->id, skb->len); 1220 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1221 skb->data, skb->len); 1222 1223 callback(ar, skb); 1224 } 1225 1226 ath10k_pci_rx_post_pipe(pipe_info); 1227 } 1228 1229 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1230 void (*callback)(struct ath10k *ar, 1231 struct sk_buff *skb)) 1232 { 1233 struct ath10k *ar = ce_state->ar; 1234 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1235 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1236 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1237 struct sk_buff *skb; 1238 struct sk_buff_head list; 1239 void *transfer_context; 1240 unsigned int nbytes, max_nbytes, nentries; 1241 int orig_len; 1242 1243 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1244 * is processed other than init and deinit. Before releasing CE5 1245 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1246 */ 1247 __skb_queue_head_init(&list); 1248 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1249 &nbytes) == 0) { 1250 skb = transfer_context; 1251 max_nbytes = skb->len + skb_tailroom(skb); 1252 1253 if (unlikely(max_nbytes < nbytes)) { 1254 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1255 nbytes, max_nbytes); 1256 continue; 1257 } 1258 1259 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1260 max_nbytes, DMA_FROM_DEVICE); 1261 skb_put(skb, nbytes); 1262 __skb_queue_tail(&list, skb); 1263 } 1264 1265 nentries = skb_queue_len(&list); 1266 while ((skb = __skb_dequeue(&list))) { 1267 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1268 ce_state->id, skb->len); 1269 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1270 skb->data, skb->len); 1271 1272 orig_len = skb->len; 1273 callback(ar, skb); 1274 skb_push(skb, orig_len - skb->len); 1275 skb_reset_tail_pointer(skb); 1276 skb_trim(skb, 0); 1277 1278 /*let device gain the buffer again*/ 1279 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1280 skb->len + skb_tailroom(skb), 1281 DMA_FROM_DEVICE); 1282 } 1283 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1284 } 1285 1286 /* Called by lower (CE) layer when data is received from the Target. */ 1287 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1288 { 1289 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1290 } 1291 1292 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1293 { 1294 /* CE4 polling needs to be done whenever CE pipe which transports 1295 * HTT Rx (target->host) is processed. 1296 */ 1297 ath10k_ce_per_engine_service(ce_state->ar, 4); 1298 1299 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1300 } 1301 1302 /* Called by lower (CE) layer when data is received from the Target. 1303 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1304 */ 1305 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1306 { 1307 ath10k_pci_process_rx_cb(ce_state, 1308 ath10k_htt_rx_pktlog_completion_handler); 1309 } 1310 1311 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1312 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1313 { 1314 struct ath10k *ar = ce_state->ar; 1315 struct sk_buff *skb; 1316 1317 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1318 /* no need to call tx completion for NULL pointers */ 1319 if (!skb) 1320 continue; 1321 1322 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1323 skb->len, DMA_TO_DEVICE); 1324 ath10k_htt_hif_tx_complete(ar, skb); 1325 } 1326 } 1327 1328 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1329 { 1330 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1331 ath10k_htt_t2h_msg_handler(ar, skb); 1332 } 1333 1334 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1335 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1336 { 1337 /* CE4 polling needs to be done whenever CE pipe which transports 1338 * HTT Rx (target->host) is processed. 1339 */ 1340 ath10k_ce_per_engine_service(ce_state->ar, 4); 1341 1342 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1343 } 1344 1345 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1346 struct ath10k_hif_sg_item *items, int n_items) 1347 { 1348 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1349 struct ath10k_ce *ce = ath10k_ce_priv(ar); 1350 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1351 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1352 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1353 unsigned int nentries_mask; 1354 unsigned int sw_index; 1355 unsigned int write_index; 1356 int err, i = 0; 1357 1358 spin_lock_bh(&ce->ce_lock); 1359 1360 nentries_mask = src_ring->nentries_mask; 1361 sw_index = src_ring->sw_index; 1362 write_index = src_ring->write_index; 1363 1364 if (unlikely(CE_RING_DELTA(nentries_mask, 1365 write_index, sw_index - 1) < n_items)) { 1366 err = -ENOBUFS; 1367 goto err; 1368 } 1369 1370 for (i = 0; i < n_items - 1; i++) { 1371 ath10k_dbg(ar, ATH10K_DBG_PCI, 1372 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1373 i, items[i].paddr, items[i].len, n_items); 1374 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1375 items[i].vaddr, items[i].len); 1376 1377 err = ath10k_ce_send_nolock(ce_pipe, 1378 items[i].transfer_context, 1379 items[i].paddr, 1380 items[i].len, 1381 items[i].transfer_id, 1382 CE_SEND_FLAG_GATHER); 1383 if (err) 1384 goto err; 1385 } 1386 1387 /* `i` is equal to `n_items -1` after for() */ 1388 1389 ath10k_dbg(ar, ATH10K_DBG_PCI, 1390 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1391 i, items[i].paddr, items[i].len, n_items); 1392 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1393 items[i].vaddr, items[i].len); 1394 1395 err = ath10k_ce_send_nolock(ce_pipe, 1396 items[i].transfer_context, 1397 items[i].paddr, 1398 items[i].len, 1399 items[i].transfer_id, 1400 0); 1401 if (err) 1402 goto err; 1403 1404 spin_unlock_bh(&ce->ce_lock); 1405 return 0; 1406 1407 err: 1408 for (; i > 0; i--) 1409 __ath10k_ce_send_revert(ce_pipe); 1410 1411 spin_unlock_bh(&ce->ce_lock); 1412 return err; 1413 } 1414 1415 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1416 size_t buf_len) 1417 { 1418 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1419 } 1420 1421 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1422 { 1423 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1424 1425 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1426 1427 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1428 } 1429 1430 static void ath10k_pci_dump_registers(struct ath10k *ar, 1431 struct ath10k_fw_crash_data *crash_data) 1432 { 1433 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1434 int i, ret; 1435 1436 lockdep_assert_held(&ar->data_lock); 1437 1438 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1439 hi_failure_state, 1440 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1441 if (ret) { 1442 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1443 return; 1444 } 1445 1446 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1447 1448 ath10k_err(ar, "firmware register dump:\n"); 1449 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1450 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1451 i, 1452 __le32_to_cpu(reg_dump_values[i]), 1453 __le32_to_cpu(reg_dump_values[i + 1]), 1454 __le32_to_cpu(reg_dump_values[i + 2]), 1455 __le32_to_cpu(reg_dump_values[i + 3])); 1456 1457 if (!crash_data) 1458 return; 1459 1460 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1461 crash_data->registers[i] = reg_dump_values[i]; 1462 } 1463 1464 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1465 { 1466 struct ath10k_fw_crash_data *crash_data; 1467 char guid[UUID_STRING_LEN + 1]; 1468 1469 spin_lock_bh(&ar->data_lock); 1470 1471 ar->stats.fw_crash_counter++; 1472 1473 crash_data = ath10k_debug_get_new_fw_crash_data(ar); 1474 1475 if (crash_data) 1476 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid); 1477 else 1478 scnprintf(guid, sizeof(guid), "n/a"); 1479 1480 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid); 1481 ath10k_print_driver_info(ar); 1482 ath10k_pci_dump_registers(ar, crash_data); 1483 ath10k_ce_dump_registers(ar, crash_data); 1484 1485 spin_unlock_bh(&ar->data_lock); 1486 1487 queue_work(ar->workqueue, &ar->restart_work); 1488 } 1489 1490 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1491 int force) 1492 { 1493 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1494 1495 if (!force) { 1496 int resources; 1497 /* 1498 * Decide whether to actually poll for completions, or just 1499 * wait for a later chance. 1500 * If there seem to be plenty of resources left, then just wait 1501 * since checking involves reading a CE register, which is a 1502 * relatively expensive operation. 1503 */ 1504 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1505 1506 /* 1507 * If at least 50% of the total resources are still available, 1508 * don't bother checking again yet. 1509 */ 1510 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1511 return; 1512 } 1513 ath10k_ce_per_engine_service(ar, pipe); 1514 } 1515 1516 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1517 { 1518 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1519 1520 del_timer_sync(&ar_pci->rx_post_retry); 1521 } 1522 1523 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1524 u8 *ul_pipe, u8 *dl_pipe) 1525 { 1526 const struct service_to_pipe *entry; 1527 bool ul_set = false, dl_set = false; 1528 int i; 1529 1530 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1531 1532 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1533 entry = &target_service_to_ce_map_wlan[i]; 1534 1535 if (__le32_to_cpu(entry->service_id) != service_id) 1536 continue; 1537 1538 switch (__le32_to_cpu(entry->pipedir)) { 1539 case PIPEDIR_NONE: 1540 break; 1541 case PIPEDIR_IN: 1542 WARN_ON(dl_set); 1543 *dl_pipe = __le32_to_cpu(entry->pipenum); 1544 dl_set = true; 1545 break; 1546 case PIPEDIR_OUT: 1547 WARN_ON(ul_set); 1548 *ul_pipe = __le32_to_cpu(entry->pipenum); 1549 ul_set = true; 1550 break; 1551 case PIPEDIR_INOUT: 1552 WARN_ON(dl_set); 1553 WARN_ON(ul_set); 1554 *dl_pipe = __le32_to_cpu(entry->pipenum); 1555 *ul_pipe = __le32_to_cpu(entry->pipenum); 1556 dl_set = true; 1557 ul_set = true; 1558 break; 1559 } 1560 } 1561 1562 if (WARN_ON(!ul_set || !dl_set)) 1563 return -ENOENT; 1564 1565 return 0; 1566 } 1567 1568 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1569 u8 *ul_pipe, u8 *dl_pipe) 1570 { 1571 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1572 1573 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1574 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1575 ul_pipe, dl_pipe); 1576 } 1577 1578 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1579 { 1580 u32 val; 1581 1582 switch (ar->hw_rev) { 1583 case ATH10K_HW_QCA988X: 1584 case ATH10K_HW_QCA9887: 1585 case ATH10K_HW_QCA6174: 1586 case ATH10K_HW_QCA9377: 1587 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1588 CORE_CTRL_ADDRESS); 1589 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1590 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1591 CORE_CTRL_ADDRESS, val); 1592 break; 1593 case ATH10K_HW_QCA99X0: 1594 case ATH10K_HW_QCA9984: 1595 case ATH10K_HW_QCA9888: 1596 case ATH10K_HW_QCA4019: 1597 /* TODO: Find appropriate register configuration for QCA99X0 1598 * to mask irq/MSI. 1599 */ 1600 break; 1601 case ATH10K_HW_WCN3990: 1602 break; 1603 } 1604 } 1605 1606 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1607 { 1608 u32 val; 1609 1610 switch (ar->hw_rev) { 1611 case ATH10K_HW_QCA988X: 1612 case ATH10K_HW_QCA9887: 1613 case ATH10K_HW_QCA6174: 1614 case ATH10K_HW_QCA9377: 1615 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1616 CORE_CTRL_ADDRESS); 1617 val |= CORE_CTRL_PCIE_REG_31_MASK; 1618 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1619 CORE_CTRL_ADDRESS, val); 1620 break; 1621 case ATH10K_HW_QCA99X0: 1622 case ATH10K_HW_QCA9984: 1623 case ATH10K_HW_QCA9888: 1624 case ATH10K_HW_QCA4019: 1625 /* TODO: Find appropriate register configuration for QCA99X0 1626 * to unmask irq/MSI. 1627 */ 1628 break; 1629 case ATH10K_HW_WCN3990: 1630 break; 1631 } 1632 } 1633 1634 static void ath10k_pci_irq_disable(struct ath10k *ar) 1635 { 1636 ath10k_ce_disable_interrupts(ar); 1637 ath10k_pci_disable_and_clear_legacy_irq(ar); 1638 ath10k_pci_irq_msi_fw_mask(ar); 1639 } 1640 1641 static void ath10k_pci_irq_sync(struct ath10k *ar) 1642 { 1643 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1644 1645 synchronize_irq(ar_pci->pdev->irq); 1646 } 1647 1648 static void ath10k_pci_irq_enable(struct ath10k *ar) 1649 { 1650 ath10k_ce_enable_interrupts(ar); 1651 ath10k_pci_enable_legacy_irq(ar); 1652 ath10k_pci_irq_msi_fw_unmask(ar); 1653 } 1654 1655 static int ath10k_pci_hif_start(struct ath10k *ar) 1656 { 1657 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1658 1659 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1660 1661 napi_enable(&ar->napi); 1662 1663 ath10k_pci_irq_enable(ar); 1664 ath10k_pci_rx_post(ar); 1665 1666 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1667 ar_pci->link_ctl); 1668 1669 return 0; 1670 } 1671 1672 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1673 { 1674 struct ath10k *ar; 1675 struct ath10k_ce_pipe *ce_pipe; 1676 struct ath10k_ce_ring *ce_ring; 1677 struct sk_buff *skb; 1678 int i; 1679 1680 ar = pci_pipe->hif_ce_state; 1681 ce_pipe = pci_pipe->ce_hdl; 1682 ce_ring = ce_pipe->dest_ring; 1683 1684 if (!ce_ring) 1685 return; 1686 1687 if (!pci_pipe->buf_sz) 1688 return; 1689 1690 for (i = 0; i < ce_ring->nentries; i++) { 1691 skb = ce_ring->per_transfer_context[i]; 1692 if (!skb) 1693 continue; 1694 1695 ce_ring->per_transfer_context[i] = NULL; 1696 1697 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1698 skb->len + skb_tailroom(skb), 1699 DMA_FROM_DEVICE); 1700 dev_kfree_skb_any(skb); 1701 } 1702 } 1703 1704 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1705 { 1706 struct ath10k *ar; 1707 struct ath10k_ce_pipe *ce_pipe; 1708 struct ath10k_ce_ring *ce_ring; 1709 struct sk_buff *skb; 1710 int i; 1711 1712 ar = pci_pipe->hif_ce_state; 1713 ce_pipe = pci_pipe->ce_hdl; 1714 ce_ring = ce_pipe->src_ring; 1715 1716 if (!ce_ring) 1717 return; 1718 1719 if (!pci_pipe->buf_sz) 1720 return; 1721 1722 for (i = 0; i < ce_ring->nentries; i++) { 1723 skb = ce_ring->per_transfer_context[i]; 1724 if (!skb) 1725 continue; 1726 1727 ce_ring->per_transfer_context[i] = NULL; 1728 1729 ath10k_htc_tx_completion_handler(ar, skb); 1730 } 1731 } 1732 1733 /* 1734 * Cleanup residual buffers for device shutdown: 1735 * buffers that were enqueued for receive 1736 * buffers that were to be sent 1737 * Note: Buffers that had completed but which were 1738 * not yet processed are on a completion queue. They 1739 * are handled when the completion thread shuts down. 1740 */ 1741 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 1742 { 1743 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1744 int pipe_num; 1745 1746 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 1747 struct ath10k_pci_pipe *pipe_info; 1748 1749 pipe_info = &ar_pci->pipe_info[pipe_num]; 1750 ath10k_pci_rx_pipe_cleanup(pipe_info); 1751 ath10k_pci_tx_pipe_cleanup(pipe_info); 1752 } 1753 } 1754 1755 void ath10k_pci_ce_deinit(struct ath10k *ar) 1756 { 1757 int i; 1758 1759 for (i = 0; i < CE_COUNT; i++) 1760 ath10k_ce_deinit_pipe(ar, i); 1761 } 1762 1763 void ath10k_pci_flush(struct ath10k *ar) 1764 { 1765 ath10k_pci_rx_retry_sync(ar); 1766 ath10k_pci_buffer_cleanup(ar); 1767 } 1768 1769 static void ath10k_pci_hif_stop(struct ath10k *ar) 1770 { 1771 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1772 unsigned long flags; 1773 1774 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 1775 1776 /* Most likely the device has HTT Rx ring configured. The only way to 1777 * prevent the device from accessing (and possible corrupting) host 1778 * memory is to reset the chip now. 1779 * 1780 * There's also no known way of masking MSI interrupts on the device. 1781 * For ranged MSI the CE-related interrupts can be masked. However 1782 * regardless how many MSI interrupts are assigned the first one 1783 * is always used for firmware indications (crashes) and cannot be 1784 * masked. To prevent the device from asserting the interrupt reset it 1785 * before proceeding with cleanup. 1786 */ 1787 ath10k_pci_safe_chip_reset(ar); 1788 1789 ath10k_pci_irq_disable(ar); 1790 ath10k_pci_irq_sync(ar); 1791 ath10k_pci_flush(ar); 1792 napi_synchronize(&ar->napi); 1793 napi_disable(&ar->napi); 1794 1795 spin_lock_irqsave(&ar_pci->ps_lock, flags); 1796 WARN_ON(ar_pci->ps_wake_refcount > 0); 1797 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 1798 } 1799 1800 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 1801 void *req, u32 req_len, 1802 void *resp, u32 *resp_len) 1803 { 1804 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1805 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 1806 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 1807 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 1808 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 1809 dma_addr_t req_paddr = 0; 1810 dma_addr_t resp_paddr = 0; 1811 struct bmi_xfer xfer = {}; 1812 void *treq, *tresp = NULL; 1813 int ret = 0; 1814 1815 might_sleep(); 1816 1817 if (resp && !resp_len) 1818 return -EINVAL; 1819 1820 if (resp && resp_len && *resp_len == 0) 1821 return -EINVAL; 1822 1823 treq = kmemdup(req, req_len, GFP_KERNEL); 1824 if (!treq) 1825 return -ENOMEM; 1826 1827 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 1828 ret = dma_mapping_error(ar->dev, req_paddr); 1829 if (ret) { 1830 ret = -EIO; 1831 goto err_dma; 1832 } 1833 1834 if (resp && resp_len) { 1835 tresp = kzalloc(*resp_len, GFP_KERNEL); 1836 if (!tresp) { 1837 ret = -ENOMEM; 1838 goto err_req; 1839 } 1840 1841 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 1842 DMA_FROM_DEVICE); 1843 ret = dma_mapping_error(ar->dev, resp_paddr); 1844 if (ret) { 1845 ret = -EIO; 1846 goto err_req; 1847 } 1848 1849 xfer.wait_for_resp = true; 1850 xfer.resp_len = 0; 1851 1852 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 1853 } 1854 1855 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 1856 if (ret) 1857 goto err_resp; 1858 1859 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 1860 if (ret) { 1861 u32 unused_buffer; 1862 unsigned int unused_nbytes; 1863 unsigned int unused_id; 1864 1865 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 1866 &unused_nbytes, &unused_id); 1867 } else { 1868 /* non-zero means we did not time out */ 1869 ret = 0; 1870 } 1871 1872 err_resp: 1873 if (resp) { 1874 u32 unused_buffer; 1875 1876 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 1877 dma_unmap_single(ar->dev, resp_paddr, 1878 *resp_len, DMA_FROM_DEVICE); 1879 } 1880 err_req: 1881 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 1882 1883 if (ret == 0 && resp_len) { 1884 *resp_len = min(*resp_len, xfer.resp_len); 1885 memcpy(resp, tresp, xfer.resp_len); 1886 } 1887 err_dma: 1888 kfree(treq); 1889 kfree(tresp); 1890 1891 return ret; 1892 } 1893 1894 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 1895 { 1896 struct bmi_xfer *xfer; 1897 1898 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 1899 return; 1900 1901 xfer->tx_done = true; 1902 } 1903 1904 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 1905 { 1906 struct ath10k *ar = ce_state->ar; 1907 struct bmi_xfer *xfer; 1908 unsigned int nbytes; 1909 1910 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 1911 &nbytes)) 1912 return; 1913 1914 if (WARN_ON_ONCE(!xfer)) 1915 return; 1916 1917 if (!xfer->wait_for_resp) { 1918 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 1919 return; 1920 } 1921 1922 xfer->resp_len = nbytes; 1923 xfer->rx_done = true; 1924 } 1925 1926 static int ath10k_pci_bmi_wait(struct ath10k *ar, 1927 struct ath10k_ce_pipe *tx_pipe, 1928 struct ath10k_ce_pipe *rx_pipe, 1929 struct bmi_xfer *xfer) 1930 { 1931 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1932 unsigned long started = jiffies; 1933 unsigned long dur; 1934 int ret; 1935 1936 while (time_before_eq(jiffies, timeout)) { 1937 ath10k_pci_bmi_send_done(tx_pipe); 1938 ath10k_pci_bmi_recv_data(rx_pipe); 1939 1940 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 1941 ret = 0; 1942 goto out; 1943 } 1944 1945 schedule(); 1946 } 1947 1948 ret = -ETIMEDOUT; 1949 1950 out: 1951 dur = jiffies - started; 1952 if (dur > HZ) 1953 ath10k_dbg(ar, ATH10K_DBG_BMI, 1954 "bmi cmd took %lu jiffies hz %d ret %d\n", 1955 dur, HZ, ret); 1956 return ret; 1957 } 1958 1959 /* 1960 * Send an interrupt to the device to wake up the Target CPU 1961 * so it has an opportunity to notice any changed state. 1962 */ 1963 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 1964 { 1965 u32 addr, val; 1966 1967 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 1968 val = ath10k_pci_read32(ar, addr); 1969 val |= CORE_CTRL_CPU_INTR_MASK; 1970 ath10k_pci_write32(ar, addr, val); 1971 1972 return 0; 1973 } 1974 1975 static int ath10k_pci_get_num_banks(struct ath10k *ar) 1976 { 1977 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1978 1979 switch (ar_pci->pdev->device) { 1980 case QCA988X_2_0_DEVICE_ID: 1981 case QCA99X0_2_0_DEVICE_ID: 1982 case QCA9888_2_0_DEVICE_ID: 1983 case QCA9984_1_0_DEVICE_ID: 1984 case QCA9887_1_0_DEVICE_ID: 1985 return 1; 1986 case QCA6164_2_1_DEVICE_ID: 1987 case QCA6174_2_1_DEVICE_ID: 1988 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { 1989 case QCA6174_HW_1_0_CHIP_ID_REV: 1990 case QCA6174_HW_1_1_CHIP_ID_REV: 1991 case QCA6174_HW_2_1_CHIP_ID_REV: 1992 case QCA6174_HW_2_2_CHIP_ID_REV: 1993 return 3; 1994 case QCA6174_HW_1_3_CHIP_ID_REV: 1995 return 2; 1996 case QCA6174_HW_3_0_CHIP_ID_REV: 1997 case QCA6174_HW_3_1_CHIP_ID_REV: 1998 case QCA6174_HW_3_2_CHIP_ID_REV: 1999 return 9; 2000 } 2001 break; 2002 case QCA9377_1_0_DEVICE_ID: 2003 return 4; 2004 } 2005 2006 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 2007 return 1; 2008 } 2009 2010 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2011 { 2012 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2013 2014 return ce->bus_ops->get_num_banks(ar); 2015 } 2016 2017 int ath10k_pci_init_config(struct ath10k *ar) 2018 { 2019 u32 interconnect_targ_addr; 2020 u32 pcie_state_targ_addr = 0; 2021 u32 pipe_cfg_targ_addr = 0; 2022 u32 svc_to_pipe_map = 0; 2023 u32 pcie_config_flags = 0; 2024 u32 ealloc_value; 2025 u32 ealloc_targ_addr; 2026 u32 flag2_value; 2027 u32 flag2_targ_addr; 2028 int ret = 0; 2029 2030 /* Download to Target the CE Config and the service-to-CE map */ 2031 interconnect_targ_addr = 2032 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2033 2034 /* Supply Target-side CE configuration */ 2035 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2036 &pcie_state_targ_addr); 2037 if (ret != 0) { 2038 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2039 return ret; 2040 } 2041 2042 if (pcie_state_targ_addr == 0) { 2043 ret = -EIO; 2044 ath10k_err(ar, "Invalid pcie state addr\n"); 2045 return ret; 2046 } 2047 2048 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2049 offsetof(struct pcie_state, 2050 pipe_cfg_addr)), 2051 &pipe_cfg_targ_addr); 2052 if (ret != 0) { 2053 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2054 return ret; 2055 } 2056 2057 if (pipe_cfg_targ_addr == 0) { 2058 ret = -EIO; 2059 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2060 return ret; 2061 } 2062 2063 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2064 target_ce_config_wlan, 2065 sizeof(struct ce_pipe_config) * 2066 NUM_TARGET_CE_CONFIG_WLAN); 2067 2068 if (ret != 0) { 2069 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2070 return ret; 2071 } 2072 2073 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2074 offsetof(struct pcie_state, 2075 svc_to_pipe_map)), 2076 &svc_to_pipe_map); 2077 if (ret != 0) { 2078 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2079 return ret; 2080 } 2081 2082 if (svc_to_pipe_map == 0) { 2083 ret = -EIO; 2084 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2085 return ret; 2086 } 2087 2088 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2089 target_service_to_ce_map_wlan, 2090 sizeof(target_service_to_ce_map_wlan)); 2091 if (ret != 0) { 2092 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2093 return ret; 2094 } 2095 2096 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2097 offsetof(struct pcie_state, 2098 config_flags)), 2099 &pcie_config_flags); 2100 if (ret != 0) { 2101 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2102 return ret; 2103 } 2104 2105 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2106 2107 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2108 offsetof(struct pcie_state, 2109 config_flags)), 2110 pcie_config_flags); 2111 if (ret != 0) { 2112 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2113 return ret; 2114 } 2115 2116 /* configure early allocation */ 2117 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2118 2119 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2120 if (ret != 0) { 2121 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2122 return ret; 2123 } 2124 2125 /* first bank is switched to IRAM */ 2126 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2127 HI_EARLY_ALLOC_MAGIC_MASK); 2128 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2129 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2130 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2131 2132 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2133 if (ret != 0) { 2134 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2135 return ret; 2136 } 2137 2138 /* Tell Target to proceed with initialization */ 2139 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2140 2141 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2142 if (ret != 0) { 2143 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2144 return ret; 2145 } 2146 2147 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2148 2149 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2150 if (ret != 0) { 2151 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2152 return ret; 2153 } 2154 2155 return 0; 2156 } 2157 2158 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2159 { 2160 struct ce_attr *attr; 2161 struct ce_pipe_config *config; 2162 2163 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2164 * since it is currently used for other feature. 2165 */ 2166 2167 /* Override Host's Copy Engine 5 configuration */ 2168 attr = &host_ce_config_wlan[5]; 2169 attr->src_sz_max = 0; 2170 attr->dest_nentries = 0; 2171 2172 /* Override Target firmware's Copy Engine configuration */ 2173 config = &target_ce_config_wlan[5]; 2174 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2175 config->nbytes_max = __cpu_to_le32(2048); 2176 2177 /* Map from service/endpoint to Copy Engine */ 2178 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1); 2179 } 2180 2181 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2182 { 2183 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2184 struct ath10k_pci_pipe *pipe; 2185 struct ath10k_ce *ce = ath10k_ce_priv(ar); 2186 int i, ret; 2187 2188 for (i = 0; i < CE_COUNT; i++) { 2189 pipe = &ar_pci->pipe_info[i]; 2190 pipe->ce_hdl = &ce->ce_states[i]; 2191 pipe->pipe_num = i; 2192 pipe->hif_ce_state = ar; 2193 2194 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 2195 if (ret) { 2196 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2197 i, ret); 2198 return ret; 2199 } 2200 2201 /* Last CE is Diagnostic Window */ 2202 if (i == CE_DIAG_PIPE) { 2203 ar_pci->ce_diag = pipe->ce_hdl; 2204 continue; 2205 } 2206 2207 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 2208 } 2209 2210 return 0; 2211 } 2212 2213 void ath10k_pci_free_pipes(struct ath10k *ar) 2214 { 2215 int i; 2216 2217 for (i = 0; i < CE_COUNT; i++) 2218 ath10k_ce_free_pipe(ar, i); 2219 } 2220 2221 int ath10k_pci_init_pipes(struct ath10k *ar) 2222 { 2223 int i, ret; 2224 2225 for (i = 0; i < CE_COUNT; i++) { 2226 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 2227 if (ret) { 2228 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2229 i, ret); 2230 return ret; 2231 } 2232 } 2233 2234 return 0; 2235 } 2236 2237 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2238 { 2239 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2240 FW_IND_EVENT_PENDING; 2241 } 2242 2243 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2244 { 2245 u32 val; 2246 2247 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2248 val &= ~FW_IND_EVENT_PENDING; 2249 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2250 } 2251 2252 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2253 { 2254 u32 val; 2255 2256 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2257 return (val == 0xffffffff); 2258 } 2259 2260 /* this function effectively clears target memory controller assert line */ 2261 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2262 { 2263 u32 val; 2264 2265 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2266 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2267 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2268 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2269 2270 msleep(10); 2271 2272 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2273 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2274 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2275 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2276 2277 msleep(10); 2278 } 2279 2280 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2281 { 2282 u32 val; 2283 2284 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2285 2286 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2287 SOC_RESET_CONTROL_ADDRESS); 2288 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2289 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2290 } 2291 2292 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2293 { 2294 u32 val; 2295 2296 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2297 SOC_RESET_CONTROL_ADDRESS); 2298 2299 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2300 val | SOC_RESET_CONTROL_CE_RST_MASK); 2301 msleep(10); 2302 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2303 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2304 } 2305 2306 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2307 { 2308 u32 val; 2309 2310 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2311 SOC_LF_TIMER_CONTROL0_ADDRESS); 2312 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 2313 SOC_LF_TIMER_CONTROL0_ADDRESS, 2314 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2315 } 2316 2317 static int ath10k_pci_warm_reset(struct ath10k *ar) 2318 { 2319 int ret; 2320 2321 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2322 2323 spin_lock_bh(&ar->data_lock); 2324 ar->stats.fw_warm_reset_counter++; 2325 spin_unlock_bh(&ar->data_lock); 2326 2327 ath10k_pci_irq_disable(ar); 2328 2329 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2330 * were to access copy engine while host performs copy engine reset 2331 * then it is possible for the device to confuse pci-e controller to 2332 * the point of bringing host system to a complete stop (i.e. hang). 2333 */ 2334 ath10k_pci_warm_reset_si0(ar); 2335 ath10k_pci_warm_reset_cpu(ar); 2336 ath10k_pci_init_pipes(ar); 2337 ath10k_pci_wait_for_target_init(ar); 2338 2339 ath10k_pci_warm_reset_clear_lf(ar); 2340 ath10k_pci_warm_reset_ce(ar); 2341 ath10k_pci_warm_reset_cpu(ar); 2342 ath10k_pci_init_pipes(ar); 2343 2344 ret = ath10k_pci_wait_for_target_init(ar); 2345 if (ret) { 2346 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2347 return ret; 2348 } 2349 2350 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2351 2352 return 0; 2353 } 2354 2355 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2356 { 2357 ath10k_pci_irq_disable(ar); 2358 return ath10k_pci_qca99x0_chip_reset(ar); 2359 } 2360 2361 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2362 { 2363 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2364 2365 if (!ar_pci->pci_soft_reset) 2366 return -ENOTSUPP; 2367 2368 return ar_pci->pci_soft_reset(ar); 2369 } 2370 2371 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2372 { 2373 int i, ret; 2374 u32 val; 2375 2376 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2377 2378 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2379 * It is thus preferred to use warm reset which is safer but may not be 2380 * able to recover the device from all possible fail scenarios. 2381 * 2382 * Warm reset doesn't always work on first try so attempt it a few 2383 * times before giving up. 2384 */ 2385 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2386 ret = ath10k_pci_warm_reset(ar); 2387 if (ret) { 2388 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2389 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2390 ret); 2391 continue; 2392 } 2393 2394 /* FIXME: Sometimes copy engine doesn't recover after warm 2395 * reset. In most cases this needs cold reset. In some of these 2396 * cases the device is in such a state that a cold reset may 2397 * lock up the host. 2398 * 2399 * Reading any host interest register via copy engine is 2400 * sufficient to verify if device is capable of booting 2401 * firmware blob. 2402 */ 2403 ret = ath10k_pci_init_pipes(ar); 2404 if (ret) { 2405 ath10k_warn(ar, "failed to init copy engine: %d\n", 2406 ret); 2407 continue; 2408 } 2409 2410 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2411 &val); 2412 if (ret) { 2413 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2414 ret); 2415 continue; 2416 } 2417 2418 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2419 return 0; 2420 } 2421 2422 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2423 ath10k_warn(ar, "refusing cold reset as requested\n"); 2424 return -EPERM; 2425 } 2426 2427 ret = ath10k_pci_cold_reset(ar); 2428 if (ret) { 2429 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2430 return ret; 2431 } 2432 2433 ret = ath10k_pci_wait_for_target_init(ar); 2434 if (ret) { 2435 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2436 ret); 2437 return ret; 2438 } 2439 2440 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2441 2442 return 0; 2443 } 2444 2445 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2446 { 2447 int ret; 2448 2449 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2450 2451 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2452 2453 ret = ath10k_pci_cold_reset(ar); 2454 if (ret) { 2455 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2456 return ret; 2457 } 2458 2459 ret = ath10k_pci_wait_for_target_init(ar); 2460 if (ret) { 2461 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2462 ret); 2463 return ret; 2464 } 2465 2466 ret = ath10k_pci_warm_reset(ar); 2467 if (ret) { 2468 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2469 return ret; 2470 } 2471 2472 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2473 2474 return 0; 2475 } 2476 2477 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2478 { 2479 int ret; 2480 2481 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2482 2483 ret = ath10k_pci_cold_reset(ar); 2484 if (ret) { 2485 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2486 return ret; 2487 } 2488 2489 ret = ath10k_pci_wait_for_target_init(ar); 2490 if (ret) { 2491 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2492 ret); 2493 return ret; 2494 } 2495 2496 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2497 2498 return 0; 2499 } 2500 2501 static int ath10k_pci_chip_reset(struct ath10k *ar) 2502 { 2503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2504 2505 if (WARN_ON(!ar_pci->pci_hard_reset)) 2506 return -ENOTSUPP; 2507 2508 return ar_pci->pci_hard_reset(ar); 2509 } 2510 2511 static int ath10k_pci_hif_power_up(struct ath10k *ar) 2512 { 2513 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2514 int ret; 2515 2516 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2517 2518 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2519 &ar_pci->link_ctl); 2520 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2521 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2522 2523 /* 2524 * Bring the target up cleanly. 2525 * 2526 * The target may be in an undefined state with an AUX-powered Target 2527 * and a Host in WoW mode. If the Host crashes, loses power, or is 2528 * restarted (without unloading the driver) then the Target is left 2529 * (aux) powered and running. On a subsequent driver load, the Target 2530 * is in an unexpected state. We try to catch that here in order to 2531 * reset the Target and retry the probe. 2532 */ 2533 ret = ath10k_pci_chip_reset(ar); 2534 if (ret) { 2535 if (ath10k_pci_has_fw_crashed(ar)) { 2536 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2537 ath10k_pci_fw_crashed_clear(ar); 2538 ath10k_pci_fw_crashed_dump(ar); 2539 } 2540 2541 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2542 goto err_sleep; 2543 } 2544 2545 ret = ath10k_pci_init_pipes(ar); 2546 if (ret) { 2547 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2548 goto err_sleep; 2549 } 2550 2551 ret = ath10k_pci_init_config(ar); 2552 if (ret) { 2553 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2554 goto err_ce; 2555 } 2556 2557 ret = ath10k_pci_wake_target_cpu(ar); 2558 if (ret) { 2559 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2560 goto err_ce; 2561 } 2562 2563 return 0; 2564 2565 err_ce: 2566 ath10k_pci_ce_deinit(ar); 2567 2568 err_sleep: 2569 return ret; 2570 } 2571 2572 void ath10k_pci_hif_power_down(struct ath10k *ar) 2573 { 2574 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2575 2576 /* Currently hif_power_up performs effectively a reset and hif_stop 2577 * resets the chip as well so there's no point in resetting here. 2578 */ 2579 } 2580 2581 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2582 { 2583 /* Nothing to do; the important stuff is in the driver suspend. */ 2584 return 0; 2585 } 2586 2587 static int ath10k_pci_suspend(struct ath10k *ar) 2588 { 2589 /* The grace timer can still be counting down and ar->ps_awake be true. 2590 * It is known that the device may be asleep after resuming regardless 2591 * of the SoC powersave state before suspending. Hence make sure the 2592 * device is asleep before proceeding. 2593 */ 2594 ath10k_pci_sleep_sync(ar); 2595 2596 return 0; 2597 } 2598 2599 static int ath10k_pci_hif_resume(struct ath10k *ar) 2600 { 2601 /* Nothing to do; the important stuff is in the driver resume. */ 2602 return 0; 2603 } 2604 2605 static int ath10k_pci_resume(struct ath10k *ar) 2606 { 2607 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2608 struct pci_dev *pdev = ar_pci->pdev; 2609 u32 val; 2610 int ret = 0; 2611 2612 ret = ath10k_pci_force_wake(ar); 2613 if (ret) { 2614 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2615 return ret; 2616 } 2617 2618 /* Suspend/Resume resets the PCI configuration space, so we have to 2619 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2620 * from interfering with C3 CPU state. pci_restore_state won't help 2621 * here since it only restores the first 64 bytes pci config header. 2622 */ 2623 pci_read_config_dword(pdev, 0x40, &val); 2624 if ((val & 0x0000ff00) != 0) 2625 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2626 2627 return ret; 2628 } 2629 2630 static bool ath10k_pci_validate_cal(void *data, size_t size) 2631 { 2632 __le16 *cal_words = data; 2633 u16 checksum = 0; 2634 size_t i; 2635 2636 if (size % 2 != 0) 2637 return false; 2638 2639 for (i = 0; i < size / 2; i++) 2640 checksum ^= le16_to_cpu(cal_words[i]); 2641 2642 return checksum == 0xffff; 2643 } 2644 2645 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2646 { 2647 /* Enable SI clock */ 2648 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2649 2650 /* Configure GPIOs for I2C operation */ 2651 ath10k_pci_write32(ar, 2652 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2653 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2654 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2655 GPIO_PIN0_CONFIG) | 2656 SM(1, GPIO_PIN0_PAD_PULL)); 2657 2658 ath10k_pci_write32(ar, 2659 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2660 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2661 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2662 SM(1, GPIO_PIN0_PAD_PULL)); 2663 2664 ath10k_pci_write32(ar, 2665 GPIO_BASE_ADDRESS + 2666 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2667 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2668 2669 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2670 ath10k_pci_write32(ar, 2671 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2672 SM(1, SI_CONFIG_ERR_INT) | 2673 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2674 SM(1, SI_CONFIG_I2C) | 2675 SM(1, SI_CONFIG_POS_SAMPLE) | 2676 SM(1, SI_CONFIG_INACTIVE_DATA) | 2677 SM(1, SI_CONFIG_INACTIVE_CLK) | 2678 SM(8, SI_CONFIG_DIVIDER)); 2679 } 2680 2681 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2682 { 2683 u32 reg; 2684 int wait_limit; 2685 2686 /* set device select byte and for the read operation */ 2687 reg = QCA9887_EEPROM_SELECT_READ | 2688 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2689 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2690 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2691 2692 /* write transmit data, transfer length, and START bit */ 2693 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 2694 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 2695 SM(4, SI_CS_TX_CNT)); 2696 2697 /* wait max 1 sec */ 2698 wait_limit = 100000; 2699 2700 /* wait for SI_CS_DONE_INT */ 2701 do { 2702 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 2703 if (MS(reg, SI_CS_DONE_INT)) 2704 break; 2705 2706 wait_limit--; 2707 udelay(10); 2708 } while (wait_limit > 0); 2709 2710 if (!MS(reg, SI_CS_DONE_INT)) { 2711 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 2712 addr); 2713 return -ETIMEDOUT; 2714 } 2715 2716 /* clear SI_CS_DONE_INT */ 2717 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 2718 2719 if (MS(reg, SI_CS_DONE_ERR)) { 2720 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 2721 return -EIO; 2722 } 2723 2724 /* extract receive data */ 2725 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 2726 *out = reg; 2727 2728 return 0; 2729 } 2730 2731 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 2732 size_t *data_len) 2733 { 2734 u8 *caldata = NULL; 2735 size_t calsize, i; 2736 int ret; 2737 2738 if (!QCA_REV_9887(ar)) 2739 return -EOPNOTSUPP; 2740 2741 calsize = ar->hw_params.cal_data_len; 2742 caldata = kmalloc(calsize, GFP_KERNEL); 2743 if (!caldata) 2744 return -ENOMEM; 2745 2746 ath10k_pci_enable_eeprom(ar); 2747 2748 for (i = 0; i < calsize; i++) { 2749 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 2750 if (ret) 2751 goto err_free; 2752 } 2753 2754 if (!ath10k_pci_validate_cal(caldata, calsize)) 2755 goto err_free; 2756 2757 *data = caldata; 2758 *data_len = calsize; 2759 2760 return 0; 2761 2762 err_free: 2763 kfree(caldata); 2764 2765 return -EINVAL; 2766 } 2767 2768 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 2769 .tx_sg = ath10k_pci_hif_tx_sg, 2770 .diag_read = ath10k_pci_hif_diag_read, 2771 .diag_write = ath10k_pci_diag_write_mem, 2772 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 2773 .start = ath10k_pci_hif_start, 2774 .stop = ath10k_pci_hif_stop, 2775 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 2776 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 2777 .send_complete_check = ath10k_pci_hif_send_complete_check, 2778 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 2779 .power_up = ath10k_pci_hif_power_up, 2780 .power_down = ath10k_pci_hif_power_down, 2781 .read32 = ath10k_pci_read32, 2782 .write32 = ath10k_pci_write32, 2783 .suspend = ath10k_pci_hif_suspend, 2784 .resume = ath10k_pci_hif_resume, 2785 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 2786 }; 2787 2788 /* 2789 * Top-level interrupt handler for all PCI interrupts from a Target. 2790 * When a block of MSI interrupts is allocated, this top-level handler 2791 * is not used; instead, we directly call the correct sub-handler. 2792 */ 2793 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 2794 { 2795 struct ath10k *ar = arg; 2796 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2797 int ret; 2798 2799 if (ath10k_pci_has_device_gone(ar)) 2800 return IRQ_NONE; 2801 2802 ret = ath10k_pci_force_wake(ar); 2803 if (ret) { 2804 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 2805 return IRQ_NONE; 2806 } 2807 2808 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 2809 !ath10k_pci_irq_pending(ar)) 2810 return IRQ_NONE; 2811 2812 ath10k_pci_disable_and_clear_legacy_irq(ar); 2813 ath10k_pci_irq_msi_fw_mask(ar); 2814 napi_schedule(&ar->napi); 2815 2816 return IRQ_HANDLED; 2817 } 2818 2819 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 2820 { 2821 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 2822 int done = 0; 2823 2824 if (ath10k_pci_has_fw_crashed(ar)) { 2825 ath10k_pci_fw_crashed_clear(ar); 2826 ath10k_pci_fw_crashed_dump(ar); 2827 napi_complete(ctx); 2828 return done; 2829 } 2830 2831 ath10k_ce_per_engine_service_any(ar); 2832 2833 done = ath10k_htt_txrx_compl_task(ar, budget); 2834 2835 if (done < budget) { 2836 napi_complete_done(ctx, done); 2837 /* In case of MSI, it is possible that interrupts are received 2838 * while NAPI poll is inprogress. So pending interrupts that are 2839 * received after processing all copy engine pipes by NAPI poll 2840 * will not be handled again. This is causing failure to 2841 * complete boot sequence in x86 platform. So before enabling 2842 * interrupts safer to check for pending interrupts for 2843 * immediate servicing. 2844 */ 2845 if (ath10k_ce_interrupt_summary(ar)) { 2846 napi_reschedule(ctx); 2847 goto out; 2848 } 2849 ath10k_pci_enable_legacy_irq(ar); 2850 ath10k_pci_irq_msi_fw_unmask(ar); 2851 } 2852 2853 out: 2854 return done; 2855 } 2856 2857 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 2858 { 2859 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2860 int ret; 2861 2862 ret = request_irq(ar_pci->pdev->irq, 2863 ath10k_pci_interrupt_handler, 2864 IRQF_SHARED, "ath10k_pci", ar); 2865 if (ret) { 2866 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 2867 ar_pci->pdev->irq, ret); 2868 return ret; 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 2875 { 2876 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2877 int ret; 2878 2879 ret = request_irq(ar_pci->pdev->irq, 2880 ath10k_pci_interrupt_handler, 2881 IRQF_SHARED, "ath10k_pci", ar); 2882 if (ret) { 2883 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 2884 ar_pci->pdev->irq, ret); 2885 return ret; 2886 } 2887 2888 return 0; 2889 } 2890 2891 static int ath10k_pci_request_irq(struct ath10k *ar) 2892 { 2893 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2894 2895 switch (ar_pci->oper_irq_mode) { 2896 case ATH10K_PCI_IRQ_LEGACY: 2897 return ath10k_pci_request_irq_legacy(ar); 2898 case ATH10K_PCI_IRQ_MSI: 2899 return ath10k_pci_request_irq_msi(ar); 2900 default: 2901 return -EINVAL; 2902 } 2903 } 2904 2905 static void ath10k_pci_free_irq(struct ath10k *ar) 2906 { 2907 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2908 2909 free_irq(ar_pci->pdev->irq, ar); 2910 } 2911 2912 void ath10k_pci_init_napi(struct ath10k *ar) 2913 { 2914 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll, 2915 ATH10K_NAPI_BUDGET); 2916 } 2917 2918 static int ath10k_pci_init_irq(struct ath10k *ar) 2919 { 2920 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2921 int ret; 2922 2923 ath10k_pci_init_napi(ar); 2924 2925 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 2926 ath10k_info(ar, "limiting irq mode to: %d\n", 2927 ath10k_pci_irq_mode); 2928 2929 /* Try MSI */ 2930 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 2931 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 2932 ret = pci_enable_msi(ar_pci->pdev); 2933 if (ret == 0) 2934 return 0; 2935 2936 /* fall-through */ 2937 } 2938 2939 /* Try legacy irq 2940 * 2941 * A potential race occurs here: The CORE_BASE write 2942 * depends on target correctly decoding AXI address but 2943 * host won't know when target writes BAR to CORE_CTRL. 2944 * This write might get lost if target has NOT written BAR. 2945 * For now, fix the race by repeating the write in below 2946 * synchronization checking. 2947 */ 2948 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 2949 2950 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2951 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 2952 2953 return 0; 2954 } 2955 2956 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 2957 { 2958 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2959 0); 2960 } 2961 2962 static int ath10k_pci_deinit_irq(struct ath10k *ar) 2963 { 2964 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2965 2966 switch (ar_pci->oper_irq_mode) { 2967 case ATH10K_PCI_IRQ_LEGACY: 2968 ath10k_pci_deinit_irq_legacy(ar); 2969 break; 2970 default: 2971 pci_disable_msi(ar_pci->pdev); 2972 break; 2973 } 2974 2975 return 0; 2976 } 2977 2978 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 2979 { 2980 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2981 unsigned long timeout; 2982 u32 val; 2983 2984 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 2985 2986 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 2987 2988 do { 2989 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2990 2991 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 2992 val); 2993 2994 /* target should never return this */ 2995 if (val == 0xffffffff) 2996 continue; 2997 2998 /* the device has crashed so don't bother trying anymore */ 2999 if (val & FW_IND_EVENT_PENDING) 3000 break; 3001 3002 if (val & FW_IND_INITIALIZED) 3003 break; 3004 3005 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 3006 /* Fix potential race by repeating CORE_BASE writes */ 3007 ath10k_pci_enable_legacy_irq(ar); 3008 3009 mdelay(10); 3010 } while (time_before(jiffies, timeout)); 3011 3012 ath10k_pci_disable_and_clear_legacy_irq(ar); 3013 ath10k_pci_irq_msi_fw_mask(ar); 3014 3015 if (val == 0xffffffff) { 3016 ath10k_err(ar, "failed to read device register, device is gone\n"); 3017 return -EIO; 3018 } 3019 3020 if (val & FW_IND_EVENT_PENDING) { 3021 ath10k_warn(ar, "device has crashed during init\n"); 3022 return -ECOMM; 3023 } 3024 3025 if (!(val & FW_IND_INITIALIZED)) { 3026 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3027 val); 3028 return -ETIMEDOUT; 3029 } 3030 3031 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3032 return 0; 3033 } 3034 3035 static int ath10k_pci_cold_reset(struct ath10k *ar) 3036 { 3037 u32 val; 3038 3039 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3040 3041 spin_lock_bh(&ar->data_lock); 3042 3043 ar->stats.fw_cold_reset_counter++; 3044 3045 spin_unlock_bh(&ar->data_lock); 3046 3047 /* Put Target, including PCIe, into RESET. */ 3048 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3049 val |= 1; 3050 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3051 3052 /* After writing into SOC_GLOBAL_RESET to put device into 3053 * reset and pulling out of reset pcie may not be stable 3054 * for any immediate pcie register access and cause bus error, 3055 * add delay before any pcie access request to fix this issue. 3056 */ 3057 msleep(20); 3058 3059 /* Pull Target, including PCIe, out of RESET. */ 3060 val &= ~1; 3061 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3062 3063 msleep(20); 3064 3065 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3066 3067 return 0; 3068 } 3069 3070 static int ath10k_pci_claim(struct ath10k *ar) 3071 { 3072 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3073 struct pci_dev *pdev = ar_pci->pdev; 3074 int ret; 3075 3076 pci_set_drvdata(pdev, ar); 3077 3078 ret = pci_enable_device(pdev); 3079 if (ret) { 3080 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3081 return ret; 3082 } 3083 3084 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3085 if (ret) { 3086 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3087 ret); 3088 goto err_device; 3089 } 3090 3091 /* Target expects 32 bit DMA. Enforce it. */ 3092 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3093 if (ret) { 3094 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3095 goto err_region; 3096 } 3097 3098 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3099 if (ret) { 3100 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 3101 ret); 3102 goto err_region; 3103 } 3104 3105 pci_set_master(pdev); 3106 3107 /* Arrange for access to Target SoC registers. */ 3108 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3109 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3110 if (!ar_pci->mem) { 3111 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3112 ret = -EIO; 3113 goto err_master; 3114 } 3115 3116 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3117 return 0; 3118 3119 err_master: 3120 pci_clear_master(pdev); 3121 3122 err_region: 3123 pci_release_region(pdev, BAR_NUM); 3124 3125 err_device: 3126 pci_disable_device(pdev); 3127 3128 return ret; 3129 } 3130 3131 static void ath10k_pci_release(struct ath10k *ar) 3132 { 3133 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3134 struct pci_dev *pdev = ar_pci->pdev; 3135 3136 pci_iounmap(pdev, ar_pci->mem); 3137 pci_release_region(pdev, BAR_NUM); 3138 pci_clear_master(pdev); 3139 pci_disable_device(pdev); 3140 } 3141 3142 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3143 { 3144 const struct ath10k_pci_supp_chip *supp_chip; 3145 int i; 3146 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3147 3148 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3149 supp_chip = &ath10k_pci_supp_chips[i]; 3150 3151 if (supp_chip->dev_id == dev_id && 3152 supp_chip->rev_id == rev_id) 3153 return true; 3154 } 3155 3156 return false; 3157 } 3158 3159 int ath10k_pci_setup_resource(struct ath10k *ar) 3160 { 3161 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3162 struct ath10k_ce *ce = ath10k_ce_priv(ar); 3163 int ret; 3164 3165 spin_lock_init(&ce->ce_lock); 3166 spin_lock_init(&ar_pci->ps_lock); 3167 3168 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0); 3169 3170 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3171 ath10k_pci_override_ce_config(ar); 3172 3173 ret = ath10k_pci_alloc_pipes(ar); 3174 if (ret) { 3175 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3176 ret); 3177 return ret; 3178 } 3179 3180 return 0; 3181 } 3182 3183 void ath10k_pci_release_resource(struct ath10k *ar) 3184 { 3185 ath10k_pci_rx_retry_sync(ar); 3186 netif_napi_del(&ar->napi); 3187 ath10k_pci_ce_deinit(ar); 3188 ath10k_pci_free_pipes(ar); 3189 } 3190 3191 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3192 .read32 = ath10k_bus_pci_read32, 3193 .write32 = ath10k_bus_pci_write32, 3194 .get_num_banks = ath10k_pci_get_num_banks, 3195 }; 3196 3197 static int ath10k_pci_probe(struct pci_dev *pdev, 3198 const struct pci_device_id *pci_dev) 3199 { 3200 int ret = 0; 3201 struct ath10k *ar; 3202 struct ath10k_pci *ar_pci; 3203 enum ath10k_hw_rev hw_rev; 3204 u32 chip_id; 3205 bool pci_ps; 3206 int (*pci_soft_reset)(struct ath10k *ar); 3207 int (*pci_hard_reset)(struct ath10k *ar); 3208 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3209 3210 switch (pci_dev->device) { 3211 case QCA988X_2_0_DEVICE_ID: 3212 hw_rev = ATH10K_HW_QCA988X; 3213 pci_ps = false; 3214 pci_soft_reset = ath10k_pci_warm_reset; 3215 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3216 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3217 break; 3218 case QCA9887_1_0_DEVICE_ID: 3219 hw_rev = ATH10K_HW_QCA9887; 3220 pci_ps = false; 3221 pci_soft_reset = ath10k_pci_warm_reset; 3222 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3223 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3224 break; 3225 case QCA6164_2_1_DEVICE_ID: 3226 case QCA6174_2_1_DEVICE_ID: 3227 hw_rev = ATH10K_HW_QCA6174; 3228 pci_ps = true; 3229 pci_soft_reset = ath10k_pci_warm_reset; 3230 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3231 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3232 break; 3233 case QCA99X0_2_0_DEVICE_ID: 3234 hw_rev = ATH10K_HW_QCA99X0; 3235 pci_ps = false; 3236 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3237 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3238 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3239 break; 3240 case QCA9984_1_0_DEVICE_ID: 3241 hw_rev = ATH10K_HW_QCA9984; 3242 pci_ps = false; 3243 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3244 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3245 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3246 break; 3247 case QCA9888_2_0_DEVICE_ID: 3248 hw_rev = ATH10K_HW_QCA9888; 3249 pci_ps = false; 3250 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3251 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3252 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3253 break; 3254 case QCA9377_1_0_DEVICE_ID: 3255 hw_rev = ATH10K_HW_QCA9377; 3256 pci_ps = true; 3257 pci_soft_reset = NULL; 3258 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3259 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3260 break; 3261 default: 3262 WARN_ON(1); 3263 return -ENOTSUPP; 3264 } 3265 3266 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3267 hw_rev, &ath10k_pci_hif_ops); 3268 if (!ar) { 3269 dev_err(&pdev->dev, "failed to allocate core\n"); 3270 return -ENOMEM; 3271 } 3272 3273 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3274 pdev->vendor, pdev->device, 3275 pdev->subsystem_vendor, pdev->subsystem_device); 3276 3277 ar_pci = ath10k_pci_priv(ar); 3278 ar_pci->pdev = pdev; 3279 ar_pci->dev = &pdev->dev; 3280 ar_pci->ar = ar; 3281 ar->dev_id = pci_dev->device; 3282 ar_pci->pci_ps = pci_ps; 3283 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops; 3284 ar_pci->pci_soft_reset = pci_soft_reset; 3285 ar_pci->pci_hard_reset = pci_hard_reset; 3286 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3287 ar->ce_priv = &ar_pci->ce; 3288 3289 ar->id.vendor = pdev->vendor; 3290 ar->id.device = pdev->device; 3291 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3292 ar->id.subsystem_device = pdev->subsystem_device; 3293 3294 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0); 3295 3296 ret = ath10k_pci_setup_resource(ar); 3297 if (ret) { 3298 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3299 goto err_core_destroy; 3300 } 3301 3302 ret = ath10k_pci_claim(ar); 3303 if (ret) { 3304 ath10k_err(ar, "failed to claim device: %d\n", ret); 3305 goto err_free_pipes; 3306 } 3307 3308 ret = ath10k_pci_force_wake(ar); 3309 if (ret) { 3310 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3311 goto err_sleep; 3312 } 3313 3314 ath10k_pci_ce_deinit(ar); 3315 ath10k_pci_irq_disable(ar); 3316 3317 ret = ath10k_pci_init_irq(ar); 3318 if (ret) { 3319 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3320 goto err_sleep; 3321 } 3322 3323 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3324 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3325 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3326 3327 ret = ath10k_pci_request_irq(ar); 3328 if (ret) { 3329 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3330 goto err_deinit_irq; 3331 } 3332 3333 ret = ath10k_pci_chip_reset(ar); 3334 if (ret) { 3335 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3336 goto err_free_irq; 3337 } 3338 3339 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3340 if (chip_id == 0xffffffff) { 3341 ath10k_err(ar, "failed to get chip id\n"); 3342 goto err_free_irq; 3343 } 3344 3345 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { 3346 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3347 pdev->device, chip_id); 3348 goto err_free_irq; 3349 } 3350 3351 ret = ath10k_core_register(ar, chip_id); 3352 if (ret) { 3353 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3354 goto err_free_irq; 3355 } 3356 3357 return 0; 3358 3359 err_free_irq: 3360 ath10k_pci_free_irq(ar); 3361 ath10k_pci_rx_retry_sync(ar); 3362 3363 err_deinit_irq: 3364 ath10k_pci_deinit_irq(ar); 3365 3366 err_sleep: 3367 ath10k_pci_sleep_sync(ar); 3368 ath10k_pci_release(ar); 3369 3370 err_free_pipes: 3371 ath10k_pci_free_pipes(ar); 3372 3373 err_core_destroy: 3374 ath10k_core_destroy(ar); 3375 3376 return ret; 3377 } 3378 3379 static void ath10k_pci_remove(struct pci_dev *pdev) 3380 { 3381 struct ath10k *ar = pci_get_drvdata(pdev); 3382 struct ath10k_pci *ar_pci; 3383 3384 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3385 3386 if (!ar) 3387 return; 3388 3389 ar_pci = ath10k_pci_priv(ar); 3390 3391 if (!ar_pci) 3392 return; 3393 3394 ath10k_core_unregister(ar); 3395 ath10k_pci_free_irq(ar); 3396 ath10k_pci_deinit_irq(ar); 3397 ath10k_pci_release_resource(ar); 3398 ath10k_pci_sleep_sync(ar); 3399 ath10k_pci_release(ar); 3400 ath10k_core_destroy(ar); 3401 } 3402 3403 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3404 3405 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev) 3406 { 3407 struct ath10k *ar = dev_get_drvdata(dev); 3408 int ret; 3409 3410 ret = ath10k_pci_suspend(ar); 3411 if (ret) 3412 ath10k_warn(ar, "failed to suspend hif: %d\n", ret); 3413 3414 return ret; 3415 } 3416 3417 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev) 3418 { 3419 struct ath10k *ar = dev_get_drvdata(dev); 3420 int ret; 3421 3422 ret = ath10k_pci_resume(ar); 3423 if (ret) 3424 ath10k_warn(ar, "failed to resume hif: %d\n", ret); 3425 3426 return ret; 3427 } 3428 3429 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops, 3430 ath10k_pci_pm_suspend, 3431 ath10k_pci_pm_resume); 3432 3433 static struct pci_driver ath10k_pci_driver = { 3434 .name = "ath10k_pci", 3435 .id_table = ath10k_pci_id_table, 3436 .probe = ath10k_pci_probe, 3437 .remove = ath10k_pci_remove, 3438 #ifdef CONFIG_PM 3439 .driver.pm = &ath10k_pci_pm_ops, 3440 #endif 3441 }; 3442 3443 static int __init ath10k_pci_init(void) 3444 { 3445 int ret; 3446 3447 ret = pci_register_driver(&ath10k_pci_driver); 3448 if (ret) 3449 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3450 ret); 3451 3452 ret = ath10k_ahb_init(); 3453 if (ret) 3454 printk(KERN_ERR "ahb init failed: %d\n", ret); 3455 3456 return ret; 3457 } 3458 module_init(ath10k_pci_init); 3459 3460 static void __exit ath10k_pci_exit(void) 3461 { 3462 pci_unregister_driver(&ath10k_pci_driver); 3463 ath10k_ahb_exit(); 3464 } 3465 3466 module_exit(ath10k_pci_exit); 3467 3468 MODULE_AUTHOR("Qualcomm Atheros"); 3469 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3470 MODULE_LICENSE("Dual BSD/GPL"); 3471 3472 /* QCA988x 2.0 firmware files */ 3473 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3474 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3475 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3476 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3477 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3478 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3479 3480 /* QCA9887 1.0 firmware files */ 3481 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3482 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3483 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3484 3485 /* QCA6174 2.1 firmware files */ 3486 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3487 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3488 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3489 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3490 3491 /* QCA6174 3.1 firmware files */ 3492 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3493 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3494 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3495 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3496 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3497 3498 /* QCA9377 1.0 firmware files */ 3499 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3500 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3501