1 /* 2 * Copyright (c) 2005-2011 Atheros Communications Inc. 3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/pci.h> 19 #include <linux/module.h> 20 #include <linux/interrupt.h> 21 #include <linux/spinlock.h> 22 #include <linux/bitops.h> 23 24 #include "core.h" 25 #include "debug.h" 26 27 #include "targaddrs.h" 28 #include "bmi.h" 29 30 #include "hif.h" 31 #include "htc.h" 32 33 #include "ce.h" 34 #include "pci.h" 35 36 enum ath10k_pci_reset_mode { 37 ATH10K_PCI_RESET_AUTO = 0, 38 ATH10K_PCI_RESET_WARM_ONLY = 1, 39 }; 40 41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; 42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; 43 44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); 45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); 46 47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); 48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); 49 50 /* how long wait to wait for target to initialise, in ms */ 51 #define ATH10K_PCI_TARGET_WAIT 3000 52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 53 54 static const struct pci_device_id ath10k_pci_id_table[] = { 55 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ 56 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */ 57 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */ 58 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */ 59 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */ 60 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */ 61 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */ 62 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */ 63 {0} 64 }; 65 66 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { 67 /* QCA988X pre 2.0 chips are not supported because they need some nasty 68 * hacks. ath10k doesn't have them and these devices crash horribly 69 * because of that. 70 */ 71 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, 72 73 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 74 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 75 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 76 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 77 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 78 79 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV }, 80 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV }, 81 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV }, 82 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV }, 83 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV }, 84 85 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV }, 86 87 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV }, 88 89 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV }, 90 91 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV }, 92 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV }, 93 94 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV }, 95 }; 96 97 static void ath10k_pci_buffer_cleanup(struct ath10k *ar); 98 static int ath10k_pci_cold_reset(struct ath10k *ar); 99 static int ath10k_pci_safe_chip_reset(struct ath10k *ar); 100 static int ath10k_pci_init_irq(struct ath10k *ar); 101 static int ath10k_pci_deinit_irq(struct ath10k *ar); 102 static int ath10k_pci_request_irq(struct ath10k *ar); 103 static void ath10k_pci_free_irq(struct ath10k *ar); 104 static int ath10k_pci_bmi_wait(struct ath10k *ar, 105 struct ath10k_ce_pipe *tx_pipe, 106 struct ath10k_ce_pipe *rx_pipe, 107 struct bmi_xfer *xfer); 108 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar); 109 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state); 110 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 111 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state); 112 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state); 113 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state); 114 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state); 115 116 static struct ce_attr host_ce_config_wlan[] = { 117 /* CE0: host->target HTC control and raw streams */ 118 { 119 .flags = CE_ATTR_FLAGS, 120 .src_nentries = 16, 121 .src_sz_max = 256, 122 .dest_nentries = 0, 123 .send_cb = ath10k_pci_htc_tx_cb, 124 }, 125 126 /* CE1: target->host HTT + HTC control */ 127 { 128 .flags = CE_ATTR_FLAGS, 129 .src_nentries = 0, 130 .src_sz_max = 2048, 131 .dest_nentries = 512, 132 .recv_cb = ath10k_pci_htt_htc_rx_cb, 133 }, 134 135 /* CE2: target->host WMI */ 136 { 137 .flags = CE_ATTR_FLAGS, 138 .src_nentries = 0, 139 .src_sz_max = 2048, 140 .dest_nentries = 128, 141 .recv_cb = ath10k_pci_htc_rx_cb, 142 }, 143 144 /* CE3: host->target WMI */ 145 { 146 .flags = CE_ATTR_FLAGS, 147 .src_nentries = 32, 148 .src_sz_max = 2048, 149 .dest_nentries = 0, 150 .send_cb = ath10k_pci_htc_tx_cb, 151 }, 152 153 /* CE4: host->target HTT */ 154 { 155 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, 156 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, 157 .src_sz_max = 256, 158 .dest_nentries = 0, 159 .send_cb = ath10k_pci_htt_tx_cb, 160 }, 161 162 /* CE5: target->host HTT (HIF->HTT) */ 163 { 164 .flags = CE_ATTR_FLAGS, 165 .src_nentries = 0, 166 .src_sz_max = 512, 167 .dest_nentries = 512, 168 .recv_cb = ath10k_pci_htt_rx_cb, 169 }, 170 171 /* CE6: target autonomous hif_memcpy */ 172 { 173 .flags = CE_ATTR_FLAGS, 174 .src_nentries = 0, 175 .src_sz_max = 0, 176 .dest_nentries = 0, 177 }, 178 179 /* CE7: ce_diag, the Diagnostic Window */ 180 { 181 .flags = CE_ATTR_FLAGS, 182 .src_nentries = 2, 183 .src_sz_max = DIAG_TRANSFER_LIMIT, 184 .dest_nentries = 2, 185 }, 186 187 /* CE8: target->host pktlog */ 188 { 189 .flags = CE_ATTR_FLAGS, 190 .src_nentries = 0, 191 .src_sz_max = 2048, 192 .dest_nentries = 128, 193 .recv_cb = ath10k_pci_pktlog_rx_cb, 194 }, 195 196 /* CE9 target autonomous qcache memcpy */ 197 { 198 .flags = CE_ATTR_FLAGS, 199 .src_nentries = 0, 200 .src_sz_max = 0, 201 .dest_nentries = 0, 202 }, 203 204 /* CE10: target autonomous hif memcpy */ 205 { 206 .flags = CE_ATTR_FLAGS, 207 .src_nentries = 0, 208 .src_sz_max = 0, 209 .dest_nentries = 0, 210 }, 211 212 /* CE11: target autonomous hif memcpy */ 213 { 214 .flags = CE_ATTR_FLAGS, 215 .src_nentries = 0, 216 .src_sz_max = 0, 217 .dest_nentries = 0, 218 }, 219 }; 220 221 /* Target firmware's Copy Engine configuration. */ 222 static struct ce_pipe_config target_ce_config_wlan[] = { 223 /* CE0: host->target HTC control and raw streams */ 224 { 225 .pipenum = __cpu_to_le32(0), 226 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 227 .nentries = __cpu_to_le32(32), 228 .nbytes_max = __cpu_to_le32(256), 229 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 230 .reserved = __cpu_to_le32(0), 231 }, 232 233 /* CE1: target->host HTT + HTC control */ 234 { 235 .pipenum = __cpu_to_le32(1), 236 .pipedir = __cpu_to_le32(PIPEDIR_IN), 237 .nentries = __cpu_to_le32(32), 238 .nbytes_max = __cpu_to_le32(2048), 239 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 240 .reserved = __cpu_to_le32(0), 241 }, 242 243 /* CE2: target->host WMI */ 244 { 245 .pipenum = __cpu_to_le32(2), 246 .pipedir = __cpu_to_le32(PIPEDIR_IN), 247 .nentries = __cpu_to_le32(64), 248 .nbytes_max = __cpu_to_le32(2048), 249 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 250 .reserved = __cpu_to_le32(0), 251 }, 252 253 /* CE3: host->target WMI */ 254 { 255 .pipenum = __cpu_to_le32(3), 256 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 257 .nentries = __cpu_to_le32(32), 258 .nbytes_max = __cpu_to_le32(2048), 259 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 260 .reserved = __cpu_to_le32(0), 261 }, 262 263 /* CE4: host->target HTT */ 264 { 265 .pipenum = __cpu_to_le32(4), 266 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 267 .nentries = __cpu_to_le32(256), 268 .nbytes_max = __cpu_to_le32(256), 269 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 270 .reserved = __cpu_to_le32(0), 271 }, 272 273 /* NB: 50% of src nentries, since tx has 2 frags */ 274 275 /* CE5: target->host HTT (HIF->HTT) */ 276 { 277 .pipenum = __cpu_to_le32(5), 278 .pipedir = __cpu_to_le32(PIPEDIR_IN), 279 .nentries = __cpu_to_le32(32), 280 .nbytes_max = __cpu_to_le32(512), 281 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 282 .reserved = __cpu_to_le32(0), 283 }, 284 285 /* CE6: Reserved for target autonomous hif_memcpy */ 286 { 287 .pipenum = __cpu_to_le32(6), 288 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 289 .nentries = __cpu_to_le32(32), 290 .nbytes_max = __cpu_to_le32(4096), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE7 used only by Host */ 296 { 297 .pipenum = __cpu_to_le32(7), 298 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 299 .nentries = __cpu_to_le32(0), 300 .nbytes_max = __cpu_to_le32(0), 301 .flags = __cpu_to_le32(0), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE8 target->host packtlog */ 306 { 307 .pipenum = __cpu_to_le32(8), 308 .pipedir = __cpu_to_le32(PIPEDIR_IN), 309 .nentries = __cpu_to_le32(64), 310 .nbytes_max = __cpu_to_le32(2048), 311 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE9 target autonomous qcache memcpy */ 316 { 317 .pipenum = __cpu_to_le32(9), 318 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 319 .nentries = __cpu_to_le32(32), 320 .nbytes_max = __cpu_to_le32(2048), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* It not necessary to send target wlan configuration for CE10 & CE11 326 * as these CEs are not actively used in target. 327 */ 328 }; 329 330 /* 331 * Map from service/endpoint to Copy Engine. 332 * This table is derived from the CE_PCI TABLE, above. 333 * It is passed to the Target at startup for use by firmware. 334 */ 335 static struct service_to_pipe target_service_to_ce_map_wlan[] = { 336 { 337 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 338 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 339 __cpu_to_le32(3), 340 }, 341 { 342 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), 343 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 344 __cpu_to_le32(2), 345 }, 346 { 347 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 348 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 349 __cpu_to_le32(3), 350 }, 351 { 352 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), 353 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 354 __cpu_to_le32(2), 355 }, 356 { 357 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 358 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 359 __cpu_to_le32(3), 360 }, 361 { 362 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), 363 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 364 __cpu_to_le32(2), 365 }, 366 { 367 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 368 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 369 __cpu_to_le32(3), 370 }, 371 { 372 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), 373 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 374 __cpu_to_le32(2), 375 }, 376 { 377 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 378 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 379 __cpu_to_le32(3), 380 }, 381 { 382 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), 383 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 384 __cpu_to_le32(2), 385 }, 386 { 387 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 388 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 389 __cpu_to_le32(0), 390 }, 391 { 392 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), 393 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 394 __cpu_to_le32(1), 395 }, 396 { /* not used */ 397 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 398 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 399 __cpu_to_le32(0), 400 }, 401 { /* not used */ 402 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), 403 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 404 __cpu_to_le32(1), 405 }, 406 { 407 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 409 __cpu_to_le32(4), 410 }, 411 { 412 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), 413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 414 __cpu_to_le32(5), 415 }, 416 417 /* (Additions here) */ 418 419 { /* must be last */ 420 __cpu_to_le32(0), 421 __cpu_to_le32(0), 422 __cpu_to_le32(0), 423 }, 424 }; 425 426 static bool ath10k_pci_is_awake(struct ath10k *ar) 427 { 428 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 429 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 430 RTC_STATE_ADDRESS); 431 432 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; 433 } 434 435 static void __ath10k_pci_wake(struct ath10k *ar) 436 { 437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 438 439 lockdep_assert_held(&ar_pci->ps_lock); 440 441 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n", 442 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 443 444 iowrite32(PCIE_SOC_WAKE_V_MASK, 445 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 446 PCIE_SOC_WAKE_ADDRESS); 447 } 448 449 static void __ath10k_pci_sleep(struct ath10k *ar) 450 { 451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 452 453 lockdep_assert_held(&ar_pci->ps_lock); 454 455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n", 456 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 457 458 iowrite32(PCIE_SOC_WAKE_RESET, 459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 460 PCIE_SOC_WAKE_ADDRESS); 461 ar_pci->ps_awake = false; 462 } 463 464 static int ath10k_pci_wake_wait(struct ath10k *ar) 465 { 466 int tot_delay = 0; 467 int curr_delay = 5; 468 469 while (tot_delay < PCIE_WAKE_TIMEOUT) { 470 if (ath10k_pci_is_awake(ar)) { 471 if (tot_delay > PCIE_WAKE_LATE_US) 472 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n", 473 tot_delay / 1000); 474 return 0; 475 } 476 477 udelay(curr_delay); 478 tot_delay += curr_delay; 479 480 if (curr_delay < 50) 481 curr_delay += 5; 482 } 483 484 return -ETIMEDOUT; 485 } 486 487 static int ath10k_pci_force_wake(struct ath10k *ar) 488 { 489 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 490 unsigned long flags; 491 int ret = 0; 492 493 if (ar_pci->pci_ps) 494 return ret; 495 496 spin_lock_irqsave(&ar_pci->ps_lock, flags); 497 498 if (!ar_pci->ps_awake) { 499 iowrite32(PCIE_SOC_WAKE_V_MASK, 500 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 501 PCIE_SOC_WAKE_ADDRESS); 502 503 ret = ath10k_pci_wake_wait(ar); 504 if (ret == 0) 505 ar_pci->ps_awake = true; 506 } 507 508 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 509 510 return ret; 511 } 512 513 static void ath10k_pci_force_sleep(struct ath10k *ar) 514 { 515 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 516 unsigned long flags; 517 518 spin_lock_irqsave(&ar_pci->ps_lock, flags); 519 520 iowrite32(PCIE_SOC_WAKE_RESET, 521 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + 522 PCIE_SOC_WAKE_ADDRESS); 523 ar_pci->ps_awake = false; 524 525 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 526 } 527 528 static int ath10k_pci_wake(struct ath10k *ar) 529 { 530 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 531 unsigned long flags; 532 int ret = 0; 533 534 if (ar_pci->pci_ps == 0) 535 return ret; 536 537 spin_lock_irqsave(&ar_pci->ps_lock, flags); 538 539 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n", 540 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 541 542 /* This function can be called very frequently. To avoid excessive 543 * CPU stalls for MMIO reads use a cache var to hold the device state. 544 */ 545 if (!ar_pci->ps_awake) { 546 __ath10k_pci_wake(ar); 547 548 ret = ath10k_pci_wake_wait(ar); 549 if (ret == 0) 550 ar_pci->ps_awake = true; 551 } 552 553 if (ret == 0) { 554 ar_pci->ps_wake_refcount++; 555 WARN_ON(ar_pci->ps_wake_refcount == 0); 556 } 557 558 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 559 560 return ret; 561 } 562 563 static void ath10k_pci_sleep(struct ath10k *ar) 564 { 565 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 566 unsigned long flags; 567 568 if (ar_pci->pci_ps == 0) 569 return; 570 571 spin_lock_irqsave(&ar_pci->ps_lock, flags); 572 573 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n", 574 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 575 576 if (WARN_ON(ar_pci->ps_wake_refcount == 0)) 577 goto skip; 578 579 ar_pci->ps_wake_refcount--; 580 581 mod_timer(&ar_pci->ps_timer, jiffies + 582 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC)); 583 584 skip: 585 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 586 } 587 588 static void ath10k_pci_ps_timer(unsigned long ptr) 589 { 590 struct ath10k *ar = (void *)ptr; 591 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 592 unsigned long flags; 593 594 spin_lock_irqsave(&ar_pci->ps_lock, flags); 595 596 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n", 597 ar_pci->ps_wake_refcount, ar_pci->ps_awake); 598 599 if (ar_pci->ps_wake_refcount > 0) 600 goto skip; 601 602 __ath10k_pci_sleep(ar); 603 604 skip: 605 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 606 } 607 608 static void ath10k_pci_sleep_sync(struct ath10k *ar) 609 { 610 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 611 unsigned long flags; 612 613 if (ar_pci->pci_ps == 0) { 614 ath10k_pci_force_sleep(ar); 615 return; 616 } 617 618 del_timer_sync(&ar_pci->ps_timer); 619 620 spin_lock_irqsave(&ar_pci->ps_lock, flags); 621 WARN_ON(ar_pci->ps_wake_refcount > 0); 622 __ath10k_pci_sleep(ar); 623 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 624 } 625 626 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value) 627 { 628 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 629 int ret; 630 631 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) { 632 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 633 offset, offset + sizeof(value), ar_pci->mem_len); 634 return; 635 } 636 637 ret = ath10k_pci_wake(ar); 638 if (ret) { 639 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n", 640 value, offset, ret); 641 return; 642 } 643 644 iowrite32(value, ar_pci->mem + offset); 645 ath10k_pci_sleep(ar); 646 } 647 648 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) 649 { 650 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 651 u32 val; 652 int ret; 653 654 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) { 655 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n", 656 offset, offset + sizeof(val), ar_pci->mem_len); 657 return 0; 658 } 659 660 ret = ath10k_pci_wake(ar); 661 if (ret) { 662 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n", 663 offset, ret); 664 return 0xffffffff; 665 } 666 667 val = ioread32(ar_pci->mem + offset); 668 ath10k_pci_sleep(ar); 669 670 return val; 671 } 672 673 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) 674 { 675 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 676 677 ar_pci->bus_ops->write32(ar, offset, value); 678 } 679 680 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) 681 { 682 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 683 684 return ar_pci->bus_ops->read32(ar, offset); 685 } 686 687 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) 688 { 689 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); 690 } 691 692 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) 693 { 694 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); 695 } 696 697 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) 698 { 699 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr); 700 } 701 702 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) 703 { 704 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val); 705 } 706 707 bool ath10k_pci_irq_pending(struct ath10k *ar) 708 { 709 u32 cause; 710 711 /* Check if the shared legacy irq is for us */ 712 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 713 PCIE_INTR_CAUSE_ADDRESS); 714 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) 715 return true; 716 717 return false; 718 } 719 720 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) 721 { 722 /* IMPORTANT: INTR_CLR register has to be set after 723 * INTR_ENABLE is set to 0, otherwise interrupt can not be 724 * really cleared. 725 */ 726 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 727 0); 728 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, 729 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 730 731 /* IMPORTANT: this extra read transaction is required to 732 * flush the posted write buffer. 733 */ 734 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 735 PCIE_INTR_ENABLE_ADDRESS); 736 } 737 738 void ath10k_pci_enable_legacy_irq(struct ath10k *ar) 739 { 740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 741 PCIE_INTR_ENABLE_ADDRESS, 742 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 743 744 /* IMPORTANT: this extra read transaction is required to 745 * flush the posted write buffer. 746 */ 747 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 748 PCIE_INTR_ENABLE_ADDRESS); 749 } 750 751 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) 752 { 753 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 754 755 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI) 756 return "msi"; 757 758 return "legacy"; 759 } 760 761 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) 762 { 763 struct ath10k *ar = pipe->hif_ce_state; 764 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 765 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 766 struct sk_buff *skb; 767 dma_addr_t paddr; 768 int ret; 769 770 skb = dev_alloc_skb(pipe->buf_sz); 771 if (!skb) 772 return -ENOMEM; 773 774 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); 775 776 paddr = dma_map_single(ar->dev, skb->data, 777 skb->len + skb_tailroom(skb), 778 DMA_FROM_DEVICE); 779 if (unlikely(dma_mapping_error(ar->dev, paddr))) { 780 ath10k_warn(ar, "failed to dma map pci rx buf\n"); 781 dev_kfree_skb_any(skb); 782 return -EIO; 783 } 784 785 ATH10K_SKB_RXCB(skb)->paddr = paddr; 786 787 spin_lock_bh(&ar_pci->ce_lock); 788 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); 789 spin_unlock_bh(&ar_pci->ce_lock); 790 if (ret) { 791 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), 792 DMA_FROM_DEVICE); 793 dev_kfree_skb_any(skb); 794 return ret; 795 } 796 797 return 0; 798 } 799 800 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) 801 { 802 struct ath10k *ar = pipe->hif_ce_state; 803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 804 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; 805 int ret, num; 806 807 if (pipe->buf_sz == 0) 808 return; 809 810 if (!ce_pipe->dest_ring) 811 return; 812 813 spin_lock_bh(&ar_pci->ce_lock); 814 num = __ath10k_ce_rx_num_free_bufs(ce_pipe); 815 spin_unlock_bh(&ar_pci->ce_lock); 816 817 while (num >= 0) { 818 ret = __ath10k_pci_rx_post_buf(pipe); 819 if (ret) { 820 if (ret == -ENOSPC) 821 break; 822 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); 823 mod_timer(&ar_pci->rx_post_retry, jiffies + 824 ATH10K_PCI_RX_POST_RETRY_MS); 825 break; 826 } 827 num--; 828 } 829 } 830 831 void ath10k_pci_rx_post(struct ath10k *ar) 832 { 833 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 834 int i; 835 836 for (i = 0; i < CE_COUNT; i++) 837 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); 838 } 839 840 void ath10k_pci_rx_replenish_retry(unsigned long ptr) 841 { 842 struct ath10k *ar = (void *)ptr; 843 844 ath10k_pci_rx_post(ar); 845 } 846 847 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 848 { 849 u32 val = 0, region = addr & 0xfffff; 850 851 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS) 852 & 0x7ff) << 21; 853 val |= 0x100000 | region; 854 return val; 855 } 856 857 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 858 { 859 u32 val = 0, region = addr & 0xfffff; 860 861 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); 862 val |= 0x100000 | region; 863 return val; 864 } 865 866 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) 867 { 868 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 869 870 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr)) 871 return -ENOTSUPP; 872 873 return ar_pci->targ_cpu_to_ce_addr(ar, addr); 874 } 875 876 /* 877 * Diagnostic read/write access is provided for startup/config/debug usage. 878 * Caller must guarantee proper alignment, when applicable, and single user 879 * at any moment. 880 */ 881 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, 882 int nbytes) 883 { 884 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 885 int ret = 0; 886 u32 *buf; 887 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; 888 struct ath10k_ce_pipe *ce_diag; 889 /* Host buffer address in CE space */ 890 u32 ce_data; 891 dma_addr_t ce_data_base = 0; 892 void *data_buf = NULL; 893 int i; 894 895 spin_lock_bh(&ar_pci->ce_lock); 896 897 ce_diag = ar_pci->ce_diag; 898 899 /* 900 * Allocate a temporary bounce buffer to hold caller's data 901 * to be DMA'ed from Target. This guarantees 902 * 1) 4-byte alignment 903 * 2) Buffer in DMA-able space 904 */ 905 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT); 906 907 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev, 908 alloc_nbytes, 909 &ce_data_base, 910 GFP_ATOMIC); 911 912 if (!data_buf) { 913 ret = -ENOMEM; 914 goto done; 915 } 916 917 remaining_bytes = nbytes; 918 ce_data = ce_data_base; 919 while (remaining_bytes) { 920 nbytes = min_t(unsigned int, remaining_bytes, 921 DIAG_TRANSFER_LIMIT); 922 923 ret = __ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data); 924 if (ret != 0) 925 goto done; 926 927 /* Request CE to send from Target(!) address to Host buffer */ 928 /* 929 * The address supplied by the caller is in the 930 * Target CPU virtual address space. 931 * 932 * In order to use this address with the diagnostic CE, 933 * convert it from Target CPU virtual address space 934 * to CE address space 935 */ 936 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 937 938 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, 939 0); 940 if (ret) 941 goto done; 942 943 i = 0; 944 while (ath10k_ce_completed_send_next_nolock(ce_diag, 945 NULL) != 0) { 946 mdelay(1); 947 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 948 ret = -EBUSY; 949 goto done; 950 } 951 } 952 953 i = 0; 954 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 955 (void **)&buf, 956 &completed_nbytes) 957 != 0) { 958 mdelay(1); 959 960 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 961 ret = -EBUSY; 962 goto done; 963 } 964 } 965 966 if (nbytes != completed_nbytes) { 967 ret = -EIO; 968 goto done; 969 } 970 971 if (*buf != ce_data) { 972 ret = -EIO; 973 goto done; 974 } 975 976 remaining_bytes -= nbytes; 977 memcpy(data, data_buf, nbytes); 978 979 address += nbytes; 980 data += nbytes; 981 } 982 983 done: 984 985 if (data_buf) 986 dma_free_coherent(ar->dev, alloc_nbytes, data_buf, 987 ce_data_base); 988 989 spin_unlock_bh(&ar_pci->ce_lock); 990 991 return ret; 992 } 993 994 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) 995 { 996 __le32 val = 0; 997 int ret; 998 999 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); 1000 *value = __le32_to_cpu(val); 1001 1002 return ret; 1003 } 1004 1005 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, 1006 u32 src, u32 len) 1007 { 1008 u32 host_addr, addr; 1009 int ret; 1010 1011 host_addr = host_interest_item_address(src); 1012 1013 ret = ath10k_pci_diag_read32(ar, host_addr, &addr); 1014 if (ret != 0) { 1015 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", 1016 src, ret); 1017 return ret; 1018 } 1019 1020 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); 1021 if (ret != 0) { 1022 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", 1023 addr, len, ret); 1024 return ret; 1025 } 1026 1027 return 0; 1028 } 1029 1030 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ 1031 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) 1032 1033 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, 1034 const void *data, int nbytes) 1035 { 1036 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1037 int ret = 0; 1038 u32 *buf; 1039 unsigned int completed_nbytes, orig_nbytes, remaining_bytes; 1040 struct ath10k_ce_pipe *ce_diag; 1041 void *data_buf = NULL; 1042 u32 ce_data; /* Host buffer address in CE space */ 1043 dma_addr_t ce_data_base = 0; 1044 int i; 1045 1046 spin_lock_bh(&ar_pci->ce_lock); 1047 1048 ce_diag = ar_pci->ce_diag; 1049 1050 /* 1051 * Allocate a temporary bounce buffer to hold caller's data 1052 * to be DMA'ed to Target. This guarantees 1053 * 1) 4-byte alignment 1054 * 2) Buffer in DMA-able space 1055 */ 1056 orig_nbytes = nbytes; 1057 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, 1058 orig_nbytes, 1059 &ce_data_base, 1060 GFP_ATOMIC); 1061 if (!data_buf) { 1062 ret = -ENOMEM; 1063 goto done; 1064 } 1065 1066 /* Copy caller's data to allocated DMA buf */ 1067 memcpy(data_buf, data, orig_nbytes); 1068 1069 /* 1070 * The address supplied by the caller is in the 1071 * Target CPU virtual address space. 1072 * 1073 * In order to use this address with the diagnostic CE, 1074 * convert it from 1075 * Target CPU virtual address space 1076 * to 1077 * CE address space 1078 */ 1079 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address); 1080 1081 remaining_bytes = orig_nbytes; 1082 ce_data = ce_data_base; 1083 while (remaining_bytes) { 1084 /* FIXME: check cast */ 1085 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); 1086 1087 /* Set up to receive directly into Target(!) address */ 1088 ret = __ath10k_ce_rx_post_buf(ce_diag, &address, address); 1089 if (ret != 0) 1090 goto done; 1091 1092 /* 1093 * Request CE to send caller-supplied data that 1094 * was copied to bounce buffer to Target(!) address. 1095 */ 1096 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, 1097 nbytes, 0, 0); 1098 if (ret != 0) 1099 goto done; 1100 1101 i = 0; 1102 while (ath10k_ce_completed_send_next_nolock(ce_diag, 1103 NULL) != 0) { 1104 mdelay(1); 1105 1106 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1107 ret = -EBUSY; 1108 goto done; 1109 } 1110 } 1111 1112 i = 0; 1113 while (ath10k_ce_completed_recv_next_nolock(ce_diag, 1114 (void **)&buf, 1115 &completed_nbytes) 1116 != 0) { 1117 mdelay(1); 1118 1119 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { 1120 ret = -EBUSY; 1121 goto done; 1122 } 1123 } 1124 1125 if (nbytes != completed_nbytes) { 1126 ret = -EIO; 1127 goto done; 1128 } 1129 1130 if (*buf != address) { 1131 ret = -EIO; 1132 goto done; 1133 } 1134 1135 remaining_bytes -= nbytes; 1136 address += nbytes; 1137 ce_data += nbytes; 1138 } 1139 1140 done: 1141 if (data_buf) { 1142 dma_free_coherent(ar->dev, orig_nbytes, data_buf, 1143 ce_data_base); 1144 } 1145 1146 if (ret != 0) 1147 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", 1148 address, ret); 1149 1150 spin_unlock_bh(&ar_pci->ce_lock); 1151 1152 return ret; 1153 } 1154 1155 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) 1156 { 1157 __le32 val = __cpu_to_le32(value); 1158 1159 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); 1160 } 1161 1162 /* Called by lower (CE) layer when a send to Target completes. */ 1163 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state) 1164 { 1165 struct ath10k *ar = ce_state->ar; 1166 struct sk_buff_head list; 1167 struct sk_buff *skb; 1168 1169 __skb_queue_head_init(&list); 1170 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1171 /* no need to call tx completion for NULL pointers */ 1172 if (skb == NULL) 1173 continue; 1174 1175 __skb_queue_tail(&list, skb); 1176 } 1177 1178 while ((skb = __skb_dequeue(&list))) 1179 ath10k_htc_tx_completion_handler(ar, skb); 1180 } 1181 1182 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state, 1183 void (*callback)(struct ath10k *ar, 1184 struct sk_buff *skb)) 1185 { 1186 struct ath10k *ar = ce_state->ar; 1187 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1188 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1189 struct sk_buff *skb; 1190 struct sk_buff_head list; 1191 void *transfer_context; 1192 unsigned int nbytes, max_nbytes; 1193 1194 __skb_queue_head_init(&list); 1195 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, 1196 &nbytes) == 0) { 1197 skb = transfer_context; 1198 max_nbytes = skb->len + skb_tailroom(skb); 1199 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1200 max_nbytes, DMA_FROM_DEVICE); 1201 1202 if (unlikely(max_nbytes < nbytes)) { 1203 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1204 nbytes, max_nbytes); 1205 dev_kfree_skb_any(skb); 1206 continue; 1207 } 1208 1209 skb_put(skb, nbytes); 1210 __skb_queue_tail(&list, skb); 1211 } 1212 1213 while ((skb = __skb_dequeue(&list))) { 1214 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1215 ce_state->id, skb->len); 1216 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1217 skb->data, skb->len); 1218 1219 callback(ar, skb); 1220 } 1221 1222 ath10k_pci_rx_post_pipe(pipe_info); 1223 } 1224 1225 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state, 1226 void (*callback)(struct ath10k *ar, 1227 struct sk_buff *skb)) 1228 { 1229 struct ath10k *ar = ce_state->ar; 1230 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1231 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; 1232 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl; 1233 struct sk_buff *skb; 1234 struct sk_buff_head list; 1235 void *transfer_context; 1236 unsigned int nbytes, max_nbytes, nentries; 1237 int orig_len; 1238 1239 /* No need to aquire ce_lock for CE5, since this is the only place CE5 1240 * is processed other than init and deinit. Before releasing CE5 1241 * buffers, interrupts are disabled. Thus CE5 access is serialized. 1242 */ 1243 __skb_queue_head_init(&list); 1244 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context, 1245 &nbytes) == 0) { 1246 skb = transfer_context; 1247 max_nbytes = skb->len + skb_tailroom(skb); 1248 1249 if (unlikely(max_nbytes < nbytes)) { 1250 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", 1251 nbytes, max_nbytes); 1252 continue; 1253 } 1254 1255 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1256 max_nbytes, DMA_FROM_DEVICE); 1257 skb_put(skb, nbytes); 1258 __skb_queue_tail(&list, skb); 1259 } 1260 1261 nentries = skb_queue_len(&list); 1262 while ((skb = __skb_dequeue(&list))) { 1263 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", 1264 ce_state->id, skb->len); 1265 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", 1266 skb->data, skb->len); 1267 1268 orig_len = skb->len; 1269 callback(ar, skb); 1270 skb_push(skb, orig_len - skb->len); 1271 skb_reset_tail_pointer(skb); 1272 skb_trim(skb, 0); 1273 1274 /*let device gain the buffer again*/ 1275 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1276 skb->len + skb_tailroom(skb), 1277 DMA_FROM_DEVICE); 1278 } 1279 ath10k_ce_rx_update_write_idx(ce_pipe, nentries); 1280 } 1281 1282 /* Called by lower (CE) layer when data is received from the Target. */ 1283 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1284 { 1285 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1286 } 1287 1288 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state) 1289 { 1290 /* CE4 polling needs to be done whenever CE pipe which transports 1291 * HTT Rx (target->host) is processed. 1292 */ 1293 ath10k_ce_per_engine_service(ce_state->ar, 4); 1294 1295 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler); 1296 } 1297 1298 /* Called by lower (CE) layer when data is received from the Target. 1299 * Only 10.4 firmware uses separate CE to transfer pktlog data. 1300 */ 1301 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state) 1302 { 1303 ath10k_pci_process_rx_cb(ce_state, 1304 ath10k_htt_rx_pktlog_completion_handler); 1305 } 1306 1307 /* Called by lower (CE) layer when a send to HTT Target completes. */ 1308 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state) 1309 { 1310 struct ath10k *ar = ce_state->ar; 1311 struct sk_buff *skb; 1312 1313 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) { 1314 /* no need to call tx completion for NULL pointers */ 1315 if (!skb) 1316 continue; 1317 1318 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, 1319 skb->len, DMA_TO_DEVICE); 1320 ath10k_htt_hif_tx_complete(ar, skb); 1321 } 1322 } 1323 1324 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb) 1325 { 1326 skb_pull(skb, sizeof(struct ath10k_htc_hdr)); 1327 ath10k_htt_t2h_msg_handler(ar, skb); 1328 } 1329 1330 /* Called by lower (CE) layer when HTT data is received from the Target. */ 1331 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state) 1332 { 1333 /* CE4 polling needs to be done whenever CE pipe which transports 1334 * HTT Rx (target->host) is processed. 1335 */ 1336 ath10k_ce_per_engine_service(ce_state->ar, 4); 1337 1338 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver); 1339 } 1340 1341 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, 1342 struct ath10k_hif_sg_item *items, int n_items) 1343 { 1344 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1345 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; 1346 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; 1347 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; 1348 unsigned int nentries_mask; 1349 unsigned int sw_index; 1350 unsigned int write_index; 1351 int err, i = 0; 1352 1353 spin_lock_bh(&ar_pci->ce_lock); 1354 1355 nentries_mask = src_ring->nentries_mask; 1356 sw_index = src_ring->sw_index; 1357 write_index = src_ring->write_index; 1358 1359 if (unlikely(CE_RING_DELTA(nentries_mask, 1360 write_index, sw_index - 1) < n_items)) { 1361 err = -ENOBUFS; 1362 goto err; 1363 } 1364 1365 for (i = 0; i < n_items - 1; i++) { 1366 ath10k_dbg(ar, ATH10K_DBG_PCI, 1367 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1368 i, items[i].paddr, items[i].len, n_items); 1369 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1370 items[i].vaddr, items[i].len); 1371 1372 err = ath10k_ce_send_nolock(ce_pipe, 1373 items[i].transfer_context, 1374 items[i].paddr, 1375 items[i].len, 1376 items[i].transfer_id, 1377 CE_SEND_FLAG_GATHER); 1378 if (err) 1379 goto err; 1380 } 1381 1382 /* `i` is equal to `n_items -1` after for() */ 1383 1384 ath10k_dbg(ar, ATH10K_DBG_PCI, 1385 "pci tx item %d paddr 0x%08x len %d n_items %d\n", 1386 i, items[i].paddr, items[i].len, n_items); 1387 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", 1388 items[i].vaddr, items[i].len); 1389 1390 err = ath10k_ce_send_nolock(ce_pipe, 1391 items[i].transfer_context, 1392 items[i].paddr, 1393 items[i].len, 1394 items[i].transfer_id, 1395 0); 1396 if (err) 1397 goto err; 1398 1399 spin_unlock_bh(&ar_pci->ce_lock); 1400 return 0; 1401 1402 err: 1403 for (; i > 0; i--) 1404 __ath10k_ce_send_revert(ce_pipe); 1405 1406 spin_unlock_bh(&ar_pci->ce_lock); 1407 return err; 1408 } 1409 1410 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, 1411 size_t buf_len) 1412 { 1413 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); 1414 } 1415 1416 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) 1417 { 1418 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1419 1420 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); 1421 1422 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); 1423 } 1424 1425 static void ath10k_pci_dump_registers(struct ath10k *ar, 1426 struct ath10k_fw_crash_data *crash_data) 1427 { 1428 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; 1429 int i, ret; 1430 1431 lockdep_assert_held(&ar->data_lock); 1432 1433 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], 1434 hi_failure_state, 1435 REG_DUMP_COUNT_QCA988X * sizeof(__le32)); 1436 if (ret) { 1437 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); 1438 return; 1439 } 1440 1441 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); 1442 1443 ath10k_err(ar, "firmware register dump:\n"); 1444 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) 1445 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", 1446 i, 1447 __le32_to_cpu(reg_dump_values[i]), 1448 __le32_to_cpu(reg_dump_values[i + 1]), 1449 __le32_to_cpu(reg_dump_values[i + 2]), 1450 __le32_to_cpu(reg_dump_values[i + 3])); 1451 1452 if (!crash_data) 1453 return; 1454 1455 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) 1456 crash_data->registers[i] = reg_dump_values[i]; 1457 } 1458 1459 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) 1460 { 1461 struct ath10k_fw_crash_data *crash_data; 1462 char uuid[50]; 1463 1464 spin_lock_bh(&ar->data_lock); 1465 1466 ar->stats.fw_crash_counter++; 1467 1468 crash_data = ath10k_debug_get_new_fw_crash_data(ar); 1469 1470 if (crash_data) 1471 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid); 1472 else 1473 scnprintf(uuid, sizeof(uuid), "n/a"); 1474 1475 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid); 1476 ath10k_print_driver_info(ar); 1477 ath10k_pci_dump_registers(ar, crash_data); 1478 ath10k_ce_dump_registers(ar, crash_data); 1479 1480 spin_unlock_bh(&ar->data_lock); 1481 1482 queue_work(ar->workqueue, &ar->restart_work); 1483 } 1484 1485 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, 1486 int force) 1487 { 1488 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); 1489 1490 if (!force) { 1491 int resources; 1492 /* 1493 * Decide whether to actually poll for completions, or just 1494 * wait for a later chance. 1495 * If there seem to be plenty of resources left, then just wait 1496 * since checking involves reading a CE register, which is a 1497 * relatively expensive operation. 1498 */ 1499 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); 1500 1501 /* 1502 * If at least 50% of the total resources are still available, 1503 * don't bother checking again yet. 1504 */ 1505 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) 1506 return; 1507 } 1508 ath10k_ce_per_engine_service(ar, pipe); 1509 } 1510 1511 static void ath10k_pci_rx_retry_sync(struct ath10k *ar) 1512 { 1513 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1514 1515 del_timer_sync(&ar_pci->rx_post_retry); 1516 } 1517 1518 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id, 1519 u8 *ul_pipe, u8 *dl_pipe) 1520 { 1521 const struct service_to_pipe *entry; 1522 bool ul_set = false, dl_set = false; 1523 int i; 1524 1525 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); 1526 1527 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { 1528 entry = &target_service_to_ce_map_wlan[i]; 1529 1530 if (__le32_to_cpu(entry->service_id) != service_id) 1531 continue; 1532 1533 switch (__le32_to_cpu(entry->pipedir)) { 1534 case PIPEDIR_NONE: 1535 break; 1536 case PIPEDIR_IN: 1537 WARN_ON(dl_set); 1538 *dl_pipe = __le32_to_cpu(entry->pipenum); 1539 dl_set = true; 1540 break; 1541 case PIPEDIR_OUT: 1542 WARN_ON(ul_set); 1543 *ul_pipe = __le32_to_cpu(entry->pipenum); 1544 ul_set = true; 1545 break; 1546 case PIPEDIR_INOUT: 1547 WARN_ON(dl_set); 1548 WARN_ON(ul_set); 1549 *dl_pipe = __le32_to_cpu(entry->pipenum); 1550 *ul_pipe = __le32_to_cpu(entry->pipenum); 1551 dl_set = true; 1552 ul_set = true; 1553 break; 1554 } 1555 } 1556 1557 if (WARN_ON(!ul_set || !dl_set)) 1558 return -ENOENT; 1559 1560 return 0; 1561 } 1562 1563 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, 1564 u8 *ul_pipe, u8 *dl_pipe) 1565 { 1566 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); 1567 1568 (void)ath10k_pci_hif_map_service_to_pipe(ar, 1569 ATH10K_HTC_SVC_ID_RSVD_CTRL, 1570 ul_pipe, dl_pipe); 1571 } 1572 1573 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) 1574 { 1575 u32 val; 1576 1577 switch (ar->hw_rev) { 1578 case ATH10K_HW_QCA988X: 1579 case ATH10K_HW_QCA9887: 1580 case ATH10K_HW_QCA6174: 1581 case ATH10K_HW_QCA9377: 1582 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1583 CORE_CTRL_ADDRESS); 1584 val &= ~CORE_CTRL_PCIE_REG_31_MASK; 1585 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1586 CORE_CTRL_ADDRESS, val); 1587 break; 1588 case ATH10K_HW_QCA99X0: 1589 case ATH10K_HW_QCA9984: 1590 case ATH10K_HW_QCA9888: 1591 case ATH10K_HW_QCA4019: 1592 /* TODO: Find appropriate register configuration for QCA99X0 1593 * to mask irq/MSI. 1594 */ 1595 break; 1596 } 1597 } 1598 1599 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) 1600 { 1601 u32 val; 1602 1603 switch (ar->hw_rev) { 1604 case ATH10K_HW_QCA988X: 1605 case ATH10K_HW_QCA9887: 1606 case ATH10K_HW_QCA6174: 1607 case ATH10K_HW_QCA9377: 1608 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + 1609 CORE_CTRL_ADDRESS); 1610 val |= CORE_CTRL_PCIE_REG_31_MASK; 1611 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + 1612 CORE_CTRL_ADDRESS, val); 1613 break; 1614 case ATH10K_HW_QCA99X0: 1615 case ATH10K_HW_QCA9984: 1616 case ATH10K_HW_QCA9888: 1617 case ATH10K_HW_QCA4019: 1618 /* TODO: Find appropriate register configuration for QCA99X0 1619 * to unmask irq/MSI. 1620 */ 1621 break; 1622 } 1623 } 1624 1625 static void ath10k_pci_irq_disable(struct ath10k *ar) 1626 { 1627 ath10k_ce_disable_interrupts(ar); 1628 ath10k_pci_disable_and_clear_legacy_irq(ar); 1629 ath10k_pci_irq_msi_fw_mask(ar); 1630 } 1631 1632 static void ath10k_pci_irq_sync(struct ath10k *ar) 1633 { 1634 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1635 1636 synchronize_irq(ar_pci->pdev->irq); 1637 } 1638 1639 static void ath10k_pci_irq_enable(struct ath10k *ar) 1640 { 1641 ath10k_ce_enable_interrupts(ar); 1642 ath10k_pci_enable_legacy_irq(ar); 1643 ath10k_pci_irq_msi_fw_unmask(ar); 1644 } 1645 1646 static int ath10k_pci_hif_start(struct ath10k *ar) 1647 { 1648 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1649 1650 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); 1651 1652 napi_enable(&ar->napi); 1653 1654 ath10k_pci_irq_enable(ar); 1655 ath10k_pci_rx_post(ar); 1656 1657 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 1658 ar_pci->link_ctl); 1659 1660 return 0; 1661 } 1662 1663 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1664 { 1665 struct ath10k *ar; 1666 struct ath10k_ce_pipe *ce_pipe; 1667 struct ath10k_ce_ring *ce_ring; 1668 struct sk_buff *skb; 1669 int i; 1670 1671 ar = pci_pipe->hif_ce_state; 1672 ce_pipe = pci_pipe->ce_hdl; 1673 ce_ring = ce_pipe->dest_ring; 1674 1675 if (!ce_ring) 1676 return; 1677 1678 if (!pci_pipe->buf_sz) 1679 return; 1680 1681 for (i = 0; i < ce_ring->nentries; i++) { 1682 skb = ce_ring->per_transfer_context[i]; 1683 if (!skb) 1684 continue; 1685 1686 ce_ring->per_transfer_context[i] = NULL; 1687 1688 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr, 1689 skb->len + skb_tailroom(skb), 1690 DMA_FROM_DEVICE); 1691 dev_kfree_skb_any(skb); 1692 } 1693 } 1694 1695 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) 1696 { 1697 struct ath10k *ar; 1698 struct ath10k_ce_pipe *ce_pipe; 1699 struct ath10k_ce_ring *ce_ring; 1700 struct sk_buff *skb; 1701 int i; 1702 1703 ar = pci_pipe->hif_ce_state; 1704 ce_pipe = pci_pipe->ce_hdl; 1705 ce_ring = ce_pipe->src_ring; 1706 1707 if (!ce_ring) 1708 return; 1709 1710 if (!pci_pipe->buf_sz) 1711 return; 1712 1713 for (i = 0; i < ce_ring->nentries; i++) { 1714 skb = ce_ring->per_transfer_context[i]; 1715 if (!skb) 1716 continue; 1717 1718 ce_ring->per_transfer_context[i] = NULL; 1719 1720 ath10k_htc_tx_completion_handler(ar, skb); 1721 } 1722 } 1723 1724 /* 1725 * Cleanup residual buffers for device shutdown: 1726 * buffers that were enqueued for receive 1727 * buffers that were to be sent 1728 * Note: Buffers that had completed but which were 1729 * not yet processed are on a completion queue. They 1730 * are handled when the completion thread shuts down. 1731 */ 1732 static void ath10k_pci_buffer_cleanup(struct ath10k *ar) 1733 { 1734 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1735 int pipe_num; 1736 1737 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { 1738 struct ath10k_pci_pipe *pipe_info; 1739 1740 pipe_info = &ar_pci->pipe_info[pipe_num]; 1741 ath10k_pci_rx_pipe_cleanup(pipe_info); 1742 ath10k_pci_tx_pipe_cleanup(pipe_info); 1743 } 1744 } 1745 1746 void ath10k_pci_ce_deinit(struct ath10k *ar) 1747 { 1748 int i; 1749 1750 for (i = 0; i < CE_COUNT; i++) 1751 ath10k_ce_deinit_pipe(ar, i); 1752 } 1753 1754 void ath10k_pci_flush(struct ath10k *ar) 1755 { 1756 ath10k_pci_rx_retry_sync(ar); 1757 ath10k_pci_buffer_cleanup(ar); 1758 } 1759 1760 static void ath10k_pci_hif_stop(struct ath10k *ar) 1761 { 1762 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1763 unsigned long flags; 1764 1765 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); 1766 1767 /* Most likely the device has HTT Rx ring configured. The only way to 1768 * prevent the device from accessing (and possible corrupting) host 1769 * memory is to reset the chip now. 1770 * 1771 * There's also no known way of masking MSI interrupts on the device. 1772 * For ranged MSI the CE-related interrupts can be masked. However 1773 * regardless how many MSI interrupts are assigned the first one 1774 * is always used for firmware indications (crashes) and cannot be 1775 * masked. To prevent the device from asserting the interrupt reset it 1776 * before proceeding with cleanup. 1777 */ 1778 ath10k_pci_safe_chip_reset(ar); 1779 1780 ath10k_pci_irq_disable(ar); 1781 ath10k_pci_irq_sync(ar); 1782 ath10k_pci_flush(ar); 1783 napi_synchronize(&ar->napi); 1784 napi_disable(&ar->napi); 1785 1786 spin_lock_irqsave(&ar_pci->ps_lock, flags); 1787 WARN_ON(ar_pci->ps_wake_refcount > 0); 1788 spin_unlock_irqrestore(&ar_pci->ps_lock, flags); 1789 } 1790 1791 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, 1792 void *req, u32 req_len, 1793 void *resp, u32 *resp_len) 1794 { 1795 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1796 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; 1797 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; 1798 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; 1799 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; 1800 dma_addr_t req_paddr = 0; 1801 dma_addr_t resp_paddr = 0; 1802 struct bmi_xfer xfer = {}; 1803 void *treq, *tresp = NULL; 1804 int ret = 0; 1805 1806 might_sleep(); 1807 1808 if (resp && !resp_len) 1809 return -EINVAL; 1810 1811 if (resp && resp_len && *resp_len == 0) 1812 return -EINVAL; 1813 1814 treq = kmemdup(req, req_len, GFP_KERNEL); 1815 if (!treq) 1816 return -ENOMEM; 1817 1818 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); 1819 ret = dma_mapping_error(ar->dev, req_paddr); 1820 if (ret) { 1821 ret = -EIO; 1822 goto err_dma; 1823 } 1824 1825 if (resp && resp_len) { 1826 tresp = kzalloc(*resp_len, GFP_KERNEL); 1827 if (!tresp) { 1828 ret = -ENOMEM; 1829 goto err_req; 1830 } 1831 1832 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, 1833 DMA_FROM_DEVICE); 1834 ret = dma_mapping_error(ar->dev, resp_paddr); 1835 if (ret) { 1836 ret = -EIO; 1837 goto err_req; 1838 } 1839 1840 xfer.wait_for_resp = true; 1841 xfer.resp_len = 0; 1842 1843 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); 1844 } 1845 1846 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); 1847 if (ret) 1848 goto err_resp; 1849 1850 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer); 1851 if (ret) { 1852 u32 unused_buffer; 1853 unsigned int unused_nbytes; 1854 unsigned int unused_id; 1855 1856 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, 1857 &unused_nbytes, &unused_id); 1858 } else { 1859 /* non-zero means we did not time out */ 1860 ret = 0; 1861 } 1862 1863 err_resp: 1864 if (resp) { 1865 u32 unused_buffer; 1866 1867 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); 1868 dma_unmap_single(ar->dev, resp_paddr, 1869 *resp_len, DMA_FROM_DEVICE); 1870 } 1871 err_req: 1872 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); 1873 1874 if (ret == 0 && resp_len) { 1875 *resp_len = min(*resp_len, xfer.resp_len); 1876 memcpy(resp, tresp, xfer.resp_len); 1877 } 1878 err_dma: 1879 kfree(treq); 1880 kfree(tresp); 1881 1882 return ret; 1883 } 1884 1885 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) 1886 { 1887 struct bmi_xfer *xfer; 1888 1889 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer)) 1890 return; 1891 1892 xfer->tx_done = true; 1893 } 1894 1895 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) 1896 { 1897 struct ath10k *ar = ce_state->ar; 1898 struct bmi_xfer *xfer; 1899 unsigned int nbytes; 1900 1901 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, 1902 &nbytes)) 1903 return; 1904 1905 if (WARN_ON_ONCE(!xfer)) 1906 return; 1907 1908 if (!xfer->wait_for_resp) { 1909 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); 1910 return; 1911 } 1912 1913 xfer->resp_len = nbytes; 1914 xfer->rx_done = true; 1915 } 1916 1917 static int ath10k_pci_bmi_wait(struct ath10k *ar, 1918 struct ath10k_ce_pipe *tx_pipe, 1919 struct ath10k_ce_pipe *rx_pipe, 1920 struct bmi_xfer *xfer) 1921 { 1922 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; 1923 unsigned long started = jiffies; 1924 unsigned long dur; 1925 int ret; 1926 1927 while (time_before_eq(jiffies, timeout)) { 1928 ath10k_pci_bmi_send_done(tx_pipe); 1929 ath10k_pci_bmi_recv_data(rx_pipe); 1930 1931 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) { 1932 ret = 0; 1933 goto out; 1934 } 1935 1936 schedule(); 1937 } 1938 1939 ret = -ETIMEDOUT; 1940 1941 out: 1942 dur = jiffies - started; 1943 if (dur > HZ) 1944 ath10k_dbg(ar, ATH10K_DBG_BMI, 1945 "bmi cmd took %lu jiffies hz %d ret %d\n", 1946 dur, HZ, ret); 1947 return ret; 1948 } 1949 1950 /* 1951 * Send an interrupt to the device to wake up the Target CPU 1952 * so it has an opportunity to notice any changed state. 1953 */ 1954 static int ath10k_pci_wake_target_cpu(struct ath10k *ar) 1955 { 1956 u32 addr, val; 1957 1958 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS; 1959 val = ath10k_pci_read32(ar, addr); 1960 val |= CORE_CTRL_CPU_INTR_MASK; 1961 ath10k_pci_write32(ar, addr, val); 1962 1963 return 0; 1964 } 1965 1966 static int ath10k_pci_get_num_banks(struct ath10k *ar) 1967 { 1968 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 1969 1970 switch (ar_pci->pdev->device) { 1971 case QCA988X_2_0_DEVICE_ID: 1972 case QCA99X0_2_0_DEVICE_ID: 1973 case QCA9888_2_0_DEVICE_ID: 1974 case QCA9984_1_0_DEVICE_ID: 1975 case QCA9887_1_0_DEVICE_ID: 1976 return 1; 1977 case QCA6164_2_1_DEVICE_ID: 1978 case QCA6174_2_1_DEVICE_ID: 1979 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) { 1980 case QCA6174_HW_1_0_CHIP_ID_REV: 1981 case QCA6174_HW_1_1_CHIP_ID_REV: 1982 case QCA6174_HW_2_1_CHIP_ID_REV: 1983 case QCA6174_HW_2_2_CHIP_ID_REV: 1984 return 3; 1985 case QCA6174_HW_1_3_CHIP_ID_REV: 1986 return 2; 1987 case QCA6174_HW_3_0_CHIP_ID_REV: 1988 case QCA6174_HW_3_1_CHIP_ID_REV: 1989 case QCA6174_HW_3_2_CHIP_ID_REV: 1990 return 9; 1991 } 1992 break; 1993 case QCA9377_1_0_DEVICE_ID: 1994 return 4; 1995 } 1996 1997 ath10k_warn(ar, "unknown number of banks, assuming 1\n"); 1998 return 1; 1999 } 2000 2001 static int ath10k_bus_get_num_banks(struct ath10k *ar) 2002 { 2003 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2004 2005 return ar_pci->bus_ops->get_num_banks(ar); 2006 } 2007 2008 int ath10k_pci_init_config(struct ath10k *ar) 2009 { 2010 u32 interconnect_targ_addr; 2011 u32 pcie_state_targ_addr = 0; 2012 u32 pipe_cfg_targ_addr = 0; 2013 u32 svc_to_pipe_map = 0; 2014 u32 pcie_config_flags = 0; 2015 u32 ealloc_value; 2016 u32 ealloc_targ_addr; 2017 u32 flag2_value; 2018 u32 flag2_targ_addr; 2019 int ret = 0; 2020 2021 /* Download to Target the CE Config and the service-to-CE map */ 2022 interconnect_targ_addr = 2023 host_interest_item_address(HI_ITEM(hi_interconnect_state)); 2024 2025 /* Supply Target-side CE configuration */ 2026 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, 2027 &pcie_state_targ_addr); 2028 if (ret != 0) { 2029 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); 2030 return ret; 2031 } 2032 2033 if (pcie_state_targ_addr == 0) { 2034 ret = -EIO; 2035 ath10k_err(ar, "Invalid pcie state addr\n"); 2036 return ret; 2037 } 2038 2039 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2040 offsetof(struct pcie_state, 2041 pipe_cfg_addr)), 2042 &pipe_cfg_targ_addr); 2043 if (ret != 0) { 2044 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); 2045 return ret; 2046 } 2047 2048 if (pipe_cfg_targ_addr == 0) { 2049 ret = -EIO; 2050 ath10k_err(ar, "Invalid pipe cfg addr\n"); 2051 return ret; 2052 } 2053 2054 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, 2055 target_ce_config_wlan, 2056 sizeof(struct ce_pipe_config) * 2057 NUM_TARGET_CE_CONFIG_WLAN); 2058 2059 if (ret != 0) { 2060 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); 2061 return ret; 2062 } 2063 2064 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2065 offsetof(struct pcie_state, 2066 svc_to_pipe_map)), 2067 &svc_to_pipe_map); 2068 if (ret != 0) { 2069 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); 2070 return ret; 2071 } 2072 2073 if (svc_to_pipe_map == 0) { 2074 ret = -EIO; 2075 ath10k_err(ar, "Invalid svc_to_pipe map\n"); 2076 return ret; 2077 } 2078 2079 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, 2080 target_service_to_ce_map_wlan, 2081 sizeof(target_service_to_ce_map_wlan)); 2082 if (ret != 0) { 2083 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); 2084 return ret; 2085 } 2086 2087 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + 2088 offsetof(struct pcie_state, 2089 config_flags)), 2090 &pcie_config_flags); 2091 if (ret != 0) { 2092 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); 2093 return ret; 2094 } 2095 2096 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; 2097 2098 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + 2099 offsetof(struct pcie_state, 2100 config_flags)), 2101 pcie_config_flags); 2102 if (ret != 0) { 2103 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); 2104 return ret; 2105 } 2106 2107 /* configure early allocation */ 2108 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); 2109 2110 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); 2111 if (ret != 0) { 2112 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret); 2113 return ret; 2114 } 2115 2116 /* first bank is switched to IRAM */ 2117 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & 2118 HI_EARLY_ALLOC_MAGIC_MASK); 2119 ealloc_value |= ((ath10k_bus_get_num_banks(ar) << 2120 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & 2121 HI_EARLY_ALLOC_IRAM_BANKS_MASK); 2122 2123 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); 2124 if (ret != 0) { 2125 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); 2126 return ret; 2127 } 2128 2129 /* Tell Target to proceed with initialization */ 2130 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); 2131 2132 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); 2133 if (ret != 0) { 2134 ath10k_err(ar, "Failed to get option val: %d\n", ret); 2135 return ret; 2136 } 2137 2138 flag2_value |= HI_OPTION_EARLY_CFG_DONE; 2139 2140 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); 2141 if (ret != 0) { 2142 ath10k_err(ar, "Failed to set option val: %d\n", ret); 2143 return ret; 2144 } 2145 2146 return 0; 2147 } 2148 2149 static void ath10k_pci_override_ce_config(struct ath10k *ar) 2150 { 2151 struct ce_attr *attr; 2152 struct ce_pipe_config *config; 2153 2154 /* For QCA6174 we're overriding the Copy Engine 5 configuration, 2155 * since it is currently used for other feature. 2156 */ 2157 2158 /* Override Host's Copy Engine 5 configuration */ 2159 attr = &host_ce_config_wlan[5]; 2160 attr->src_sz_max = 0; 2161 attr->dest_nentries = 0; 2162 2163 /* Override Target firmware's Copy Engine configuration */ 2164 config = &target_ce_config_wlan[5]; 2165 config->pipedir = __cpu_to_le32(PIPEDIR_OUT); 2166 config->nbytes_max = __cpu_to_le32(2048); 2167 2168 /* Map from service/endpoint to Copy Engine */ 2169 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1); 2170 } 2171 2172 int ath10k_pci_alloc_pipes(struct ath10k *ar) 2173 { 2174 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2175 struct ath10k_pci_pipe *pipe; 2176 int i, ret; 2177 2178 for (i = 0; i < CE_COUNT; i++) { 2179 pipe = &ar_pci->pipe_info[i]; 2180 pipe->ce_hdl = &ar_pci->ce_states[i]; 2181 pipe->pipe_num = i; 2182 pipe->hif_ce_state = ar; 2183 2184 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]); 2185 if (ret) { 2186 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", 2187 i, ret); 2188 return ret; 2189 } 2190 2191 /* Last CE is Diagnostic Window */ 2192 if (i == CE_DIAG_PIPE) { 2193 ar_pci->ce_diag = pipe->ce_hdl; 2194 continue; 2195 } 2196 2197 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); 2198 } 2199 2200 return 0; 2201 } 2202 2203 void ath10k_pci_free_pipes(struct ath10k *ar) 2204 { 2205 int i; 2206 2207 for (i = 0; i < CE_COUNT; i++) 2208 ath10k_ce_free_pipe(ar, i); 2209 } 2210 2211 int ath10k_pci_init_pipes(struct ath10k *ar) 2212 { 2213 int i, ret; 2214 2215 for (i = 0; i < CE_COUNT; i++) { 2216 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); 2217 if (ret) { 2218 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", 2219 i, ret); 2220 return ret; 2221 } 2222 } 2223 2224 return 0; 2225 } 2226 2227 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) 2228 { 2229 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & 2230 FW_IND_EVENT_PENDING; 2231 } 2232 2233 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) 2234 { 2235 u32 val; 2236 2237 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2238 val &= ~FW_IND_EVENT_PENDING; 2239 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); 2240 } 2241 2242 static bool ath10k_pci_has_device_gone(struct ath10k *ar) 2243 { 2244 u32 val; 2245 2246 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2247 return (val == 0xffffffff); 2248 } 2249 2250 /* this function effectively clears target memory controller assert line */ 2251 static void ath10k_pci_warm_reset_si0(struct ath10k *ar) 2252 { 2253 u32 val; 2254 2255 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2256 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2257 val | SOC_RESET_CONTROL_SI0_RST_MASK); 2258 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2259 2260 msleep(10); 2261 2262 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2263 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, 2264 val & ~SOC_RESET_CONTROL_SI0_RST_MASK); 2265 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); 2266 2267 msleep(10); 2268 } 2269 2270 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) 2271 { 2272 u32 val; 2273 2274 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); 2275 2276 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2277 SOC_RESET_CONTROL_ADDRESS); 2278 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2279 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); 2280 } 2281 2282 static void ath10k_pci_warm_reset_ce(struct ath10k *ar) 2283 { 2284 u32 val; 2285 2286 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2287 SOC_RESET_CONTROL_ADDRESS); 2288 2289 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2290 val | SOC_RESET_CONTROL_CE_RST_MASK); 2291 msleep(10); 2292 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, 2293 val & ~SOC_RESET_CONTROL_CE_RST_MASK); 2294 } 2295 2296 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) 2297 { 2298 u32 val; 2299 2300 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + 2301 SOC_LF_TIMER_CONTROL0_ADDRESS); 2302 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + 2303 SOC_LF_TIMER_CONTROL0_ADDRESS, 2304 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); 2305 } 2306 2307 static int ath10k_pci_warm_reset(struct ath10k *ar) 2308 { 2309 int ret; 2310 2311 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); 2312 2313 spin_lock_bh(&ar->data_lock); 2314 ar->stats.fw_warm_reset_counter++; 2315 spin_unlock_bh(&ar->data_lock); 2316 2317 ath10k_pci_irq_disable(ar); 2318 2319 /* Make sure the target CPU is not doing anything dangerous, e.g. if it 2320 * were to access copy engine while host performs copy engine reset 2321 * then it is possible for the device to confuse pci-e controller to 2322 * the point of bringing host system to a complete stop (i.e. hang). 2323 */ 2324 ath10k_pci_warm_reset_si0(ar); 2325 ath10k_pci_warm_reset_cpu(ar); 2326 ath10k_pci_init_pipes(ar); 2327 ath10k_pci_wait_for_target_init(ar); 2328 2329 ath10k_pci_warm_reset_clear_lf(ar); 2330 ath10k_pci_warm_reset_ce(ar); 2331 ath10k_pci_warm_reset_cpu(ar); 2332 ath10k_pci_init_pipes(ar); 2333 2334 ret = ath10k_pci_wait_for_target_init(ar); 2335 if (ret) { 2336 ath10k_warn(ar, "failed to wait for target init: %d\n", ret); 2337 return ret; 2338 } 2339 2340 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); 2341 2342 return 0; 2343 } 2344 2345 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) 2346 { 2347 ath10k_pci_irq_disable(ar); 2348 return ath10k_pci_qca99x0_chip_reset(ar); 2349 } 2350 2351 static int ath10k_pci_safe_chip_reset(struct ath10k *ar) 2352 { 2353 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2354 2355 if (!ar_pci->pci_soft_reset) 2356 return -ENOTSUPP; 2357 2358 return ar_pci->pci_soft_reset(ar); 2359 } 2360 2361 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar) 2362 { 2363 int i, ret; 2364 u32 val; 2365 2366 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n"); 2367 2368 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. 2369 * It is thus preferred to use warm reset which is safer but may not be 2370 * able to recover the device from all possible fail scenarios. 2371 * 2372 * Warm reset doesn't always work on first try so attempt it a few 2373 * times before giving up. 2374 */ 2375 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { 2376 ret = ath10k_pci_warm_reset(ar); 2377 if (ret) { 2378 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", 2379 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, 2380 ret); 2381 continue; 2382 } 2383 2384 /* FIXME: Sometimes copy engine doesn't recover after warm 2385 * reset. In most cases this needs cold reset. In some of these 2386 * cases the device is in such a state that a cold reset may 2387 * lock up the host. 2388 * 2389 * Reading any host interest register via copy engine is 2390 * sufficient to verify if device is capable of booting 2391 * firmware blob. 2392 */ 2393 ret = ath10k_pci_init_pipes(ar); 2394 if (ret) { 2395 ath10k_warn(ar, "failed to init copy engine: %d\n", 2396 ret); 2397 continue; 2398 } 2399 2400 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, 2401 &val); 2402 if (ret) { 2403 ath10k_warn(ar, "failed to poke copy engine: %d\n", 2404 ret); 2405 continue; 2406 } 2407 2408 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); 2409 return 0; 2410 } 2411 2412 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { 2413 ath10k_warn(ar, "refusing cold reset as requested\n"); 2414 return -EPERM; 2415 } 2416 2417 ret = ath10k_pci_cold_reset(ar); 2418 if (ret) { 2419 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2420 return ret; 2421 } 2422 2423 ret = ath10k_pci_wait_for_target_init(ar); 2424 if (ret) { 2425 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2426 ret); 2427 return ret; 2428 } 2429 2430 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n"); 2431 2432 return 0; 2433 } 2434 2435 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar) 2436 { 2437 int ret; 2438 2439 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n"); 2440 2441 /* FIXME: QCA6174 requires cold + warm reset to work. */ 2442 2443 ret = ath10k_pci_cold_reset(ar); 2444 if (ret) { 2445 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2446 return ret; 2447 } 2448 2449 ret = ath10k_pci_wait_for_target_init(ar); 2450 if (ret) { 2451 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2452 ret); 2453 return ret; 2454 } 2455 2456 ret = ath10k_pci_warm_reset(ar); 2457 if (ret) { 2458 ath10k_warn(ar, "failed to warm reset: %d\n", ret); 2459 return ret; 2460 } 2461 2462 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n"); 2463 2464 return 0; 2465 } 2466 2467 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar) 2468 { 2469 int ret; 2470 2471 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n"); 2472 2473 ret = ath10k_pci_cold_reset(ar); 2474 if (ret) { 2475 ath10k_warn(ar, "failed to cold reset: %d\n", ret); 2476 return ret; 2477 } 2478 2479 ret = ath10k_pci_wait_for_target_init(ar); 2480 if (ret) { 2481 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", 2482 ret); 2483 return ret; 2484 } 2485 2486 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n"); 2487 2488 return 0; 2489 } 2490 2491 static int ath10k_pci_chip_reset(struct ath10k *ar) 2492 { 2493 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2494 2495 if (WARN_ON(!ar_pci->pci_hard_reset)) 2496 return -ENOTSUPP; 2497 2498 return ar_pci->pci_hard_reset(ar); 2499 } 2500 2501 static int ath10k_pci_hif_power_up(struct ath10k *ar) 2502 { 2503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2504 int ret; 2505 2506 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); 2507 2508 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2509 &ar_pci->link_ctl); 2510 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, 2511 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 2512 2513 /* 2514 * Bring the target up cleanly. 2515 * 2516 * The target may be in an undefined state with an AUX-powered Target 2517 * and a Host in WoW mode. If the Host crashes, loses power, or is 2518 * restarted (without unloading the driver) then the Target is left 2519 * (aux) powered and running. On a subsequent driver load, the Target 2520 * is in an unexpected state. We try to catch that here in order to 2521 * reset the Target and retry the probe. 2522 */ 2523 ret = ath10k_pci_chip_reset(ar); 2524 if (ret) { 2525 if (ath10k_pci_has_fw_crashed(ar)) { 2526 ath10k_warn(ar, "firmware crashed during chip reset\n"); 2527 ath10k_pci_fw_crashed_clear(ar); 2528 ath10k_pci_fw_crashed_dump(ar); 2529 } 2530 2531 ath10k_err(ar, "failed to reset chip: %d\n", ret); 2532 goto err_sleep; 2533 } 2534 2535 ret = ath10k_pci_init_pipes(ar); 2536 if (ret) { 2537 ath10k_err(ar, "failed to initialize CE: %d\n", ret); 2538 goto err_sleep; 2539 } 2540 2541 ret = ath10k_pci_init_config(ar); 2542 if (ret) { 2543 ath10k_err(ar, "failed to setup init config: %d\n", ret); 2544 goto err_ce; 2545 } 2546 2547 ret = ath10k_pci_wake_target_cpu(ar); 2548 if (ret) { 2549 ath10k_err(ar, "could not wake up target CPU: %d\n", ret); 2550 goto err_ce; 2551 } 2552 2553 return 0; 2554 2555 err_ce: 2556 ath10k_pci_ce_deinit(ar); 2557 2558 err_sleep: 2559 return ret; 2560 } 2561 2562 void ath10k_pci_hif_power_down(struct ath10k *ar) 2563 { 2564 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); 2565 2566 /* Currently hif_power_up performs effectively a reset and hif_stop 2567 * resets the chip as well so there's no point in resetting here. 2568 */ 2569 } 2570 2571 #ifdef CONFIG_PM 2572 2573 static int ath10k_pci_hif_suspend(struct ath10k *ar) 2574 { 2575 /* The grace timer can still be counting down and ar->ps_awake be true. 2576 * It is known that the device may be asleep after resuming regardless 2577 * of the SoC powersave state before suspending. Hence make sure the 2578 * device is asleep before proceeding. 2579 */ 2580 ath10k_pci_sleep_sync(ar); 2581 2582 return 0; 2583 } 2584 2585 static int ath10k_pci_hif_resume(struct ath10k *ar) 2586 { 2587 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2588 struct pci_dev *pdev = ar_pci->pdev; 2589 u32 val; 2590 int ret = 0; 2591 2592 ret = ath10k_pci_force_wake(ar); 2593 if (ret) { 2594 ath10k_err(ar, "failed to wake up target: %d\n", ret); 2595 return ret; 2596 } 2597 2598 /* Suspend/Resume resets the PCI configuration space, so we have to 2599 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries 2600 * from interfering with C3 CPU state. pci_restore_state won't help 2601 * here since it only restores the first 64 bytes pci config header. 2602 */ 2603 pci_read_config_dword(pdev, 0x40, &val); 2604 if ((val & 0x0000ff00) != 0) 2605 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 2606 2607 return ret; 2608 } 2609 #endif 2610 2611 static bool ath10k_pci_validate_cal(void *data, size_t size) 2612 { 2613 __le16 *cal_words = data; 2614 u16 checksum = 0; 2615 size_t i; 2616 2617 if (size % 2 != 0) 2618 return false; 2619 2620 for (i = 0; i < size / 2; i++) 2621 checksum ^= le16_to_cpu(cal_words[i]); 2622 2623 return checksum == 0xffff; 2624 } 2625 2626 static void ath10k_pci_enable_eeprom(struct ath10k *ar) 2627 { 2628 /* Enable SI clock */ 2629 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0); 2630 2631 /* Configure GPIOs for I2C operation */ 2632 ath10k_pci_write32(ar, 2633 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2634 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN, 2635 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG, 2636 GPIO_PIN0_CONFIG) | 2637 SM(1, GPIO_PIN0_PAD_PULL)); 2638 2639 ath10k_pci_write32(ar, 2640 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET + 2641 4 * QCA9887_1_0_SI_CLK_GPIO_PIN, 2642 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) | 2643 SM(1, GPIO_PIN0_PAD_PULL)); 2644 2645 ath10k_pci_write32(ar, 2646 GPIO_BASE_ADDRESS + 2647 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS, 2648 1u << QCA9887_1_0_SI_CLK_GPIO_PIN); 2649 2650 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */ 2651 ath10k_pci_write32(ar, 2652 SI_BASE_ADDRESS + SI_CONFIG_OFFSET, 2653 SM(1, SI_CONFIG_ERR_INT) | 2654 SM(1, SI_CONFIG_BIDIR_OD_DATA) | 2655 SM(1, SI_CONFIG_I2C) | 2656 SM(1, SI_CONFIG_POS_SAMPLE) | 2657 SM(1, SI_CONFIG_INACTIVE_DATA) | 2658 SM(1, SI_CONFIG_INACTIVE_CLK) | 2659 SM(8, SI_CONFIG_DIVIDER)); 2660 } 2661 2662 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out) 2663 { 2664 u32 reg; 2665 int wait_limit; 2666 2667 /* set device select byte and for the read operation */ 2668 reg = QCA9887_EEPROM_SELECT_READ | 2669 SM(addr, QCA9887_EEPROM_ADDR_LO) | 2670 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI); 2671 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg); 2672 2673 /* write transmit data, transfer length, and START bit */ 2674 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, 2675 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) | 2676 SM(4, SI_CS_TX_CNT)); 2677 2678 /* wait max 1 sec */ 2679 wait_limit = 100000; 2680 2681 /* wait for SI_CS_DONE_INT */ 2682 do { 2683 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET); 2684 if (MS(reg, SI_CS_DONE_INT)) 2685 break; 2686 2687 wait_limit--; 2688 udelay(10); 2689 } while (wait_limit > 0); 2690 2691 if (!MS(reg, SI_CS_DONE_INT)) { 2692 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n", 2693 addr); 2694 return -ETIMEDOUT; 2695 } 2696 2697 /* clear SI_CS_DONE_INT */ 2698 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg); 2699 2700 if (MS(reg, SI_CS_DONE_ERR)) { 2701 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr); 2702 return -EIO; 2703 } 2704 2705 /* extract receive data */ 2706 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET); 2707 *out = reg; 2708 2709 return 0; 2710 } 2711 2712 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data, 2713 size_t *data_len) 2714 { 2715 u8 *caldata = NULL; 2716 size_t calsize, i; 2717 int ret; 2718 2719 if (!QCA_REV_9887(ar)) 2720 return -EOPNOTSUPP; 2721 2722 calsize = ar->hw_params.cal_data_len; 2723 caldata = kmalloc(calsize, GFP_KERNEL); 2724 if (!caldata) 2725 return -ENOMEM; 2726 2727 ath10k_pci_enable_eeprom(ar); 2728 2729 for (i = 0; i < calsize; i++) { 2730 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]); 2731 if (ret) 2732 goto err_free; 2733 } 2734 2735 if (!ath10k_pci_validate_cal(caldata, calsize)) 2736 goto err_free; 2737 2738 *data = caldata; 2739 *data_len = calsize; 2740 2741 return 0; 2742 2743 err_free: 2744 kfree(caldata); 2745 2746 return -EINVAL; 2747 } 2748 2749 static const struct ath10k_hif_ops ath10k_pci_hif_ops = { 2750 .tx_sg = ath10k_pci_hif_tx_sg, 2751 .diag_read = ath10k_pci_hif_diag_read, 2752 .diag_write = ath10k_pci_diag_write_mem, 2753 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, 2754 .start = ath10k_pci_hif_start, 2755 .stop = ath10k_pci_hif_stop, 2756 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, 2757 .get_default_pipe = ath10k_pci_hif_get_default_pipe, 2758 .send_complete_check = ath10k_pci_hif_send_complete_check, 2759 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, 2760 .power_up = ath10k_pci_hif_power_up, 2761 .power_down = ath10k_pci_hif_power_down, 2762 .read32 = ath10k_pci_read32, 2763 .write32 = ath10k_pci_write32, 2764 #ifdef CONFIG_PM 2765 .suspend = ath10k_pci_hif_suspend, 2766 .resume = ath10k_pci_hif_resume, 2767 #endif 2768 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom, 2769 }; 2770 2771 /* 2772 * Top-level interrupt handler for all PCI interrupts from a Target. 2773 * When a block of MSI interrupts is allocated, this top-level handler 2774 * is not used; instead, we directly call the correct sub-handler. 2775 */ 2776 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) 2777 { 2778 struct ath10k *ar = arg; 2779 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2780 int ret; 2781 2782 if (ath10k_pci_has_device_gone(ar)) 2783 return IRQ_NONE; 2784 2785 ret = ath10k_pci_force_wake(ar); 2786 if (ret) { 2787 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret); 2788 return IRQ_NONE; 2789 } 2790 2791 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) && 2792 !ath10k_pci_irq_pending(ar)) 2793 return IRQ_NONE; 2794 2795 ath10k_pci_disable_and_clear_legacy_irq(ar); 2796 ath10k_pci_irq_msi_fw_mask(ar); 2797 napi_schedule(&ar->napi); 2798 2799 return IRQ_HANDLED; 2800 } 2801 2802 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) 2803 { 2804 struct ath10k *ar = container_of(ctx, struct ath10k, napi); 2805 int done = 0; 2806 2807 if (ath10k_pci_has_fw_crashed(ar)) { 2808 ath10k_pci_fw_crashed_clear(ar); 2809 ath10k_pci_fw_crashed_dump(ar); 2810 napi_complete(ctx); 2811 return done; 2812 } 2813 2814 ath10k_ce_per_engine_service_any(ar); 2815 2816 done = ath10k_htt_txrx_compl_task(ar, budget); 2817 2818 if (done < budget) { 2819 napi_complete_done(ctx, done); 2820 /* In case of MSI, it is possible that interrupts are received 2821 * while NAPI poll is inprogress. So pending interrupts that are 2822 * received after processing all copy engine pipes by NAPI poll 2823 * will not be handled again. This is causing failure to 2824 * complete boot sequence in x86 platform. So before enabling 2825 * interrupts safer to check for pending interrupts for 2826 * immediate servicing. 2827 */ 2828 if (CE_INTERRUPT_SUMMARY(ar)) { 2829 napi_reschedule(ctx); 2830 goto out; 2831 } 2832 ath10k_pci_enable_legacy_irq(ar); 2833 ath10k_pci_irq_msi_fw_unmask(ar); 2834 } 2835 2836 out: 2837 return done; 2838 } 2839 2840 static int ath10k_pci_request_irq_msi(struct ath10k *ar) 2841 { 2842 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2843 int ret; 2844 2845 ret = request_irq(ar_pci->pdev->irq, 2846 ath10k_pci_interrupt_handler, 2847 IRQF_SHARED, "ath10k_pci", ar); 2848 if (ret) { 2849 ath10k_warn(ar, "failed to request MSI irq %d: %d\n", 2850 ar_pci->pdev->irq, ret); 2851 return ret; 2852 } 2853 2854 return 0; 2855 } 2856 2857 static int ath10k_pci_request_irq_legacy(struct ath10k *ar) 2858 { 2859 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2860 int ret; 2861 2862 ret = request_irq(ar_pci->pdev->irq, 2863 ath10k_pci_interrupt_handler, 2864 IRQF_SHARED, "ath10k_pci", ar); 2865 if (ret) { 2866 ath10k_warn(ar, "failed to request legacy irq %d: %d\n", 2867 ar_pci->pdev->irq, ret); 2868 return ret; 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int ath10k_pci_request_irq(struct ath10k *ar) 2875 { 2876 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2877 2878 switch (ar_pci->oper_irq_mode) { 2879 case ATH10K_PCI_IRQ_LEGACY: 2880 return ath10k_pci_request_irq_legacy(ar); 2881 case ATH10K_PCI_IRQ_MSI: 2882 return ath10k_pci_request_irq_msi(ar); 2883 default: 2884 return -EINVAL; 2885 } 2886 } 2887 2888 static void ath10k_pci_free_irq(struct ath10k *ar) 2889 { 2890 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2891 2892 free_irq(ar_pci->pdev->irq, ar); 2893 } 2894 2895 void ath10k_pci_init_napi(struct ath10k *ar) 2896 { 2897 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll, 2898 ATH10K_NAPI_BUDGET); 2899 } 2900 2901 static int ath10k_pci_init_irq(struct ath10k *ar) 2902 { 2903 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2904 int ret; 2905 2906 ath10k_pci_init_napi(ar); 2907 2908 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) 2909 ath10k_info(ar, "limiting irq mode to: %d\n", 2910 ath10k_pci_irq_mode); 2911 2912 /* Try MSI */ 2913 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { 2914 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI; 2915 ret = pci_enable_msi(ar_pci->pdev); 2916 if (ret == 0) 2917 return 0; 2918 2919 /* fall-through */ 2920 } 2921 2922 /* Try legacy irq 2923 * 2924 * A potential race occurs here: The CORE_BASE write 2925 * depends on target correctly decoding AXI address but 2926 * host won't know when target writes BAR to CORE_CTRL. 2927 * This write might get lost if target has NOT written BAR. 2928 * For now, fix the race by repeating the write in below 2929 * synchronization checking. 2930 */ 2931 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; 2932 2933 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2934 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); 2935 2936 return 0; 2937 } 2938 2939 static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) 2940 { 2941 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, 2942 0); 2943 } 2944 2945 static int ath10k_pci_deinit_irq(struct ath10k *ar) 2946 { 2947 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2948 2949 switch (ar_pci->oper_irq_mode) { 2950 case ATH10K_PCI_IRQ_LEGACY: 2951 ath10k_pci_deinit_irq_legacy(ar); 2952 break; 2953 default: 2954 pci_disable_msi(ar_pci->pdev); 2955 break; 2956 } 2957 2958 return 0; 2959 } 2960 2961 int ath10k_pci_wait_for_target_init(struct ath10k *ar) 2962 { 2963 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 2964 unsigned long timeout; 2965 u32 val; 2966 2967 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); 2968 2969 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); 2970 2971 do { 2972 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); 2973 2974 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", 2975 val); 2976 2977 /* target should never return this */ 2978 if (val == 0xffffffff) 2979 continue; 2980 2981 /* the device has crashed so don't bother trying anymore */ 2982 if (val & FW_IND_EVENT_PENDING) 2983 break; 2984 2985 if (val & FW_IND_INITIALIZED) 2986 break; 2987 2988 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) 2989 /* Fix potential race by repeating CORE_BASE writes */ 2990 ath10k_pci_enable_legacy_irq(ar); 2991 2992 mdelay(10); 2993 } while (time_before(jiffies, timeout)); 2994 2995 ath10k_pci_disable_and_clear_legacy_irq(ar); 2996 ath10k_pci_irq_msi_fw_mask(ar); 2997 2998 if (val == 0xffffffff) { 2999 ath10k_err(ar, "failed to read device register, device is gone\n"); 3000 return -EIO; 3001 } 3002 3003 if (val & FW_IND_EVENT_PENDING) { 3004 ath10k_warn(ar, "device has crashed during init\n"); 3005 return -ECOMM; 3006 } 3007 3008 if (!(val & FW_IND_INITIALIZED)) { 3009 ath10k_err(ar, "failed to receive initialized event from target: %08x\n", 3010 val); 3011 return -ETIMEDOUT; 3012 } 3013 3014 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); 3015 return 0; 3016 } 3017 3018 static int ath10k_pci_cold_reset(struct ath10k *ar) 3019 { 3020 u32 val; 3021 3022 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); 3023 3024 spin_lock_bh(&ar->data_lock); 3025 3026 ar->stats.fw_cold_reset_counter++; 3027 3028 spin_unlock_bh(&ar->data_lock); 3029 3030 /* Put Target, including PCIe, into RESET. */ 3031 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); 3032 val |= 1; 3033 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3034 3035 /* After writing into SOC_GLOBAL_RESET to put device into 3036 * reset and pulling out of reset pcie may not be stable 3037 * for any immediate pcie register access and cause bus error, 3038 * add delay before any pcie access request to fix this issue. 3039 */ 3040 msleep(20); 3041 3042 /* Pull Target, including PCIe, out of RESET. */ 3043 val &= ~1; 3044 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); 3045 3046 msleep(20); 3047 3048 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); 3049 3050 return 0; 3051 } 3052 3053 static int ath10k_pci_claim(struct ath10k *ar) 3054 { 3055 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3056 struct pci_dev *pdev = ar_pci->pdev; 3057 int ret; 3058 3059 pci_set_drvdata(pdev, ar); 3060 3061 ret = pci_enable_device(pdev); 3062 if (ret) { 3063 ath10k_err(ar, "failed to enable pci device: %d\n", ret); 3064 return ret; 3065 } 3066 3067 ret = pci_request_region(pdev, BAR_NUM, "ath"); 3068 if (ret) { 3069 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, 3070 ret); 3071 goto err_device; 3072 } 3073 3074 /* Target expects 32 bit DMA. Enforce it. */ 3075 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3076 if (ret) { 3077 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); 3078 goto err_region; 3079 } 3080 3081 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 3082 if (ret) { 3083 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", 3084 ret); 3085 goto err_region; 3086 } 3087 3088 pci_set_master(pdev); 3089 3090 /* Arrange for access to Target SoC registers. */ 3091 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM); 3092 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); 3093 if (!ar_pci->mem) { 3094 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); 3095 ret = -EIO; 3096 goto err_master; 3097 } 3098 3099 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem); 3100 return 0; 3101 3102 err_master: 3103 pci_clear_master(pdev); 3104 3105 err_region: 3106 pci_release_region(pdev, BAR_NUM); 3107 3108 err_device: 3109 pci_disable_device(pdev); 3110 3111 return ret; 3112 } 3113 3114 static void ath10k_pci_release(struct ath10k *ar) 3115 { 3116 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3117 struct pci_dev *pdev = ar_pci->pdev; 3118 3119 pci_iounmap(pdev, ar_pci->mem); 3120 pci_release_region(pdev, BAR_NUM); 3121 pci_clear_master(pdev); 3122 pci_disable_device(pdev); 3123 } 3124 3125 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) 3126 { 3127 const struct ath10k_pci_supp_chip *supp_chip; 3128 int i; 3129 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); 3130 3131 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { 3132 supp_chip = &ath10k_pci_supp_chips[i]; 3133 3134 if (supp_chip->dev_id == dev_id && 3135 supp_chip->rev_id == rev_id) 3136 return true; 3137 } 3138 3139 return false; 3140 } 3141 3142 int ath10k_pci_setup_resource(struct ath10k *ar) 3143 { 3144 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); 3145 int ret; 3146 3147 spin_lock_init(&ar_pci->ce_lock); 3148 spin_lock_init(&ar_pci->ps_lock); 3149 3150 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 3151 (unsigned long)ar); 3152 3153 if (QCA_REV_6174(ar) || QCA_REV_9377(ar)) 3154 ath10k_pci_override_ce_config(ar); 3155 3156 ret = ath10k_pci_alloc_pipes(ar); 3157 if (ret) { 3158 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", 3159 ret); 3160 return ret; 3161 } 3162 3163 return 0; 3164 } 3165 3166 void ath10k_pci_release_resource(struct ath10k *ar) 3167 { 3168 ath10k_pci_rx_retry_sync(ar); 3169 netif_napi_del(&ar->napi); 3170 ath10k_pci_ce_deinit(ar); 3171 ath10k_pci_free_pipes(ar); 3172 } 3173 3174 static const struct ath10k_bus_ops ath10k_pci_bus_ops = { 3175 .read32 = ath10k_bus_pci_read32, 3176 .write32 = ath10k_bus_pci_write32, 3177 .get_num_banks = ath10k_pci_get_num_banks, 3178 }; 3179 3180 static int ath10k_pci_probe(struct pci_dev *pdev, 3181 const struct pci_device_id *pci_dev) 3182 { 3183 int ret = 0; 3184 struct ath10k *ar; 3185 struct ath10k_pci *ar_pci; 3186 enum ath10k_hw_rev hw_rev; 3187 u32 chip_id; 3188 bool pci_ps; 3189 int (*pci_soft_reset)(struct ath10k *ar); 3190 int (*pci_hard_reset)(struct ath10k *ar); 3191 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr); 3192 3193 switch (pci_dev->device) { 3194 case QCA988X_2_0_DEVICE_ID: 3195 hw_rev = ATH10K_HW_QCA988X; 3196 pci_ps = false; 3197 pci_soft_reset = ath10k_pci_warm_reset; 3198 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3199 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3200 break; 3201 case QCA9887_1_0_DEVICE_ID: 3202 hw_rev = ATH10K_HW_QCA9887; 3203 pci_ps = false; 3204 pci_soft_reset = ath10k_pci_warm_reset; 3205 pci_hard_reset = ath10k_pci_qca988x_chip_reset; 3206 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3207 break; 3208 case QCA6164_2_1_DEVICE_ID: 3209 case QCA6174_2_1_DEVICE_ID: 3210 hw_rev = ATH10K_HW_QCA6174; 3211 pci_ps = true; 3212 pci_soft_reset = ath10k_pci_warm_reset; 3213 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3214 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3215 break; 3216 case QCA99X0_2_0_DEVICE_ID: 3217 hw_rev = ATH10K_HW_QCA99X0; 3218 pci_ps = false; 3219 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3220 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3221 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3222 break; 3223 case QCA9984_1_0_DEVICE_ID: 3224 hw_rev = ATH10K_HW_QCA9984; 3225 pci_ps = false; 3226 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3227 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3228 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3229 break; 3230 case QCA9888_2_0_DEVICE_ID: 3231 hw_rev = ATH10K_HW_QCA9888; 3232 pci_ps = false; 3233 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; 3234 pci_hard_reset = ath10k_pci_qca99x0_chip_reset; 3235 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; 3236 break; 3237 case QCA9377_1_0_DEVICE_ID: 3238 hw_rev = ATH10K_HW_QCA9377; 3239 pci_ps = true; 3240 pci_soft_reset = NULL; 3241 pci_hard_reset = ath10k_pci_qca6174_chip_reset; 3242 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr; 3243 break; 3244 default: 3245 WARN_ON(1); 3246 return -ENOTSUPP; 3247 } 3248 3249 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI, 3250 hw_rev, &ath10k_pci_hif_ops); 3251 if (!ar) { 3252 dev_err(&pdev->dev, "failed to allocate core\n"); 3253 return -ENOMEM; 3254 } 3255 3256 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 3257 pdev->vendor, pdev->device, 3258 pdev->subsystem_vendor, pdev->subsystem_device); 3259 3260 ar_pci = ath10k_pci_priv(ar); 3261 ar_pci->pdev = pdev; 3262 ar_pci->dev = &pdev->dev; 3263 ar_pci->ar = ar; 3264 ar->dev_id = pci_dev->device; 3265 ar_pci->pci_ps = pci_ps; 3266 ar_pci->bus_ops = &ath10k_pci_bus_ops; 3267 ar_pci->pci_soft_reset = pci_soft_reset; 3268 ar_pci->pci_hard_reset = pci_hard_reset; 3269 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; 3270 3271 ar->id.vendor = pdev->vendor; 3272 ar->id.device = pdev->device; 3273 ar->id.subsystem_vendor = pdev->subsystem_vendor; 3274 ar->id.subsystem_device = pdev->subsystem_device; 3275 3276 setup_timer(&ar_pci->ps_timer, ath10k_pci_ps_timer, 3277 (unsigned long)ar); 3278 3279 ret = ath10k_pci_setup_resource(ar); 3280 if (ret) { 3281 ath10k_err(ar, "failed to setup resource: %d\n", ret); 3282 goto err_core_destroy; 3283 } 3284 3285 ret = ath10k_pci_claim(ar); 3286 if (ret) { 3287 ath10k_err(ar, "failed to claim device: %d\n", ret); 3288 goto err_free_pipes; 3289 } 3290 3291 ret = ath10k_pci_force_wake(ar); 3292 if (ret) { 3293 ath10k_warn(ar, "failed to wake up device : %d\n", ret); 3294 goto err_sleep; 3295 } 3296 3297 ath10k_pci_ce_deinit(ar); 3298 ath10k_pci_irq_disable(ar); 3299 3300 ret = ath10k_pci_init_irq(ar); 3301 if (ret) { 3302 ath10k_err(ar, "failed to init irqs: %d\n", ret); 3303 goto err_sleep; 3304 } 3305 3306 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n", 3307 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode, 3308 ath10k_pci_irq_mode, ath10k_pci_reset_mode); 3309 3310 ret = ath10k_pci_request_irq(ar); 3311 if (ret) { 3312 ath10k_warn(ar, "failed to request irqs: %d\n", ret); 3313 goto err_deinit_irq; 3314 } 3315 3316 ret = ath10k_pci_chip_reset(ar); 3317 if (ret) { 3318 ath10k_err(ar, "failed to reset chip: %d\n", ret); 3319 goto err_free_irq; 3320 } 3321 3322 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); 3323 if (chip_id == 0xffffffff) { 3324 ath10k_err(ar, "failed to get chip id\n"); 3325 goto err_free_irq; 3326 } 3327 3328 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { 3329 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", 3330 pdev->device, chip_id); 3331 goto err_free_irq; 3332 } 3333 3334 ret = ath10k_core_register(ar, chip_id); 3335 if (ret) { 3336 ath10k_err(ar, "failed to register driver core: %d\n", ret); 3337 goto err_free_irq; 3338 } 3339 3340 return 0; 3341 3342 err_free_irq: 3343 ath10k_pci_free_irq(ar); 3344 ath10k_pci_rx_retry_sync(ar); 3345 3346 err_deinit_irq: 3347 ath10k_pci_deinit_irq(ar); 3348 3349 err_sleep: 3350 ath10k_pci_sleep_sync(ar); 3351 ath10k_pci_release(ar); 3352 3353 err_free_pipes: 3354 ath10k_pci_free_pipes(ar); 3355 3356 err_core_destroy: 3357 ath10k_core_destroy(ar); 3358 3359 return ret; 3360 } 3361 3362 static void ath10k_pci_remove(struct pci_dev *pdev) 3363 { 3364 struct ath10k *ar = pci_get_drvdata(pdev); 3365 struct ath10k_pci *ar_pci; 3366 3367 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); 3368 3369 if (!ar) 3370 return; 3371 3372 ar_pci = ath10k_pci_priv(ar); 3373 3374 if (!ar_pci) 3375 return; 3376 3377 ath10k_core_unregister(ar); 3378 ath10k_pci_free_irq(ar); 3379 ath10k_pci_deinit_irq(ar); 3380 ath10k_pci_release_resource(ar); 3381 ath10k_pci_sleep_sync(ar); 3382 ath10k_pci_release(ar); 3383 ath10k_core_destroy(ar); 3384 } 3385 3386 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); 3387 3388 static struct pci_driver ath10k_pci_driver = { 3389 .name = "ath10k_pci", 3390 .id_table = ath10k_pci_id_table, 3391 .probe = ath10k_pci_probe, 3392 .remove = ath10k_pci_remove, 3393 }; 3394 3395 static int __init ath10k_pci_init(void) 3396 { 3397 int ret; 3398 3399 ret = pci_register_driver(&ath10k_pci_driver); 3400 if (ret) 3401 printk(KERN_ERR "failed to register ath10k pci driver: %d\n", 3402 ret); 3403 3404 ret = ath10k_ahb_init(); 3405 if (ret) 3406 printk(KERN_ERR "ahb init failed: %d\n", ret); 3407 3408 return ret; 3409 } 3410 module_init(ath10k_pci_init); 3411 3412 static void __exit ath10k_pci_exit(void) 3413 { 3414 pci_unregister_driver(&ath10k_pci_driver); 3415 ath10k_ahb_exit(); 3416 } 3417 3418 module_exit(ath10k_pci_exit); 3419 3420 MODULE_AUTHOR("Qualcomm Atheros"); 3421 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices"); 3422 MODULE_LICENSE("Dual BSD/GPL"); 3423 3424 /* QCA988x 2.0 firmware files */ 3425 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); 3426 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); 3427 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3428 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3429 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); 3430 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3431 3432 /* QCA9887 1.0 firmware files */ 3433 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3434 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE); 3435 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3436 3437 /* QCA6174 2.1 firmware files */ 3438 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE); 3439 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE); 3440 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE); 3441 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3442 3443 /* QCA6174 3.1 firmware files */ 3444 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE); 3445 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3446 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE); 3447 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE); 3448 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE); 3449 3450 /* QCA9377 1.0 firmware files */ 3451 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE); 3452 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE); 3453